core.c 19 KB

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  1. /*
  2. * linux/drivers/video/omap2/dss/core.c
  3. *
  4. * Copyright (C) 2009 Nokia Corporation
  5. * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
  6. *
  7. * Some code and ideas taken from drivers/video/omap/ driver
  8. * by Imre Deak.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License version 2 as published by
  12. * the Free Software Foundation.
  13. *
  14. * This program is distributed in the hope that it will be useful, but WITHOUT
  15. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  17. * more details.
  18. *
  19. * You should have received a copy of the GNU General Public License along with
  20. * this program. If not, see <http://www.gnu.org/licenses/>.
  21. */
  22. #define DSS_SUBSYS_NAME "CORE"
  23. #include <linux/kernel.h>
  24. #include <linux/module.h>
  25. #include <linux/clk.h>
  26. #include <linux/err.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/seq_file.h>
  29. #include <linux/debugfs.h>
  30. #include <linux/io.h>
  31. #include <linux/device.h>
  32. #include <plat/display.h>
  33. #include <plat/clock.h>
  34. #include "dss.h"
  35. static struct {
  36. struct platform_device *pdev;
  37. int ctx_id;
  38. struct clk *dss_ick;
  39. struct clk *dss1_fck;
  40. struct clk *dss2_fck;
  41. struct clk *dss_54m_fck;
  42. struct clk *dss_96m_fck;
  43. unsigned num_clks_enabled;
  44. } core;
  45. static void dss_clk_enable_all_no_ctx(void);
  46. static void dss_clk_disable_all_no_ctx(void);
  47. static void dss_clk_enable_no_ctx(enum dss_clock clks);
  48. static void dss_clk_disable_no_ctx(enum dss_clock clks);
  49. static char *def_disp_name;
  50. module_param_named(def_disp, def_disp_name, charp, 0);
  51. MODULE_PARM_DESC(def_disp_name, "default display name");
  52. #ifdef DEBUG
  53. unsigned int dss_debug;
  54. module_param_named(debug, dss_debug, bool, 0644);
  55. #endif
  56. /* CONTEXT */
  57. static int dss_get_ctx_id(void)
  58. {
  59. struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
  60. int r;
  61. if (!pdata->get_last_off_on_transaction_id)
  62. return 0;
  63. r = pdata->get_last_off_on_transaction_id(&core.pdev->dev);
  64. if (r < 0) {
  65. dev_err(&core.pdev->dev, "getting transaction ID failed, "
  66. "will force context restore\n");
  67. r = -1;
  68. }
  69. return r;
  70. }
  71. int dss_need_ctx_restore(void)
  72. {
  73. int id = dss_get_ctx_id();
  74. if (id < 0 || id != core.ctx_id) {
  75. DSSDBG("ctx id %d -> id %d\n",
  76. core.ctx_id, id);
  77. core.ctx_id = id;
  78. return 1;
  79. } else {
  80. return 0;
  81. }
  82. }
  83. static void save_all_ctx(void)
  84. {
  85. DSSDBG("save context\n");
  86. dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
  87. dss_save_context();
  88. dispc_save_context();
  89. #ifdef CONFIG_OMAP2_DSS_DSI
  90. dsi_save_context();
  91. #endif
  92. dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK1);
  93. }
  94. static void restore_all_ctx(void)
  95. {
  96. DSSDBG("restore context\n");
  97. dss_clk_enable_all_no_ctx();
  98. dss_restore_context();
  99. dispc_restore_context();
  100. #ifdef CONFIG_OMAP2_DSS_DSI
  101. dsi_restore_context();
  102. #endif
  103. dss_clk_disable_all_no_ctx();
  104. }
  105. /* CLOCKS */
  106. static void core_dump_clocks(struct seq_file *s)
  107. {
  108. int i;
  109. struct clk *clocks[5] = {
  110. core.dss_ick,
  111. core.dss1_fck,
  112. core.dss2_fck,
  113. core.dss_54m_fck,
  114. core.dss_96m_fck
  115. };
  116. seq_printf(s, "- CORE -\n");
  117. seq_printf(s, "internal clk count\t\t%u\n", core.num_clks_enabled);
  118. for (i = 0; i < 5; i++) {
  119. if (!clocks[i])
  120. continue;
  121. seq_printf(s, "%-15s\t%lu\t%d\n",
  122. clocks[i]->name,
  123. clk_get_rate(clocks[i]),
  124. clocks[i]->usecount);
  125. }
  126. }
  127. static int dss_get_clock(struct clk **clock, const char *clk_name)
  128. {
  129. struct clk *clk;
  130. clk = clk_get(&core.pdev->dev, clk_name);
  131. if (IS_ERR(clk)) {
  132. DSSERR("can't get clock %s", clk_name);
  133. return PTR_ERR(clk);
  134. }
  135. *clock = clk;
  136. DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk));
  137. return 0;
  138. }
  139. static int dss_get_clocks(void)
  140. {
  141. int r;
  142. core.dss_ick = NULL;
  143. core.dss1_fck = NULL;
  144. core.dss2_fck = NULL;
  145. core.dss_54m_fck = NULL;
  146. core.dss_96m_fck = NULL;
  147. r = dss_get_clock(&core.dss_ick, "ick");
  148. if (r)
  149. goto err;
  150. r = dss_get_clock(&core.dss1_fck, "dss1_fck");
  151. if (r)
  152. goto err;
  153. r = dss_get_clock(&core.dss2_fck, "dss2_fck");
  154. if (r)
  155. goto err;
  156. r = dss_get_clock(&core.dss_54m_fck, "tv_fck");
  157. if (r)
  158. goto err;
  159. r = dss_get_clock(&core.dss_96m_fck, "video_fck");
  160. if (r)
  161. goto err;
  162. return 0;
  163. err:
  164. if (core.dss_ick)
  165. clk_put(core.dss_ick);
  166. if (core.dss1_fck)
  167. clk_put(core.dss1_fck);
  168. if (core.dss2_fck)
  169. clk_put(core.dss2_fck);
  170. if (core.dss_54m_fck)
  171. clk_put(core.dss_54m_fck);
  172. if (core.dss_96m_fck)
  173. clk_put(core.dss_96m_fck);
  174. return r;
  175. }
  176. static void dss_put_clocks(void)
  177. {
  178. if (core.dss_96m_fck)
  179. clk_put(core.dss_96m_fck);
  180. clk_put(core.dss_54m_fck);
  181. clk_put(core.dss1_fck);
  182. clk_put(core.dss2_fck);
  183. clk_put(core.dss_ick);
  184. }
  185. unsigned long dss_clk_get_rate(enum dss_clock clk)
  186. {
  187. switch (clk) {
  188. case DSS_CLK_ICK:
  189. return clk_get_rate(core.dss_ick);
  190. case DSS_CLK_FCK1:
  191. return clk_get_rate(core.dss1_fck);
  192. case DSS_CLK_FCK2:
  193. return clk_get_rate(core.dss2_fck);
  194. case DSS_CLK_54M:
  195. return clk_get_rate(core.dss_54m_fck);
  196. case DSS_CLK_96M:
  197. return clk_get_rate(core.dss_96m_fck);
  198. }
  199. BUG();
  200. return 0;
  201. }
  202. static unsigned count_clk_bits(enum dss_clock clks)
  203. {
  204. unsigned num_clks = 0;
  205. if (clks & DSS_CLK_ICK)
  206. ++num_clks;
  207. if (clks & DSS_CLK_FCK1)
  208. ++num_clks;
  209. if (clks & DSS_CLK_FCK2)
  210. ++num_clks;
  211. if (clks & DSS_CLK_54M)
  212. ++num_clks;
  213. if (clks & DSS_CLK_96M)
  214. ++num_clks;
  215. return num_clks;
  216. }
  217. static void dss_clk_enable_no_ctx(enum dss_clock clks)
  218. {
  219. unsigned num_clks = count_clk_bits(clks);
  220. if (clks & DSS_CLK_ICK)
  221. clk_enable(core.dss_ick);
  222. if (clks & DSS_CLK_FCK1)
  223. clk_enable(core.dss1_fck);
  224. if (clks & DSS_CLK_FCK2)
  225. clk_enable(core.dss2_fck);
  226. if (clks & DSS_CLK_54M)
  227. clk_enable(core.dss_54m_fck);
  228. if (clks & DSS_CLK_96M)
  229. clk_enable(core.dss_96m_fck);
  230. core.num_clks_enabled += num_clks;
  231. }
  232. void dss_clk_enable(enum dss_clock clks)
  233. {
  234. dss_clk_enable_no_ctx(clks);
  235. if (cpu_is_omap34xx() && dss_need_ctx_restore())
  236. restore_all_ctx();
  237. }
  238. static void dss_clk_disable_no_ctx(enum dss_clock clks)
  239. {
  240. unsigned num_clks = count_clk_bits(clks);
  241. if (clks & DSS_CLK_ICK)
  242. clk_disable(core.dss_ick);
  243. if (clks & DSS_CLK_FCK1)
  244. clk_disable(core.dss1_fck);
  245. if (clks & DSS_CLK_FCK2)
  246. clk_disable(core.dss2_fck);
  247. if (clks & DSS_CLK_54M)
  248. clk_disable(core.dss_54m_fck);
  249. if (clks & DSS_CLK_96M)
  250. clk_disable(core.dss_96m_fck);
  251. core.num_clks_enabled -= num_clks;
  252. }
  253. void dss_clk_disable(enum dss_clock clks)
  254. {
  255. if (cpu_is_omap34xx()) {
  256. unsigned num_clks = count_clk_bits(clks);
  257. BUG_ON(core.num_clks_enabled < num_clks);
  258. if (core.num_clks_enabled == num_clks)
  259. save_all_ctx();
  260. }
  261. dss_clk_disable_no_ctx(clks);
  262. }
  263. static void dss_clk_enable_all_no_ctx(void)
  264. {
  265. enum dss_clock clks;
  266. clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
  267. if (cpu_is_omap34xx())
  268. clks |= DSS_CLK_96M;
  269. dss_clk_enable_no_ctx(clks);
  270. }
  271. static void dss_clk_disable_all_no_ctx(void)
  272. {
  273. enum dss_clock clks;
  274. clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
  275. if (cpu_is_omap34xx())
  276. clks |= DSS_CLK_96M;
  277. dss_clk_disable_no_ctx(clks);
  278. }
  279. static void dss_clk_disable_all(void)
  280. {
  281. enum dss_clock clks;
  282. clks = DSS_CLK_ICK | DSS_CLK_FCK1 | DSS_CLK_FCK2 | DSS_CLK_54M;
  283. if (cpu_is_omap34xx())
  284. clks |= DSS_CLK_96M;
  285. dss_clk_disable(clks);
  286. }
  287. /* DEBUGFS */
  288. #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
  289. static void dss_debug_dump_clocks(struct seq_file *s)
  290. {
  291. core_dump_clocks(s);
  292. dss_dump_clocks(s);
  293. dispc_dump_clocks(s);
  294. #ifdef CONFIG_OMAP2_DSS_DSI
  295. dsi_dump_clocks(s);
  296. #endif
  297. }
  298. static int dss_debug_show(struct seq_file *s, void *unused)
  299. {
  300. void (*func)(struct seq_file *) = s->private;
  301. func(s);
  302. return 0;
  303. }
  304. static int dss_debug_open(struct inode *inode, struct file *file)
  305. {
  306. return single_open(file, dss_debug_show, inode->i_private);
  307. }
  308. static const struct file_operations dss_debug_fops = {
  309. .open = dss_debug_open,
  310. .read = seq_read,
  311. .llseek = seq_lseek,
  312. .release = single_release,
  313. };
  314. static struct dentry *dss_debugfs_dir;
  315. static int dss_initialize_debugfs(void)
  316. {
  317. dss_debugfs_dir = debugfs_create_dir("omapdss", NULL);
  318. if (IS_ERR(dss_debugfs_dir)) {
  319. int err = PTR_ERR(dss_debugfs_dir);
  320. dss_debugfs_dir = NULL;
  321. return err;
  322. }
  323. debugfs_create_file("clk", S_IRUGO, dss_debugfs_dir,
  324. &dss_debug_dump_clocks, &dss_debug_fops);
  325. debugfs_create_file("dss", S_IRUGO, dss_debugfs_dir,
  326. &dss_dump_regs, &dss_debug_fops);
  327. debugfs_create_file("dispc", S_IRUGO, dss_debugfs_dir,
  328. &dispc_dump_regs, &dss_debug_fops);
  329. #ifdef CONFIG_OMAP2_DSS_RFBI
  330. debugfs_create_file("rfbi", S_IRUGO, dss_debugfs_dir,
  331. &rfbi_dump_regs, &dss_debug_fops);
  332. #endif
  333. #ifdef CONFIG_OMAP2_DSS_DSI
  334. debugfs_create_file("dsi", S_IRUGO, dss_debugfs_dir,
  335. &dsi_dump_regs, &dss_debug_fops);
  336. #endif
  337. #ifdef CONFIG_OMAP2_DSS_VENC
  338. debugfs_create_file("venc", S_IRUGO, dss_debugfs_dir,
  339. &venc_dump_regs, &dss_debug_fops);
  340. #endif
  341. return 0;
  342. }
  343. static void dss_uninitialize_debugfs(void)
  344. {
  345. if (dss_debugfs_dir)
  346. debugfs_remove_recursive(dss_debugfs_dir);
  347. }
  348. #endif /* CONFIG_DEBUG_FS && CONFIG_OMAP2_DSS_DEBUG_SUPPORT */
  349. /* PLATFORM DEVICE */
  350. static int omap_dss_probe(struct platform_device *pdev)
  351. {
  352. struct omap_dss_board_info *pdata = pdev->dev.platform_data;
  353. int skip_init = 0;
  354. int r;
  355. int i;
  356. core.pdev = pdev;
  357. dss_init_overlay_managers(pdev);
  358. dss_init_overlays(pdev);
  359. r = dss_get_clocks();
  360. if (r)
  361. goto fail0;
  362. dss_clk_enable_all_no_ctx();
  363. core.ctx_id = dss_get_ctx_id();
  364. DSSDBG("initial ctx id %u\n", core.ctx_id);
  365. #ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
  366. /* DISPC_CONTROL */
  367. if (omap_readl(0x48050440) & 1) /* LCD enabled? */
  368. skip_init = 1;
  369. #endif
  370. r = dss_init(skip_init);
  371. if (r) {
  372. DSSERR("Failed to initialize DSS\n");
  373. goto fail0;
  374. }
  375. #ifdef CONFIG_OMAP2_DSS_RFBI
  376. r = rfbi_init();
  377. if (r) {
  378. DSSERR("Failed to initialize rfbi\n");
  379. goto fail0;
  380. }
  381. #endif
  382. r = dpi_init();
  383. if (r) {
  384. DSSERR("Failed to initialize dpi\n");
  385. goto fail0;
  386. }
  387. r = dispc_init();
  388. if (r) {
  389. DSSERR("Failed to initialize dispc\n");
  390. goto fail0;
  391. }
  392. #ifdef CONFIG_OMAP2_DSS_VENC
  393. r = venc_init(pdev);
  394. if (r) {
  395. DSSERR("Failed to initialize venc\n");
  396. goto fail0;
  397. }
  398. #endif
  399. if (cpu_is_omap34xx()) {
  400. #ifdef CONFIG_OMAP2_DSS_SDI
  401. r = sdi_init(skip_init);
  402. if (r) {
  403. DSSERR("Failed to initialize SDI\n");
  404. goto fail0;
  405. }
  406. #endif
  407. #ifdef CONFIG_OMAP2_DSS_DSI
  408. r = dsi_init(pdev);
  409. if (r) {
  410. DSSERR("Failed to initialize DSI\n");
  411. goto fail0;
  412. }
  413. #endif
  414. }
  415. #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
  416. r = dss_initialize_debugfs();
  417. if (r)
  418. goto fail0;
  419. #endif
  420. for (i = 0; i < pdata->num_devices; ++i) {
  421. struct omap_dss_device *dssdev = pdata->devices[i];
  422. r = omap_dss_register_device(dssdev);
  423. if (r)
  424. DSSERR("device reg failed %d\n", i);
  425. if (def_disp_name && strcmp(def_disp_name, dssdev->name) == 0)
  426. pdata->default_device = dssdev;
  427. }
  428. dss_clk_disable_all();
  429. return 0;
  430. /* XXX fail correctly */
  431. fail0:
  432. return r;
  433. }
  434. static int omap_dss_remove(struct platform_device *pdev)
  435. {
  436. struct omap_dss_board_info *pdata = pdev->dev.platform_data;
  437. int i;
  438. int c;
  439. #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
  440. dss_uninitialize_debugfs();
  441. #endif
  442. #ifdef CONFIG_OMAP2_DSS_VENC
  443. venc_exit();
  444. #endif
  445. dispc_exit();
  446. dpi_exit();
  447. #ifdef CONFIG_OMAP2_DSS_RFBI
  448. rfbi_exit();
  449. #endif
  450. if (cpu_is_omap34xx()) {
  451. #ifdef CONFIG_OMAP2_DSS_DSI
  452. dsi_exit();
  453. #endif
  454. #ifdef CONFIG_OMAP2_DSS_SDI
  455. sdi_exit();
  456. #endif
  457. }
  458. dss_exit();
  459. /* these should be removed at some point */
  460. c = core.dss_ick->usecount;
  461. if (c > 0) {
  462. DSSERR("warning: dss_ick usecount %d, disabling\n", c);
  463. while (c-- > 0)
  464. clk_disable(core.dss_ick);
  465. }
  466. c = core.dss1_fck->usecount;
  467. if (c > 0) {
  468. DSSERR("warning: dss1_fck usecount %d, disabling\n", c);
  469. while (c-- > 0)
  470. clk_disable(core.dss1_fck);
  471. }
  472. c = core.dss2_fck->usecount;
  473. if (c > 0) {
  474. DSSERR("warning: dss2_fck usecount %d, disabling\n", c);
  475. while (c-- > 0)
  476. clk_disable(core.dss2_fck);
  477. }
  478. c = core.dss_54m_fck->usecount;
  479. if (c > 0) {
  480. DSSERR("warning: dss_54m_fck usecount %d, disabling\n", c);
  481. while (c-- > 0)
  482. clk_disable(core.dss_54m_fck);
  483. }
  484. if (core.dss_96m_fck) {
  485. c = core.dss_96m_fck->usecount;
  486. if (c > 0) {
  487. DSSERR("warning: dss_96m_fck usecount %d, disabling\n",
  488. c);
  489. while (c-- > 0)
  490. clk_disable(core.dss_96m_fck);
  491. }
  492. }
  493. dss_put_clocks();
  494. dss_uninit_overlays(pdev);
  495. dss_uninit_overlay_managers(pdev);
  496. for (i = 0; i < pdata->num_devices; ++i)
  497. omap_dss_unregister_device(pdata->devices[i]);
  498. return 0;
  499. }
  500. static void omap_dss_shutdown(struct platform_device *pdev)
  501. {
  502. DSSDBG("shutdown\n");
  503. dss_disable_all_devices();
  504. }
  505. static int omap_dss_suspend(struct platform_device *pdev, pm_message_t state)
  506. {
  507. DSSDBG("suspend %d\n", state.event);
  508. return dss_suspend_all_devices();
  509. }
  510. static int omap_dss_resume(struct platform_device *pdev)
  511. {
  512. DSSDBG("resume\n");
  513. return dss_resume_all_devices();
  514. }
  515. static struct platform_driver omap_dss_driver = {
  516. .probe = omap_dss_probe,
  517. .remove = omap_dss_remove,
  518. .shutdown = omap_dss_shutdown,
  519. .suspend = omap_dss_suspend,
  520. .resume = omap_dss_resume,
  521. .driver = {
  522. .name = "omapdss",
  523. .owner = THIS_MODULE,
  524. },
  525. };
  526. /* BUS */
  527. static int dss_bus_match(struct device *dev, struct device_driver *driver)
  528. {
  529. struct omap_dss_device *dssdev = to_dss_device(dev);
  530. DSSDBG("bus_match. dev %s/%s, drv %s\n",
  531. dev_name(dev), dssdev->driver_name, driver->name);
  532. return strcmp(dssdev->driver_name, driver->name) == 0;
  533. }
  534. static ssize_t device_name_show(struct device *dev,
  535. struct device_attribute *attr, char *buf)
  536. {
  537. struct omap_dss_device *dssdev = to_dss_device(dev);
  538. return snprintf(buf, PAGE_SIZE, "%s\n",
  539. dssdev->name ?
  540. dssdev->name : "");
  541. }
  542. static struct device_attribute default_dev_attrs[] = {
  543. __ATTR(name, S_IRUGO, device_name_show, NULL),
  544. __ATTR_NULL,
  545. };
  546. static ssize_t driver_name_show(struct device_driver *drv, char *buf)
  547. {
  548. struct omap_dss_driver *dssdrv = to_dss_driver(drv);
  549. return snprintf(buf, PAGE_SIZE, "%s\n",
  550. dssdrv->driver.name ?
  551. dssdrv->driver.name : "");
  552. }
  553. static struct driver_attribute default_drv_attrs[] = {
  554. __ATTR(name, S_IRUGO, driver_name_show, NULL),
  555. __ATTR_NULL,
  556. };
  557. static struct bus_type dss_bus_type = {
  558. .name = "omapdss",
  559. .match = dss_bus_match,
  560. .dev_attrs = default_dev_attrs,
  561. .drv_attrs = default_drv_attrs,
  562. };
  563. static void dss_bus_release(struct device *dev)
  564. {
  565. DSSDBG("bus_release\n");
  566. }
  567. static struct device dss_bus = {
  568. .release = dss_bus_release,
  569. };
  570. struct bus_type *dss_get_bus(void)
  571. {
  572. return &dss_bus_type;
  573. }
  574. /* DRIVER */
  575. static int dss_driver_probe(struct device *dev)
  576. {
  577. int r;
  578. struct omap_dss_driver *dssdrv = to_dss_driver(dev->driver);
  579. struct omap_dss_device *dssdev = to_dss_device(dev);
  580. struct omap_dss_board_info *pdata = core.pdev->dev.platform_data;
  581. bool force;
  582. DSSDBG("driver_probe: dev %s/%s, drv %s\n",
  583. dev_name(dev), dssdev->driver_name,
  584. dssdrv->driver.name);
  585. dss_init_device(core.pdev, dssdev);
  586. /* skip this if the device is behind a ctrl */
  587. if (!dssdev->panel.ctrl) {
  588. force = pdata->default_device == dssdev;
  589. dss_recheck_connections(dssdev, force);
  590. }
  591. r = dssdrv->probe(dssdev);
  592. if (r) {
  593. DSSERR("driver probe failed: %d\n", r);
  594. return r;
  595. }
  596. DSSDBG("probe done for device %s\n", dev_name(dev));
  597. dssdev->driver = dssdrv;
  598. return 0;
  599. }
  600. static int dss_driver_remove(struct device *dev)
  601. {
  602. struct omap_dss_driver *dssdrv = to_dss_driver(dev->driver);
  603. struct omap_dss_device *dssdev = to_dss_device(dev);
  604. DSSDBG("driver_remove: dev %s/%s\n", dev_name(dev),
  605. dssdev->driver_name);
  606. dssdrv->remove(dssdev);
  607. dss_uninit_device(core.pdev, dssdev);
  608. dssdev->driver = NULL;
  609. return 0;
  610. }
  611. int omap_dss_register_driver(struct omap_dss_driver *dssdriver)
  612. {
  613. dssdriver->driver.bus = &dss_bus_type;
  614. dssdriver->driver.probe = dss_driver_probe;
  615. dssdriver->driver.remove = dss_driver_remove;
  616. return driver_register(&dssdriver->driver);
  617. }
  618. EXPORT_SYMBOL(omap_dss_register_driver);
  619. void omap_dss_unregister_driver(struct omap_dss_driver *dssdriver)
  620. {
  621. driver_unregister(&dssdriver->driver);
  622. }
  623. EXPORT_SYMBOL(omap_dss_unregister_driver);
  624. /* DEVICE */
  625. static void reset_device(struct device *dev, int check)
  626. {
  627. u8 *dev_p = (u8 *)dev;
  628. u8 *dev_end = dev_p + sizeof(*dev);
  629. void *saved_pdata;
  630. saved_pdata = dev->platform_data;
  631. if (check) {
  632. /*
  633. * Check if there is any other setting than platform_data
  634. * in struct device; warn that these will be reset by our
  635. * init.
  636. */
  637. dev->platform_data = NULL;
  638. while (dev_p < dev_end) {
  639. if (*dev_p) {
  640. WARN("%s: struct device fields will be "
  641. "discarded\n",
  642. __func__);
  643. break;
  644. }
  645. dev_p++;
  646. }
  647. }
  648. memset(dev, 0, sizeof(*dev));
  649. dev->platform_data = saved_pdata;
  650. }
  651. static void omap_dss_dev_release(struct device *dev)
  652. {
  653. reset_device(dev, 0);
  654. }
  655. int omap_dss_register_device(struct omap_dss_device *dssdev)
  656. {
  657. static int dev_num;
  658. static int panel_num;
  659. int r;
  660. WARN_ON(!dssdev->driver_name);
  661. reset_device(&dssdev->dev, 1);
  662. dssdev->dev.bus = &dss_bus_type;
  663. dssdev->dev.parent = &dss_bus;
  664. dssdev->dev.release = omap_dss_dev_release;
  665. dev_set_name(&dssdev->dev, "display%d", dev_num++);
  666. r = device_register(&dssdev->dev);
  667. if (r)
  668. return r;
  669. if (dssdev->ctrl.panel) {
  670. struct omap_dss_device *panel = dssdev->ctrl.panel;
  671. panel->panel.ctrl = dssdev;
  672. reset_device(&panel->dev, 1);
  673. panel->dev.bus = &dss_bus_type;
  674. panel->dev.parent = &dssdev->dev;
  675. panel->dev.release = omap_dss_dev_release;
  676. dev_set_name(&panel->dev, "panel%d", panel_num++);
  677. r = device_register(&panel->dev);
  678. if (r)
  679. return r;
  680. }
  681. return 0;
  682. }
  683. void omap_dss_unregister_device(struct omap_dss_device *dssdev)
  684. {
  685. device_unregister(&dssdev->dev);
  686. if (dssdev->ctrl.panel) {
  687. struct omap_dss_device *panel = dssdev->ctrl.panel;
  688. device_unregister(&panel->dev);
  689. }
  690. }
  691. /* BUS */
  692. static int omap_dss_bus_register(void)
  693. {
  694. int r;
  695. r = bus_register(&dss_bus_type);
  696. if (r) {
  697. DSSERR("bus register failed\n");
  698. return r;
  699. }
  700. dev_set_name(&dss_bus, "omapdss");
  701. r = device_register(&dss_bus);
  702. if (r) {
  703. DSSERR("bus driver register failed\n");
  704. bus_unregister(&dss_bus_type);
  705. return r;
  706. }
  707. return 0;
  708. }
  709. /* INIT */
  710. #ifdef CONFIG_OMAP2_DSS_MODULE
  711. static void omap_dss_bus_unregister(void)
  712. {
  713. device_unregister(&dss_bus);
  714. bus_unregister(&dss_bus_type);
  715. }
  716. static int __init omap_dss_init(void)
  717. {
  718. int r;
  719. r = omap_dss_bus_register();
  720. if (r)
  721. return r;
  722. r = platform_driver_register(&omap_dss_driver);
  723. if (r) {
  724. omap_dss_bus_unregister();
  725. return r;
  726. }
  727. return 0;
  728. }
  729. static void __exit omap_dss_exit(void)
  730. {
  731. platform_driver_unregister(&omap_dss_driver);
  732. omap_dss_bus_unregister();
  733. }
  734. module_init(omap_dss_init);
  735. module_exit(omap_dss_exit);
  736. #else
  737. static int __init omap_dss_init(void)
  738. {
  739. return omap_dss_bus_register();
  740. }
  741. static int __init omap_dss_init2(void)
  742. {
  743. return platform_driver_register(&omap_dss_driver);
  744. }
  745. core_initcall(omap_dss_init);
  746. device_initcall(omap_dss_init2);
  747. #endif
  748. MODULE_AUTHOR("Tomi Valkeinen <tomi.valkeinen@nokia.com>");
  749. MODULE_DESCRIPTION("OMAP2/3 Display Subsystem");
  750. MODULE_LICENSE("GPL v2");