qla_init.c 144 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2011 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_gbl.h"
  9. #include <linux/delay.h>
  10. #include <linux/slab.h>
  11. #include <linux/vmalloc.h>
  12. #include "qla_devtbl.h"
  13. #ifdef CONFIG_SPARC
  14. #include <asm/prom.h>
  15. #endif
  16. /*
  17. * QLogic ISP2x00 Hardware Support Function Prototypes.
  18. */
  19. static int qla2x00_isp_firmware(scsi_qla_host_t *);
  20. static int qla2x00_setup_chip(scsi_qla_host_t *);
  21. static int qla2x00_init_rings(scsi_qla_host_t *);
  22. static int qla2x00_fw_ready(scsi_qla_host_t *);
  23. static int qla2x00_configure_hba(scsi_qla_host_t *);
  24. static int qla2x00_configure_loop(scsi_qla_host_t *);
  25. static int qla2x00_configure_local_loop(scsi_qla_host_t *);
  26. static int qla2x00_configure_fabric(scsi_qla_host_t *);
  27. static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
  28. static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
  29. uint16_t *);
  30. static int qla2x00_restart_isp(scsi_qla_host_t *);
  31. static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
  32. static int qla84xx_init_chip(scsi_qla_host_t *);
  33. static int qla25xx_init_queues(struct qla_hw_data *);
  34. /* SRB Extensions ---------------------------------------------------------- */
  35. void
  36. qla2x00_sp_timeout(unsigned long __data)
  37. {
  38. srb_t *sp = (srb_t *)__data;
  39. struct srb_iocb *iocb;
  40. fc_port_t *fcport = sp->fcport;
  41. struct qla_hw_data *ha = fcport->vha->hw;
  42. struct req_que *req;
  43. unsigned long flags;
  44. spin_lock_irqsave(&ha->hardware_lock, flags);
  45. req = ha->req_q_map[0];
  46. req->outstanding_cmds[sp->handle] = NULL;
  47. iocb = &sp->u.iocb_cmd;
  48. iocb->timeout(sp);
  49. sp->free(fcport->vha, sp);
  50. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  51. }
  52. void
  53. qla2x00_sp_free(void *data, void *ptr)
  54. {
  55. srb_t *sp = (srb_t *)ptr;
  56. struct srb_iocb *iocb = &sp->u.iocb_cmd;
  57. struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
  58. del_timer(&iocb->timer);
  59. mempool_free(sp, vha->hw->srb_mempool);
  60. QLA_VHA_MARK_NOT_BUSY(vha);
  61. }
  62. /* Asynchronous Login/Logout Routines -------------------------------------- */
  63. static inline unsigned long
  64. qla2x00_get_async_timeout(struct scsi_qla_host *vha)
  65. {
  66. unsigned long tmo;
  67. struct qla_hw_data *ha = vha->hw;
  68. /* Firmware should use switch negotiated r_a_tov for timeout. */
  69. tmo = ha->r_a_tov / 10 * 2;
  70. if (!IS_FWI2_CAPABLE(ha)) {
  71. /*
  72. * Except for earlier ISPs where the timeout is seeded from the
  73. * initialization control block.
  74. */
  75. tmo = ha->login_timeout;
  76. }
  77. return tmo;
  78. }
  79. static void
  80. qla2x00_async_iocb_timeout(void *data)
  81. {
  82. srb_t *sp = (srb_t *)data;
  83. fc_port_t *fcport = sp->fcport;
  84. ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
  85. "Async-%s timeout - hdl=%x portid=%02x%02x%02x.\n",
  86. sp->name, sp->handle, fcport->d_id.b.domain, fcport->d_id.b.area,
  87. fcport->d_id.b.al_pa);
  88. fcport->flags &= ~FCF_ASYNC_SENT;
  89. if (sp->type == SRB_LOGIN_CMD) {
  90. struct srb_iocb *lio = &sp->u.iocb_cmd;
  91. qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
  92. /* Retry as needed. */
  93. lio->u.logio.data[0] = MBS_COMMAND_ERROR;
  94. lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  95. QLA_LOGIO_LOGIN_RETRIED : 0;
  96. qla2x00_post_async_login_done_work(fcport->vha, fcport,
  97. lio->u.logio.data);
  98. }
  99. }
  100. static void
  101. qla2x00_async_login_sp_done(void *data, void *ptr, int res)
  102. {
  103. srb_t *sp = (srb_t *)ptr;
  104. struct srb_iocb *lio = &sp->u.iocb_cmd;
  105. struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
  106. if (!test_bit(UNLOADING, &vha->dpc_flags))
  107. qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
  108. lio->u.logio.data);
  109. sp->free(sp->fcport->vha, sp);
  110. }
  111. int
  112. qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
  113. uint16_t *data)
  114. {
  115. srb_t *sp;
  116. struct srb_iocb *lio;
  117. int rval;
  118. rval = QLA_FUNCTION_FAILED;
  119. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  120. if (!sp)
  121. goto done;
  122. sp->type = SRB_LOGIN_CMD;
  123. sp->name = "login";
  124. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
  125. lio = &sp->u.iocb_cmd;
  126. lio->timeout = qla2x00_async_iocb_timeout;
  127. sp->done = qla2x00_async_login_sp_done;
  128. lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
  129. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  130. lio->u.logio.flags |= SRB_LOGIN_RETRIED;
  131. rval = qla2x00_start_sp(sp);
  132. if (rval != QLA_SUCCESS)
  133. goto done_free_sp;
  134. ql_dbg(ql_dbg_disc, vha, 0x2072,
  135. "Async-login - hdl=%x, loopid=%x portid=%02x%02x%02x "
  136. "retries=%d.\n", sp->handle, fcport->loop_id,
  137. fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
  138. fcport->login_retry);
  139. return rval;
  140. done_free_sp:
  141. sp->free(fcport->vha, sp);
  142. done:
  143. return rval;
  144. }
  145. static void
  146. qla2x00_async_logout_sp_done(void *data, void *ptr, int res)
  147. {
  148. srb_t *sp = (srb_t *)ptr;
  149. struct srb_iocb *lio = &sp->u.iocb_cmd;
  150. struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
  151. if (!test_bit(UNLOADING, &vha->dpc_flags))
  152. qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
  153. lio->u.logio.data);
  154. sp->free(sp->fcport->vha, sp);
  155. }
  156. int
  157. qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
  158. {
  159. srb_t *sp;
  160. struct srb_iocb *lio;
  161. int rval;
  162. rval = QLA_FUNCTION_FAILED;
  163. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  164. if (!sp)
  165. goto done;
  166. sp->type = SRB_LOGOUT_CMD;
  167. sp->name = "logout";
  168. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
  169. lio = &sp->u.iocb_cmd;
  170. lio->timeout = qla2x00_async_iocb_timeout;
  171. sp->done = qla2x00_async_logout_sp_done;
  172. rval = qla2x00_start_sp(sp);
  173. if (rval != QLA_SUCCESS)
  174. goto done_free_sp;
  175. ql_dbg(ql_dbg_disc, vha, 0x2070,
  176. "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
  177. sp->handle, fcport->loop_id, fcport->d_id.b.domain,
  178. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  179. return rval;
  180. done_free_sp:
  181. sp->free(fcport->vha, sp);
  182. done:
  183. return rval;
  184. }
  185. static void
  186. qla2x00_async_adisc_sp_done(void *data, void *ptr, int res)
  187. {
  188. srb_t *sp = (srb_t *)ptr;
  189. struct srb_iocb *lio = &sp->u.iocb_cmd;
  190. struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
  191. if (!test_bit(UNLOADING, &vha->dpc_flags))
  192. qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
  193. lio->u.logio.data);
  194. sp->free(sp->fcport->vha, sp);
  195. }
  196. int
  197. qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
  198. uint16_t *data)
  199. {
  200. srb_t *sp;
  201. struct srb_iocb *lio;
  202. int rval;
  203. rval = QLA_FUNCTION_FAILED;
  204. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  205. if (!sp)
  206. goto done;
  207. sp->type = SRB_ADISC_CMD;
  208. sp->name = "adisc";
  209. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
  210. lio = &sp->u.iocb_cmd;
  211. lio->timeout = qla2x00_async_iocb_timeout;
  212. sp->done = qla2x00_async_adisc_sp_done;
  213. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  214. lio->u.logio.flags |= SRB_LOGIN_RETRIED;
  215. rval = qla2x00_start_sp(sp);
  216. if (rval != QLA_SUCCESS)
  217. goto done_free_sp;
  218. ql_dbg(ql_dbg_disc, vha, 0x206f,
  219. "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
  220. sp->handle, fcport->loop_id, fcport->d_id.b.domain,
  221. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  222. return rval;
  223. done_free_sp:
  224. sp->free(fcport->vha, sp);
  225. done:
  226. return rval;
  227. }
  228. static void
  229. qla2x00_async_tm_cmd_done(void *data, void *ptr, int res)
  230. {
  231. srb_t *sp = (srb_t *)ptr;
  232. struct srb_iocb *iocb = &sp->u.iocb_cmd;
  233. struct scsi_qla_host *vha = (scsi_qla_host_t *)data;
  234. uint32_t flags;
  235. uint16_t lun;
  236. int rval;
  237. if (!test_bit(UNLOADING, &vha->dpc_flags)) {
  238. flags = iocb->u.tmf.flags;
  239. lun = (uint16_t)iocb->u.tmf.lun;
  240. /* Issue Marker IOCB */
  241. rval = qla2x00_marker(vha, vha->hw->req_q_map[0],
  242. vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
  243. flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
  244. if ((rval != QLA_SUCCESS) || iocb->u.tmf.data) {
  245. ql_dbg(ql_dbg_taskm, vha, 0x8030,
  246. "TM IOCB failed (%x).\n", rval);
  247. }
  248. }
  249. sp->free(sp->fcport->vha, sp);
  250. }
  251. int
  252. qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t tm_flags, uint32_t lun,
  253. uint32_t tag)
  254. {
  255. struct scsi_qla_host *vha = fcport->vha;
  256. srb_t *sp;
  257. struct srb_iocb *tcf;
  258. int rval;
  259. rval = QLA_FUNCTION_FAILED;
  260. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  261. if (!sp)
  262. goto done;
  263. sp->type = SRB_TM_CMD;
  264. sp->name = "tmf";
  265. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
  266. tcf = &sp->u.iocb_cmd;
  267. tcf->u.tmf.flags = tm_flags;
  268. tcf->u.tmf.lun = lun;
  269. tcf->u.tmf.data = tag;
  270. tcf->timeout = qla2x00_async_iocb_timeout;
  271. sp->done = qla2x00_async_tm_cmd_done;
  272. rval = qla2x00_start_sp(sp);
  273. if (rval != QLA_SUCCESS)
  274. goto done_free_sp;
  275. ql_dbg(ql_dbg_taskm, vha, 0x802f,
  276. "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
  277. sp->handle, fcport->loop_id, fcport->d_id.b.domain,
  278. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  279. return rval;
  280. done_free_sp:
  281. sp->free(fcport->vha, sp);
  282. done:
  283. return rval;
  284. }
  285. void
  286. qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  287. uint16_t *data)
  288. {
  289. int rval;
  290. switch (data[0]) {
  291. case MBS_COMMAND_COMPLETE:
  292. /*
  293. * Driver must validate login state - If PRLI not complete,
  294. * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
  295. * requests.
  296. */
  297. rval = qla2x00_get_port_database(vha, fcport, 0);
  298. if (rval != QLA_SUCCESS) {
  299. qla2x00_post_async_logout_work(vha, fcport, NULL);
  300. qla2x00_post_async_login_work(vha, fcport, NULL);
  301. break;
  302. }
  303. if (fcport->flags & FCF_FCP2_DEVICE) {
  304. qla2x00_post_async_adisc_work(vha, fcport, data);
  305. break;
  306. }
  307. qla2x00_update_fcport(vha, fcport);
  308. break;
  309. case MBS_COMMAND_ERROR:
  310. fcport->flags &= ~FCF_ASYNC_SENT;
  311. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  312. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  313. else
  314. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  315. break;
  316. case MBS_PORT_ID_USED:
  317. fcport->loop_id = data[1];
  318. qla2x00_post_async_logout_work(vha, fcport, NULL);
  319. qla2x00_post_async_login_work(vha, fcport, NULL);
  320. break;
  321. case MBS_LOOP_ID_USED:
  322. fcport->loop_id++;
  323. rval = qla2x00_find_new_loop_id(vha, fcport);
  324. if (rval != QLA_SUCCESS) {
  325. fcport->flags &= ~FCF_ASYNC_SENT;
  326. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  327. break;
  328. }
  329. qla2x00_post_async_login_work(vha, fcport, NULL);
  330. break;
  331. }
  332. return;
  333. }
  334. void
  335. qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  336. uint16_t *data)
  337. {
  338. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  339. return;
  340. }
  341. void
  342. qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  343. uint16_t *data)
  344. {
  345. if (data[0] == MBS_COMMAND_COMPLETE) {
  346. qla2x00_update_fcport(vha, fcport);
  347. return;
  348. }
  349. /* Retry login. */
  350. fcport->flags &= ~FCF_ASYNC_SENT;
  351. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  352. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  353. else
  354. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  355. return;
  356. }
  357. /****************************************************************************/
  358. /* QLogic ISP2x00 Hardware Support Functions. */
  359. /****************************************************************************/
  360. /*
  361. * qla2x00_initialize_adapter
  362. * Initialize board.
  363. *
  364. * Input:
  365. * ha = adapter block pointer.
  366. *
  367. * Returns:
  368. * 0 = success
  369. */
  370. int
  371. qla2x00_initialize_adapter(scsi_qla_host_t *vha)
  372. {
  373. int rval;
  374. struct qla_hw_data *ha = vha->hw;
  375. struct req_que *req = ha->req_q_map[0];
  376. /* Clear adapter flags. */
  377. vha->flags.online = 0;
  378. ha->flags.chip_reset_done = 0;
  379. vha->flags.reset_active = 0;
  380. ha->flags.pci_channel_io_perm_failure = 0;
  381. ha->flags.eeh_busy = 0;
  382. ha->flags.thermal_supported = 1;
  383. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  384. atomic_set(&vha->loop_state, LOOP_DOWN);
  385. vha->device_flags = DFLG_NO_CABLE;
  386. vha->dpc_flags = 0;
  387. vha->flags.management_server_logged_in = 0;
  388. vha->marker_needed = 0;
  389. ha->isp_abort_cnt = 0;
  390. ha->beacon_blink_led = 0;
  391. set_bit(0, ha->req_qid_map);
  392. set_bit(0, ha->rsp_qid_map);
  393. ql_dbg(ql_dbg_init, vha, 0x0040,
  394. "Configuring PCI space...\n");
  395. rval = ha->isp_ops->pci_config(vha);
  396. if (rval) {
  397. ql_log(ql_log_warn, vha, 0x0044,
  398. "Unable to configure PCI space.\n");
  399. return (rval);
  400. }
  401. ha->isp_ops->reset_chip(vha);
  402. rval = qla2xxx_get_flash_info(vha);
  403. if (rval) {
  404. ql_log(ql_log_fatal, vha, 0x004f,
  405. "Unable to validate FLASH data.\n");
  406. return (rval);
  407. }
  408. ha->isp_ops->get_flash_version(vha, req->ring);
  409. ql_dbg(ql_dbg_init, vha, 0x0061,
  410. "Configure NVRAM parameters...\n");
  411. ha->isp_ops->nvram_config(vha);
  412. if (ha->flags.disable_serdes) {
  413. /* Mask HBA via NVRAM settings? */
  414. ql_log(ql_log_info, vha, 0x0077,
  415. "Masking HBA WWPN "
  416. "%02x%02x%02x%02x%02x%02x%02x%02x (via NVRAM).\n",
  417. vha->port_name[0], vha->port_name[1],
  418. vha->port_name[2], vha->port_name[3],
  419. vha->port_name[4], vha->port_name[5],
  420. vha->port_name[6], vha->port_name[7]);
  421. return QLA_FUNCTION_FAILED;
  422. }
  423. ql_dbg(ql_dbg_init, vha, 0x0078,
  424. "Verifying loaded RISC code...\n");
  425. if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
  426. rval = ha->isp_ops->chip_diag(vha);
  427. if (rval)
  428. return (rval);
  429. rval = qla2x00_setup_chip(vha);
  430. if (rval)
  431. return (rval);
  432. }
  433. if (IS_QLA84XX(ha)) {
  434. ha->cs84xx = qla84xx_get_chip(vha);
  435. if (!ha->cs84xx) {
  436. ql_log(ql_log_warn, vha, 0x00d0,
  437. "Unable to configure ISP84XX.\n");
  438. return QLA_FUNCTION_FAILED;
  439. }
  440. }
  441. rval = qla2x00_init_rings(vha);
  442. ha->flags.chip_reset_done = 1;
  443. if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
  444. /* Issue verify 84xx FW IOCB to complete 84xx initialization */
  445. rval = qla84xx_init_chip(vha);
  446. if (rval != QLA_SUCCESS) {
  447. ql_log(ql_log_warn, vha, 0x00d4,
  448. "Unable to initialize ISP84XX.\n");
  449. qla84xx_put_chip(vha);
  450. }
  451. }
  452. if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
  453. qla24xx_read_fcp_prio_cfg(vha);
  454. return (rval);
  455. }
  456. /**
  457. * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
  458. * @ha: HA context
  459. *
  460. * Returns 0 on success.
  461. */
  462. int
  463. qla2100_pci_config(scsi_qla_host_t *vha)
  464. {
  465. uint16_t w;
  466. unsigned long flags;
  467. struct qla_hw_data *ha = vha->hw;
  468. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  469. pci_set_master(ha->pdev);
  470. pci_try_set_mwi(ha->pdev);
  471. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  472. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  473. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  474. pci_disable_rom(ha->pdev);
  475. /* Get PCI bus information. */
  476. spin_lock_irqsave(&ha->hardware_lock, flags);
  477. ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
  478. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  479. return QLA_SUCCESS;
  480. }
  481. /**
  482. * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
  483. * @ha: HA context
  484. *
  485. * Returns 0 on success.
  486. */
  487. int
  488. qla2300_pci_config(scsi_qla_host_t *vha)
  489. {
  490. uint16_t w;
  491. unsigned long flags = 0;
  492. uint32_t cnt;
  493. struct qla_hw_data *ha = vha->hw;
  494. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  495. pci_set_master(ha->pdev);
  496. pci_try_set_mwi(ha->pdev);
  497. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  498. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  499. if (IS_QLA2322(ha) || IS_QLA6322(ha))
  500. w &= ~PCI_COMMAND_INTX_DISABLE;
  501. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  502. /*
  503. * If this is a 2300 card and not 2312, reset the
  504. * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
  505. * the 2310 also reports itself as a 2300 so we need to get the
  506. * fb revision level -- a 6 indicates it really is a 2300 and
  507. * not a 2310.
  508. */
  509. if (IS_QLA2300(ha)) {
  510. spin_lock_irqsave(&ha->hardware_lock, flags);
  511. /* Pause RISC. */
  512. WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
  513. for (cnt = 0; cnt < 30000; cnt++) {
  514. if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
  515. break;
  516. udelay(10);
  517. }
  518. /* Select FPM registers. */
  519. WRT_REG_WORD(&reg->ctrl_status, 0x20);
  520. RD_REG_WORD(&reg->ctrl_status);
  521. /* Get the fb rev level */
  522. ha->fb_rev = RD_FB_CMD_REG(ha, reg);
  523. if (ha->fb_rev == FPM_2300)
  524. pci_clear_mwi(ha->pdev);
  525. /* Deselect FPM registers. */
  526. WRT_REG_WORD(&reg->ctrl_status, 0x0);
  527. RD_REG_WORD(&reg->ctrl_status);
  528. /* Release RISC module. */
  529. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  530. for (cnt = 0; cnt < 30000; cnt++) {
  531. if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
  532. break;
  533. udelay(10);
  534. }
  535. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  536. }
  537. pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
  538. pci_disable_rom(ha->pdev);
  539. /* Get PCI bus information. */
  540. spin_lock_irqsave(&ha->hardware_lock, flags);
  541. ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
  542. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  543. return QLA_SUCCESS;
  544. }
  545. /**
  546. * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
  547. * @ha: HA context
  548. *
  549. * Returns 0 on success.
  550. */
  551. int
  552. qla24xx_pci_config(scsi_qla_host_t *vha)
  553. {
  554. uint16_t w;
  555. unsigned long flags = 0;
  556. struct qla_hw_data *ha = vha->hw;
  557. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  558. pci_set_master(ha->pdev);
  559. pci_try_set_mwi(ha->pdev);
  560. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  561. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  562. w &= ~PCI_COMMAND_INTX_DISABLE;
  563. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  564. pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
  565. /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
  566. if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
  567. pcix_set_mmrbc(ha->pdev, 2048);
  568. /* PCIe -- adjust Maximum Read Request Size (2048). */
  569. if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP))
  570. pcie_set_readrq(ha->pdev, 2048);
  571. pci_disable_rom(ha->pdev);
  572. ha->chip_revision = ha->pdev->revision;
  573. /* Get PCI bus information. */
  574. spin_lock_irqsave(&ha->hardware_lock, flags);
  575. ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
  576. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  577. return QLA_SUCCESS;
  578. }
  579. /**
  580. * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
  581. * @ha: HA context
  582. *
  583. * Returns 0 on success.
  584. */
  585. int
  586. qla25xx_pci_config(scsi_qla_host_t *vha)
  587. {
  588. uint16_t w;
  589. struct qla_hw_data *ha = vha->hw;
  590. pci_set_master(ha->pdev);
  591. pci_try_set_mwi(ha->pdev);
  592. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  593. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  594. w &= ~PCI_COMMAND_INTX_DISABLE;
  595. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  596. /* PCIe -- adjust Maximum Read Request Size (2048). */
  597. if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP))
  598. pcie_set_readrq(ha->pdev, 2048);
  599. pci_disable_rom(ha->pdev);
  600. ha->chip_revision = ha->pdev->revision;
  601. return QLA_SUCCESS;
  602. }
  603. /**
  604. * qla2x00_isp_firmware() - Choose firmware image.
  605. * @ha: HA context
  606. *
  607. * Returns 0 on success.
  608. */
  609. static int
  610. qla2x00_isp_firmware(scsi_qla_host_t *vha)
  611. {
  612. int rval;
  613. uint16_t loop_id, topo, sw_cap;
  614. uint8_t domain, area, al_pa;
  615. struct qla_hw_data *ha = vha->hw;
  616. /* Assume loading risc code */
  617. rval = QLA_FUNCTION_FAILED;
  618. if (ha->flags.disable_risc_code_load) {
  619. ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
  620. /* Verify checksum of loaded RISC code. */
  621. rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
  622. if (rval == QLA_SUCCESS) {
  623. /* And, verify we are not in ROM code. */
  624. rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
  625. &area, &domain, &topo, &sw_cap);
  626. }
  627. }
  628. if (rval)
  629. ql_dbg(ql_dbg_init, vha, 0x007a,
  630. "**** Load RISC code ****.\n");
  631. return (rval);
  632. }
  633. /**
  634. * qla2x00_reset_chip() - Reset ISP chip.
  635. * @ha: HA context
  636. *
  637. * Returns 0 on success.
  638. */
  639. void
  640. qla2x00_reset_chip(scsi_qla_host_t *vha)
  641. {
  642. unsigned long flags = 0;
  643. struct qla_hw_data *ha = vha->hw;
  644. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  645. uint32_t cnt;
  646. uint16_t cmd;
  647. if (unlikely(pci_channel_offline(ha->pdev)))
  648. return;
  649. ha->isp_ops->disable_intrs(ha);
  650. spin_lock_irqsave(&ha->hardware_lock, flags);
  651. /* Turn off master enable */
  652. cmd = 0;
  653. pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
  654. cmd &= ~PCI_COMMAND_MASTER;
  655. pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
  656. if (!IS_QLA2100(ha)) {
  657. /* Pause RISC. */
  658. WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
  659. if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
  660. for (cnt = 0; cnt < 30000; cnt++) {
  661. if ((RD_REG_WORD(&reg->hccr) &
  662. HCCR_RISC_PAUSE) != 0)
  663. break;
  664. udelay(100);
  665. }
  666. } else {
  667. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  668. udelay(10);
  669. }
  670. /* Select FPM registers. */
  671. WRT_REG_WORD(&reg->ctrl_status, 0x20);
  672. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  673. /* FPM Soft Reset. */
  674. WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
  675. RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
  676. /* Toggle Fpm Reset. */
  677. if (!IS_QLA2200(ha)) {
  678. WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
  679. RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
  680. }
  681. /* Select frame buffer registers. */
  682. WRT_REG_WORD(&reg->ctrl_status, 0x10);
  683. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  684. /* Reset frame buffer FIFOs. */
  685. if (IS_QLA2200(ha)) {
  686. WRT_FB_CMD_REG(ha, reg, 0xa000);
  687. RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
  688. } else {
  689. WRT_FB_CMD_REG(ha, reg, 0x00fc);
  690. /* Read back fb_cmd until zero or 3 seconds max */
  691. for (cnt = 0; cnt < 3000; cnt++) {
  692. if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
  693. break;
  694. udelay(100);
  695. }
  696. }
  697. /* Select RISC module registers. */
  698. WRT_REG_WORD(&reg->ctrl_status, 0);
  699. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  700. /* Reset RISC processor. */
  701. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  702. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  703. /* Release RISC processor. */
  704. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  705. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  706. }
  707. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  708. WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
  709. /* Reset ISP chip. */
  710. WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
  711. /* Wait for RISC to recover from reset. */
  712. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  713. /*
  714. * It is necessary to for a delay here since the card doesn't
  715. * respond to PCI reads during a reset. On some architectures
  716. * this will result in an MCA.
  717. */
  718. udelay(20);
  719. for (cnt = 30000; cnt; cnt--) {
  720. if ((RD_REG_WORD(&reg->ctrl_status) &
  721. CSR_ISP_SOFT_RESET) == 0)
  722. break;
  723. udelay(100);
  724. }
  725. } else
  726. udelay(10);
  727. /* Reset RISC processor. */
  728. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  729. WRT_REG_WORD(&reg->semaphore, 0);
  730. /* Release RISC processor. */
  731. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  732. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  733. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  734. for (cnt = 0; cnt < 30000; cnt++) {
  735. if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
  736. break;
  737. udelay(100);
  738. }
  739. } else
  740. udelay(100);
  741. /* Turn on master enable */
  742. cmd |= PCI_COMMAND_MASTER;
  743. pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
  744. /* Disable RISC pause on FPM parity error. */
  745. if (!IS_QLA2100(ha)) {
  746. WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
  747. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  748. }
  749. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  750. }
  751. /**
  752. * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
  753. *
  754. * Returns 0 on success.
  755. */
  756. int
  757. qla81xx_reset_mpi(scsi_qla_host_t *vha)
  758. {
  759. uint16_t mb[4] = {0x1010, 0, 1, 0};
  760. if (!IS_QLA81XX(vha->hw))
  761. return QLA_SUCCESS;
  762. return qla81xx_write_mpi_register(vha, mb);
  763. }
  764. /**
  765. * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
  766. * @ha: HA context
  767. *
  768. * Returns 0 on success.
  769. */
  770. static inline void
  771. qla24xx_reset_risc(scsi_qla_host_t *vha)
  772. {
  773. unsigned long flags = 0;
  774. struct qla_hw_data *ha = vha->hw;
  775. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  776. uint32_t cnt, d2;
  777. uint16_t wd;
  778. static int abts_cnt; /* ISP abort retry counts */
  779. spin_lock_irqsave(&ha->hardware_lock, flags);
  780. /* Reset RISC. */
  781. WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
  782. for (cnt = 0; cnt < 30000; cnt++) {
  783. if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
  784. break;
  785. udelay(10);
  786. }
  787. WRT_REG_DWORD(&reg->ctrl_status,
  788. CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
  789. pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
  790. udelay(100);
  791. /* Wait for firmware to complete NVRAM accesses. */
  792. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  793. for (cnt = 10000 ; cnt && d2; cnt--) {
  794. udelay(5);
  795. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  796. barrier();
  797. }
  798. /* Wait for soft-reset to complete. */
  799. d2 = RD_REG_DWORD(&reg->ctrl_status);
  800. for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
  801. udelay(5);
  802. d2 = RD_REG_DWORD(&reg->ctrl_status);
  803. barrier();
  804. }
  805. /* If required, do an MPI FW reset now */
  806. if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
  807. if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
  808. if (++abts_cnt < 5) {
  809. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  810. set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
  811. } else {
  812. /*
  813. * We exhausted the ISP abort retries. We have to
  814. * set the board offline.
  815. */
  816. abts_cnt = 0;
  817. vha->flags.online = 0;
  818. }
  819. }
  820. }
  821. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
  822. RD_REG_DWORD(&reg->hccr);
  823. WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
  824. RD_REG_DWORD(&reg->hccr);
  825. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
  826. RD_REG_DWORD(&reg->hccr);
  827. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  828. for (cnt = 6000000 ; cnt && d2; cnt--) {
  829. udelay(5);
  830. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  831. barrier();
  832. }
  833. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  834. if (IS_NOPOLLING_TYPE(ha))
  835. ha->isp_ops->enable_intrs(ha);
  836. }
  837. /**
  838. * qla24xx_reset_chip() - Reset ISP24xx chip.
  839. * @ha: HA context
  840. *
  841. * Returns 0 on success.
  842. */
  843. void
  844. qla24xx_reset_chip(scsi_qla_host_t *vha)
  845. {
  846. struct qla_hw_data *ha = vha->hw;
  847. if (pci_channel_offline(ha->pdev) &&
  848. ha->flags.pci_channel_io_perm_failure) {
  849. return;
  850. }
  851. ha->isp_ops->disable_intrs(ha);
  852. /* Perform RISC reset. */
  853. qla24xx_reset_risc(vha);
  854. }
  855. /**
  856. * qla2x00_chip_diag() - Test chip for proper operation.
  857. * @ha: HA context
  858. *
  859. * Returns 0 on success.
  860. */
  861. int
  862. qla2x00_chip_diag(scsi_qla_host_t *vha)
  863. {
  864. int rval;
  865. struct qla_hw_data *ha = vha->hw;
  866. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  867. unsigned long flags = 0;
  868. uint16_t data;
  869. uint32_t cnt;
  870. uint16_t mb[5];
  871. struct req_que *req = ha->req_q_map[0];
  872. /* Assume a failed state */
  873. rval = QLA_FUNCTION_FAILED;
  874. ql_dbg(ql_dbg_init, vha, 0x007b,
  875. "Testing device at %lx.\n", (u_long)&reg->flash_address);
  876. spin_lock_irqsave(&ha->hardware_lock, flags);
  877. /* Reset ISP chip. */
  878. WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
  879. /*
  880. * We need to have a delay here since the card will not respond while
  881. * in reset causing an MCA on some architectures.
  882. */
  883. udelay(20);
  884. data = qla2x00_debounce_register(&reg->ctrl_status);
  885. for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
  886. udelay(5);
  887. data = RD_REG_WORD(&reg->ctrl_status);
  888. barrier();
  889. }
  890. if (!cnt)
  891. goto chip_diag_failed;
  892. ql_dbg(ql_dbg_init, vha, 0x007c,
  893. "Reset register cleared by chip reset.\n");
  894. /* Reset RISC processor. */
  895. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  896. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  897. /* Workaround for QLA2312 PCI parity error */
  898. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  899. data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
  900. for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
  901. udelay(5);
  902. data = RD_MAILBOX_REG(ha, reg, 0);
  903. barrier();
  904. }
  905. } else
  906. udelay(10);
  907. if (!cnt)
  908. goto chip_diag_failed;
  909. /* Check product ID of chip */
  910. ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
  911. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  912. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  913. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  914. mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
  915. if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
  916. mb[3] != PROD_ID_3) {
  917. ql_log(ql_log_warn, vha, 0x0062,
  918. "Wrong product ID = 0x%x,0x%x,0x%x.\n",
  919. mb[1], mb[2], mb[3]);
  920. goto chip_diag_failed;
  921. }
  922. ha->product_id[0] = mb[1];
  923. ha->product_id[1] = mb[2];
  924. ha->product_id[2] = mb[3];
  925. ha->product_id[3] = mb[4];
  926. /* Adjust fw RISC transfer size */
  927. if (req->length > 1024)
  928. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
  929. else
  930. ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
  931. req->length;
  932. if (IS_QLA2200(ha) &&
  933. RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
  934. /* Limit firmware transfer size with a 2200A */
  935. ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
  936. ha->device_type |= DT_ISP2200A;
  937. ha->fw_transfer_size = 128;
  938. }
  939. /* Wrap Incoming Mailboxes Test. */
  940. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  941. ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
  942. rval = qla2x00_mbx_reg_test(vha);
  943. if (rval)
  944. ql_log(ql_log_warn, vha, 0x0080,
  945. "Failed mailbox send register test.\n");
  946. else
  947. /* Flag a successful rval */
  948. rval = QLA_SUCCESS;
  949. spin_lock_irqsave(&ha->hardware_lock, flags);
  950. chip_diag_failed:
  951. if (rval)
  952. ql_log(ql_log_info, vha, 0x0081,
  953. "Chip diagnostics **** FAILED ****.\n");
  954. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  955. return (rval);
  956. }
  957. /**
  958. * qla24xx_chip_diag() - Test ISP24xx for proper operation.
  959. * @ha: HA context
  960. *
  961. * Returns 0 on success.
  962. */
  963. int
  964. qla24xx_chip_diag(scsi_qla_host_t *vha)
  965. {
  966. int rval;
  967. struct qla_hw_data *ha = vha->hw;
  968. struct req_que *req = ha->req_q_map[0];
  969. if (IS_QLA82XX(ha))
  970. return QLA_SUCCESS;
  971. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
  972. rval = qla2x00_mbx_reg_test(vha);
  973. if (rval) {
  974. ql_log(ql_log_warn, vha, 0x0082,
  975. "Failed mailbox send register test.\n");
  976. } else {
  977. /* Flag a successful rval */
  978. rval = QLA_SUCCESS;
  979. }
  980. return rval;
  981. }
  982. void
  983. qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
  984. {
  985. int rval;
  986. uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
  987. eft_size, fce_size, mq_size;
  988. dma_addr_t tc_dma;
  989. void *tc;
  990. struct qla_hw_data *ha = vha->hw;
  991. struct req_que *req = ha->req_q_map[0];
  992. struct rsp_que *rsp = ha->rsp_q_map[0];
  993. if (ha->fw_dump) {
  994. ql_dbg(ql_dbg_init, vha, 0x00bd,
  995. "Firmware dump already allocated.\n");
  996. return;
  997. }
  998. ha->fw_dumped = 0;
  999. fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
  1000. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  1001. fixed_size = sizeof(struct qla2100_fw_dump);
  1002. } else if (IS_QLA23XX(ha)) {
  1003. fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
  1004. mem_size = (ha->fw_memory_size - 0x11000 + 1) *
  1005. sizeof(uint16_t);
  1006. } else if (IS_FWI2_CAPABLE(ha)) {
  1007. if (IS_QLA83XX(ha))
  1008. fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
  1009. else if (IS_QLA81XX(ha))
  1010. fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
  1011. else if (IS_QLA25XX(ha))
  1012. fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
  1013. else
  1014. fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
  1015. mem_size = (ha->fw_memory_size - 0x100000 + 1) *
  1016. sizeof(uint32_t);
  1017. if (ha->mqenable) {
  1018. if (!IS_QLA83XX(ha))
  1019. mq_size = sizeof(struct qla2xxx_mq_chain);
  1020. /*
  1021. * Allocate maximum buffer size for all queues.
  1022. * Resizing must be done at end-of-dump processing.
  1023. */
  1024. mq_size += ha->max_req_queues *
  1025. (req->length * sizeof(request_t));
  1026. mq_size += ha->max_rsp_queues *
  1027. (rsp->length * sizeof(response_t));
  1028. }
  1029. /* Allocate memory for Fibre Channel Event Buffer. */
  1030. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
  1031. goto try_eft;
  1032. tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
  1033. GFP_KERNEL);
  1034. if (!tc) {
  1035. ql_log(ql_log_warn, vha, 0x00be,
  1036. "Unable to allocate (%d KB) for FCE.\n",
  1037. FCE_SIZE / 1024);
  1038. goto try_eft;
  1039. }
  1040. memset(tc, 0, FCE_SIZE);
  1041. rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
  1042. ha->fce_mb, &ha->fce_bufs);
  1043. if (rval) {
  1044. ql_log(ql_log_warn, vha, 0x00bf,
  1045. "Unable to initialize FCE (%d).\n", rval);
  1046. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
  1047. tc_dma);
  1048. ha->flags.fce_enabled = 0;
  1049. goto try_eft;
  1050. }
  1051. ql_dbg(ql_dbg_init, vha, 0x00c0,
  1052. "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
  1053. fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
  1054. ha->flags.fce_enabled = 1;
  1055. ha->fce_dma = tc_dma;
  1056. ha->fce = tc;
  1057. try_eft:
  1058. /* Allocate memory for Extended Trace Buffer. */
  1059. tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
  1060. GFP_KERNEL);
  1061. if (!tc) {
  1062. ql_log(ql_log_warn, vha, 0x00c1,
  1063. "Unable to allocate (%d KB) for EFT.\n",
  1064. EFT_SIZE / 1024);
  1065. goto cont_alloc;
  1066. }
  1067. memset(tc, 0, EFT_SIZE);
  1068. rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
  1069. if (rval) {
  1070. ql_log(ql_log_warn, vha, 0x00c2,
  1071. "Unable to initialize EFT (%d).\n", rval);
  1072. dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
  1073. tc_dma);
  1074. goto cont_alloc;
  1075. }
  1076. ql_dbg(ql_dbg_init, vha, 0x00c3,
  1077. "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
  1078. eft_size = EFT_SIZE;
  1079. ha->eft_dma = tc_dma;
  1080. ha->eft = tc;
  1081. }
  1082. cont_alloc:
  1083. req_q_size = req->length * sizeof(request_t);
  1084. rsp_q_size = rsp->length * sizeof(response_t);
  1085. dump_size = offsetof(struct qla2xxx_fw_dump, isp);
  1086. dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
  1087. ha->chain_offset = dump_size;
  1088. dump_size += mq_size + fce_size;
  1089. ha->fw_dump = vmalloc(dump_size);
  1090. if (!ha->fw_dump) {
  1091. ql_log(ql_log_warn, vha, 0x00c4,
  1092. "Unable to allocate (%d KB) for firmware dump.\n",
  1093. dump_size / 1024);
  1094. if (ha->fce) {
  1095. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
  1096. ha->fce_dma);
  1097. ha->fce = NULL;
  1098. ha->fce_dma = 0;
  1099. }
  1100. if (ha->eft) {
  1101. dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
  1102. ha->eft_dma);
  1103. ha->eft = NULL;
  1104. ha->eft_dma = 0;
  1105. }
  1106. return;
  1107. }
  1108. ql_dbg(ql_dbg_init, vha, 0x00c5,
  1109. "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
  1110. ha->fw_dump_len = dump_size;
  1111. ha->fw_dump->signature[0] = 'Q';
  1112. ha->fw_dump->signature[1] = 'L';
  1113. ha->fw_dump->signature[2] = 'G';
  1114. ha->fw_dump->signature[3] = 'C';
  1115. ha->fw_dump->version = __constant_htonl(1);
  1116. ha->fw_dump->fixed_size = htonl(fixed_size);
  1117. ha->fw_dump->mem_size = htonl(mem_size);
  1118. ha->fw_dump->req_q_size = htonl(req_q_size);
  1119. ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
  1120. ha->fw_dump->eft_size = htonl(eft_size);
  1121. ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
  1122. ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
  1123. ha->fw_dump->header_size =
  1124. htonl(offsetof(struct qla2xxx_fw_dump, isp));
  1125. }
  1126. static int
  1127. qla81xx_mpi_sync(scsi_qla_host_t *vha)
  1128. {
  1129. #define MPS_MASK 0xe0
  1130. int rval;
  1131. uint16_t dc;
  1132. uint32_t dw;
  1133. if (!IS_QLA81XX(vha->hw))
  1134. return QLA_SUCCESS;
  1135. rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
  1136. if (rval != QLA_SUCCESS) {
  1137. ql_log(ql_log_warn, vha, 0x0105,
  1138. "Unable to acquire semaphore.\n");
  1139. goto done;
  1140. }
  1141. pci_read_config_word(vha->hw->pdev, 0x54, &dc);
  1142. rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
  1143. if (rval != QLA_SUCCESS) {
  1144. ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
  1145. goto done_release;
  1146. }
  1147. dc &= MPS_MASK;
  1148. if (dc == (dw & MPS_MASK))
  1149. goto done_release;
  1150. dw &= ~MPS_MASK;
  1151. dw |= dc;
  1152. rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
  1153. if (rval != QLA_SUCCESS) {
  1154. ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
  1155. }
  1156. done_release:
  1157. rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
  1158. if (rval != QLA_SUCCESS) {
  1159. ql_log(ql_log_warn, vha, 0x006d,
  1160. "Unable to release semaphore.\n");
  1161. }
  1162. done:
  1163. return rval;
  1164. }
  1165. /**
  1166. * qla2x00_setup_chip() - Load and start RISC firmware.
  1167. * @ha: HA context
  1168. *
  1169. * Returns 0 on success.
  1170. */
  1171. static int
  1172. qla2x00_setup_chip(scsi_qla_host_t *vha)
  1173. {
  1174. int rval;
  1175. uint32_t srisc_address = 0;
  1176. struct qla_hw_data *ha = vha->hw;
  1177. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1178. unsigned long flags;
  1179. uint16_t fw_major_version;
  1180. if (IS_QLA82XX(ha)) {
  1181. rval = ha->isp_ops->load_risc(vha, &srisc_address);
  1182. if (rval == QLA_SUCCESS) {
  1183. qla2x00_stop_firmware(vha);
  1184. goto enable_82xx_npiv;
  1185. } else
  1186. goto failed;
  1187. }
  1188. if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
  1189. /* Disable SRAM, Instruction RAM and GP RAM parity. */
  1190. spin_lock_irqsave(&ha->hardware_lock, flags);
  1191. WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
  1192. RD_REG_WORD(&reg->hccr);
  1193. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1194. }
  1195. qla81xx_mpi_sync(vha);
  1196. /* Load firmware sequences */
  1197. rval = ha->isp_ops->load_risc(vha, &srisc_address);
  1198. if (rval == QLA_SUCCESS) {
  1199. ql_dbg(ql_dbg_init, vha, 0x00c9,
  1200. "Verifying Checksum of loaded RISC code.\n");
  1201. rval = qla2x00_verify_checksum(vha, srisc_address);
  1202. if (rval == QLA_SUCCESS) {
  1203. /* Start firmware execution. */
  1204. ql_dbg(ql_dbg_init, vha, 0x00ca,
  1205. "Starting firmware.\n");
  1206. rval = qla2x00_execute_fw(vha, srisc_address);
  1207. /* Retrieve firmware information. */
  1208. if (rval == QLA_SUCCESS) {
  1209. enable_82xx_npiv:
  1210. fw_major_version = ha->fw_major_version;
  1211. if (IS_QLA82XX(ha))
  1212. qla82xx_check_md_needed(vha);
  1213. else
  1214. rval = qla2x00_get_fw_version(vha);
  1215. if (rval != QLA_SUCCESS)
  1216. goto failed;
  1217. ha->flags.npiv_supported = 0;
  1218. if (IS_QLA2XXX_MIDTYPE(ha) &&
  1219. (ha->fw_attributes & BIT_2)) {
  1220. ha->flags.npiv_supported = 1;
  1221. if ((!ha->max_npiv_vports) ||
  1222. ((ha->max_npiv_vports + 1) %
  1223. MIN_MULTI_ID_FABRIC))
  1224. ha->max_npiv_vports =
  1225. MIN_MULTI_ID_FABRIC - 1;
  1226. }
  1227. qla2x00_get_resource_cnts(vha, NULL,
  1228. &ha->fw_xcb_count, NULL, NULL,
  1229. &ha->max_npiv_vports, NULL);
  1230. if (!fw_major_version && ql2xallocfwdump
  1231. && !IS_QLA82XX(ha))
  1232. qla2x00_alloc_fw_dump(vha);
  1233. }
  1234. } else {
  1235. ql_log(ql_log_fatal, vha, 0x00cd,
  1236. "ISP Firmware failed checksum.\n");
  1237. goto failed;
  1238. }
  1239. }
  1240. if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
  1241. /* Enable proper parity. */
  1242. spin_lock_irqsave(&ha->hardware_lock, flags);
  1243. if (IS_QLA2300(ha))
  1244. /* SRAM parity */
  1245. WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
  1246. else
  1247. /* SRAM, Instruction RAM and GP RAM parity */
  1248. WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
  1249. RD_REG_WORD(&reg->hccr);
  1250. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1251. }
  1252. if (IS_QLA83XX(ha))
  1253. goto skip_fac_check;
  1254. if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
  1255. uint32_t size;
  1256. rval = qla81xx_fac_get_sector_size(vha, &size);
  1257. if (rval == QLA_SUCCESS) {
  1258. ha->flags.fac_supported = 1;
  1259. ha->fdt_block_size = size << 2;
  1260. } else {
  1261. ql_log(ql_log_warn, vha, 0x00ce,
  1262. "Unsupported FAC firmware (%d.%02d.%02d).\n",
  1263. ha->fw_major_version, ha->fw_minor_version,
  1264. ha->fw_subminor_version);
  1265. skip_fac_check:
  1266. if (IS_QLA83XX(ha)) {
  1267. ha->flags.fac_supported = 0;
  1268. rval = QLA_SUCCESS;
  1269. }
  1270. }
  1271. }
  1272. failed:
  1273. if (rval) {
  1274. ql_log(ql_log_fatal, vha, 0x00cf,
  1275. "Setup chip ****FAILED****.\n");
  1276. }
  1277. return (rval);
  1278. }
  1279. /**
  1280. * qla2x00_init_response_q_entries() - Initializes response queue entries.
  1281. * @ha: HA context
  1282. *
  1283. * Beginning of request ring has initialization control block already built
  1284. * by nvram config routine.
  1285. *
  1286. * Returns 0 on success.
  1287. */
  1288. void
  1289. qla2x00_init_response_q_entries(struct rsp_que *rsp)
  1290. {
  1291. uint16_t cnt;
  1292. response_t *pkt;
  1293. rsp->ring_ptr = rsp->ring;
  1294. rsp->ring_index = 0;
  1295. rsp->status_srb = NULL;
  1296. pkt = rsp->ring_ptr;
  1297. for (cnt = 0; cnt < rsp->length; cnt++) {
  1298. pkt->signature = RESPONSE_PROCESSED;
  1299. pkt++;
  1300. }
  1301. }
  1302. /**
  1303. * qla2x00_update_fw_options() - Read and process firmware options.
  1304. * @ha: HA context
  1305. *
  1306. * Returns 0 on success.
  1307. */
  1308. void
  1309. qla2x00_update_fw_options(scsi_qla_host_t *vha)
  1310. {
  1311. uint16_t swing, emphasis, tx_sens, rx_sens;
  1312. struct qla_hw_data *ha = vha->hw;
  1313. memset(ha->fw_options, 0, sizeof(ha->fw_options));
  1314. qla2x00_get_fw_options(vha, ha->fw_options);
  1315. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  1316. return;
  1317. /* Serial Link options. */
  1318. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
  1319. "Serial link options.\n");
  1320. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
  1321. (uint8_t *)&ha->fw_seriallink_options,
  1322. sizeof(ha->fw_seriallink_options));
  1323. ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
  1324. if (ha->fw_seriallink_options[3] & BIT_2) {
  1325. ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
  1326. /* 1G settings */
  1327. swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
  1328. emphasis = (ha->fw_seriallink_options[2] &
  1329. (BIT_4 | BIT_3)) >> 3;
  1330. tx_sens = ha->fw_seriallink_options[0] &
  1331. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  1332. rx_sens = (ha->fw_seriallink_options[0] &
  1333. (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
  1334. ha->fw_options[10] = (emphasis << 14) | (swing << 8);
  1335. if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  1336. if (rx_sens == 0x0)
  1337. rx_sens = 0x3;
  1338. ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
  1339. } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1340. ha->fw_options[10] |= BIT_5 |
  1341. ((rx_sens & (BIT_1 | BIT_0)) << 2) |
  1342. (tx_sens & (BIT_1 | BIT_0));
  1343. /* 2G settings */
  1344. swing = (ha->fw_seriallink_options[2] &
  1345. (BIT_7 | BIT_6 | BIT_5)) >> 5;
  1346. emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
  1347. tx_sens = ha->fw_seriallink_options[1] &
  1348. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  1349. rx_sens = (ha->fw_seriallink_options[1] &
  1350. (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
  1351. ha->fw_options[11] = (emphasis << 14) | (swing << 8);
  1352. if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  1353. if (rx_sens == 0x0)
  1354. rx_sens = 0x3;
  1355. ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
  1356. } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1357. ha->fw_options[11] |= BIT_5 |
  1358. ((rx_sens & (BIT_1 | BIT_0)) << 2) |
  1359. (tx_sens & (BIT_1 | BIT_0));
  1360. }
  1361. /* FCP2 options. */
  1362. /* Return command IOCBs without waiting for an ABTS to complete. */
  1363. ha->fw_options[3] |= BIT_13;
  1364. /* LED scheme. */
  1365. if (ha->flags.enable_led_scheme)
  1366. ha->fw_options[2] |= BIT_12;
  1367. /* Detect ISP6312. */
  1368. if (IS_QLA6312(ha))
  1369. ha->fw_options[2] |= BIT_13;
  1370. /* Update firmware options. */
  1371. qla2x00_set_fw_options(vha, ha->fw_options);
  1372. }
  1373. void
  1374. qla24xx_update_fw_options(scsi_qla_host_t *vha)
  1375. {
  1376. int rval;
  1377. struct qla_hw_data *ha = vha->hw;
  1378. if (IS_QLA82XX(ha))
  1379. return;
  1380. /* Update Serial Link options. */
  1381. if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
  1382. return;
  1383. rval = qla2x00_set_serdes_params(vha,
  1384. le16_to_cpu(ha->fw_seriallink_options24[1]),
  1385. le16_to_cpu(ha->fw_seriallink_options24[2]),
  1386. le16_to_cpu(ha->fw_seriallink_options24[3]));
  1387. if (rval != QLA_SUCCESS) {
  1388. ql_log(ql_log_warn, vha, 0x0104,
  1389. "Unable to update Serial Link options (%x).\n", rval);
  1390. }
  1391. }
  1392. void
  1393. qla2x00_config_rings(struct scsi_qla_host *vha)
  1394. {
  1395. struct qla_hw_data *ha = vha->hw;
  1396. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1397. struct req_que *req = ha->req_q_map[0];
  1398. struct rsp_que *rsp = ha->rsp_q_map[0];
  1399. /* Setup ring parameters in initialization control block. */
  1400. ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
  1401. ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
  1402. ha->init_cb->request_q_length = cpu_to_le16(req->length);
  1403. ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
  1404. ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
  1405. ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
  1406. ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
  1407. ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
  1408. WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
  1409. WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
  1410. WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
  1411. WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
  1412. RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
  1413. }
  1414. void
  1415. qla24xx_config_rings(struct scsi_qla_host *vha)
  1416. {
  1417. struct qla_hw_data *ha = vha->hw;
  1418. device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
  1419. struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
  1420. struct qla_msix_entry *msix;
  1421. struct init_cb_24xx *icb;
  1422. uint16_t rid = 0;
  1423. struct req_que *req = ha->req_q_map[0];
  1424. struct rsp_que *rsp = ha->rsp_q_map[0];
  1425. /* Setup ring parameters in initialization control block. */
  1426. icb = (struct init_cb_24xx *)ha->init_cb;
  1427. icb->request_q_outpointer = __constant_cpu_to_le16(0);
  1428. icb->response_q_inpointer = __constant_cpu_to_le16(0);
  1429. icb->request_q_length = cpu_to_le16(req->length);
  1430. icb->response_q_length = cpu_to_le16(rsp->length);
  1431. icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
  1432. icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
  1433. icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
  1434. icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
  1435. if (ha->mqenable || IS_QLA83XX(ha)) {
  1436. icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
  1437. icb->rid = __constant_cpu_to_le16(rid);
  1438. if (ha->flags.msix_enabled) {
  1439. msix = &ha->msix_entries[1];
  1440. ql_dbg(ql_dbg_init, vha, 0x00fd,
  1441. "Registering vector 0x%x for base que.\n",
  1442. msix->entry);
  1443. icb->msix = cpu_to_le16(msix->entry);
  1444. }
  1445. /* Use alternate PCI bus number */
  1446. if (MSB(rid))
  1447. icb->firmware_options_2 |=
  1448. __constant_cpu_to_le32(BIT_19);
  1449. /* Use alternate PCI devfn */
  1450. if (LSB(rid))
  1451. icb->firmware_options_2 |=
  1452. __constant_cpu_to_le32(BIT_18);
  1453. /* Use Disable MSIX Handshake mode for capable adapters */
  1454. if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
  1455. (ha->flags.msix_enabled)) {
  1456. icb->firmware_options_2 &=
  1457. __constant_cpu_to_le32(~BIT_22);
  1458. ha->flags.disable_msix_handshake = 1;
  1459. ql_dbg(ql_dbg_init, vha, 0x00fe,
  1460. "MSIX Handshake Disable Mode turned on.\n");
  1461. } else {
  1462. icb->firmware_options_2 |=
  1463. __constant_cpu_to_le32(BIT_22);
  1464. }
  1465. icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
  1466. WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
  1467. WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
  1468. WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
  1469. WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
  1470. } else {
  1471. WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
  1472. WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
  1473. WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
  1474. WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
  1475. }
  1476. /* PCI posting */
  1477. RD_REG_DWORD(&ioreg->hccr);
  1478. }
  1479. /**
  1480. * qla2x00_init_rings() - Initializes firmware.
  1481. * @ha: HA context
  1482. *
  1483. * Beginning of request ring has initialization control block already built
  1484. * by nvram config routine.
  1485. *
  1486. * Returns 0 on success.
  1487. */
  1488. static int
  1489. qla2x00_init_rings(scsi_qla_host_t *vha)
  1490. {
  1491. int rval;
  1492. unsigned long flags = 0;
  1493. int cnt, que;
  1494. struct qla_hw_data *ha = vha->hw;
  1495. struct req_que *req;
  1496. struct rsp_que *rsp;
  1497. struct mid_init_cb_24xx *mid_init_cb =
  1498. (struct mid_init_cb_24xx *) ha->init_cb;
  1499. spin_lock_irqsave(&ha->hardware_lock, flags);
  1500. /* Clear outstanding commands array. */
  1501. for (que = 0; que < ha->max_req_queues; que++) {
  1502. req = ha->req_q_map[que];
  1503. if (!req)
  1504. continue;
  1505. for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++)
  1506. req->outstanding_cmds[cnt] = NULL;
  1507. req->current_outstanding_cmd = 1;
  1508. /* Initialize firmware. */
  1509. req->ring_ptr = req->ring;
  1510. req->ring_index = 0;
  1511. req->cnt = req->length;
  1512. }
  1513. for (que = 0; que < ha->max_rsp_queues; que++) {
  1514. rsp = ha->rsp_q_map[que];
  1515. if (!rsp)
  1516. continue;
  1517. /* Initialize response queue entries */
  1518. qla2x00_init_response_q_entries(rsp);
  1519. }
  1520. spin_lock(&ha->vport_slock);
  1521. spin_unlock(&ha->vport_slock);
  1522. ha->isp_ops->config_rings(vha);
  1523. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1524. /* Update any ISP specific firmware options before initialization. */
  1525. ha->isp_ops->update_fw_options(vha);
  1526. ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
  1527. if (ha->flags.npiv_supported) {
  1528. if (ha->operating_mode == LOOP)
  1529. ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
  1530. mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
  1531. }
  1532. if (IS_FWI2_CAPABLE(ha)) {
  1533. mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
  1534. mid_init_cb->init_cb.execution_throttle =
  1535. cpu_to_le16(ha->fw_xcb_count);
  1536. }
  1537. rval = qla2x00_init_firmware(vha, ha->init_cb_size);
  1538. if (rval) {
  1539. ql_log(ql_log_fatal, vha, 0x00d2,
  1540. "Init Firmware **** FAILED ****.\n");
  1541. } else {
  1542. ql_dbg(ql_dbg_init, vha, 0x00d3,
  1543. "Init Firmware -- success.\n");
  1544. }
  1545. return (rval);
  1546. }
  1547. /**
  1548. * qla2x00_fw_ready() - Waits for firmware ready.
  1549. * @ha: HA context
  1550. *
  1551. * Returns 0 on success.
  1552. */
  1553. static int
  1554. qla2x00_fw_ready(scsi_qla_host_t *vha)
  1555. {
  1556. int rval;
  1557. unsigned long wtime, mtime, cs84xx_time;
  1558. uint16_t min_wait; /* Minimum wait time if loop is down */
  1559. uint16_t wait_time; /* Wait time if loop is coming ready */
  1560. uint16_t state[5];
  1561. struct qla_hw_data *ha = vha->hw;
  1562. rval = QLA_SUCCESS;
  1563. /* 20 seconds for loop down. */
  1564. min_wait = 20;
  1565. /*
  1566. * Firmware should take at most one RATOV to login, plus 5 seconds for
  1567. * our own processing.
  1568. */
  1569. if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
  1570. wait_time = min_wait;
  1571. }
  1572. /* Min wait time if loop down */
  1573. mtime = jiffies + (min_wait * HZ);
  1574. /* wait time before firmware ready */
  1575. wtime = jiffies + (wait_time * HZ);
  1576. /* Wait for ISP to finish LIP */
  1577. if (!vha->flags.init_done)
  1578. ql_log(ql_log_info, vha, 0x801e,
  1579. "Waiting for LIP to complete.\n");
  1580. do {
  1581. rval = qla2x00_get_firmware_state(vha, state);
  1582. if (rval == QLA_SUCCESS) {
  1583. if (state[0] < FSTATE_LOSS_OF_SYNC) {
  1584. vha->device_flags &= ~DFLG_NO_CABLE;
  1585. }
  1586. if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
  1587. ql_dbg(ql_dbg_taskm, vha, 0x801f,
  1588. "fw_state=%x 84xx=%x.\n", state[0],
  1589. state[2]);
  1590. if ((state[2] & FSTATE_LOGGED_IN) &&
  1591. (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
  1592. ql_dbg(ql_dbg_taskm, vha, 0x8028,
  1593. "Sending verify iocb.\n");
  1594. cs84xx_time = jiffies;
  1595. rval = qla84xx_init_chip(vha);
  1596. if (rval != QLA_SUCCESS) {
  1597. ql_log(ql_log_warn,
  1598. vha, 0x8007,
  1599. "Init chip failed.\n");
  1600. break;
  1601. }
  1602. /* Add time taken to initialize. */
  1603. cs84xx_time = jiffies - cs84xx_time;
  1604. wtime += cs84xx_time;
  1605. mtime += cs84xx_time;
  1606. ql_dbg(ql_dbg_taskm, vha, 0x8008,
  1607. "Increasing wait time by %ld. "
  1608. "New time %ld.\n", cs84xx_time,
  1609. wtime);
  1610. }
  1611. } else if (state[0] == FSTATE_READY) {
  1612. ql_dbg(ql_dbg_taskm, vha, 0x8037,
  1613. "F/W Ready - OK.\n");
  1614. qla2x00_get_retry_cnt(vha, &ha->retry_count,
  1615. &ha->login_timeout, &ha->r_a_tov);
  1616. rval = QLA_SUCCESS;
  1617. break;
  1618. }
  1619. rval = QLA_FUNCTION_FAILED;
  1620. if (atomic_read(&vha->loop_down_timer) &&
  1621. state[0] != FSTATE_READY) {
  1622. /* Loop down. Timeout on min_wait for states
  1623. * other than Wait for Login.
  1624. */
  1625. if (time_after_eq(jiffies, mtime)) {
  1626. ql_log(ql_log_info, vha, 0x8038,
  1627. "Cable is unplugged...\n");
  1628. vha->device_flags |= DFLG_NO_CABLE;
  1629. break;
  1630. }
  1631. }
  1632. } else {
  1633. /* Mailbox cmd failed. Timeout on min_wait. */
  1634. if (time_after_eq(jiffies, mtime) ||
  1635. ha->flags.isp82xx_fw_hung)
  1636. break;
  1637. }
  1638. if (time_after_eq(jiffies, wtime))
  1639. break;
  1640. /* Delay for a while */
  1641. msleep(500);
  1642. } while (1);
  1643. ql_dbg(ql_dbg_taskm, vha, 0x803a,
  1644. "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
  1645. state[1], state[2], state[3], state[4], jiffies);
  1646. if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
  1647. ql_log(ql_log_warn, vha, 0x803b,
  1648. "Firmware ready **** FAILED ****.\n");
  1649. }
  1650. return (rval);
  1651. }
  1652. /*
  1653. * qla2x00_configure_hba
  1654. * Setup adapter context.
  1655. *
  1656. * Input:
  1657. * ha = adapter state pointer.
  1658. *
  1659. * Returns:
  1660. * 0 = success
  1661. *
  1662. * Context:
  1663. * Kernel context.
  1664. */
  1665. static int
  1666. qla2x00_configure_hba(scsi_qla_host_t *vha)
  1667. {
  1668. int rval;
  1669. uint16_t loop_id;
  1670. uint16_t topo;
  1671. uint16_t sw_cap;
  1672. uint8_t al_pa;
  1673. uint8_t area;
  1674. uint8_t domain;
  1675. char connect_type[22];
  1676. struct qla_hw_data *ha = vha->hw;
  1677. /* Get host addresses. */
  1678. rval = qla2x00_get_adapter_id(vha,
  1679. &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
  1680. if (rval != QLA_SUCCESS) {
  1681. if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
  1682. IS_CNA_CAPABLE(ha) ||
  1683. (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
  1684. ql_dbg(ql_dbg_disc, vha, 0x2008,
  1685. "Loop is in a transition state.\n");
  1686. } else {
  1687. ql_log(ql_log_warn, vha, 0x2009,
  1688. "Unable to get host loop ID.\n");
  1689. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1690. }
  1691. return (rval);
  1692. }
  1693. if (topo == 4) {
  1694. ql_log(ql_log_info, vha, 0x200a,
  1695. "Cannot get topology - retrying.\n");
  1696. return (QLA_FUNCTION_FAILED);
  1697. }
  1698. vha->loop_id = loop_id;
  1699. /* initialize */
  1700. ha->min_external_loopid = SNS_FIRST_LOOP_ID;
  1701. ha->operating_mode = LOOP;
  1702. ha->switch_cap = 0;
  1703. switch (topo) {
  1704. case 0:
  1705. ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
  1706. ha->current_topology = ISP_CFG_NL;
  1707. strcpy(connect_type, "(Loop)");
  1708. break;
  1709. case 1:
  1710. ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
  1711. ha->switch_cap = sw_cap;
  1712. ha->current_topology = ISP_CFG_FL;
  1713. strcpy(connect_type, "(FL_Port)");
  1714. break;
  1715. case 2:
  1716. ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
  1717. ha->operating_mode = P2P;
  1718. ha->current_topology = ISP_CFG_N;
  1719. strcpy(connect_type, "(N_Port-to-N_Port)");
  1720. break;
  1721. case 3:
  1722. ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
  1723. ha->switch_cap = sw_cap;
  1724. ha->operating_mode = P2P;
  1725. ha->current_topology = ISP_CFG_F;
  1726. strcpy(connect_type, "(F_Port)");
  1727. break;
  1728. default:
  1729. ql_dbg(ql_dbg_disc, vha, 0x200f,
  1730. "HBA in unknown topology %x, using NL.\n", topo);
  1731. ha->current_topology = ISP_CFG_NL;
  1732. strcpy(connect_type, "(Loop)");
  1733. break;
  1734. }
  1735. /* Save Host port and loop ID. */
  1736. /* byte order - Big Endian */
  1737. vha->d_id.b.domain = domain;
  1738. vha->d_id.b.area = area;
  1739. vha->d_id.b.al_pa = al_pa;
  1740. if (!vha->flags.init_done)
  1741. ql_log(ql_log_info, vha, 0x2010,
  1742. "Topology - %s, Host Loop address 0x%x.\n",
  1743. connect_type, vha->loop_id);
  1744. if (rval) {
  1745. ql_log(ql_log_warn, vha, 0x2011,
  1746. "%s FAILED\n", __func__);
  1747. } else {
  1748. ql_dbg(ql_dbg_disc, vha, 0x2012,
  1749. "%s success\n", __func__);
  1750. }
  1751. return(rval);
  1752. }
  1753. inline void
  1754. qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
  1755. char *def)
  1756. {
  1757. char *st, *en;
  1758. uint16_t index;
  1759. struct qla_hw_data *ha = vha->hw;
  1760. int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
  1761. !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
  1762. if (memcmp(model, BINZERO, len) != 0) {
  1763. strncpy(ha->model_number, model, len);
  1764. st = en = ha->model_number;
  1765. en += len - 1;
  1766. while (en > st) {
  1767. if (*en != 0x20 && *en != 0x00)
  1768. break;
  1769. *en-- = '\0';
  1770. }
  1771. index = (ha->pdev->subsystem_device & 0xff);
  1772. if (use_tbl &&
  1773. ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
  1774. index < QLA_MODEL_NAMES)
  1775. strncpy(ha->model_desc,
  1776. qla2x00_model_name[index * 2 + 1],
  1777. sizeof(ha->model_desc) - 1);
  1778. } else {
  1779. index = (ha->pdev->subsystem_device & 0xff);
  1780. if (use_tbl &&
  1781. ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
  1782. index < QLA_MODEL_NAMES) {
  1783. strcpy(ha->model_number,
  1784. qla2x00_model_name[index * 2]);
  1785. strncpy(ha->model_desc,
  1786. qla2x00_model_name[index * 2 + 1],
  1787. sizeof(ha->model_desc) - 1);
  1788. } else {
  1789. strcpy(ha->model_number, def);
  1790. }
  1791. }
  1792. if (IS_FWI2_CAPABLE(ha))
  1793. qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
  1794. sizeof(ha->model_desc));
  1795. }
  1796. /* On sparc systems, obtain port and node WWN from firmware
  1797. * properties.
  1798. */
  1799. static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
  1800. {
  1801. #ifdef CONFIG_SPARC
  1802. struct qla_hw_data *ha = vha->hw;
  1803. struct pci_dev *pdev = ha->pdev;
  1804. struct device_node *dp = pci_device_to_OF_node(pdev);
  1805. const u8 *val;
  1806. int len;
  1807. val = of_get_property(dp, "port-wwn", &len);
  1808. if (val && len >= WWN_SIZE)
  1809. memcpy(nv->port_name, val, WWN_SIZE);
  1810. val = of_get_property(dp, "node-wwn", &len);
  1811. if (val && len >= WWN_SIZE)
  1812. memcpy(nv->node_name, val, WWN_SIZE);
  1813. #endif
  1814. }
  1815. /*
  1816. * NVRAM configuration for ISP 2xxx
  1817. *
  1818. * Input:
  1819. * ha = adapter block pointer.
  1820. *
  1821. * Output:
  1822. * initialization control block in response_ring
  1823. * host adapters parameters in host adapter block
  1824. *
  1825. * Returns:
  1826. * 0 = success.
  1827. */
  1828. int
  1829. qla2x00_nvram_config(scsi_qla_host_t *vha)
  1830. {
  1831. int rval;
  1832. uint8_t chksum = 0;
  1833. uint16_t cnt;
  1834. uint8_t *dptr1, *dptr2;
  1835. struct qla_hw_data *ha = vha->hw;
  1836. init_cb_t *icb = ha->init_cb;
  1837. nvram_t *nv = ha->nvram;
  1838. uint8_t *ptr = ha->nvram;
  1839. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1840. rval = QLA_SUCCESS;
  1841. /* Determine NVRAM starting address. */
  1842. ha->nvram_size = sizeof(nvram_t);
  1843. ha->nvram_base = 0;
  1844. if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
  1845. if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
  1846. ha->nvram_base = 0x80;
  1847. /* Get NVRAM data and calculate checksum. */
  1848. ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
  1849. for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
  1850. chksum += *ptr++;
  1851. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
  1852. "Contents of NVRAM.\n");
  1853. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
  1854. (uint8_t *)nv, ha->nvram_size);
  1855. /* Bad NVRAM data, set defaults parameters. */
  1856. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
  1857. nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
  1858. /* Reset NVRAM data. */
  1859. ql_log(ql_log_warn, vha, 0x0064,
  1860. "Inconisistent NVRAM "
  1861. "detected: checksum=0x%x id=%c version=0x%x.\n",
  1862. chksum, nv->id[0], nv->nvram_version);
  1863. ql_log(ql_log_warn, vha, 0x0065,
  1864. "Falling back to "
  1865. "functioning (yet invalid -- WWPN) defaults.\n");
  1866. /*
  1867. * Set default initialization control block.
  1868. */
  1869. memset(nv, 0, ha->nvram_size);
  1870. nv->parameter_block_version = ICB_VERSION;
  1871. if (IS_QLA23XX(ha)) {
  1872. nv->firmware_options[0] = BIT_2 | BIT_1;
  1873. nv->firmware_options[1] = BIT_7 | BIT_5;
  1874. nv->add_firmware_options[0] = BIT_5;
  1875. nv->add_firmware_options[1] = BIT_5 | BIT_4;
  1876. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  1877. nv->special_options[1] = BIT_7;
  1878. } else if (IS_QLA2200(ha)) {
  1879. nv->firmware_options[0] = BIT_2 | BIT_1;
  1880. nv->firmware_options[1] = BIT_7 | BIT_5;
  1881. nv->add_firmware_options[0] = BIT_5;
  1882. nv->add_firmware_options[1] = BIT_5 | BIT_4;
  1883. nv->frame_payload_size = __constant_cpu_to_le16(1024);
  1884. } else if (IS_QLA2100(ha)) {
  1885. nv->firmware_options[0] = BIT_3 | BIT_1;
  1886. nv->firmware_options[1] = BIT_5;
  1887. nv->frame_payload_size = __constant_cpu_to_le16(1024);
  1888. }
  1889. nv->max_iocb_allocation = __constant_cpu_to_le16(256);
  1890. nv->execution_throttle = __constant_cpu_to_le16(16);
  1891. nv->retry_count = 8;
  1892. nv->retry_delay = 1;
  1893. nv->port_name[0] = 33;
  1894. nv->port_name[3] = 224;
  1895. nv->port_name[4] = 139;
  1896. qla2xxx_nvram_wwn_from_ofw(vha, nv);
  1897. nv->login_timeout = 4;
  1898. /*
  1899. * Set default host adapter parameters
  1900. */
  1901. nv->host_p[1] = BIT_2;
  1902. nv->reset_delay = 5;
  1903. nv->port_down_retry_count = 8;
  1904. nv->max_luns_per_target = __constant_cpu_to_le16(8);
  1905. nv->link_down_timeout = 60;
  1906. rval = 1;
  1907. }
  1908. #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
  1909. /*
  1910. * The SN2 does not provide BIOS emulation which means you can't change
  1911. * potentially bogus BIOS settings. Force the use of default settings
  1912. * for link rate and frame size. Hope that the rest of the settings
  1913. * are valid.
  1914. */
  1915. if (ia64_platform_is("sn2")) {
  1916. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  1917. if (IS_QLA23XX(ha))
  1918. nv->special_options[1] = BIT_7;
  1919. }
  1920. #endif
  1921. /* Reset Initialization control block */
  1922. memset(icb, 0, ha->init_cb_size);
  1923. /*
  1924. * Setup driver NVRAM options.
  1925. */
  1926. nv->firmware_options[0] |= (BIT_6 | BIT_1);
  1927. nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
  1928. nv->firmware_options[1] |= (BIT_5 | BIT_0);
  1929. nv->firmware_options[1] &= ~BIT_4;
  1930. if (IS_QLA23XX(ha)) {
  1931. nv->firmware_options[0] |= BIT_2;
  1932. nv->firmware_options[0] &= ~BIT_3;
  1933. nv->firmware_options[0] &= ~BIT_6;
  1934. nv->add_firmware_options[1] |= BIT_5 | BIT_4;
  1935. if (IS_QLA2300(ha)) {
  1936. if (ha->fb_rev == FPM_2310) {
  1937. strcpy(ha->model_number, "QLA2310");
  1938. } else {
  1939. strcpy(ha->model_number, "QLA2300");
  1940. }
  1941. } else {
  1942. qla2x00_set_model_info(vha, nv->model_number,
  1943. sizeof(nv->model_number), "QLA23xx");
  1944. }
  1945. } else if (IS_QLA2200(ha)) {
  1946. nv->firmware_options[0] |= BIT_2;
  1947. /*
  1948. * 'Point-to-point preferred, else loop' is not a safe
  1949. * connection mode setting.
  1950. */
  1951. if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
  1952. (BIT_5 | BIT_4)) {
  1953. /* Force 'loop preferred, else point-to-point'. */
  1954. nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
  1955. nv->add_firmware_options[0] |= BIT_5;
  1956. }
  1957. strcpy(ha->model_number, "QLA22xx");
  1958. } else /*if (IS_QLA2100(ha))*/ {
  1959. strcpy(ha->model_number, "QLA2100");
  1960. }
  1961. /*
  1962. * Copy over NVRAM RISC parameter block to initialization control block.
  1963. */
  1964. dptr1 = (uint8_t *)icb;
  1965. dptr2 = (uint8_t *)&nv->parameter_block_version;
  1966. cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
  1967. while (cnt--)
  1968. *dptr1++ = *dptr2++;
  1969. /* Copy 2nd half. */
  1970. dptr1 = (uint8_t *)icb->add_firmware_options;
  1971. cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
  1972. while (cnt--)
  1973. *dptr1++ = *dptr2++;
  1974. /* Use alternate WWN? */
  1975. if (nv->host_p[1] & BIT_7) {
  1976. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  1977. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  1978. }
  1979. /* Prepare nodename */
  1980. if ((icb->firmware_options[1] & BIT_6) == 0) {
  1981. /*
  1982. * Firmware will apply the following mask if the nodename was
  1983. * not provided.
  1984. */
  1985. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  1986. icb->node_name[0] &= 0xF0;
  1987. }
  1988. /*
  1989. * Set host adapter parameters.
  1990. */
  1991. /*
  1992. * BIT_7 in the host-parameters section allows for modification to
  1993. * internal driver logging.
  1994. */
  1995. if (nv->host_p[0] & BIT_7)
  1996. ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
  1997. ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
  1998. /* Always load RISC code on non ISP2[12]00 chips. */
  1999. if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
  2000. ha->flags.disable_risc_code_load = 0;
  2001. ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
  2002. ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
  2003. ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
  2004. ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
  2005. ha->flags.disable_serdes = 0;
  2006. ha->operating_mode =
  2007. (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
  2008. memcpy(ha->fw_seriallink_options, nv->seriallink_options,
  2009. sizeof(ha->fw_seriallink_options));
  2010. /* save HBA serial number */
  2011. ha->serial0 = icb->port_name[5];
  2012. ha->serial1 = icb->port_name[6];
  2013. ha->serial2 = icb->port_name[7];
  2014. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  2015. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  2016. icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  2017. ha->retry_count = nv->retry_count;
  2018. /* Set minimum login_timeout to 4 seconds. */
  2019. if (nv->login_timeout != ql2xlogintimeout)
  2020. nv->login_timeout = ql2xlogintimeout;
  2021. if (nv->login_timeout < 4)
  2022. nv->login_timeout = 4;
  2023. ha->login_timeout = nv->login_timeout;
  2024. icb->login_timeout = nv->login_timeout;
  2025. /* Set minimum RATOV to 100 tenths of a second. */
  2026. ha->r_a_tov = 100;
  2027. ha->loop_reset_delay = nv->reset_delay;
  2028. /* Link Down Timeout = 0:
  2029. *
  2030. * When Port Down timer expires we will start returning
  2031. * I/O's to OS with "DID_NO_CONNECT".
  2032. *
  2033. * Link Down Timeout != 0:
  2034. *
  2035. * The driver waits for the link to come up after link down
  2036. * before returning I/Os to OS with "DID_NO_CONNECT".
  2037. */
  2038. if (nv->link_down_timeout == 0) {
  2039. ha->loop_down_abort_time =
  2040. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  2041. } else {
  2042. ha->link_down_timeout = nv->link_down_timeout;
  2043. ha->loop_down_abort_time =
  2044. (LOOP_DOWN_TIME - ha->link_down_timeout);
  2045. }
  2046. /*
  2047. * Need enough time to try and get the port back.
  2048. */
  2049. ha->port_down_retry_count = nv->port_down_retry_count;
  2050. if (qlport_down_retry)
  2051. ha->port_down_retry_count = qlport_down_retry;
  2052. /* Set login_retry_count */
  2053. ha->login_retry_count = nv->retry_count;
  2054. if (ha->port_down_retry_count == nv->port_down_retry_count &&
  2055. ha->port_down_retry_count > 3)
  2056. ha->login_retry_count = ha->port_down_retry_count;
  2057. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  2058. ha->login_retry_count = ha->port_down_retry_count;
  2059. if (ql2xloginretrycount)
  2060. ha->login_retry_count = ql2xloginretrycount;
  2061. icb->lun_enables = __constant_cpu_to_le16(0);
  2062. icb->command_resource_count = 0;
  2063. icb->immediate_notify_resource_count = 0;
  2064. icb->timeout = __constant_cpu_to_le16(0);
  2065. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  2066. /* Enable RIO */
  2067. icb->firmware_options[0] &= ~BIT_3;
  2068. icb->add_firmware_options[0] &=
  2069. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
  2070. icb->add_firmware_options[0] |= BIT_2;
  2071. icb->response_accumulation_timer = 3;
  2072. icb->interrupt_delay_timer = 5;
  2073. vha->flags.process_response_queue = 1;
  2074. } else {
  2075. /* Enable ZIO. */
  2076. if (!vha->flags.init_done) {
  2077. ha->zio_mode = icb->add_firmware_options[0] &
  2078. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  2079. ha->zio_timer = icb->interrupt_delay_timer ?
  2080. icb->interrupt_delay_timer: 2;
  2081. }
  2082. icb->add_firmware_options[0] &=
  2083. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
  2084. vha->flags.process_response_queue = 0;
  2085. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  2086. ha->zio_mode = QLA_ZIO_MODE_6;
  2087. ql_log(ql_log_info, vha, 0x0068,
  2088. "ZIO mode %d enabled; timer delay (%d us).\n",
  2089. ha->zio_mode, ha->zio_timer * 100);
  2090. icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
  2091. icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
  2092. vha->flags.process_response_queue = 1;
  2093. }
  2094. }
  2095. if (rval) {
  2096. ql_log(ql_log_warn, vha, 0x0069,
  2097. "NVRAM configuration failed.\n");
  2098. }
  2099. return (rval);
  2100. }
  2101. static void
  2102. qla2x00_rport_del(void *data)
  2103. {
  2104. fc_port_t *fcport = data;
  2105. struct fc_rport *rport;
  2106. unsigned long flags;
  2107. spin_lock_irqsave(fcport->vha->host->host_lock, flags);
  2108. rport = fcport->drport ? fcport->drport: fcport->rport;
  2109. fcport->drport = NULL;
  2110. spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
  2111. if (rport)
  2112. fc_remote_port_delete(rport);
  2113. }
  2114. /**
  2115. * qla2x00_alloc_fcport() - Allocate a generic fcport.
  2116. * @ha: HA context
  2117. * @flags: allocation flags
  2118. *
  2119. * Returns a pointer to the allocated fcport, or NULL, if none available.
  2120. */
  2121. fc_port_t *
  2122. qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
  2123. {
  2124. fc_port_t *fcport;
  2125. fcport = kzalloc(sizeof(fc_port_t), flags);
  2126. if (!fcport)
  2127. return NULL;
  2128. /* Setup fcport template structure. */
  2129. fcport->vha = vha;
  2130. fcport->vp_idx = vha->vp_idx;
  2131. fcport->port_type = FCT_UNKNOWN;
  2132. fcport->loop_id = FC_NO_LOOP_ID;
  2133. qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
  2134. fcport->supported_classes = FC_COS_UNSPECIFIED;
  2135. return fcport;
  2136. }
  2137. /*
  2138. * qla2x00_configure_loop
  2139. * Updates Fibre Channel Device Database with what is actually on loop.
  2140. *
  2141. * Input:
  2142. * ha = adapter block pointer.
  2143. *
  2144. * Returns:
  2145. * 0 = success.
  2146. * 1 = error.
  2147. * 2 = database was full and device was not configured.
  2148. */
  2149. static int
  2150. qla2x00_configure_loop(scsi_qla_host_t *vha)
  2151. {
  2152. int rval;
  2153. unsigned long flags, save_flags;
  2154. struct qla_hw_data *ha = vha->hw;
  2155. rval = QLA_SUCCESS;
  2156. /* Get Initiator ID */
  2157. if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
  2158. rval = qla2x00_configure_hba(vha);
  2159. if (rval != QLA_SUCCESS) {
  2160. ql_dbg(ql_dbg_disc, vha, 0x2013,
  2161. "Unable to configure HBA.\n");
  2162. return (rval);
  2163. }
  2164. }
  2165. save_flags = flags = vha->dpc_flags;
  2166. ql_dbg(ql_dbg_disc, vha, 0x2014,
  2167. "Configure loop -- dpc flags = 0x%lx.\n", flags);
  2168. /*
  2169. * If we have both an RSCN and PORT UPDATE pending then handle them
  2170. * both at the same time.
  2171. */
  2172. clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2173. clear_bit(RSCN_UPDATE, &vha->dpc_flags);
  2174. qla2x00_get_data_rate(vha);
  2175. /* Determine what we need to do */
  2176. if (ha->current_topology == ISP_CFG_FL &&
  2177. (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
  2178. set_bit(RSCN_UPDATE, &flags);
  2179. } else if (ha->current_topology == ISP_CFG_F &&
  2180. (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
  2181. set_bit(RSCN_UPDATE, &flags);
  2182. clear_bit(LOCAL_LOOP_UPDATE, &flags);
  2183. } else if (ha->current_topology == ISP_CFG_N) {
  2184. clear_bit(RSCN_UPDATE, &flags);
  2185. } else if (!vha->flags.online ||
  2186. (test_bit(ABORT_ISP_ACTIVE, &flags))) {
  2187. set_bit(RSCN_UPDATE, &flags);
  2188. set_bit(LOCAL_LOOP_UPDATE, &flags);
  2189. }
  2190. if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
  2191. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  2192. ql_dbg(ql_dbg_disc, vha, 0x2015,
  2193. "Loop resync needed, failing.\n");
  2194. rval = QLA_FUNCTION_FAILED;
  2195. }
  2196. else
  2197. rval = qla2x00_configure_local_loop(vha);
  2198. }
  2199. if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
  2200. if (LOOP_TRANSITION(vha)) {
  2201. ql_dbg(ql_dbg_disc, vha, 0x201e,
  2202. "Needs RSCN update and loop transition.\n");
  2203. rval = QLA_FUNCTION_FAILED;
  2204. }
  2205. else
  2206. rval = qla2x00_configure_fabric(vha);
  2207. }
  2208. if (rval == QLA_SUCCESS) {
  2209. if (atomic_read(&vha->loop_down_timer) ||
  2210. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  2211. rval = QLA_FUNCTION_FAILED;
  2212. } else {
  2213. atomic_set(&vha->loop_state, LOOP_READY);
  2214. ql_dbg(ql_dbg_disc, vha, 0x2069,
  2215. "LOOP READY.\n");
  2216. }
  2217. }
  2218. if (rval) {
  2219. ql_dbg(ql_dbg_disc, vha, 0x206a,
  2220. "%s *** FAILED ***.\n", __func__);
  2221. } else {
  2222. ql_dbg(ql_dbg_disc, vha, 0x206b,
  2223. "%s: exiting normally.\n", __func__);
  2224. }
  2225. /* Restore state if a resync event occurred during processing */
  2226. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  2227. if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
  2228. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2229. if (test_bit(RSCN_UPDATE, &save_flags)) {
  2230. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  2231. }
  2232. }
  2233. return (rval);
  2234. }
  2235. /*
  2236. * qla2x00_configure_local_loop
  2237. * Updates Fibre Channel Device Database with local loop devices.
  2238. *
  2239. * Input:
  2240. * ha = adapter block pointer.
  2241. *
  2242. * Returns:
  2243. * 0 = success.
  2244. */
  2245. static int
  2246. qla2x00_configure_local_loop(scsi_qla_host_t *vha)
  2247. {
  2248. int rval, rval2;
  2249. int found_devs;
  2250. int found;
  2251. fc_port_t *fcport, *new_fcport;
  2252. uint16_t index;
  2253. uint16_t entries;
  2254. char *id_iter;
  2255. uint16_t loop_id;
  2256. uint8_t domain, area, al_pa;
  2257. struct qla_hw_data *ha = vha->hw;
  2258. found_devs = 0;
  2259. new_fcport = NULL;
  2260. entries = MAX_FIBRE_DEVICES;
  2261. ql_dbg(ql_dbg_disc, vha, 0x2016,
  2262. "Getting FCAL position map.\n");
  2263. if (ql2xextended_error_logging & ql_dbg_disc)
  2264. qla2x00_get_fcal_position_map(vha, NULL);
  2265. /* Get list of logged in devices. */
  2266. memset(ha->gid_list, 0, GID_LIST_SIZE);
  2267. rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
  2268. &entries);
  2269. if (rval != QLA_SUCCESS)
  2270. goto cleanup_allocation;
  2271. ql_dbg(ql_dbg_disc, vha, 0x2017,
  2272. "Entries in ID list (%d).\n", entries);
  2273. ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
  2274. (uint8_t *)ha->gid_list,
  2275. entries * sizeof(struct gid_list_info));
  2276. /* Allocate temporary fcport for any new fcports discovered. */
  2277. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2278. if (new_fcport == NULL) {
  2279. ql_log(ql_log_warn, vha, 0x2018,
  2280. "Memory allocation failed for fcport.\n");
  2281. rval = QLA_MEMORY_ALLOC_FAILED;
  2282. goto cleanup_allocation;
  2283. }
  2284. new_fcport->flags &= ~FCF_FABRIC_DEVICE;
  2285. /*
  2286. * Mark local devices that were present with FCF_DEVICE_LOST for now.
  2287. */
  2288. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2289. if (atomic_read(&fcport->state) == FCS_ONLINE &&
  2290. fcport->port_type != FCT_BROADCAST &&
  2291. (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
  2292. ql_dbg(ql_dbg_disc, vha, 0x2019,
  2293. "Marking port lost loop_id=0x%04x.\n",
  2294. fcport->loop_id);
  2295. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  2296. }
  2297. }
  2298. /* Add devices to port list. */
  2299. id_iter = (char *)ha->gid_list;
  2300. for (index = 0; index < entries; index++) {
  2301. domain = ((struct gid_list_info *)id_iter)->domain;
  2302. area = ((struct gid_list_info *)id_iter)->area;
  2303. al_pa = ((struct gid_list_info *)id_iter)->al_pa;
  2304. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  2305. loop_id = (uint16_t)
  2306. ((struct gid_list_info *)id_iter)->loop_id_2100;
  2307. else
  2308. loop_id = le16_to_cpu(
  2309. ((struct gid_list_info *)id_iter)->loop_id);
  2310. id_iter += ha->gid_list_info_size;
  2311. /* Bypass reserved domain fields. */
  2312. if ((domain & 0xf0) == 0xf0)
  2313. continue;
  2314. /* Bypass if not same domain and area of adapter. */
  2315. if (area && domain &&
  2316. (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
  2317. continue;
  2318. /* Bypass invalid local loop ID. */
  2319. if (loop_id > LAST_LOCAL_LOOP_ID)
  2320. continue;
  2321. /* Fill in member data. */
  2322. new_fcport->d_id.b.domain = domain;
  2323. new_fcport->d_id.b.area = area;
  2324. new_fcport->d_id.b.al_pa = al_pa;
  2325. new_fcport->loop_id = loop_id;
  2326. new_fcport->vp_idx = vha->vp_idx;
  2327. rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
  2328. if (rval2 != QLA_SUCCESS) {
  2329. ql_dbg(ql_dbg_disc, vha, 0x201a,
  2330. "Failed to retrieve fcport information "
  2331. "-- get_port_database=%x, loop_id=0x%04x.\n",
  2332. rval2, new_fcport->loop_id);
  2333. ql_dbg(ql_dbg_disc, vha, 0x201b,
  2334. "Scheduling resync.\n");
  2335. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  2336. continue;
  2337. }
  2338. /* Check for matching device in port list. */
  2339. found = 0;
  2340. fcport = NULL;
  2341. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2342. if (memcmp(new_fcport->port_name, fcport->port_name,
  2343. WWN_SIZE))
  2344. continue;
  2345. fcport->flags &= ~FCF_FABRIC_DEVICE;
  2346. fcport->loop_id = new_fcport->loop_id;
  2347. fcport->port_type = new_fcport->port_type;
  2348. fcport->d_id.b24 = new_fcport->d_id.b24;
  2349. memcpy(fcport->node_name, new_fcport->node_name,
  2350. WWN_SIZE);
  2351. found++;
  2352. break;
  2353. }
  2354. if (!found) {
  2355. /* New device, add to fcports list. */
  2356. if (vha->vp_idx) {
  2357. new_fcport->vha = vha;
  2358. new_fcport->vp_idx = vha->vp_idx;
  2359. }
  2360. list_add_tail(&new_fcport->list, &vha->vp_fcports);
  2361. /* Allocate a new replacement fcport. */
  2362. fcport = new_fcport;
  2363. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2364. if (new_fcport == NULL) {
  2365. ql_log(ql_log_warn, vha, 0x201c,
  2366. "Failed to allocate memory for fcport.\n");
  2367. rval = QLA_MEMORY_ALLOC_FAILED;
  2368. goto cleanup_allocation;
  2369. }
  2370. new_fcport->flags &= ~FCF_FABRIC_DEVICE;
  2371. }
  2372. /* Base iIDMA settings on HBA port speed. */
  2373. fcport->fp_speed = ha->link_data_rate;
  2374. qla2x00_update_fcport(vha, fcport);
  2375. found_devs++;
  2376. }
  2377. cleanup_allocation:
  2378. kfree(new_fcport);
  2379. if (rval != QLA_SUCCESS) {
  2380. ql_dbg(ql_dbg_disc, vha, 0x201d,
  2381. "Configure local loop error exit: rval=%x.\n", rval);
  2382. }
  2383. return (rval);
  2384. }
  2385. static void
  2386. qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
  2387. {
  2388. #define LS_UNKNOWN 2
  2389. static char *link_speeds[] = { "1", "2", "?", "4", "8", "10" };
  2390. char *link_speed;
  2391. int rval;
  2392. uint16_t mb[4];
  2393. struct qla_hw_data *ha = vha->hw;
  2394. if (!IS_IIDMA_CAPABLE(ha))
  2395. return;
  2396. if (atomic_read(&fcport->state) != FCS_ONLINE)
  2397. return;
  2398. if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
  2399. fcport->fp_speed > ha->link_data_rate)
  2400. return;
  2401. rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
  2402. mb);
  2403. if (rval != QLA_SUCCESS) {
  2404. ql_dbg(ql_dbg_disc, vha, 0x2004,
  2405. "Unable to adjust iIDMA "
  2406. "%02x%02x%02x%02x%02x%02x%02x%02x -- %04x %x %04x "
  2407. "%04x.\n", fcport->port_name[0], fcport->port_name[1],
  2408. fcport->port_name[2], fcport->port_name[3],
  2409. fcport->port_name[4], fcport->port_name[5],
  2410. fcport->port_name[6], fcport->port_name[7], rval,
  2411. fcport->fp_speed, mb[0], mb[1]);
  2412. } else {
  2413. link_speed = link_speeds[LS_UNKNOWN];
  2414. if (fcport->fp_speed < 5)
  2415. link_speed = link_speeds[fcport->fp_speed];
  2416. else if (fcport->fp_speed == 0x13)
  2417. link_speed = link_speeds[5];
  2418. ql_dbg(ql_dbg_disc, vha, 0x2005,
  2419. "iIDMA adjusted to %s GB/s "
  2420. "on %02x%02x%02x%02x%02x%02x%02x%02x.\n", link_speed,
  2421. fcport->port_name[0], fcport->port_name[1],
  2422. fcport->port_name[2], fcport->port_name[3],
  2423. fcport->port_name[4], fcport->port_name[5],
  2424. fcport->port_name[6], fcport->port_name[7]);
  2425. }
  2426. }
  2427. static void
  2428. qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
  2429. {
  2430. struct fc_rport_identifiers rport_ids;
  2431. struct fc_rport *rport;
  2432. unsigned long flags;
  2433. qla2x00_rport_del(fcport);
  2434. rport_ids.node_name = wwn_to_u64(fcport->node_name);
  2435. rport_ids.port_name = wwn_to_u64(fcport->port_name);
  2436. rport_ids.port_id = fcport->d_id.b.domain << 16 |
  2437. fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
  2438. rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
  2439. fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
  2440. if (!rport) {
  2441. ql_log(ql_log_warn, vha, 0x2006,
  2442. "Unable to allocate fc remote port.\n");
  2443. return;
  2444. }
  2445. spin_lock_irqsave(fcport->vha->host->host_lock, flags);
  2446. *((fc_port_t **)rport->dd_data) = fcport;
  2447. spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
  2448. rport->supported_classes = fcport->supported_classes;
  2449. rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
  2450. if (fcport->port_type == FCT_INITIATOR)
  2451. rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
  2452. if (fcport->port_type == FCT_TARGET)
  2453. rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
  2454. fc_remote_port_rolechg(rport, rport_ids.roles);
  2455. }
  2456. /*
  2457. * qla2x00_update_fcport
  2458. * Updates device on list.
  2459. *
  2460. * Input:
  2461. * ha = adapter block pointer.
  2462. * fcport = port structure pointer.
  2463. *
  2464. * Return:
  2465. * 0 - Success
  2466. * BIT_0 - error
  2467. *
  2468. * Context:
  2469. * Kernel context.
  2470. */
  2471. void
  2472. qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
  2473. {
  2474. fcport->vha = vha;
  2475. fcport->login_retry = 0;
  2476. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  2477. qla2x00_iidma_fcport(vha, fcport);
  2478. qla24xx_update_fcport_fcp_prio(vha, fcport);
  2479. qla2x00_reg_remote_port(vha, fcport);
  2480. qla2x00_set_fcport_state(fcport, FCS_ONLINE);
  2481. }
  2482. /*
  2483. * qla2x00_configure_fabric
  2484. * Setup SNS devices with loop ID's.
  2485. *
  2486. * Input:
  2487. * ha = adapter block pointer.
  2488. *
  2489. * Returns:
  2490. * 0 = success.
  2491. * BIT_0 = error
  2492. */
  2493. static int
  2494. qla2x00_configure_fabric(scsi_qla_host_t *vha)
  2495. {
  2496. int rval;
  2497. fc_port_t *fcport, *fcptemp;
  2498. uint16_t next_loopid;
  2499. uint16_t mb[MAILBOX_REGISTER_COUNT];
  2500. uint16_t loop_id;
  2501. LIST_HEAD(new_fcports);
  2502. struct qla_hw_data *ha = vha->hw;
  2503. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  2504. /* If FL port exists, then SNS is present */
  2505. if (IS_FWI2_CAPABLE(ha))
  2506. loop_id = NPH_F_PORT;
  2507. else
  2508. loop_id = SNS_FL_PORT;
  2509. rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
  2510. if (rval != QLA_SUCCESS) {
  2511. ql_dbg(ql_dbg_disc, vha, 0x201f,
  2512. "MBX_GET_PORT_NAME failed, No FL Port.\n");
  2513. vha->device_flags &= ~SWITCH_FOUND;
  2514. return (QLA_SUCCESS);
  2515. }
  2516. vha->device_flags |= SWITCH_FOUND;
  2517. do {
  2518. /* FDMI support. */
  2519. if (ql2xfdmienable &&
  2520. test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
  2521. qla2x00_fdmi_register(vha);
  2522. /* Ensure we are logged into the SNS. */
  2523. if (IS_FWI2_CAPABLE(ha))
  2524. loop_id = NPH_SNS;
  2525. else
  2526. loop_id = SIMPLE_NAME_SERVER;
  2527. rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
  2528. 0xfc, mb, BIT_1|BIT_0);
  2529. if (rval != QLA_SUCCESS) {
  2530. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  2531. return rval;
  2532. }
  2533. if (mb[0] != MBS_COMMAND_COMPLETE) {
  2534. ql_dbg(ql_dbg_disc, vha, 0x2042,
  2535. "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
  2536. "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
  2537. mb[2], mb[6], mb[7]);
  2538. return (QLA_SUCCESS);
  2539. }
  2540. if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
  2541. if (qla2x00_rft_id(vha)) {
  2542. /* EMPTY */
  2543. ql_dbg(ql_dbg_disc, vha, 0x2045,
  2544. "Register FC-4 TYPE failed.\n");
  2545. }
  2546. if (qla2x00_rff_id(vha)) {
  2547. /* EMPTY */
  2548. ql_dbg(ql_dbg_disc, vha, 0x2049,
  2549. "Register FC-4 Features failed.\n");
  2550. }
  2551. if (qla2x00_rnn_id(vha)) {
  2552. /* EMPTY */
  2553. ql_dbg(ql_dbg_disc, vha, 0x204f,
  2554. "Register Node Name failed.\n");
  2555. } else if (qla2x00_rsnn_nn(vha)) {
  2556. /* EMPTY */
  2557. ql_dbg(ql_dbg_disc, vha, 0x2053,
  2558. "Register Symobilic Node Name failed.\n");
  2559. }
  2560. }
  2561. #define QLA_FCPORT_SCAN 1
  2562. #define QLA_FCPORT_FOUND 2
  2563. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2564. fcport->scan_state = QLA_FCPORT_SCAN;
  2565. }
  2566. rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
  2567. if (rval != QLA_SUCCESS)
  2568. break;
  2569. /*
  2570. * Logout all previous fabric devices marked lost, except
  2571. * FCP2 devices.
  2572. */
  2573. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2574. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2575. break;
  2576. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
  2577. continue;
  2578. if (fcport->scan_state == QLA_FCPORT_SCAN &&
  2579. atomic_read(&fcport->state) == FCS_ONLINE) {
  2580. qla2x00_mark_device_lost(vha, fcport,
  2581. ql2xplogiabsentdevice, 0);
  2582. if (fcport->loop_id != FC_NO_LOOP_ID &&
  2583. (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
  2584. fcport->port_type != FCT_INITIATOR &&
  2585. fcport->port_type != FCT_BROADCAST) {
  2586. ha->isp_ops->fabric_logout(vha,
  2587. fcport->loop_id,
  2588. fcport->d_id.b.domain,
  2589. fcport->d_id.b.area,
  2590. fcport->d_id.b.al_pa);
  2591. fcport->loop_id = FC_NO_LOOP_ID;
  2592. }
  2593. }
  2594. }
  2595. /* Starting free loop ID. */
  2596. next_loopid = ha->min_external_loopid;
  2597. /*
  2598. * Scan through our port list and login entries that need to be
  2599. * logged in.
  2600. */
  2601. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2602. if (atomic_read(&vha->loop_down_timer) ||
  2603. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2604. break;
  2605. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
  2606. (fcport->flags & FCF_LOGIN_NEEDED) == 0)
  2607. continue;
  2608. if (fcport->loop_id == FC_NO_LOOP_ID) {
  2609. fcport->loop_id = next_loopid;
  2610. rval = qla2x00_find_new_loop_id(
  2611. base_vha, fcport);
  2612. if (rval != QLA_SUCCESS) {
  2613. /* Ran out of IDs to use */
  2614. break;
  2615. }
  2616. }
  2617. /* Login and update database */
  2618. qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
  2619. }
  2620. /* Exit if out of loop IDs. */
  2621. if (rval != QLA_SUCCESS) {
  2622. break;
  2623. }
  2624. /*
  2625. * Login and add the new devices to our port list.
  2626. */
  2627. list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
  2628. if (atomic_read(&vha->loop_down_timer) ||
  2629. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2630. break;
  2631. /* Find a new loop ID to use. */
  2632. fcport->loop_id = next_loopid;
  2633. rval = qla2x00_find_new_loop_id(base_vha, fcport);
  2634. if (rval != QLA_SUCCESS) {
  2635. /* Ran out of IDs to use */
  2636. break;
  2637. }
  2638. /* Login and update database */
  2639. qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
  2640. if (vha->vp_idx) {
  2641. fcport->vha = vha;
  2642. fcport->vp_idx = vha->vp_idx;
  2643. }
  2644. list_move_tail(&fcport->list, &vha->vp_fcports);
  2645. }
  2646. } while (0);
  2647. /* Free all new device structures not processed. */
  2648. list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
  2649. list_del(&fcport->list);
  2650. kfree(fcport);
  2651. }
  2652. if (rval) {
  2653. ql_dbg(ql_dbg_disc, vha, 0x2068,
  2654. "Configure fabric error exit rval=%d.\n", rval);
  2655. }
  2656. return (rval);
  2657. }
  2658. /*
  2659. * qla2x00_find_all_fabric_devs
  2660. *
  2661. * Input:
  2662. * ha = adapter block pointer.
  2663. * dev = database device entry pointer.
  2664. *
  2665. * Returns:
  2666. * 0 = success.
  2667. *
  2668. * Context:
  2669. * Kernel context.
  2670. */
  2671. static int
  2672. qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
  2673. struct list_head *new_fcports)
  2674. {
  2675. int rval;
  2676. uint16_t loop_id;
  2677. fc_port_t *fcport, *new_fcport, *fcptemp;
  2678. int found;
  2679. sw_info_t *swl;
  2680. int swl_idx;
  2681. int first_dev, last_dev;
  2682. port_id_t wrap = {}, nxt_d_id;
  2683. struct qla_hw_data *ha = vha->hw;
  2684. struct scsi_qla_host *vp, *base_vha = pci_get_drvdata(ha->pdev);
  2685. struct scsi_qla_host *tvp;
  2686. rval = QLA_SUCCESS;
  2687. /* Try GID_PT to get device list, else GAN. */
  2688. swl = kcalloc(MAX_FIBRE_DEVICES, sizeof(sw_info_t), GFP_KERNEL);
  2689. if (!swl) {
  2690. /*EMPTY*/
  2691. ql_dbg(ql_dbg_disc, vha, 0x2054,
  2692. "GID_PT allocations failed, fallback on GA_NXT.\n");
  2693. } else {
  2694. if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
  2695. kfree(swl);
  2696. swl = NULL;
  2697. } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
  2698. kfree(swl);
  2699. swl = NULL;
  2700. } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
  2701. kfree(swl);
  2702. swl = NULL;
  2703. } else if (ql2xiidmaenable &&
  2704. qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
  2705. qla2x00_gpsc(vha, swl);
  2706. }
  2707. /* If other queries succeeded probe for FC-4 type */
  2708. if (swl)
  2709. qla2x00_gff_id(vha, swl);
  2710. }
  2711. swl_idx = 0;
  2712. /* Allocate temporary fcport for any new fcports discovered. */
  2713. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2714. if (new_fcport == NULL) {
  2715. ql_log(ql_log_warn, vha, 0x205e,
  2716. "Failed to allocate memory for fcport.\n");
  2717. kfree(swl);
  2718. return (QLA_MEMORY_ALLOC_FAILED);
  2719. }
  2720. new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
  2721. /* Set start port ID scan at adapter ID. */
  2722. first_dev = 1;
  2723. last_dev = 0;
  2724. /* Starting free loop ID. */
  2725. loop_id = ha->min_external_loopid;
  2726. for (; loop_id <= ha->max_loop_id; loop_id++) {
  2727. if (qla2x00_is_reserved_id(vha, loop_id))
  2728. continue;
  2729. if (ha->current_topology == ISP_CFG_FL &&
  2730. (atomic_read(&vha->loop_down_timer) ||
  2731. LOOP_TRANSITION(vha))) {
  2732. atomic_set(&vha->loop_down_timer, 0);
  2733. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  2734. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2735. break;
  2736. }
  2737. if (swl != NULL) {
  2738. if (last_dev) {
  2739. wrap.b24 = new_fcport->d_id.b24;
  2740. } else {
  2741. new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
  2742. memcpy(new_fcport->node_name,
  2743. swl[swl_idx].node_name, WWN_SIZE);
  2744. memcpy(new_fcport->port_name,
  2745. swl[swl_idx].port_name, WWN_SIZE);
  2746. memcpy(new_fcport->fabric_port_name,
  2747. swl[swl_idx].fabric_port_name, WWN_SIZE);
  2748. new_fcport->fp_speed = swl[swl_idx].fp_speed;
  2749. new_fcport->fc4_type = swl[swl_idx].fc4_type;
  2750. if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
  2751. last_dev = 1;
  2752. }
  2753. swl_idx++;
  2754. }
  2755. } else {
  2756. /* Send GA_NXT to the switch */
  2757. rval = qla2x00_ga_nxt(vha, new_fcport);
  2758. if (rval != QLA_SUCCESS) {
  2759. ql_log(ql_log_warn, vha, 0x2064,
  2760. "SNS scan failed -- assuming "
  2761. "zero-entry result.\n");
  2762. list_for_each_entry_safe(fcport, fcptemp,
  2763. new_fcports, list) {
  2764. list_del(&fcport->list);
  2765. kfree(fcport);
  2766. }
  2767. rval = QLA_SUCCESS;
  2768. break;
  2769. }
  2770. }
  2771. /* If wrap on switch device list, exit. */
  2772. if (first_dev) {
  2773. wrap.b24 = new_fcport->d_id.b24;
  2774. first_dev = 0;
  2775. } else if (new_fcport->d_id.b24 == wrap.b24) {
  2776. ql_dbg(ql_dbg_disc, vha, 0x2065,
  2777. "Device wrap (%02x%02x%02x).\n",
  2778. new_fcport->d_id.b.domain,
  2779. new_fcport->d_id.b.area,
  2780. new_fcport->d_id.b.al_pa);
  2781. break;
  2782. }
  2783. /* Bypass if same physical adapter. */
  2784. if (new_fcport->d_id.b24 == base_vha->d_id.b24)
  2785. continue;
  2786. /* Bypass virtual ports of the same host. */
  2787. found = 0;
  2788. if (ha->num_vhosts) {
  2789. unsigned long flags;
  2790. spin_lock_irqsave(&ha->vport_slock, flags);
  2791. list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
  2792. if (new_fcport->d_id.b24 == vp->d_id.b24) {
  2793. found = 1;
  2794. break;
  2795. }
  2796. }
  2797. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2798. if (found)
  2799. continue;
  2800. }
  2801. /* Bypass if same domain and area of adapter. */
  2802. if (((new_fcport->d_id.b24 & 0xffff00) ==
  2803. (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
  2804. ISP_CFG_FL)
  2805. continue;
  2806. /* Bypass reserved domain fields. */
  2807. if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
  2808. continue;
  2809. /* Bypass ports whose FCP-4 type is not FCP_SCSI */
  2810. if (ql2xgffidenable &&
  2811. (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
  2812. new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
  2813. continue;
  2814. /* Locate matching device in database. */
  2815. found = 0;
  2816. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2817. if (memcmp(new_fcport->port_name, fcport->port_name,
  2818. WWN_SIZE))
  2819. continue;
  2820. fcport->scan_state = QLA_FCPORT_FOUND;
  2821. found++;
  2822. /* Update port state. */
  2823. memcpy(fcport->fabric_port_name,
  2824. new_fcport->fabric_port_name, WWN_SIZE);
  2825. fcport->fp_speed = new_fcport->fp_speed;
  2826. /*
  2827. * If address the same and state FCS_ONLINE, nothing
  2828. * changed.
  2829. */
  2830. if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
  2831. atomic_read(&fcport->state) == FCS_ONLINE) {
  2832. break;
  2833. }
  2834. /*
  2835. * If device was not a fabric device before.
  2836. */
  2837. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
  2838. fcport->d_id.b24 = new_fcport->d_id.b24;
  2839. fcport->loop_id = FC_NO_LOOP_ID;
  2840. fcport->flags |= (FCF_FABRIC_DEVICE |
  2841. FCF_LOGIN_NEEDED);
  2842. break;
  2843. }
  2844. /*
  2845. * Port ID changed or device was marked to be updated;
  2846. * Log it out if still logged in and mark it for
  2847. * relogin later.
  2848. */
  2849. fcport->d_id.b24 = new_fcport->d_id.b24;
  2850. fcport->flags |= FCF_LOGIN_NEEDED;
  2851. if (fcport->loop_id != FC_NO_LOOP_ID &&
  2852. (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
  2853. fcport->port_type != FCT_INITIATOR &&
  2854. fcport->port_type != FCT_BROADCAST) {
  2855. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  2856. fcport->d_id.b.domain, fcport->d_id.b.area,
  2857. fcport->d_id.b.al_pa);
  2858. fcport->loop_id = FC_NO_LOOP_ID;
  2859. }
  2860. break;
  2861. }
  2862. if (found)
  2863. continue;
  2864. /* If device was not in our fcports list, then add it. */
  2865. list_add_tail(&new_fcport->list, new_fcports);
  2866. /* Allocate a new replacement fcport. */
  2867. nxt_d_id.b24 = new_fcport->d_id.b24;
  2868. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2869. if (new_fcport == NULL) {
  2870. ql_log(ql_log_warn, vha, 0x2066,
  2871. "Memory allocation failed for fcport.\n");
  2872. kfree(swl);
  2873. return (QLA_MEMORY_ALLOC_FAILED);
  2874. }
  2875. new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
  2876. new_fcport->d_id.b24 = nxt_d_id.b24;
  2877. }
  2878. kfree(swl);
  2879. kfree(new_fcport);
  2880. return (rval);
  2881. }
  2882. /*
  2883. * qla2x00_find_new_loop_id
  2884. * Scan through our port list and find a new usable loop ID.
  2885. *
  2886. * Input:
  2887. * ha: adapter state pointer.
  2888. * dev: port structure pointer.
  2889. *
  2890. * Returns:
  2891. * qla2x00 local function return status code.
  2892. *
  2893. * Context:
  2894. * Kernel context.
  2895. */
  2896. int
  2897. qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
  2898. {
  2899. int rval;
  2900. int found;
  2901. fc_port_t *fcport;
  2902. uint16_t first_loop_id;
  2903. struct qla_hw_data *ha = vha->hw;
  2904. struct scsi_qla_host *vp;
  2905. struct scsi_qla_host *tvp;
  2906. unsigned long flags = 0;
  2907. rval = QLA_SUCCESS;
  2908. /* Save starting loop ID. */
  2909. first_loop_id = dev->loop_id;
  2910. for (;;) {
  2911. /* Skip loop ID if already used by adapter. */
  2912. if (dev->loop_id == vha->loop_id)
  2913. dev->loop_id++;
  2914. /* Skip reserved loop IDs. */
  2915. while (qla2x00_is_reserved_id(vha, dev->loop_id))
  2916. dev->loop_id++;
  2917. /* Reset loop ID if passed the end. */
  2918. if (dev->loop_id > ha->max_loop_id) {
  2919. /* first loop ID. */
  2920. dev->loop_id = ha->min_external_loopid;
  2921. }
  2922. /* Check for loop ID being already in use. */
  2923. found = 0;
  2924. fcport = NULL;
  2925. spin_lock_irqsave(&ha->vport_slock, flags);
  2926. list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
  2927. list_for_each_entry(fcport, &vp->vp_fcports, list) {
  2928. if (fcport->loop_id == dev->loop_id &&
  2929. fcport != dev) {
  2930. /* ID possibly in use */
  2931. found++;
  2932. break;
  2933. }
  2934. }
  2935. if (found)
  2936. break;
  2937. }
  2938. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2939. /* If not in use then it is free to use. */
  2940. if (!found) {
  2941. ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
  2942. "Assigning new loopid=%x, portid=%x.\n",
  2943. dev->loop_id, dev->d_id.b24);
  2944. break;
  2945. }
  2946. /* ID in use. Try next value. */
  2947. dev->loop_id++;
  2948. /* If wrap around. No free ID to use. */
  2949. if (dev->loop_id == first_loop_id) {
  2950. dev->loop_id = FC_NO_LOOP_ID;
  2951. rval = QLA_FUNCTION_FAILED;
  2952. break;
  2953. }
  2954. }
  2955. return (rval);
  2956. }
  2957. /*
  2958. * qla2x00_fabric_dev_login
  2959. * Login fabric target device and update FC port database.
  2960. *
  2961. * Input:
  2962. * ha: adapter state pointer.
  2963. * fcport: port structure list pointer.
  2964. * next_loopid: contains value of a new loop ID that can be used
  2965. * by the next login attempt.
  2966. *
  2967. * Returns:
  2968. * qla2x00 local function return status code.
  2969. *
  2970. * Context:
  2971. * Kernel context.
  2972. */
  2973. static int
  2974. qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
  2975. uint16_t *next_loopid)
  2976. {
  2977. int rval;
  2978. int retry;
  2979. uint8_t opts;
  2980. struct qla_hw_data *ha = vha->hw;
  2981. rval = QLA_SUCCESS;
  2982. retry = 0;
  2983. if (IS_ALOGIO_CAPABLE(ha)) {
  2984. if (fcport->flags & FCF_ASYNC_SENT)
  2985. return rval;
  2986. fcport->flags |= FCF_ASYNC_SENT;
  2987. rval = qla2x00_post_async_login_work(vha, fcport, NULL);
  2988. if (!rval)
  2989. return rval;
  2990. }
  2991. fcport->flags &= ~FCF_ASYNC_SENT;
  2992. rval = qla2x00_fabric_login(vha, fcport, next_loopid);
  2993. if (rval == QLA_SUCCESS) {
  2994. /* Send an ADISC to FCP2 devices.*/
  2995. opts = 0;
  2996. if (fcport->flags & FCF_FCP2_DEVICE)
  2997. opts |= BIT_1;
  2998. rval = qla2x00_get_port_database(vha, fcport, opts);
  2999. if (rval != QLA_SUCCESS) {
  3000. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  3001. fcport->d_id.b.domain, fcport->d_id.b.area,
  3002. fcport->d_id.b.al_pa);
  3003. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  3004. } else {
  3005. qla2x00_update_fcport(vha, fcport);
  3006. }
  3007. } else {
  3008. /* Retry Login. */
  3009. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  3010. }
  3011. return (rval);
  3012. }
  3013. /*
  3014. * qla2x00_fabric_login
  3015. * Issue fabric login command.
  3016. *
  3017. * Input:
  3018. * ha = adapter block pointer.
  3019. * device = pointer to FC device type structure.
  3020. *
  3021. * Returns:
  3022. * 0 - Login successfully
  3023. * 1 - Login failed
  3024. * 2 - Initiator device
  3025. * 3 - Fatal error
  3026. */
  3027. int
  3028. qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
  3029. uint16_t *next_loopid)
  3030. {
  3031. int rval;
  3032. int retry;
  3033. uint16_t tmp_loopid;
  3034. uint16_t mb[MAILBOX_REGISTER_COUNT];
  3035. struct qla_hw_data *ha = vha->hw;
  3036. retry = 0;
  3037. tmp_loopid = 0;
  3038. for (;;) {
  3039. ql_dbg(ql_dbg_disc, vha, 0x2000,
  3040. "Trying Fabric Login w/loop id 0x%04x for port "
  3041. "%02x%02x%02x.\n",
  3042. fcport->loop_id, fcport->d_id.b.domain,
  3043. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  3044. /* Login fcport on switch. */
  3045. rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
  3046. fcport->d_id.b.domain, fcport->d_id.b.area,
  3047. fcport->d_id.b.al_pa, mb, BIT_0);
  3048. if (rval != QLA_SUCCESS) {
  3049. return rval;
  3050. }
  3051. if (mb[0] == MBS_PORT_ID_USED) {
  3052. /*
  3053. * Device has another loop ID. The firmware team
  3054. * recommends the driver perform an implicit login with
  3055. * the specified ID again. The ID we just used is save
  3056. * here so we return with an ID that can be tried by
  3057. * the next login.
  3058. */
  3059. retry++;
  3060. tmp_loopid = fcport->loop_id;
  3061. fcport->loop_id = mb[1];
  3062. ql_dbg(ql_dbg_disc, vha, 0x2001,
  3063. "Fabric Login: port in use - next loop "
  3064. "id=0x%04x, port id= %02x%02x%02x.\n",
  3065. fcport->loop_id, fcport->d_id.b.domain,
  3066. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  3067. } else if (mb[0] == MBS_COMMAND_COMPLETE) {
  3068. /*
  3069. * Login succeeded.
  3070. */
  3071. if (retry) {
  3072. /* A retry occurred before. */
  3073. *next_loopid = tmp_loopid;
  3074. } else {
  3075. /*
  3076. * No retry occurred before. Just increment the
  3077. * ID value for next login.
  3078. */
  3079. *next_loopid = (fcport->loop_id + 1);
  3080. }
  3081. if (mb[1] & BIT_0) {
  3082. fcport->port_type = FCT_INITIATOR;
  3083. } else {
  3084. fcport->port_type = FCT_TARGET;
  3085. if (mb[1] & BIT_1) {
  3086. fcport->flags |= FCF_FCP2_DEVICE;
  3087. }
  3088. }
  3089. if (mb[10] & BIT_0)
  3090. fcport->supported_classes |= FC_COS_CLASS2;
  3091. if (mb[10] & BIT_1)
  3092. fcport->supported_classes |= FC_COS_CLASS3;
  3093. rval = QLA_SUCCESS;
  3094. break;
  3095. } else if (mb[0] == MBS_LOOP_ID_USED) {
  3096. /*
  3097. * Loop ID already used, try next loop ID.
  3098. */
  3099. fcport->loop_id++;
  3100. rval = qla2x00_find_new_loop_id(vha, fcport);
  3101. if (rval != QLA_SUCCESS) {
  3102. /* Ran out of loop IDs to use */
  3103. break;
  3104. }
  3105. } else if (mb[0] == MBS_COMMAND_ERROR) {
  3106. /*
  3107. * Firmware possibly timed out during login. If NO
  3108. * retries are left to do then the device is declared
  3109. * dead.
  3110. */
  3111. *next_loopid = fcport->loop_id;
  3112. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  3113. fcport->d_id.b.domain, fcport->d_id.b.area,
  3114. fcport->d_id.b.al_pa);
  3115. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  3116. rval = 1;
  3117. break;
  3118. } else {
  3119. /*
  3120. * unrecoverable / not handled error
  3121. */
  3122. ql_dbg(ql_dbg_disc, vha, 0x2002,
  3123. "Failed=%x port_id=%02x%02x%02x loop_id=%x "
  3124. "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
  3125. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  3126. fcport->loop_id, jiffies);
  3127. *next_loopid = fcport->loop_id;
  3128. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  3129. fcport->d_id.b.domain, fcport->d_id.b.area,
  3130. fcport->d_id.b.al_pa);
  3131. fcport->loop_id = FC_NO_LOOP_ID;
  3132. fcport->login_retry = 0;
  3133. rval = 3;
  3134. break;
  3135. }
  3136. }
  3137. return (rval);
  3138. }
  3139. /*
  3140. * qla2x00_local_device_login
  3141. * Issue local device login command.
  3142. *
  3143. * Input:
  3144. * ha = adapter block pointer.
  3145. * loop_id = loop id of device to login to.
  3146. *
  3147. * Returns (Where's the #define!!!!):
  3148. * 0 - Login successfully
  3149. * 1 - Login failed
  3150. * 3 - Fatal error
  3151. */
  3152. int
  3153. qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
  3154. {
  3155. int rval;
  3156. uint16_t mb[MAILBOX_REGISTER_COUNT];
  3157. memset(mb, 0, sizeof(mb));
  3158. rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
  3159. if (rval == QLA_SUCCESS) {
  3160. /* Interrogate mailbox registers for any errors */
  3161. if (mb[0] == MBS_COMMAND_ERROR)
  3162. rval = 1;
  3163. else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
  3164. /* device not in PCB table */
  3165. rval = 3;
  3166. }
  3167. return (rval);
  3168. }
  3169. /*
  3170. * qla2x00_loop_resync
  3171. * Resync with fibre channel devices.
  3172. *
  3173. * Input:
  3174. * ha = adapter block pointer.
  3175. *
  3176. * Returns:
  3177. * 0 = success
  3178. */
  3179. int
  3180. qla2x00_loop_resync(scsi_qla_host_t *vha)
  3181. {
  3182. int rval = QLA_SUCCESS;
  3183. uint32_t wait_time;
  3184. struct req_que *req;
  3185. struct rsp_que *rsp;
  3186. if (vha->hw->flags.cpu_affinity_enabled)
  3187. req = vha->hw->req_q_map[0];
  3188. else
  3189. req = vha->req;
  3190. rsp = req->rsp;
  3191. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3192. if (vha->flags.online) {
  3193. if (!(rval = qla2x00_fw_ready(vha))) {
  3194. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  3195. wait_time = 256;
  3196. do {
  3197. /* Issue a marker after FW becomes ready. */
  3198. qla2x00_marker(vha, req, rsp, 0, 0,
  3199. MK_SYNC_ALL);
  3200. vha->marker_needed = 0;
  3201. /* Remap devices on Loop. */
  3202. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  3203. qla2x00_configure_loop(vha);
  3204. wait_time--;
  3205. } while (!atomic_read(&vha->loop_down_timer) &&
  3206. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  3207. && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
  3208. &vha->dpc_flags)));
  3209. }
  3210. }
  3211. if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  3212. return (QLA_FUNCTION_FAILED);
  3213. if (rval)
  3214. ql_dbg(ql_dbg_disc, vha, 0x206c,
  3215. "%s *** FAILED ***.\n", __func__);
  3216. return (rval);
  3217. }
  3218. /*
  3219. * qla2x00_perform_loop_resync
  3220. * Description: This function will set the appropriate flags and call
  3221. * qla2x00_loop_resync. If successful loop will be resynced
  3222. * Arguments : scsi_qla_host_t pointer
  3223. * returm : Success or Failure
  3224. */
  3225. int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
  3226. {
  3227. int32_t rval = 0;
  3228. if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
  3229. /*Configure the flags so that resync happens properly*/
  3230. atomic_set(&ha->loop_down_timer, 0);
  3231. if (!(ha->device_flags & DFLG_NO_CABLE)) {
  3232. atomic_set(&ha->loop_state, LOOP_UP);
  3233. set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
  3234. set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
  3235. set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
  3236. rval = qla2x00_loop_resync(ha);
  3237. } else
  3238. atomic_set(&ha->loop_state, LOOP_DEAD);
  3239. clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
  3240. }
  3241. return rval;
  3242. }
  3243. void
  3244. qla2x00_update_fcports(scsi_qla_host_t *base_vha)
  3245. {
  3246. fc_port_t *fcport;
  3247. struct scsi_qla_host *vha;
  3248. struct qla_hw_data *ha = base_vha->hw;
  3249. unsigned long flags;
  3250. spin_lock_irqsave(&ha->vport_slock, flags);
  3251. /* Go with deferred removal of rport references. */
  3252. list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
  3253. atomic_inc(&vha->vref_count);
  3254. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  3255. if (fcport->drport &&
  3256. atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
  3257. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3258. qla2x00_rport_del(fcport);
  3259. spin_lock_irqsave(&ha->vport_slock, flags);
  3260. }
  3261. }
  3262. atomic_dec(&vha->vref_count);
  3263. }
  3264. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3265. }
  3266. /*
  3267. * qla82xx_quiescent_state_cleanup
  3268. * Description: This function will block the new I/Os
  3269. * Its not aborting any I/Os as context
  3270. * is not destroyed during quiescence
  3271. * Arguments: scsi_qla_host_t
  3272. * return : void
  3273. */
  3274. void
  3275. qla82xx_quiescent_state_cleanup(scsi_qla_host_t *vha)
  3276. {
  3277. struct qla_hw_data *ha = vha->hw;
  3278. struct scsi_qla_host *vp;
  3279. ql_dbg(ql_dbg_p3p, vha, 0xb002,
  3280. "Performing ISP error recovery - ha=%p.\n", ha);
  3281. atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
  3282. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  3283. atomic_set(&vha->loop_state, LOOP_DOWN);
  3284. qla2x00_mark_all_devices_lost(vha, 0);
  3285. list_for_each_entry(vp, &ha->vp_list, list)
  3286. qla2x00_mark_all_devices_lost(vha, 0);
  3287. } else {
  3288. if (!atomic_read(&vha->loop_down_timer))
  3289. atomic_set(&vha->loop_down_timer,
  3290. LOOP_DOWN_TIME);
  3291. }
  3292. /* Wait for pending cmds to complete */
  3293. qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
  3294. }
  3295. void
  3296. qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
  3297. {
  3298. struct qla_hw_data *ha = vha->hw;
  3299. struct scsi_qla_host *vp;
  3300. unsigned long flags;
  3301. fc_port_t *fcport;
  3302. /* For ISP82XX, driver waits for completion of the commands.
  3303. * online flag should be set.
  3304. */
  3305. if (!IS_QLA82XX(ha))
  3306. vha->flags.online = 0;
  3307. ha->flags.chip_reset_done = 0;
  3308. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  3309. ha->qla_stats.total_isp_aborts++;
  3310. ql_log(ql_log_info, vha, 0x00af,
  3311. "Performing ISP error recovery - ha=%p.\n", ha);
  3312. /* For ISP82XX, reset_chip is just disabling interrupts.
  3313. * Driver waits for the completion of the commands.
  3314. * the interrupts need to be enabled.
  3315. */
  3316. if (!IS_QLA82XX(ha))
  3317. ha->isp_ops->reset_chip(vha);
  3318. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  3319. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  3320. atomic_set(&vha->loop_state, LOOP_DOWN);
  3321. qla2x00_mark_all_devices_lost(vha, 0);
  3322. spin_lock_irqsave(&ha->vport_slock, flags);
  3323. list_for_each_entry(vp, &ha->vp_list, list) {
  3324. atomic_inc(&vp->vref_count);
  3325. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3326. qla2x00_mark_all_devices_lost(vp, 0);
  3327. spin_lock_irqsave(&ha->vport_slock, flags);
  3328. atomic_dec(&vp->vref_count);
  3329. }
  3330. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3331. } else {
  3332. if (!atomic_read(&vha->loop_down_timer))
  3333. atomic_set(&vha->loop_down_timer,
  3334. LOOP_DOWN_TIME);
  3335. }
  3336. /* Clear all async request states across all VPs. */
  3337. list_for_each_entry(fcport, &vha->vp_fcports, list)
  3338. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  3339. spin_lock_irqsave(&ha->vport_slock, flags);
  3340. list_for_each_entry(vp, &ha->vp_list, list) {
  3341. atomic_inc(&vp->vref_count);
  3342. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3343. list_for_each_entry(fcport, &vp->vp_fcports, list)
  3344. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  3345. spin_lock_irqsave(&ha->vport_slock, flags);
  3346. atomic_dec(&vp->vref_count);
  3347. }
  3348. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3349. if (!ha->flags.eeh_busy) {
  3350. /* Make sure for ISP 82XX IO DMA is complete */
  3351. if (IS_QLA82XX(ha)) {
  3352. qla82xx_chip_reset_cleanup(vha);
  3353. ql_log(ql_log_info, vha, 0x00b4,
  3354. "Done chip reset cleanup.\n");
  3355. /* Done waiting for pending commands.
  3356. * Reset the online flag.
  3357. */
  3358. vha->flags.online = 0;
  3359. }
  3360. /* Requeue all commands in outstanding command list. */
  3361. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  3362. }
  3363. }
  3364. /*
  3365. * qla2x00_abort_isp
  3366. * Resets ISP and aborts all outstanding commands.
  3367. *
  3368. * Input:
  3369. * ha = adapter block pointer.
  3370. *
  3371. * Returns:
  3372. * 0 = success
  3373. */
  3374. int
  3375. qla2x00_abort_isp(scsi_qla_host_t *vha)
  3376. {
  3377. int rval;
  3378. uint8_t status = 0;
  3379. struct qla_hw_data *ha = vha->hw;
  3380. struct scsi_qla_host *vp;
  3381. struct req_que *req = ha->req_q_map[0];
  3382. unsigned long flags;
  3383. if (vha->flags.online) {
  3384. qla2x00_abort_isp_cleanup(vha);
  3385. if (unlikely(pci_channel_offline(ha->pdev) &&
  3386. ha->flags.pci_channel_io_perm_failure)) {
  3387. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3388. status = 0;
  3389. return status;
  3390. }
  3391. ha->isp_ops->get_flash_version(vha, req->ring);
  3392. ha->isp_ops->nvram_config(vha);
  3393. if (!qla2x00_restart_isp(vha)) {
  3394. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  3395. if (!atomic_read(&vha->loop_down_timer)) {
  3396. /*
  3397. * Issue marker command only when we are going
  3398. * to start the I/O .
  3399. */
  3400. vha->marker_needed = 1;
  3401. }
  3402. vha->flags.online = 1;
  3403. ha->isp_ops->enable_intrs(ha);
  3404. ha->isp_abort_cnt = 0;
  3405. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3406. if (IS_QLA81XX(ha) || IS_QLA8031(ha))
  3407. qla2x00_get_fw_version(vha);
  3408. if (ha->fce) {
  3409. ha->flags.fce_enabled = 1;
  3410. memset(ha->fce, 0,
  3411. fce_calc_size(ha->fce_bufs));
  3412. rval = qla2x00_enable_fce_trace(vha,
  3413. ha->fce_dma, ha->fce_bufs, ha->fce_mb,
  3414. &ha->fce_bufs);
  3415. if (rval) {
  3416. ql_log(ql_log_warn, vha, 0x8033,
  3417. "Unable to reinitialize FCE "
  3418. "(%d).\n", rval);
  3419. ha->flags.fce_enabled = 0;
  3420. }
  3421. }
  3422. if (ha->eft) {
  3423. memset(ha->eft, 0, EFT_SIZE);
  3424. rval = qla2x00_enable_eft_trace(vha,
  3425. ha->eft_dma, EFT_NUM_BUFFERS);
  3426. if (rval) {
  3427. ql_log(ql_log_warn, vha, 0x8034,
  3428. "Unable to reinitialize EFT "
  3429. "(%d).\n", rval);
  3430. }
  3431. }
  3432. } else { /* failed the ISP abort */
  3433. vha->flags.online = 1;
  3434. if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  3435. if (ha->isp_abort_cnt == 0) {
  3436. ql_log(ql_log_fatal, vha, 0x8035,
  3437. "ISP error recover failed - "
  3438. "board disabled.\n");
  3439. /*
  3440. * The next call disables the board
  3441. * completely.
  3442. */
  3443. ha->isp_ops->reset_adapter(vha);
  3444. vha->flags.online = 0;
  3445. clear_bit(ISP_ABORT_RETRY,
  3446. &vha->dpc_flags);
  3447. status = 0;
  3448. } else { /* schedule another ISP abort */
  3449. ha->isp_abort_cnt--;
  3450. ql_dbg(ql_dbg_taskm, vha, 0x8020,
  3451. "ISP abort - retry remaining %d.\n",
  3452. ha->isp_abort_cnt);
  3453. status = 1;
  3454. }
  3455. } else {
  3456. ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
  3457. ql_dbg(ql_dbg_taskm, vha, 0x8021,
  3458. "ISP error recovery - retrying (%d) "
  3459. "more times.\n", ha->isp_abort_cnt);
  3460. set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3461. status = 1;
  3462. }
  3463. }
  3464. }
  3465. if (!status) {
  3466. ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
  3467. spin_lock_irqsave(&ha->vport_slock, flags);
  3468. list_for_each_entry(vp, &ha->vp_list, list) {
  3469. if (vp->vp_idx) {
  3470. atomic_inc(&vp->vref_count);
  3471. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3472. qla2x00_vp_abort_isp(vp);
  3473. spin_lock_irqsave(&ha->vport_slock, flags);
  3474. atomic_dec(&vp->vref_count);
  3475. }
  3476. }
  3477. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3478. } else {
  3479. ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
  3480. __func__);
  3481. }
  3482. return(status);
  3483. }
  3484. /*
  3485. * qla2x00_restart_isp
  3486. * restarts the ISP after a reset
  3487. *
  3488. * Input:
  3489. * ha = adapter block pointer.
  3490. *
  3491. * Returns:
  3492. * 0 = success
  3493. */
  3494. static int
  3495. qla2x00_restart_isp(scsi_qla_host_t *vha)
  3496. {
  3497. int status = 0;
  3498. uint32_t wait_time;
  3499. struct qla_hw_data *ha = vha->hw;
  3500. struct req_que *req = ha->req_q_map[0];
  3501. struct rsp_que *rsp = ha->rsp_q_map[0];
  3502. /* If firmware needs to be loaded */
  3503. if (qla2x00_isp_firmware(vha)) {
  3504. vha->flags.online = 0;
  3505. status = ha->isp_ops->chip_diag(vha);
  3506. if (!status)
  3507. status = qla2x00_setup_chip(vha);
  3508. }
  3509. if (!status && !(status = qla2x00_init_rings(vha))) {
  3510. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  3511. ha->flags.chip_reset_done = 1;
  3512. /* Initialize the queues in use */
  3513. qla25xx_init_queues(ha);
  3514. status = qla2x00_fw_ready(vha);
  3515. if (!status) {
  3516. ql_dbg(ql_dbg_taskm, vha, 0x8031,
  3517. "Start configure loop status = %d.\n", status);
  3518. /* Issue a marker after FW becomes ready. */
  3519. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  3520. vha->flags.online = 1;
  3521. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  3522. wait_time = 256;
  3523. do {
  3524. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  3525. qla2x00_configure_loop(vha);
  3526. wait_time--;
  3527. } while (!atomic_read(&vha->loop_down_timer) &&
  3528. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  3529. && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
  3530. &vha->dpc_flags)));
  3531. }
  3532. /* if no cable then assume it's good */
  3533. if ((vha->device_flags & DFLG_NO_CABLE))
  3534. status = 0;
  3535. ql_dbg(ql_dbg_taskm, vha, 0x8032,
  3536. "Configure loop done, status = 0x%x.\n", status);
  3537. }
  3538. return (status);
  3539. }
  3540. static int
  3541. qla25xx_init_queues(struct qla_hw_data *ha)
  3542. {
  3543. struct rsp_que *rsp = NULL;
  3544. struct req_que *req = NULL;
  3545. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  3546. int ret = -1;
  3547. int i;
  3548. for (i = 1; i < ha->max_rsp_queues; i++) {
  3549. rsp = ha->rsp_q_map[i];
  3550. if (rsp) {
  3551. rsp->options &= ~BIT_0;
  3552. ret = qla25xx_init_rsp_que(base_vha, rsp);
  3553. if (ret != QLA_SUCCESS)
  3554. ql_dbg(ql_dbg_init, base_vha, 0x00ff,
  3555. "%s Rsp que: %d init failed.\n",
  3556. __func__, rsp->id);
  3557. else
  3558. ql_dbg(ql_dbg_init, base_vha, 0x0100,
  3559. "%s Rsp que: %d inited.\n",
  3560. __func__, rsp->id);
  3561. }
  3562. }
  3563. for (i = 1; i < ha->max_req_queues; i++) {
  3564. req = ha->req_q_map[i];
  3565. if (req) {
  3566. /* Clear outstanding commands array. */
  3567. req->options &= ~BIT_0;
  3568. ret = qla25xx_init_req_que(base_vha, req);
  3569. if (ret != QLA_SUCCESS)
  3570. ql_dbg(ql_dbg_init, base_vha, 0x0101,
  3571. "%s Req que: %d init failed.\n",
  3572. __func__, req->id);
  3573. else
  3574. ql_dbg(ql_dbg_init, base_vha, 0x0102,
  3575. "%s Req que: %d inited.\n",
  3576. __func__, req->id);
  3577. }
  3578. }
  3579. return ret;
  3580. }
  3581. /*
  3582. * qla2x00_reset_adapter
  3583. * Reset adapter.
  3584. *
  3585. * Input:
  3586. * ha = adapter block pointer.
  3587. */
  3588. void
  3589. qla2x00_reset_adapter(scsi_qla_host_t *vha)
  3590. {
  3591. unsigned long flags = 0;
  3592. struct qla_hw_data *ha = vha->hw;
  3593. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  3594. vha->flags.online = 0;
  3595. ha->isp_ops->disable_intrs(ha);
  3596. spin_lock_irqsave(&ha->hardware_lock, flags);
  3597. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  3598. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  3599. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  3600. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  3601. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3602. }
  3603. void
  3604. qla24xx_reset_adapter(scsi_qla_host_t *vha)
  3605. {
  3606. unsigned long flags = 0;
  3607. struct qla_hw_data *ha = vha->hw;
  3608. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  3609. if (IS_QLA82XX(ha))
  3610. return;
  3611. vha->flags.online = 0;
  3612. ha->isp_ops->disable_intrs(ha);
  3613. spin_lock_irqsave(&ha->hardware_lock, flags);
  3614. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
  3615. RD_REG_DWORD(&reg->hccr);
  3616. WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
  3617. RD_REG_DWORD(&reg->hccr);
  3618. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3619. if (IS_NOPOLLING_TYPE(ha))
  3620. ha->isp_ops->enable_intrs(ha);
  3621. }
  3622. /* On sparc systems, obtain port and node WWN from firmware
  3623. * properties.
  3624. */
  3625. static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
  3626. struct nvram_24xx *nv)
  3627. {
  3628. #ifdef CONFIG_SPARC
  3629. struct qla_hw_data *ha = vha->hw;
  3630. struct pci_dev *pdev = ha->pdev;
  3631. struct device_node *dp = pci_device_to_OF_node(pdev);
  3632. const u8 *val;
  3633. int len;
  3634. val = of_get_property(dp, "port-wwn", &len);
  3635. if (val && len >= WWN_SIZE)
  3636. memcpy(nv->port_name, val, WWN_SIZE);
  3637. val = of_get_property(dp, "node-wwn", &len);
  3638. if (val && len >= WWN_SIZE)
  3639. memcpy(nv->node_name, val, WWN_SIZE);
  3640. #endif
  3641. }
  3642. int
  3643. qla24xx_nvram_config(scsi_qla_host_t *vha)
  3644. {
  3645. int rval;
  3646. struct init_cb_24xx *icb;
  3647. struct nvram_24xx *nv;
  3648. uint32_t *dptr;
  3649. uint8_t *dptr1, *dptr2;
  3650. uint32_t chksum;
  3651. uint16_t cnt;
  3652. struct qla_hw_data *ha = vha->hw;
  3653. rval = QLA_SUCCESS;
  3654. icb = (struct init_cb_24xx *)ha->init_cb;
  3655. nv = ha->nvram;
  3656. /* Determine NVRAM starting address. */
  3657. if (ha->flags.port0) {
  3658. ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
  3659. ha->vpd_base = FA_NVRAM_VPD0_ADDR;
  3660. } else {
  3661. ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
  3662. ha->vpd_base = FA_NVRAM_VPD1_ADDR;
  3663. }
  3664. ha->nvram_size = sizeof(struct nvram_24xx);
  3665. ha->vpd_size = FA_NVRAM_VPD_SIZE;
  3666. if (IS_QLA82XX(ha))
  3667. ha->vpd_size = FA_VPD_SIZE_82XX;
  3668. /* Get VPD data into cache */
  3669. ha->vpd = ha->nvram + VPD_OFFSET;
  3670. ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
  3671. ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
  3672. /* Get NVRAM data into cache and calculate checksum. */
  3673. dptr = (uint32_t *)nv;
  3674. ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
  3675. ha->nvram_size);
  3676. for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
  3677. chksum += le32_to_cpu(*dptr++);
  3678. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
  3679. "Contents of NVRAM\n");
  3680. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
  3681. (uint8_t *)nv, ha->nvram_size);
  3682. /* Bad NVRAM data, set defaults parameters. */
  3683. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
  3684. || nv->id[3] != ' ' ||
  3685. nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
  3686. /* Reset NVRAM data. */
  3687. ql_log(ql_log_warn, vha, 0x006b,
  3688. "Inconisistent NVRAM detected: checksum=0x%x id=%c "
  3689. "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
  3690. ql_log(ql_log_warn, vha, 0x006c,
  3691. "Falling back to functioning (yet invalid -- WWPN) "
  3692. "defaults.\n");
  3693. /*
  3694. * Set default initialization control block.
  3695. */
  3696. memset(nv, 0, ha->nvram_size);
  3697. nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
  3698. nv->version = __constant_cpu_to_le16(ICB_VERSION);
  3699. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  3700. nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  3701. nv->exchange_count = __constant_cpu_to_le16(0);
  3702. nv->hard_address = __constant_cpu_to_le16(124);
  3703. nv->port_name[0] = 0x21;
  3704. nv->port_name[1] = 0x00 + ha->port_no;
  3705. nv->port_name[2] = 0x00;
  3706. nv->port_name[3] = 0xe0;
  3707. nv->port_name[4] = 0x8b;
  3708. nv->port_name[5] = 0x1c;
  3709. nv->port_name[6] = 0x55;
  3710. nv->port_name[7] = 0x86;
  3711. nv->node_name[0] = 0x20;
  3712. nv->node_name[1] = 0x00;
  3713. nv->node_name[2] = 0x00;
  3714. nv->node_name[3] = 0xe0;
  3715. nv->node_name[4] = 0x8b;
  3716. nv->node_name[5] = 0x1c;
  3717. nv->node_name[6] = 0x55;
  3718. nv->node_name[7] = 0x86;
  3719. qla24xx_nvram_wwn_from_ofw(vha, nv);
  3720. nv->login_retry_count = __constant_cpu_to_le16(8);
  3721. nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
  3722. nv->login_timeout = __constant_cpu_to_le16(0);
  3723. nv->firmware_options_1 =
  3724. __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
  3725. nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
  3726. nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
  3727. nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
  3728. nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
  3729. nv->efi_parameters = __constant_cpu_to_le32(0);
  3730. nv->reset_delay = 5;
  3731. nv->max_luns_per_target = __constant_cpu_to_le16(128);
  3732. nv->port_down_retry_count = __constant_cpu_to_le16(30);
  3733. nv->link_down_timeout = __constant_cpu_to_le16(30);
  3734. rval = 1;
  3735. }
  3736. /* Reset Initialization control block */
  3737. memset(icb, 0, ha->init_cb_size);
  3738. /* Copy 1st segment. */
  3739. dptr1 = (uint8_t *)icb;
  3740. dptr2 = (uint8_t *)&nv->version;
  3741. cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
  3742. while (cnt--)
  3743. *dptr1++ = *dptr2++;
  3744. icb->login_retry_count = nv->login_retry_count;
  3745. icb->link_down_on_nos = nv->link_down_on_nos;
  3746. /* Copy 2nd segment. */
  3747. dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
  3748. dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
  3749. cnt = (uint8_t *)&icb->reserved_3 -
  3750. (uint8_t *)&icb->interrupt_delay_timer;
  3751. while (cnt--)
  3752. *dptr1++ = *dptr2++;
  3753. /*
  3754. * Setup driver NVRAM options.
  3755. */
  3756. qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
  3757. "QLA2462");
  3758. /* Use alternate WWN? */
  3759. if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
  3760. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  3761. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  3762. }
  3763. /* Prepare nodename */
  3764. if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
  3765. /*
  3766. * Firmware will apply the following mask if the nodename was
  3767. * not provided.
  3768. */
  3769. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  3770. icb->node_name[0] &= 0xF0;
  3771. }
  3772. /* Set host adapter parameters. */
  3773. ha->flags.disable_risc_code_load = 0;
  3774. ha->flags.enable_lip_reset = 0;
  3775. ha->flags.enable_lip_full_login =
  3776. le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
  3777. ha->flags.enable_target_reset =
  3778. le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
  3779. ha->flags.enable_led_scheme = 0;
  3780. ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
  3781. ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
  3782. (BIT_6 | BIT_5 | BIT_4)) >> 4;
  3783. memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
  3784. sizeof(ha->fw_seriallink_options24));
  3785. /* save HBA serial number */
  3786. ha->serial0 = icb->port_name[5];
  3787. ha->serial1 = icb->port_name[6];
  3788. ha->serial2 = icb->port_name[7];
  3789. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  3790. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  3791. icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  3792. ha->retry_count = le16_to_cpu(nv->login_retry_count);
  3793. /* Set minimum login_timeout to 4 seconds. */
  3794. if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
  3795. nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
  3796. if (le16_to_cpu(nv->login_timeout) < 4)
  3797. nv->login_timeout = __constant_cpu_to_le16(4);
  3798. ha->login_timeout = le16_to_cpu(nv->login_timeout);
  3799. icb->login_timeout = nv->login_timeout;
  3800. /* Set minimum RATOV to 100 tenths of a second. */
  3801. ha->r_a_tov = 100;
  3802. ha->loop_reset_delay = nv->reset_delay;
  3803. /* Link Down Timeout = 0:
  3804. *
  3805. * When Port Down timer expires we will start returning
  3806. * I/O's to OS with "DID_NO_CONNECT".
  3807. *
  3808. * Link Down Timeout != 0:
  3809. *
  3810. * The driver waits for the link to come up after link down
  3811. * before returning I/Os to OS with "DID_NO_CONNECT".
  3812. */
  3813. if (le16_to_cpu(nv->link_down_timeout) == 0) {
  3814. ha->loop_down_abort_time =
  3815. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  3816. } else {
  3817. ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
  3818. ha->loop_down_abort_time =
  3819. (LOOP_DOWN_TIME - ha->link_down_timeout);
  3820. }
  3821. /* Need enough time to try and get the port back. */
  3822. ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
  3823. if (qlport_down_retry)
  3824. ha->port_down_retry_count = qlport_down_retry;
  3825. /* Set login_retry_count */
  3826. ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
  3827. if (ha->port_down_retry_count ==
  3828. le16_to_cpu(nv->port_down_retry_count) &&
  3829. ha->port_down_retry_count > 3)
  3830. ha->login_retry_count = ha->port_down_retry_count;
  3831. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  3832. ha->login_retry_count = ha->port_down_retry_count;
  3833. if (ql2xloginretrycount)
  3834. ha->login_retry_count = ql2xloginretrycount;
  3835. /* Enable ZIO. */
  3836. if (!vha->flags.init_done) {
  3837. ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
  3838. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  3839. ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
  3840. le16_to_cpu(icb->interrupt_delay_timer): 2;
  3841. }
  3842. icb->firmware_options_2 &= __constant_cpu_to_le32(
  3843. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
  3844. vha->flags.process_response_queue = 0;
  3845. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  3846. ha->zio_mode = QLA_ZIO_MODE_6;
  3847. ql_log(ql_log_info, vha, 0x006f,
  3848. "ZIO mode %d enabled; timer delay (%d us).\n",
  3849. ha->zio_mode, ha->zio_timer * 100);
  3850. icb->firmware_options_2 |= cpu_to_le32(
  3851. (uint32_t)ha->zio_mode);
  3852. icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
  3853. vha->flags.process_response_queue = 1;
  3854. }
  3855. if (rval) {
  3856. ql_log(ql_log_warn, vha, 0x0070,
  3857. "NVRAM configuration failed.\n");
  3858. }
  3859. return (rval);
  3860. }
  3861. static int
  3862. qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
  3863. uint32_t faddr)
  3864. {
  3865. int rval = QLA_SUCCESS;
  3866. int segments, fragment;
  3867. uint32_t *dcode, dlen;
  3868. uint32_t risc_addr;
  3869. uint32_t risc_size;
  3870. uint32_t i;
  3871. struct qla_hw_data *ha = vha->hw;
  3872. struct req_que *req = ha->req_q_map[0];
  3873. ql_dbg(ql_dbg_init, vha, 0x008b,
  3874. "FW: Loading firmware from flash (%x).\n", faddr);
  3875. rval = QLA_SUCCESS;
  3876. segments = FA_RISC_CODE_SEGMENTS;
  3877. dcode = (uint32_t *)req->ring;
  3878. *srisc_addr = 0;
  3879. /* Validate firmware image by checking version. */
  3880. qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
  3881. for (i = 0; i < 4; i++)
  3882. dcode[i] = be32_to_cpu(dcode[i]);
  3883. if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
  3884. dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
  3885. (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
  3886. dcode[3] == 0)) {
  3887. ql_log(ql_log_fatal, vha, 0x008c,
  3888. "Unable to verify the integrity of flash firmware "
  3889. "image.\n");
  3890. ql_log(ql_log_fatal, vha, 0x008d,
  3891. "Firmware data: %08x %08x %08x %08x.\n",
  3892. dcode[0], dcode[1], dcode[2], dcode[3]);
  3893. return QLA_FUNCTION_FAILED;
  3894. }
  3895. while (segments && rval == QLA_SUCCESS) {
  3896. /* Read segment's load information. */
  3897. qla24xx_read_flash_data(vha, dcode, faddr, 4);
  3898. risc_addr = be32_to_cpu(dcode[2]);
  3899. *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
  3900. risc_size = be32_to_cpu(dcode[3]);
  3901. fragment = 0;
  3902. while (risc_size > 0 && rval == QLA_SUCCESS) {
  3903. dlen = (uint32_t)(ha->fw_transfer_size >> 2);
  3904. if (dlen > risc_size)
  3905. dlen = risc_size;
  3906. ql_dbg(ql_dbg_init, vha, 0x008e,
  3907. "Loading risc segment@ risc addr %x "
  3908. "number of dwords 0x%x offset 0x%x.\n",
  3909. risc_addr, dlen, faddr);
  3910. qla24xx_read_flash_data(vha, dcode, faddr, dlen);
  3911. for (i = 0; i < dlen; i++)
  3912. dcode[i] = swab32(dcode[i]);
  3913. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  3914. dlen);
  3915. if (rval) {
  3916. ql_log(ql_log_fatal, vha, 0x008f,
  3917. "Failed to load segment %d of firmware.\n",
  3918. fragment);
  3919. break;
  3920. }
  3921. faddr += dlen;
  3922. risc_addr += dlen;
  3923. risc_size -= dlen;
  3924. fragment++;
  3925. }
  3926. /* Next segment. */
  3927. segments--;
  3928. }
  3929. return rval;
  3930. }
  3931. #define QLA_FW_URL "ftp://ftp.qlogic.com/outgoing/linux/firmware/"
  3932. int
  3933. qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  3934. {
  3935. int rval;
  3936. int i, fragment;
  3937. uint16_t *wcode, *fwcode;
  3938. uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
  3939. struct fw_blob *blob;
  3940. struct qla_hw_data *ha = vha->hw;
  3941. struct req_que *req = ha->req_q_map[0];
  3942. /* Load firmware blob. */
  3943. blob = qla2x00_request_firmware(vha);
  3944. if (!blob) {
  3945. ql_log(ql_log_info, vha, 0x0083,
  3946. "Fimware image unavailable.\n");
  3947. ql_log(ql_log_info, vha, 0x0084,
  3948. "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
  3949. return QLA_FUNCTION_FAILED;
  3950. }
  3951. rval = QLA_SUCCESS;
  3952. wcode = (uint16_t *)req->ring;
  3953. *srisc_addr = 0;
  3954. fwcode = (uint16_t *)blob->fw->data;
  3955. fwclen = 0;
  3956. /* Validate firmware image by checking version. */
  3957. if (blob->fw->size < 8 * sizeof(uint16_t)) {
  3958. ql_log(ql_log_fatal, vha, 0x0085,
  3959. "Unable to verify integrity of firmware image (%Zd).\n",
  3960. blob->fw->size);
  3961. goto fail_fw_integrity;
  3962. }
  3963. for (i = 0; i < 4; i++)
  3964. wcode[i] = be16_to_cpu(fwcode[i + 4]);
  3965. if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
  3966. wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
  3967. wcode[2] == 0 && wcode[3] == 0)) {
  3968. ql_log(ql_log_fatal, vha, 0x0086,
  3969. "Unable to verify integrity of firmware image.\n");
  3970. ql_log(ql_log_fatal, vha, 0x0087,
  3971. "Firmware data: %04x %04x %04x %04x.\n",
  3972. wcode[0], wcode[1], wcode[2], wcode[3]);
  3973. goto fail_fw_integrity;
  3974. }
  3975. seg = blob->segs;
  3976. while (*seg && rval == QLA_SUCCESS) {
  3977. risc_addr = *seg;
  3978. *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
  3979. risc_size = be16_to_cpu(fwcode[3]);
  3980. /* Validate firmware image size. */
  3981. fwclen += risc_size * sizeof(uint16_t);
  3982. if (blob->fw->size < fwclen) {
  3983. ql_log(ql_log_fatal, vha, 0x0088,
  3984. "Unable to verify integrity of firmware image "
  3985. "(%Zd).\n", blob->fw->size);
  3986. goto fail_fw_integrity;
  3987. }
  3988. fragment = 0;
  3989. while (risc_size > 0 && rval == QLA_SUCCESS) {
  3990. wlen = (uint16_t)(ha->fw_transfer_size >> 1);
  3991. if (wlen > risc_size)
  3992. wlen = risc_size;
  3993. ql_dbg(ql_dbg_init, vha, 0x0089,
  3994. "Loading risc segment@ risc addr %x number of "
  3995. "words 0x%x.\n", risc_addr, wlen);
  3996. for (i = 0; i < wlen; i++)
  3997. wcode[i] = swab16(fwcode[i]);
  3998. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  3999. wlen);
  4000. if (rval) {
  4001. ql_log(ql_log_fatal, vha, 0x008a,
  4002. "Failed to load segment %d of firmware.\n",
  4003. fragment);
  4004. break;
  4005. }
  4006. fwcode += wlen;
  4007. risc_addr += wlen;
  4008. risc_size -= wlen;
  4009. fragment++;
  4010. }
  4011. /* Next segment. */
  4012. seg++;
  4013. }
  4014. return rval;
  4015. fail_fw_integrity:
  4016. return QLA_FUNCTION_FAILED;
  4017. }
  4018. static int
  4019. qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4020. {
  4021. int rval;
  4022. int segments, fragment;
  4023. uint32_t *dcode, dlen;
  4024. uint32_t risc_addr;
  4025. uint32_t risc_size;
  4026. uint32_t i;
  4027. struct fw_blob *blob;
  4028. uint32_t *fwcode, fwclen;
  4029. struct qla_hw_data *ha = vha->hw;
  4030. struct req_que *req = ha->req_q_map[0];
  4031. /* Load firmware blob. */
  4032. blob = qla2x00_request_firmware(vha);
  4033. if (!blob) {
  4034. ql_log(ql_log_warn, vha, 0x0090,
  4035. "Fimware image unavailable.\n");
  4036. ql_log(ql_log_warn, vha, 0x0091,
  4037. "Firmware images can be retrieved from: "
  4038. QLA_FW_URL ".\n");
  4039. return QLA_FUNCTION_FAILED;
  4040. }
  4041. ql_dbg(ql_dbg_init, vha, 0x0092,
  4042. "FW: Loading via request-firmware.\n");
  4043. rval = QLA_SUCCESS;
  4044. segments = FA_RISC_CODE_SEGMENTS;
  4045. dcode = (uint32_t *)req->ring;
  4046. *srisc_addr = 0;
  4047. fwcode = (uint32_t *)blob->fw->data;
  4048. fwclen = 0;
  4049. /* Validate firmware image by checking version. */
  4050. if (blob->fw->size < 8 * sizeof(uint32_t)) {
  4051. ql_log(ql_log_fatal, vha, 0x0093,
  4052. "Unable to verify integrity of firmware image (%Zd).\n",
  4053. blob->fw->size);
  4054. goto fail_fw_integrity;
  4055. }
  4056. for (i = 0; i < 4; i++)
  4057. dcode[i] = be32_to_cpu(fwcode[i + 4]);
  4058. if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
  4059. dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
  4060. (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
  4061. dcode[3] == 0)) {
  4062. ql_log(ql_log_fatal, vha, 0x0094,
  4063. "Unable to verify integrity of firmware image (%Zd).\n",
  4064. blob->fw->size);
  4065. ql_log(ql_log_fatal, vha, 0x0095,
  4066. "Firmware data: %08x %08x %08x %08x.\n",
  4067. dcode[0], dcode[1], dcode[2], dcode[3]);
  4068. goto fail_fw_integrity;
  4069. }
  4070. while (segments && rval == QLA_SUCCESS) {
  4071. risc_addr = be32_to_cpu(fwcode[2]);
  4072. *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
  4073. risc_size = be32_to_cpu(fwcode[3]);
  4074. /* Validate firmware image size. */
  4075. fwclen += risc_size * sizeof(uint32_t);
  4076. if (blob->fw->size < fwclen) {
  4077. ql_log(ql_log_fatal, vha, 0x0096,
  4078. "Unable to verify integrity of firmware image "
  4079. "(%Zd).\n", blob->fw->size);
  4080. goto fail_fw_integrity;
  4081. }
  4082. fragment = 0;
  4083. while (risc_size > 0 && rval == QLA_SUCCESS) {
  4084. dlen = (uint32_t)(ha->fw_transfer_size >> 2);
  4085. if (dlen > risc_size)
  4086. dlen = risc_size;
  4087. ql_dbg(ql_dbg_init, vha, 0x0097,
  4088. "Loading risc segment@ risc addr %x "
  4089. "number of dwords 0x%x.\n", risc_addr, dlen);
  4090. for (i = 0; i < dlen; i++)
  4091. dcode[i] = swab32(fwcode[i]);
  4092. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  4093. dlen);
  4094. if (rval) {
  4095. ql_log(ql_log_fatal, vha, 0x0098,
  4096. "Failed to load segment %d of firmware.\n",
  4097. fragment);
  4098. break;
  4099. }
  4100. fwcode += dlen;
  4101. risc_addr += dlen;
  4102. risc_size -= dlen;
  4103. fragment++;
  4104. }
  4105. /* Next segment. */
  4106. segments--;
  4107. }
  4108. return rval;
  4109. fail_fw_integrity:
  4110. return QLA_FUNCTION_FAILED;
  4111. }
  4112. int
  4113. qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4114. {
  4115. int rval;
  4116. if (ql2xfwloadbin == 1)
  4117. return qla81xx_load_risc(vha, srisc_addr);
  4118. /*
  4119. * FW Load priority:
  4120. * 1) Firmware via request-firmware interface (.bin file).
  4121. * 2) Firmware residing in flash.
  4122. */
  4123. rval = qla24xx_load_risc_blob(vha, srisc_addr);
  4124. if (rval == QLA_SUCCESS)
  4125. return rval;
  4126. return qla24xx_load_risc_flash(vha, srisc_addr,
  4127. vha->hw->flt_region_fw);
  4128. }
  4129. int
  4130. qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4131. {
  4132. int rval;
  4133. struct qla_hw_data *ha = vha->hw;
  4134. if (ql2xfwloadbin == 2)
  4135. goto try_blob_fw;
  4136. /*
  4137. * FW Load priority:
  4138. * 1) Firmware residing in flash.
  4139. * 2) Firmware via request-firmware interface (.bin file).
  4140. * 3) Golden-Firmware residing in flash -- limited operation.
  4141. */
  4142. rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
  4143. if (rval == QLA_SUCCESS)
  4144. return rval;
  4145. try_blob_fw:
  4146. rval = qla24xx_load_risc_blob(vha, srisc_addr);
  4147. if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
  4148. return rval;
  4149. ql_log(ql_log_info, vha, 0x0099,
  4150. "Attempting to fallback to golden firmware.\n");
  4151. rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
  4152. if (rval != QLA_SUCCESS)
  4153. return rval;
  4154. ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
  4155. ha->flags.running_gold_fw = 1;
  4156. return rval;
  4157. }
  4158. void
  4159. qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
  4160. {
  4161. int ret, retries;
  4162. struct qla_hw_data *ha = vha->hw;
  4163. if (ha->flags.pci_channel_io_perm_failure)
  4164. return;
  4165. if (!IS_FWI2_CAPABLE(ha))
  4166. return;
  4167. if (!ha->fw_major_version)
  4168. return;
  4169. ret = qla2x00_stop_firmware(vha);
  4170. for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
  4171. ret != QLA_INVALID_COMMAND && retries ; retries--) {
  4172. ha->isp_ops->reset_chip(vha);
  4173. if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
  4174. continue;
  4175. if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
  4176. continue;
  4177. ql_log(ql_log_info, vha, 0x8015,
  4178. "Attempting retry of stop-firmware command.\n");
  4179. ret = qla2x00_stop_firmware(vha);
  4180. }
  4181. }
  4182. int
  4183. qla24xx_configure_vhba(scsi_qla_host_t *vha)
  4184. {
  4185. int rval = QLA_SUCCESS;
  4186. int rval2;
  4187. uint16_t mb[MAILBOX_REGISTER_COUNT];
  4188. struct qla_hw_data *ha = vha->hw;
  4189. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  4190. struct req_que *req;
  4191. struct rsp_que *rsp;
  4192. if (!vha->vp_idx)
  4193. return -EINVAL;
  4194. rval = qla2x00_fw_ready(base_vha);
  4195. if (ha->flags.cpu_affinity_enabled)
  4196. req = ha->req_q_map[0];
  4197. else
  4198. req = vha->req;
  4199. rsp = req->rsp;
  4200. if (rval == QLA_SUCCESS) {
  4201. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4202. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  4203. }
  4204. vha->flags.management_server_logged_in = 0;
  4205. /* Login to SNS first */
  4206. rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
  4207. BIT_1);
  4208. if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
  4209. if (rval2 == QLA_MEMORY_ALLOC_FAILED)
  4210. ql_dbg(ql_dbg_init, vha, 0x0120,
  4211. "Failed SNS login: loop_id=%x, rval2=%d\n",
  4212. NPH_SNS, rval2);
  4213. else
  4214. ql_dbg(ql_dbg_init, vha, 0x0103,
  4215. "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
  4216. "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
  4217. NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
  4218. return (QLA_FUNCTION_FAILED);
  4219. }
  4220. atomic_set(&vha->loop_down_timer, 0);
  4221. atomic_set(&vha->loop_state, LOOP_UP);
  4222. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  4223. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  4224. rval = qla2x00_loop_resync(base_vha);
  4225. return rval;
  4226. }
  4227. /* 84XX Support **************************************************************/
  4228. static LIST_HEAD(qla_cs84xx_list);
  4229. static DEFINE_MUTEX(qla_cs84xx_mutex);
  4230. static struct qla_chip_state_84xx *
  4231. qla84xx_get_chip(struct scsi_qla_host *vha)
  4232. {
  4233. struct qla_chip_state_84xx *cs84xx;
  4234. struct qla_hw_data *ha = vha->hw;
  4235. mutex_lock(&qla_cs84xx_mutex);
  4236. /* Find any shared 84xx chip. */
  4237. list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
  4238. if (cs84xx->bus == ha->pdev->bus) {
  4239. kref_get(&cs84xx->kref);
  4240. goto done;
  4241. }
  4242. }
  4243. cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
  4244. if (!cs84xx)
  4245. goto done;
  4246. kref_init(&cs84xx->kref);
  4247. spin_lock_init(&cs84xx->access_lock);
  4248. mutex_init(&cs84xx->fw_update_mutex);
  4249. cs84xx->bus = ha->pdev->bus;
  4250. list_add_tail(&cs84xx->list, &qla_cs84xx_list);
  4251. done:
  4252. mutex_unlock(&qla_cs84xx_mutex);
  4253. return cs84xx;
  4254. }
  4255. static void
  4256. __qla84xx_chip_release(struct kref *kref)
  4257. {
  4258. struct qla_chip_state_84xx *cs84xx =
  4259. container_of(kref, struct qla_chip_state_84xx, kref);
  4260. mutex_lock(&qla_cs84xx_mutex);
  4261. list_del(&cs84xx->list);
  4262. mutex_unlock(&qla_cs84xx_mutex);
  4263. kfree(cs84xx);
  4264. }
  4265. void
  4266. qla84xx_put_chip(struct scsi_qla_host *vha)
  4267. {
  4268. struct qla_hw_data *ha = vha->hw;
  4269. if (ha->cs84xx)
  4270. kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
  4271. }
  4272. static int
  4273. qla84xx_init_chip(scsi_qla_host_t *vha)
  4274. {
  4275. int rval;
  4276. uint16_t status[2];
  4277. struct qla_hw_data *ha = vha->hw;
  4278. mutex_lock(&ha->cs84xx->fw_update_mutex);
  4279. rval = qla84xx_verify_chip(vha, status);
  4280. mutex_unlock(&ha->cs84xx->fw_update_mutex);
  4281. return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
  4282. QLA_SUCCESS;
  4283. }
  4284. /* 81XX Support **************************************************************/
  4285. int
  4286. qla81xx_nvram_config(scsi_qla_host_t *vha)
  4287. {
  4288. int rval;
  4289. struct init_cb_81xx *icb;
  4290. struct nvram_81xx *nv;
  4291. uint32_t *dptr;
  4292. uint8_t *dptr1, *dptr2;
  4293. uint32_t chksum;
  4294. uint16_t cnt;
  4295. struct qla_hw_data *ha = vha->hw;
  4296. rval = QLA_SUCCESS;
  4297. icb = (struct init_cb_81xx *)ha->init_cb;
  4298. nv = ha->nvram;
  4299. /* Determine NVRAM starting address. */
  4300. ha->nvram_size = sizeof(struct nvram_81xx);
  4301. ha->vpd_size = FA_NVRAM_VPD_SIZE;
  4302. /* Get VPD data into cache */
  4303. ha->vpd = ha->nvram + VPD_OFFSET;
  4304. ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
  4305. ha->vpd_size);
  4306. /* Get NVRAM data into cache and calculate checksum. */
  4307. ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
  4308. ha->nvram_size);
  4309. dptr = (uint32_t *)nv;
  4310. for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
  4311. chksum += le32_to_cpu(*dptr++);
  4312. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
  4313. "Contents of NVRAM:\n");
  4314. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
  4315. (uint8_t *)nv, ha->nvram_size);
  4316. /* Bad NVRAM data, set defaults parameters. */
  4317. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
  4318. || nv->id[3] != ' ' ||
  4319. nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
  4320. /* Reset NVRAM data. */
  4321. ql_log(ql_log_info, vha, 0x0073,
  4322. "Inconisistent NVRAM detected: checksum=0x%x id=%c "
  4323. "version=0x%x.\n", chksum, nv->id[0],
  4324. le16_to_cpu(nv->nvram_version));
  4325. ql_log(ql_log_info, vha, 0x0074,
  4326. "Falling back to functioning (yet invalid -- WWPN) "
  4327. "defaults.\n");
  4328. /*
  4329. * Set default initialization control block.
  4330. */
  4331. memset(nv, 0, ha->nvram_size);
  4332. nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
  4333. nv->version = __constant_cpu_to_le16(ICB_VERSION);
  4334. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  4335. nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  4336. nv->exchange_count = __constant_cpu_to_le16(0);
  4337. nv->port_name[0] = 0x21;
  4338. nv->port_name[1] = 0x00 + ha->port_no;
  4339. nv->port_name[2] = 0x00;
  4340. nv->port_name[3] = 0xe0;
  4341. nv->port_name[4] = 0x8b;
  4342. nv->port_name[5] = 0x1c;
  4343. nv->port_name[6] = 0x55;
  4344. nv->port_name[7] = 0x86;
  4345. nv->node_name[0] = 0x20;
  4346. nv->node_name[1] = 0x00;
  4347. nv->node_name[2] = 0x00;
  4348. nv->node_name[3] = 0xe0;
  4349. nv->node_name[4] = 0x8b;
  4350. nv->node_name[5] = 0x1c;
  4351. nv->node_name[6] = 0x55;
  4352. nv->node_name[7] = 0x86;
  4353. nv->login_retry_count = __constant_cpu_to_le16(8);
  4354. nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
  4355. nv->login_timeout = __constant_cpu_to_le16(0);
  4356. nv->firmware_options_1 =
  4357. __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
  4358. nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
  4359. nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
  4360. nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
  4361. nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
  4362. nv->efi_parameters = __constant_cpu_to_le32(0);
  4363. nv->reset_delay = 5;
  4364. nv->max_luns_per_target = __constant_cpu_to_le16(128);
  4365. nv->port_down_retry_count = __constant_cpu_to_le16(30);
  4366. nv->link_down_timeout = __constant_cpu_to_le16(180);
  4367. nv->enode_mac[0] = 0x00;
  4368. nv->enode_mac[1] = 0xC0;
  4369. nv->enode_mac[2] = 0xDD;
  4370. nv->enode_mac[3] = 0x04;
  4371. nv->enode_mac[4] = 0x05;
  4372. nv->enode_mac[5] = 0x06 + ha->port_no;
  4373. rval = 1;
  4374. }
  4375. /* Reset Initialization control block */
  4376. memset(icb, 0, ha->init_cb_size);
  4377. /* Copy 1st segment. */
  4378. dptr1 = (uint8_t *)icb;
  4379. dptr2 = (uint8_t *)&nv->version;
  4380. cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
  4381. while (cnt--)
  4382. *dptr1++ = *dptr2++;
  4383. icb->login_retry_count = nv->login_retry_count;
  4384. /* Copy 2nd segment. */
  4385. dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
  4386. dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
  4387. cnt = (uint8_t *)&icb->reserved_5 -
  4388. (uint8_t *)&icb->interrupt_delay_timer;
  4389. while (cnt--)
  4390. *dptr1++ = *dptr2++;
  4391. memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
  4392. /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
  4393. if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
  4394. icb->enode_mac[0] = 0x00;
  4395. icb->enode_mac[1] = 0xC0;
  4396. icb->enode_mac[2] = 0xDD;
  4397. icb->enode_mac[3] = 0x04;
  4398. icb->enode_mac[4] = 0x05;
  4399. icb->enode_mac[5] = 0x06 + ha->port_no;
  4400. }
  4401. /* Use extended-initialization control block. */
  4402. memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
  4403. /*
  4404. * Setup driver NVRAM options.
  4405. */
  4406. qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
  4407. "QLE8XXX");
  4408. /* Use alternate WWN? */
  4409. if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
  4410. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  4411. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  4412. }
  4413. /* Prepare nodename */
  4414. if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
  4415. /*
  4416. * Firmware will apply the following mask if the nodename was
  4417. * not provided.
  4418. */
  4419. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  4420. icb->node_name[0] &= 0xF0;
  4421. }
  4422. /* Set host adapter parameters. */
  4423. ha->flags.disable_risc_code_load = 0;
  4424. ha->flags.enable_lip_reset = 0;
  4425. ha->flags.enable_lip_full_login =
  4426. le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
  4427. ha->flags.enable_target_reset =
  4428. le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
  4429. ha->flags.enable_led_scheme = 0;
  4430. ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
  4431. ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
  4432. (BIT_6 | BIT_5 | BIT_4)) >> 4;
  4433. /* save HBA serial number */
  4434. ha->serial0 = icb->port_name[5];
  4435. ha->serial1 = icb->port_name[6];
  4436. ha->serial2 = icb->port_name[7];
  4437. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  4438. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  4439. icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  4440. ha->retry_count = le16_to_cpu(nv->login_retry_count);
  4441. /* Set minimum login_timeout to 4 seconds. */
  4442. if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
  4443. nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
  4444. if (le16_to_cpu(nv->login_timeout) < 4)
  4445. nv->login_timeout = __constant_cpu_to_le16(4);
  4446. ha->login_timeout = le16_to_cpu(nv->login_timeout);
  4447. icb->login_timeout = nv->login_timeout;
  4448. /* Set minimum RATOV to 100 tenths of a second. */
  4449. ha->r_a_tov = 100;
  4450. ha->loop_reset_delay = nv->reset_delay;
  4451. /* Link Down Timeout = 0:
  4452. *
  4453. * When Port Down timer expires we will start returning
  4454. * I/O's to OS with "DID_NO_CONNECT".
  4455. *
  4456. * Link Down Timeout != 0:
  4457. *
  4458. * The driver waits for the link to come up after link down
  4459. * before returning I/Os to OS with "DID_NO_CONNECT".
  4460. */
  4461. if (le16_to_cpu(nv->link_down_timeout) == 0) {
  4462. ha->loop_down_abort_time =
  4463. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  4464. } else {
  4465. ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
  4466. ha->loop_down_abort_time =
  4467. (LOOP_DOWN_TIME - ha->link_down_timeout);
  4468. }
  4469. /* Need enough time to try and get the port back. */
  4470. ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
  4471. if (qlport_down_retry)
  4472. ha->port_down_retry_count = qlport_down_retry;
  4473. /* Set login_retry_count */
  4474. ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
  4475. if (ha->port_down_retry_count ==
  4476. le16_to_cpu(nv->port_down_retry_count) &&
  4477. ha->port_down_retry_count > 3)
  4478. ha->login_retry_count = ha->port_down_retry_count;
  4479. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  4480. ha->login_retry_count = ha->port_down_retry_count;
  4481. if (ql2xloginretrycount)
  4482. ha->login_retry_count = ql2xloginretrycount;
  4483. /* if not running MSI-X we need handshaking on interrupts */
  4484. if (!vha->hw->flags.msix_enabled && IS_QLA83XX(ha))
  4485. icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_22);
  4486. /* Enable ZIO. */
  4487. if (!vha->flags.init_done) {
  4488. ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
  4489. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  4490. ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
  4491. le16_to_cpu(icb->interrupt_delay_timer): 2;
  4492. }
  4493. icb->firmware_options_2 &= __constant_cpu_to_le32(
  4494. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
  4495. vha->flags.process_response_queue = 0;
  4496. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  4497. ha->zio_mode = QLA_ZIO_MODE_6;
  4498. ql_log(ql_log_info, vha, 0x0075,
  4499. "ZIO mode %d enabled; timer delay (%d us).\n",
  4500. ha->zio_mode,
  4501. ha->zio_timer * 100);
  4502. icb->firmware_options_2 |= cpu_to_le32(
  4503. (uint32_t)ha->zio_mode);
  4504. icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
  4505. vha->flags.process_response_queue = 1;
  4506. }
  4507. if (rval) {
  4508. ql_log(ql_log_warn, vha, 0x0076,
  4509. "NVRAM configuration failed.\n");
  4510. }
  4511. return (rval);
  4512. }
  4513. int
  4514. qla82xx_restart_isp(scsi_qla_host_t *vha)
  4515. {
  4516. int status, rval;
  4517. uint32_t wait_time;
  4518. struct qla_hw_data *ha = vha->hw;
  4519. struct req_que *req = ha->req_q_map[0];
  4520. struct rsp_que *rsp = ha->rsp_q_map[0];
  4521. struct scsi_qla_host *vp;
  4522. unsigned long flags;
  4523. status = qla2x00_init_rings(vha);
  4524. if (!status) {
  4525. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4526. ha->flags.chip_reset_done = 1;
  4527. status = qla2x00_fw_ready(vha);
  4528. if (!status) {
  4529. ql_log(ql_log_info, vha, 0x803c,
  4530. "Start configure loop, status =%d.\n", status);
  4531. /* Issue a marker after FW becomes ready. */
  4532. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  4533. vha->flags.online = 1;
  4534. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  4535. wait_time = 256;
  4536. do {
  4537. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  4538. qla2x00_configure_loop(vha);
  4539. wait_time--;
  4540. } while (!atomic_read(&vha->loop_down_timer) &&
  4541. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) &&
  4542. wait_time &&
  4543. (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)));
  4544. }
  4545. /* if no cable then assume it's good */
  4546. if ((vha->device_flags & DFLG_NO_CABLE))
  4547. status = 0;
  4548. ql_log(ql_log_info, vha, 0x8000,
  4549. "Configure loop done, status = 0x%x.\n", status);
  4550. }
  4551. if (!status) {
  4552. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4553. if (!atomic_read(&vha->loop_down_timer)) {
  4554. /*
  4555. * Issue marker command only when we are going
  4556. * to start the I/O .
  4557. */
  4558. vha->marker_needed = 1;
  4559. }
  4560. vha->flags.online = 1;
  4561. ha->isp_ops->enable_intrs(ha);
  4562. ha->isp_abort_cnt = 0;
  4563. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  4564. /* Update the firmware version */
  4565. status = qla82xx_check_md_needed(vha);
  4566. if (ha->fce) {
  4567. ha->flags.fce_enabled = 1;
  4568. memset(ha->fce, 0,
  4569. fce_calc_size(ha->fce_bufs));
  4570. rval = qla2x00_enable_fce_trace(vha,
  4571. ha->fce_dma, ha->fce_bufs, ha->fce_mb,
  4572. &ha->fce_bufs);
  4573. if (rval) {
  4574. ql_log(ql_log_warn, vha, 0x8001,
  4575. "Unable to reinitialize FCE (%d).\n",
  4576. rval);
  4577. ha->flags.fce_enabled = 0;
  4578. }
  4579. }
  4580. if (ha->eft) {
  4581. memset(ha->eft, 0, EFT_SIZE);
  4582. rval = qla2x00_enable_eft_trace(vha,
  4583. ha->eft_dma, EFT_NUM_BUFFERS);
  4584. if (rval) {
  4585. ql_log(ql_log_warn, vha, 0x8010,
  4586. "Unable to reinitialize EFT (%d).\n",
  4587. rval);
  4588. }
  4589. }
  4590. }
  4591. if (!status) {
  4592. ql_dbg(ql_dbg_taskm, vha, 0x8011,
  4593. "qla82xx_restart_isp succeeded.\n");
  4594. spin_lock_irqsave(&ha->vport_slock, flags);
  4595. list_for_each_entry(vp, &ha->vp_list, list) {
  4596. if (vp->vp_idx) {
  4597. atomic_inc(&vp->vref_count);
  4598. spin_unlock_irqrestore(&ha->vport_slock, flags);
  4599. qla2x00_vp_abort_isp(vp);
  4600. spin_lock_irqsave(&ha->vport_slock, flags);
  4601. atomic_dec(&vp->vref_count);
  4602. }
  4603. }
  4604. spin_unlock_irqrestore(&ha->vport_slock, flags);
  4605. } else {
  4606. ql_log(ql_log_warn, vha, 0x8016,
  4607. "qla82xx_restart_isp **** FAILED ****.\n");
  4608. }
  4609. return status;
  4610. }
  4611. void
  4612. qla81xx_update_fw_options(scsi_qla_host_t *vha)
  4613. {
  4614. struct qla_hw_data *ha = vha->hw;
  4615. if (!ql2xetsenable)
  4616. return;
  4617. /* Enable ETS Burst. */
  4618. memset(ha->fw_options, 0, sizeof(ha->fw_options));
  4619. ha->fw_options[2] |= BIT_9;
  4620. qla2x00_set_fw_options(vha, ha->fw_options);
  4621. }
  4622. /*
  4623. * qla24xx_get_fcp_prio
  4624. * Gets the fcp cmd priority value for the logged in port.
  4625. * Looks for a match of the port descriptors within
  4626. * each of the fcp prio config entries. If a match is found,
  4627. * the tag (priority) value is returned.
  4628. *
  4629. * Input:
  4630. * vha = scsi host structure pointer.
  4631. * fcport = port structure pointer.
  4632. *
  4633. * Return:
  4634. * non-zero (if found)
  4635. * -1 (if not found)
  4636. *
  4637. * Context:
  4638. * Kernel context
  4639. */
  4640. static int
  4641. qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
  4642. {
  4643. int i, entries;
  4644. uint8_t pid_match, wwn_match;
  4645. int priority;
  4646. uint32_t pid1, pid2;
  4647. uint64_t wwn1, wwn2;
  4648. struct qla_fcp_prio_entry *pri_entry;
  4649. struct qla_hw_data *ha = vha->hw;
  4650. if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
  4651. return -1;
  4652. priority = -1;
  4653. entries = ha->fcp_prio_cfg->num_entries;
  4654. pri_entry = &ha->fcp_prio_cfg->entry[0];
  4655. for (i = 0; i < entries; i++) {
  4656. pid_match = wwn_match = 0;
  4657. if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
  4658. pri_entry++;
  4659. continue;
  4660. }
  4661. /* check source pid for a match */
  4662. if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
  4663. pid1 = pri_entry->src_pid & INVALID_PORT_ID;
  4664. pid2 = vha->d_id.b24 & INVALID_PORT_ID;
  4665. if (pid1 == INVALID_PORT_ID)
  4666. pid_match++;
  4667. else if (pid1 == pid2)
  4668. pid_match++;
  4669. }
  4670. /* check destination pid for a match */
  4671. if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
  4672. pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
  4673. pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
  4674. if (pid1 == INVALID_PORT_ID)
  4675. pid_match++;
  4676. else if (pid1 == pid2)
  4677. pid_match++;
  4678. }
  4679. /* check source WWN for a match */
  4680. if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
  4681. wwn1 = wwn_to_u64(vha->port_name);
  4682. wwn2 = wwn_to_u64(pri_entry->src_wwpn);
  4683. if (wwn2 == (uint64_t)-1)
  4684. wwn_match++;
  4685. else if (wwn1 == wwn2)
  4686. wwn_match++;
  4687. }
  4688. /* check destination WWN for a match */
  4689. if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
  4690. wwn1 = wwn_to_u64(fcport->port_name);
  4691. wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
  4692. if (wwn2 == (uint64_t)-1)
  4693. wwn_match++;
  4694. else if (wwn1 == wwn2)
  4695. wwn_match++;
  4696. }
  4697. if (pid_match == 2 || wwn_match == 2) {
  4698. /* Found a matching entry */
  4699. if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
  4700. priority = pri_entry->tag;
  4701. break;
  4702. }
  4703. pri_entry++;
  4704. }
  4705. return priority;
  4706. }
  4707. /*
  4708. * qla24xx_update_fcport_fcp_prio
  4709. * Activates fcp priority for the logged in fc port
  4710. *
  4711. * Input:
  4712. * vha = scsi host structure pointer.
  4713. * fcp = port structure pointer.
  4714. *
  4715. * Return:
  4716. * QLA_SUCCESS or QLA_FUNCTION_FAILED
  4717. *
  4718. * Context:
  4719. * Kernel context.
  4720. */
  4721. int
  4722. qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
  4723. {
  4724. int ret;
  4725. int priority;
  4726. uint16_t mb[5];
  4727. if (fcport->port_type != FCT_TARGET ||
  4728. fcport->loop_id == FC_NO_LOOP_ID)
  4729. return QLA_FUNCTION_FAILED;
  4730. priority = qla24xx_get_fcp_prio(vha, fcport);
  4731. if (priority < 0)
  4732. return QLA_FUNCTION_FAILED;
  4733. if (IS_QLA82XX(vha->hw)) {
  4734. fcport->fcp_prio = priority & 0xf;
  4735. return QLA_SUCCESS;
  4736. }
  4737. ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
  4738. if (ret == QLA_SUCCESS) {
  4739. if (fcport->fcp_prio != priority)
  4740. ql_dbg(ql_dbg_user, vha, 0x709e,
  4741. "Updated FCP_CMND priority - value=%d loop_id=%d "
  4742. "port_id=%02x%02x%02x.\n", priority,
  4743. fcport->loop_id, fcport->d_id.b.domain,
  4744. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  4745. fcport->fcp_prio = priority & 0xf;
  4746. } else
  4747. ql_dbg(ql_dbg_user, vha, 0x704f,
  4748. "Unable to update FCP_CMND priority - ret=0x%x for "
  4749. "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
  4750. fcport->d_id.b.domain, fcport->d_id.b.area,
  4751. fcport->d_id.b.al_pa);
  4752. return ret;
  4753. }
  4754. /*
  4755. * qla24xx_update_all_fcp_prio
  4756. * Activates fcp priority for all the logged in ports
  4757. *
  4758. * Input:
  4759. * ha = adapter block pointer.
  4760. *
  4761. * Return:
  4762. * QLA_SUCCESS or QLA_FUNCTION_FAILED
  4763. *
  4764. * Context:
  4765. * Kernel context.
  4766. */
  4767. int
  4768. qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
  4769. {
  4770. int ret;
  4771. fc_port_t *fcport;
  4772. ret = QLA_FUNCTION_FAILED;
  4773. /* We need to set priority for all logged in ports */
  4774. list_for_each_entry(fcport, &vha->vp_fcports, list)
  4775. ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
  4776. return ret;
  4777. }