intel_display.c 247 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/dmi.h>
  27. #include <linux/module.h>
  28. #include <linux/input.h>
  29. #include <linux/i2c.h>
  30. #include <linux/kernel.h>
  31. #include <linux/slab.h>
  32. #include <linux/vgaarb.h>
  33. #include <drm/drm_edid.h>
  34. #include <drm/drmP.h>
  35. #include "intel_drv.h"
  36. #include <drm/i915_drm.h>
  37. #include "i915_drv.h"
  38. #include "i915_trace.h"
  39. #include <drm/drm_dp_helper.h>
  40. #include <drm/drm_crtc_helper.h>
  41. #include <linux/dma_remapping.h>
  42. bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  43. static void intel_increase_pllclock(struct drm_crtc *crtc);
  44. static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  45. typedef struct {
  46. /* given values */
  47. int n;
  48. int m1, m2;
  49. int p1, p2;
  50. /* derived values */
  51. int dot;
  52. int vco;
  53. int m;
  54. int p;
  55. } intel_clock_t;
  56. typedef struct {
  57. int min, max;
  58. } intel_range_t;
  59. typedef struct {
  60. int dot_limit;
  61. int p2_slow, p2_fast;
  62. } intel_p2_t;
  63. #define INTEL_P2_NUM 2
  64. typedef struct intel_limit intel_limit_t;
  65. struct intel_limit {
  66. intel_range_t dot, vco, n, m, m1, m2, p, p1;
  67. intel_p2_t p2;
  68. bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  69. int, int, intel_clock_t *, intel_clock_t *);
  70. };
  71. /* FDI */
  72. #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
  73. int
  74. intel_pch_rawclk(struct drm_device *dev)
  75. {
  76. struct drm_i915_private *dev_priv = dev->dev_private;
  77. WARN_ON(!HAS_PCH_SPLIT(dev));
  78. return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  79. }
  80. static bool
  81. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  82. int target, int refclk, intel_clock_t *match_clock,
  83. intel_clock_t *best_clock);
  84. static bool
  85. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  86. int target, int refclk, intel_clock_t *match_clock,
  87. intel_clock_t *best_clock);
  88. static bool
  89. intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  90. int target, int refclk, intel_clock_t *match_clock,
  91. intel_clock_t *best_clock);
  92. static bool
  93. intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  94. int target, int refclk, intel_clock_t *match_clock,
  95. intel_clock_t *best_clock);
  96. static bool
  97. intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
  98. int target, int refclk, intel_clock_t *match_clock,
  99. intel_clock_t *best_clock);
  100. static inline u32 /* units of 100MHz */
  101. intel_fdi_link_freq(struct drm_device *dev)
  102. {
  103. if (IS_GEN5(dev)) {
  104. struct drm_i915_private *dev_priv = dev->dev_private;
  105. return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  106. } else
  107. return 27;
  108. }
  109. static const intel_limit_t intel_limits_i8xx_dvo = {
  110. .dot = { .min = 25000, .max = 350000 },
  111. .vco = { .min = 930000, .max = 1400000 },
  112. .n = { .min = 3, .max = 16 },
  113. .m = { .min = 96, .max = 140 },
  114. .m1 = { .min = 18, .max = 26 },
  115. .m2 = { .min = 6, .max = 16 },
  116. .p = { .min = 4, .max = 128 },
  117. .p1 = { .min = 2, .max = 33 },
  118. .p2 = { .dot_limit = 165000,
  119. .p2_slow = 4, .p2_fast = 2 },
  120. .find_pll = intel_find_best_PLL,
  121. };
  122. static const intel_limit_t intel_limits_i8xx_lvds = {
  123. .dot = { .min = 25000, .max = 350000 },
  124. .vco = { .min = 930000, .max = 1400000 },
  125. .n = { .min = 3, .max = 16 },
  126. .m = { .min = 96, .max = 140 },
  127. .m1 = { .min = 18, .max = 26 },
  128. .m2 = { .min = 6, .max = 16 },
  129. .p = { .min = 4, .max = 128 },
  130. .p1 = { .min = 1, .max = 6 },
  131. .p2 = { .dot_limit = 165000,
  132. .p2_slow = 14, .p2_fast = 7 },
  133. .find_pll = intel_find_best_PLL,
  134. };
  135. static const intel_limit_t intel_limits_i9xx_sdvo = {
  136. .dot = { .min = 20000, .max = 400000 },
  137. .vco = { .min = 1400000, .max = 2800000 },
  138. .n = { .min = 1, .max = 6 },
  139. .m = { .min = 70, .max = 120 },
  140. .m1 = { .min = 10, .max = 22 },
  141. .m2 = { .min = 5, .max = 9 },
  142. .p = { .min = 5, .max = 80 },
  143. .p1 = { .min = 1, .max = 8 },
  144. .p2 = { .dot_limit = 200000,
  145. .p2_slow = 10, .p2_fast = 5 },
  146. .find_pll = intel_find_best_PLL,
  147. };
  148. static const intel_limit_t intel_limits_i9xx_lvds = {
  149. .dot = { .min = 20000, .max = 400000 },
  150. .vco = { .min = 1400000, .max = 2800000 },
  151. .n = { .min = 1, .max = 6 },
  152. .m = { .min = 70, .max = 120 },
  153. .m1 = { .min = 10, .max = 22 },
  154. .m2 = { .min = 5, .max = 9 },
  155. .p = { .min = 7, .max = 98 },
  156. .p1 = { .min = 1, .max = 8 },
  157. .p2 = { .dot_limit = 112000,
  158. .p2_slow = 14, .p2_fast = 7 },
  159. .find_pll = intel_find_best_PLL,
  160. };
  161. static const intel_limit_t intel_limits_g4x_sdvo = {
  162. .dot = { .min = 25000, .max = 270000 },
  163. .vco = { .min = 1750000, .max = 3500000},
  164. .n = { .min = 1, .max = 4 },
  165. .m = { .min = 104, .max = 138 },
  166. .m1 = { .min = 17, .max = 23 },
  167. .m2 = { .min = 5, .max = 11 },
  168. .p = { .min = 10, .max = 30 },
  169. .p1 = { .min = 1, .max = 3},
  170. .p2 = { .dot_limit = 270000,
  171. .p2_slow = 10,
  172. .p2_fast = 10
  173. },
  174. .find_pll = intel_g4x_find_best_PLL,
  175. };
  176. static const intel_limit_t intel_limits_g4x_hdmi = {
  177. .dot = { .min = 22000, .max = 400000 },
  178. .vco = { .min = 1750000, .max = 3500000},
  179. .n = { .min = 1, .max = 4 },
  180. .m = { .min = 104, .max = 138 },
  181. .m1 = { .min = 16, .max = 23 },
  182. .m2 = { .min = 5, .max = 11 },
  183. .p = { .min = 5, .max = 80 },
  184. .p1 = { .min = 1, .max = 8},
  185. .p2 = { .dot_limit = 165000,
  186. .p2_slow = 10, .p2_fast = 5 },
  187. .find_pll = intel_g4x_find_best_PLL,
  188. };
  189. static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
  190. .dot = { .min = 20000, .max = 115000 },
  191. .vco = { .min = 1750000, .max = 3500000 },
  192. .n = { .min = 1, .max = 3 },
  193. .m = { .min = 104, .max = 138 },
  194. .m1 = { .min = 17, .max = 23 },
  195. .m2 = { .min = 5, .max = 11 },
  196. .p = { .min = 28, .max = 112 },
  197. .p1 = { .min = 2, .max = 8 },
  198. .p2 = { .dot_limit = 0,
  199. .p2_slow = 14, .p2_fast = 14
  200. },
  201. .find_pll = intel_g4x_find_best_PLL,
  202. };
  203. static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
  204. .dot = { .min = 80000, .max = 224000 },
  205. .vco = { .min = 1750000, .max = 3500000 },
  206. .n = { .min = 1, .max = 3 },
  207. .m = { .min = 104, .max = 138 },
  208. .m1 = { .min = 17, .max = 23 },
  209. .m2 = { .min = 5, .max = 11 },
  210. .p = { .min = 14, .max = 42 },
  211. .p1 = { .min = 2, .max = 6 },
  212. .p2 = { .dot_limit = 0,
  213. .p2_slow = 7, .p2_fast = 7
  214. },
  215. .find_pll = intel_g4x_find_best_PLL,
  216. };
  217. static const intel_limit_t intel_limits_g4x_display_port = {
  218. .dot = { .min = 161670, .max = 227000 },
  219. .vco = { .min = 1750000, .max = 3500000},
  220. .n = { .min = 1, .max = 2 },
  221. .m = { .min = 97, .max = 108 },
  222. .m1 = { .min = 0x10, .max = 0x12 },
  223. .m2 = { .min = 0x05, .max = 0x06 },
  224. .p = { .min = 10, .max = 20 },
  225. .p1 = { .min = 1, .max = 2},
  226. .p2 = { .dot_limit = 0,
  227. .p2_slow = 10, .p2_fast = 10 },
  228. .find_pll = intel_find_pll_g4x_dp,
  229. };
  230. static const intel_limit_t intel_limits_pineview_sdvo = {
  231. .dot = { .min = 20000, .max = 400000},
  232. .vco = { .min = 1700000, .max = 3500000 },
  233. /* Pineview's Ncounter is a ring counter */
  234. .n = { .min = 3, .max = 6 },
  235. .m = { .min = 2, .max = 256 },
  236. /* Pineview only has one combined m divider, which we treat as m2. */
  237. .m1 = { .min = 0, .max = 0 },
  238. .m2 = { .min = 0, .max = 254 },
  239. .p = { .min = 5, .max = 80 },
  240. .p1 = { .min = 1, .max = 8 },
  241. .p2 = { .dot_limit = 200000,
  242. .p2_slow = 10, .p2_fast = 5 },
  243. .find_pll = intel_find_best_PLL,
  244. };
  245. static const intel_limit_t intel_limits_pineview_lvds = {
  246. .dot = { .min = 20000, .max = 400000 },
  247. .vco = { .min = 1700000, .max = 3500000 },
  248. .n = { .min = 3, .max = 6 },
  249. .m = { .min = 2, .max = 256 },
  250. .m1 = { .min = 0, .max = 0 },
  251. .m2 = { .min = 0, .max = 254 },
  252. .p = { .min = 7, .max = 112 },
  253. .p1 = { .min = 1, .max = 8 },
  254. .p2 = { .dot_limit = 112000,
  255. .p2_slow = 14, .p2_fast = 14 },
  256. .find_pll = intel_find_best_PLL,
  257. };
  258. /* Ironlake / Sandybridge
  259. *
  260. * We calculate clock using (register_value + 2) for N/M1/M2, so here
  261. * the range value for them is (actual_value - 2).
  262. */
  263. static const intel_limit_t intel_limits_ironlake_dac = {
  264. .dot = { .min = 25000, .max = 350000 },
  265. .vco = { .min = 1760000, .max = 3510000 },
  266. .n = { .min = 1, .max = 5 },
  267. .m = { .min = 79, .max = 127 },
  268. .m1 = { .min = 12, .max = 22 },
  269. .m2 = { .min = 5, .max = 9 },
  270. .p = { .min = 5, .max = 80 },
  271. .p1 = { .min = 1, .max = 8 },
  272. .p2 = { .dot_limit = 225000,
  273. .p2_slow = 10, .p2_fast = 5 },
  274. .find_pll = intel_g4x_find_best_PLL,
  275. };
  276. static const intel_limit_t intel_limits_ironlake_single_lvds = {
  277. .dot = { .min = 25000, .max = 350000 },
  278. .vco = { .min = 1760000, .max = 3510000 },
  279. .n = { .min = 1, .max = 3 },
  280. .m = { .min = 79, .max = 118 },
  281. .m1 = { .min = 12, .max = 22 },
  282. .m2 = { .min = 5, .max = 9 },
  283. .p = { .min = 28, .max = 112 },
  284. .p1 = { .min = 2, .max = 8 },
  285. .p2 = { .dot_limit = 225000,
  286. .p2_slow = 14, .p2_fast = 14 },
  287. .find_pll = intel_g4x_find_best_PLL,
  288. };
  289. static const intel_limit_t intel_limits_ironlake_dual_lvds = {
  290. .dot = { .min = 25000, .max = 350000 },
  291. .vco = { .min = 1760000, .max = 3510000 },
  292. .n = { .min = 1, .max = 3 },
  293. .m = { .min = 79, .max = 127 },
  294. .m1 = { .min = 12, .max = 22 },
  295. .m2 = { .min = 5, .max = 9 },
  296. .p = { .min = 14, .max = 56 },
  297. .p1 = { .min = 2, .max = 8 },
  298. .p2 = { .dot_limit = 225000,
  299. .p2_slow = 7, .p2_fast = 7 },
  300. .find_pll = intel_g4x_find_best_PLL,
  301. };
  302. /* LVDS 100mhz refclk limits. */
  303. static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
  304. .dot = { .min = 25000, .max = 350000 },
  305. .vco = { .min = 1760000, .max = 3510000 },
  306. .n = { .min = 1, .max = 2 },
  307. .m = { .min = 79, .max = 126 },
  308. .m1 = { .min = 12, .max = 22 },
  309. .m2 = { .min = 5, .max = 9 },
  310. .p = { .min = 28, .max = 112 },
  311. .p1 = { .min = 2, .max = 8 },
  312. .p2 = { .dot_limit = 225000,
  313. .p2_slow = 14, .p2_fast = 14 },
  314. .find_pll = intel_g4x_find_best_PLL,
  315. };
  316. static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
  317. .dot = { .min = 25000, .max = 350000 },
  318. .vco = { .min = 1760000, .max = 3510000 },
  319. .n = { .min = 1, .max = 3 },
  320. .m = { .min = 79, .max = 126 },
  321. .m1 = { .min = 12, .max = 22 },
  322. .m2 = { .min = 5, .max = 9 },
  323. .p = { .min = 14, .max = 42 },
  324. .p1 = { .min = 2, .max = 6 },
  325. .p2 = { .dot_limit = 225000,
  326. .p2_slow = 7, .p2_fast = 7 },
  327. .find_pll = intel_g4x_find_best_PLL,
  328. };
  329. static const intel_limit_t intel_limits_ironlake_display_port = {
  330. .dot = { .min = 25000, .max = 350000 },
  331. .vco = { .min = 1760000, .max = 3510000},
  332. .n = { .min = 1, .max = 2 },
  333. .m = { .min = 81, .max = 90 },
  334. .m1 = { .min = 12, .max = 22 },
  335. .m2 = { .min = 5, .max = 9 },
  336. .p = { .min = 10, .max = 20 },
  337. .p1 = { .min = 1, .max = 2},
  338. .p2 = { .dot_limit = 0,
  339. .p2_slow = 10, .p2_fast = 10 },
  340. .find_pll = intel_find_pll_ironlake_dp,
  341. };
  342. static const intel_limit_t intel_limits_vlv_dac = {
  343. .dot = { .min = 25000, .max = 270000 },
  344. .vco = { .min = 4000000, .max = 6000000 },
  345. .n = { .min = 1, .max = 7 },
  346. .m = { .min = 22, .max = 450 }, /* guess */
  347. .m1 = { .min = 2, .max = 3 },
  348. .m2 = { .min = 11, .max = 156 },
  349. .p = { .min = 10, .max = 30 },
  350. .p1 = { .min = 2, .max = 3 },
  351. .p2 = { .dot_limit = 270000,
  352. .p2_slow = 2, .p2_fast = 20 },
  353. .find_pll = intel_vlv_find_best_pll,
  354. };
  355. static const intel_limit_t intel_limits_vlv_hdmi = {
  356. .dot = { .min = 20000, .max = 165000 },
  357. .vco = { .min = 4000000, .max = 5994000},
  358. .n = { .min = 1, .max = 7 },
  359. .m = { .min = 60, .max = 300 }, /* guess */
  360. .m1 = { .min = 2, .max = 3 },
  361. .m2 = { .min = 11, .max = 156 },
  362. .p = { .min = 10, .max = 30 },
  363. .p1 = { .min = 2, .max = 3 },
  364. .p2 = { .dot_limit = 270000,
  365. .p2_slow = 2, .p2_fast = 20 },
  366. .find_pll = intel_vlv_find_best_pll,
  367. };
  368. static const intel_limit_t intel_limits_vlv_dp = {
  369. .dot = { .min = 25000, .max = 270000 },
  370. .vco = { .min = 4000000, .max = 6000000 },
  371. .n = { .min = 1, .max = 7 },
  372. .m = { .min = 22, .max = 450 },
  373. .m1 = { .min = 2, .max = 3 },
  374. .m2 = { .min = 11, .max = 156 },
  375. .p = { .min = 10, .max = 30 },
  376. .p1 = { .min = 2, .max = 3 },
  377. .p2 = { .dot_limit = 270000,
  378. .p2_slow = 2, .p2_fast = 20 },
  379. .find_pll = intel_vlv_find_best_pll,
  380. };
  381. u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
  382. {
  383. WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
  384. if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
  385. DRM_ERROR("DPIO idle wait timed out\n");
  386. return 0;
  387. }
  388. I915_WRITE(DPIO_REG, reg);
  389. I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
  390. DPIO_BYTE);
  391. if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
  392. DRM_ERROR("DPIO read wait timed out\n");
  393. return 0;
  394. }
  395. return I915_READ(DPIO_DATA);
  396. }
  397. static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
  398. u32 val)
  399. {
  400. WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
  401. if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
  402. DRM_ERROR("DPIO idle wait timed out\n");
  403. return;
  404. }
  405. I915_WRITE(DPIO_DATA, val);
  406. I915_WRITE(DPIO_REG, reg);
  407. I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
  408. DPIO_BYTE);
  409. if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
  410. DRM_ERROR("DPIO write wait timed out\n");
  411. }
  412. static void vlv_init_dpio(struct drm_device *dev)
  413. {
  414. struct drm_i915_private *dev_priv = dev->dev_private;
  415. /* Reset the DPIO config */
  416. I915_WRITE(DPIO_CTL, 0);
  417. POSTING_READ(DPIO_CTL);
  418. I915_WRITE(DPIO_CTL, 1);
  419. POSTING_READ(DPIO_CTL);
  420. }
  421. static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
  422. int refclk)
  423. {
  424. struct drm_device *dev = crtc->dev;
  425. const intel_limit_t *limit;
  426. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  427. if (intel_is_dual_link_lvds(dev)) {
  428. /* LVDS dual channel */
  429. if (refclk == 100000)
  430. limit = &intel_limits_ironlake_dual_lvds_100m;
  431. else
  432. limit = &intel_limits_ironlake_dual_lvds;
  433. } else {
  434. if (refclk == 100000)
  435. limit = &intel_limits_ironlake_single_lvds_100m;
  436. else
  437. limit = &intel_limits_ironlake_single_lvds;
  438. }
  439. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
  440. intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  441. limit = &intel_limits_ironlake_display_port;
  442. else
  443. limit = &intel_limits_ironlake_dac;
  444. return limit;
  445. }
  446. static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
  447. {
  448. struct drm_device *dev = crtc->dev;
  449. const intel_limit_t *limit;
  450. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  451. if (intel_is_dual_link_lvds(dev))
  452. /* LVDS with dual channel */
  453. limit = &intel_limits_g4x_dual_channel_lvds;
  454. else
  455. /* LVDS with dual channel */
  456. limit = &intel_limits_g4x_single_channel_lvds;
  457. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
  458. intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  459. limit = &intel_limits_g4x_hdmi;
  460. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
  461. limit = &intel_limits_g4x_sdvo;
  462. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  463. limit = &intel_limits_g4x_display_port;
  464. } else /* The option is for other outputs */
  465. limit = &intel_limits_i9xx_sdvo;
  466. return limit;
  467. }
  468. static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
  469. {
  470. struct drm_device *dev = crtc->dev;
  471. const intel_limit_t *limit;
  472. if (HAS_PCH_SPLIT(dev))
  473. limit = intel_ironlake_limit(crtc, refclk);
  474. else if (IS_G4X(dev)) {
  475. limit = intel_g4x_limit(crtc);
  476. } else if (IS_PINEVIEW(dev)) {
  477. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  478. limit = &intel_limits_pineview_lvds;
  479. else
  480. limit = &intel_limits_pineview_sdvo;
  481. } else if (IS_VALLEYVIEW(dev)) {
  482. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
  483. limit = &intel_limits_vlv_dac;
  484. else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
  485. limit = &intel_limits_vlv_hdmi;
  486. else
  487. limit = &intel_limits_vlv_dp;
  488. } else if (!IS_GEN2(dev)) {
  489. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  490. limit = &intel_limits_i9xx_lvds;
  491. else
  492. limit = &intel_limits_i9xx_sdvo;
  493. } else {
  494. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  495. limit = &intel_limits_i8xx_lvds;
  496. else
  497. limit = &intel_limits_i8xx_dvo;
  498. }
  499. return limit;
  500. }
  501. /* m1 is reserved as 0 in Pineview, n is a ring counter */
  502. static void pineview_clock(int refclk, intel_clock_t *clock)
  503. {
  504. clock->m = clock->m2 + 2;
  505. clock->p = clock->p1 * clock->p2;
  506. clock->vco = refclk * clock->m / clock->n;
  507. clock->dot = clock->vco / clock->p;
  508. }
  509. static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
  510. {
  511. if (IS_PINEVIEW(dev)) {
  512. pineview_clock(refclk, clock);
  513. return;
  514. }
  515. clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
  516. clock->p = clock->p1 * clock->p2;
  517. clock->vco = refclk * clock->m / (clock->n + 2);
  518. clock->dot = clock->vco / clock->p;
  519. }
  520. /**
  521. * Returns whether any output on the specified pipe is of the specified type
  522. */
  523. bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
  524. {
  525. struct drm_device *dev = crtc->dev;
  526. struct intel_encoder *encoder;
  527. for_each_encoder_on_crtc(dev, crtc, encoder)
  528. if (encoder->type == type)
  529. return true;
  530. return false;
  531. }
  532. #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
  533. /**
  534. * Returns whether the given set of divisors are valid for a given refclk with
  535. * the given connectors.
  536. */
  537. static bool intel_PLL_is_valid(struct drm_device *dev,
  538. const intel_limit_t *limit,
  539. const intel_clock_t *clock)
  540. {
  541. if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
  542. INTELPllInvalid("p1 out of range\n");
  543. if (clock->p < limit->p.min || limit->p.max < clock->p)
  544. INTELPllInvalid("p out of range\n");
  545. if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
  546. INTELPllInvalid("m2 out of range\n");
  547. if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
  548. INTELPllInvalid("m1 out of range\n");
  549. if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
  550. INTELPllInvalid("m1 <= m2\n");
  551. if (clock->m < limit->m.min || limit->m.max < clock->m)
  552. INTELPllInvalid("m out of range\n");
  553. if (clock->n < limit->n.min || limit->n.max < clock->n)
  554. INTELPllInvalid("n out of range\n");
  555. if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
  556. INTELPllInvalid("vco out of range\n");
  557. /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
  558. * connector, etc., rather than just a single range.
  559. */
  560. if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
  561. INTELPllInvalid("dot out of range\n");
  562. return true;
  563. }
  564. static bool
  565. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  566. int target, int refclk, intel_clock_t *match_clock,
  567. intel_clock_t *best_clock)
  568. {
  569. struct drm_device *dev = crtc->dev;
  570. intel_clock_t clock;
  571. int err = target;
  572. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  573. /*
  574. * For LVDS just rely on its current settings for dual-channel.
  575. * We haven't figured out how to reliably set up different
  576. * single/dual channel state, if we even can.
  577. */
  578. if (intel_is_dual_link_lvds(dev))
  579. clock.p2 = limit->p2.p2_fast;
  580. else
  581. clock.p2 = limit->p2.p2_slow;
  582. } else {
  583. if (target < limit->p2.dot_limit)
  584. clock.p2 = limit->p2.p2_slow;
  585. else
  586. clock.p2 = limit->p2.p2_fast;
  587. }
  588. memset(best_clock, 0, sizeof(*best_clock));
  589. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  590. clock.m1++) {
  591. for (clock.m2 = limit->m2.min;
  592. clock.m2 <= limit->m2.max; clock.m2++) {
  593. /* m1 is always 0 in Pineview */
  594. if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
  595. break;
  596. for (clock.n = limit->n.min;
  597. clock.n <= limit->n.max; clock.n++) {
  598. for (clock.p1 = limit->p1.min;
  599. clock.p1 <= limit->p1.max; clock.p1++) {
  600. int this_err;
  601. intel_clock(dev, refclk, &clock);
  602. if (!intel_PLL_is_valid(dev, limit,
  603. &clock))
  604. continue;
  605. if (match_clock &&
  606. clock.p != match_clock->p)
  607. continue;
  608. this_err = abs(clock.dot - target);
  609. if (this_err < err) {
  610. *best_clock = clock;
  611. err = this_err;
  612. }
  613. }
  614. }
  615. }
  616. }
  617. return (err != target);
  618. }
  619. static bool
  620. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  621. int target, int refclk, intel_clock_t *match_clock,
  622. intel_clock_t *best_clock)
  623. {
  624. struct drm_device *dev = crtc->dev;
  625. intel_clock_t clock;
  626. int max_n;
  627. bool found;
  628. /* approximately equals target * 0.00585 */
  629. int err_most = (target >> 8) + (target >> 9);
  630. found = false;
  631. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  632. int lvds_reg;
  633. if (HAS_PCH_SPLIT(dev))
  634. lvds_reg = PCH_LVDS;
  635. else
  636. lvds_reg = LVDS;
  637. if (intel_is_dual_link_lvds(dev))
  638. clock.p2 = limit->p2.p2_fast;
  639. else
  640. clock.p2 = limit->p2.p2_slow;
  641. } else {
  642. if (target < limit->p2.dot_limit)
  643. clock.p2 = limit->p2.p2_slow;
  644. else
  645. clock.p2 = limit->p2.p2_fast;
  646. }
  647. memset(best_clock, 0, sizeof(*best_clock));
  648. max_n = limit->n.max;
  649. /* based on hardware requirement, prefer smaller n to precision */
  650. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  651. /* based on hardware requirement, prefere larger m1,m2 */
  652. for (clock.m1 = limit->m1.max;
  653. clock.m1 >= limit->m1.min; clock.m1--) {
  654. for (clock.m2 = limit->m2.max;
  655. clock.m2 >= limit->m2.min; clock.m2--) {
  656. for (clock.p1 = limit->p1.max;
  657. clock.p1 >= limit->p1.min; clock.p1--) {
  658. int this_err;
  659. intel_clock(dev, refclk, &clock);
  660. if (!intel_PLL_is_valid(dev, limit,
  661. &clock))
  662. continue;
  663. if (match_clock &&
  664. clock.p != match_clock->p)
  665. continue;
  666. this_err = abs(clock.dot - target);
  667. if (this_err < err_most) {
  668. *best_clock = clock;
  669. err_most = this_err;
  670. max_n = clock.n;
  671. found = true;
  672. }
  673. }
  674. }
  675. }
  676. }
  677. return found;
  678. }
  679. static bool
  680. intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  681. int target, int refclk, intel_clock_t *match_clock,
  682. intel_clock_t *best_clock)
  683. {
  684. struct drm_device *dev = crtc->dev;
  685. intel_clock_t clock;
  686. if (target < 200000) {
  687. clock.n = 1;
  688. clock.p1 = 2;
  689. clock.p2 = 10;
  690. clock.m1 = 12;
  691. clock.m2 = 9;
  692. } else {
  693. clock.n = 2;
  694. clock.p1 = 1;
  695. clock.p2 = 10;
  696. clock.m1 = 14;
  697. clock.m2 = 8;
  698. }
  699. intel_clock(dev, refclk, &clock);
  700. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  701. return true;
  702. }
  703. /* DisplayPort has only two frequencies, 162MHz and 270MHz */
  704. static bool
  705. intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  706. int target, int refclk, intel_clock_t *match_clock,
  707. intel_clock_t *best_clock)
  708. {
  709. intel_clock_t clock;
  710. if (target < 200000) {
  711. clock.p1 = 2;
  712. clock.p2 = 10;
  713. clock.n = 2;
  714. clock.m1 = 23;
  715. clock.m2 = 8;
  716. } else {
  717. clock.p1 = 1;
  718. clock.p2 = 10;
  719. clock.n = 1;
  720. clock.m1 = 14;
  721. clock.m2 = 2;
  722. }
  723. clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
  724. clock.p = (clock.p1 * clock.p2);
  725. clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
  726. clock.vco = 0;
  727. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  728. return true;
  729. }
  730. static bool
  731. intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
  732. int target, int refclk, intel_clock_t *match_clock,
  733. intel_clock_t *best_clock)
  734. {
  735. u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
  736. u32 m, n, fastclk;
  737. u32 updrate, minupdate, fracbits, p;
  738. unsigned long bestppm, ppm, absppm;
  739. int dotclk, flag;
  740. flag = 0;
  741. dotclk = target * 1000;
  742. bestppm = 1000000;
  743. ppm = absppm = 0;
  744. fastclk = dotclk / (2*100);
  745. updrate = 0;
  746. minupdate = 19200;
  747. fracbits = 1;
  748. n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
  749. bestm1 = bestm2 = bestp1 = bestp2 = 0;
  750. /* based on hardware requirement, prefer smaller n to precision */
  751. for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
  752. updrate = refclk / n;
  753. for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
  754. for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
  755. if (p2 > 10)
  756. p2 = p2 - 1;
  757. p = p1 * p2;
  758. /* based on hardware requirement, prefer bigger m1,m2 values */
  759. for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
  760. m2 = (((2*(fastclk * p * n / m1 )) +
  761. refclk) / (2*refclk));
  762. m = m1 * m2;
  763. vco = updrate * m;
  764. if (vco >= limit->vco.min && vco < limit->vco.max) {
  765. ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
  766. absppm = (ppm > 0) ? ppm : (-ppm);
  767. if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
  768. bestppm = 0;
  769. flag = 1;
  770. }
  771. if (absppm < bestppm - 10) {
  772. bestppm = absppm;
  773. flag = 1;
  774. }
  775. if (flag) {
  776. bestn = n;
  777. bestm1 = m1;
  778. bestm2 = m2;
  779. bestp1 = p1;
  780. bestp2 = p2;
  781. flag = 0;
  782. }
  783. }
  784. }
  785. }
  786. }
  787. }
  788. best_clock->n = bestn;
  789. best_clock->m1 = bestm1;
  790. best_clock->m2 = bestm2;
  791. best_clock->p1 = bestp1;
  792. best_clock->p2 = bestp2;
  793. return true;
  794. }
  795. enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
  796. enum pipe pipe)
  797. {
  798. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  799. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  800. return intel_crtc->cpu_transcoder;
  801. }
  802. static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
  803. {
  804. struct drm_i915_private *dev_priv = dev->dev_private;
  805. u32 frame, frame_reg = PIPEFRAME(pipe);
  806. frame = I915_READ(frame_reg);
  807. if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
  808. DRM_DEBUG_KMS("vblank wait timed out\n");
  809. }
  810. /**
  811. * intel_wait_for_vblank - wait for vblank on a given pipe
  812. * @dev: drm device
  813. * @pipe: pipe to wait for
  814. *
  815. * Wait for vblank to occur on a given pipe. Needed for various bits of
  816. * mode setting code.
  817. */
  818. void intel_wait_for_vblank(struct drm_device *dev, int pipe)
  819. {
  820. struct drm_i915_private *dev_priv = dev->dev_private;
  821. int pipestat_reg = PIPESTAT(pipe);
  822. if (INTEL_INFO(dev)->gen >= 5) {
  823. ironlake_wait_for_vblank(dev, pipe);
  824. return;
  825. }
  826. /* Clear existing vblank status. Note this will clear any other
  827. * sticky status fields as well.
  828. *
  829. * This races with i915_driver_irq_handler() with the result
  830. * that either function could miss a vblank event. Here it is not
  831. * fatal, as we will either wait upon the next vblank interrupt or
  832. * timeout. Generally speaking intel_wait_for_vblank() is only
  833. * called during modeset at which time the GPU should be idle and
  834. * should *not* be performing page flips and thus not waiting on
  835. * vblanks...
  836. * Currently, the result of us stealing a vblank from the irq
  837. * handler is that a single frame will be skipped during swapbuffers.
  838. */
  839. I915_WRITE(pipestat_reg,
  840. I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
  841. /* Wait for vblank interrupt bit to set */
  842. if (wait_for(I915_READ(pipestat_reg) &
  843. PIPE_VBLANK_INTERRUPT_STATUS,
  844. 50))
  845. DRM_DEBUG_KMS("vblank wait timed out\n");
  846. }
  847. /*
  848. * intel_wait_for_pipe_off - wait for pipe to turn off
  849. * @dev: drm device
  850. * @pipe: pipe to wait for
  851. *
  852. * After disabling a pipe, we can't wait for vblank in the usual way,
  853. * spinning on the vblank interrupt status bit, since we won't actually
  854. * see an interrupt when the pipe is disabled.
  855. *
  856. * On Gen4 and above:
  857. * wait for the pipe register state bit to turn off
  858. *
  859. * Otherwise:
  860. * wait for the display line value to settle (it usually
  861. * ends up stopping at the start of the next frame).
  862. *
  863. */
  864. void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
  865. {
  866. struct drm_i915_private *dev_priv = dev->dev_private;
  867. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  868. pipe);
  869. if (INTEL_INFO(dev)->gen >= 4) {
  870. int reg = PIPECONF(cpu_transcoder);
  871. /* Wait for the Pipe State to go off */
  872. if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
  873. 100))
  874. WARN(1, "pipe_off wait timed out\n");
  875. } else {
  876. u32 last_line, line_mask;
  877. int reg = PIPEDSL(pipe);
  878. unsigned long timeout = jiffies + msecs_to_jiffies(100);
  879. if (IS_GEN2(dev))
  880. line_mask = DSL_LINEMASK_GEN2;
  881. else
  882. line_mask = DSL_LINEMASK_GEN3;
  883. /* Wait for the display line to settle */
  884. do {
  885. last_line = I915_READ(reg) & line_mask;
  886. mdelay(5);
  887. } while (((I915_READ(reg) & line_mask) != last_line) &&
  888. time_after(timeout, jiffies));
  889. if (time_after(jiffies, timeout))
  890. WARN(1, "pipe_off wait timed out\n");
  891. }
  892. }
  893. /*
  894. * ibx_digital_port_connected - is the specified port connected?
  895. * @dev_priv: i915 private structure
  896. * @port: the port to test
  897. *
  898. * Returns true if @port is connected, false otherwise.
  899. */
  900. bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
  901. struct intel_digital_port *port)
  902. {
  903. u32 bit;
  904. if (HAS_PCH_IBX(dev_priv->dev)) {
  905. switch(port->port) {
  906. case PORT_B:
  907. bit = SDE_PORTB_HOTPLUG;
  908. break;
  909. case PORT_C:
  910. bit = SDE_PORTC_HOTPLUG;
  911. break;
  912. case PORT_D:
  913. bit = SDE_PORTD_HOTPLUG;
  914. break;
  915. default:
  916. return true;
  917. }
  918. } else {
  919. switch(port->port) {
  920. case PORT_B:
  921. bit = SDE_PORTB_HOTPLUG_CPT;
  922. break;
  923. case PORT_C:
  924. bit = SDE_PORTC_HOTPLUG_CPT;
  925. break;
  926. case PORT_D:
  927. bit = SDE_PORTD_HOTPLUG_CPT;
  928. break;
  929. default:
  930. return true;
  931. }
  932. }
  933. return I915_READ(SDEISR) & bit;
  934. }
  935. static const char *state_string(bool enabled)
  936. {
  937. return enabled ? "on" : "off";
  938. }
  939. /* Only for pre-ILK configs */
  940. static void assert_pll(struct drm_i915_private *dev_priv,
  941. enum pipe pipe, bool state)
  942. {
  943. int reg;
  944. u32 val;
  945. bool cur_state;
  946. reg = DPLL(pipe);
  947. val = I915_READ(reg);
  948. cur_state = !!(val & DPLL_VCO_ENABLE);
  949. WARN(cur_state != state,
  950. "PLL state assertion failure (expected %s, current %s)\n",
  951. state_string(state), state_string(cur_state));
  952. }
  953. #define assert_pll_enabled(d, p) assert_pll(d, p, true)
  954. #define assert_pll_disabled(d, p) assert_pll(d, p, false)
  955. /* For ILK+ */
  956. static void assert_pch_pll(struct drm_i915_private *dev_priv,
  957. struct intel_pch_pll *pll,
  958. struct intel_crtc *crtc,
  959. bool state)
  960. {
  961. u32 val;
  962. bool cur_state;
  963. if (HAS_PCH_LPT(dev_priv->dev)) {
  964. DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
  965. return;
  966. }
  967. if (WARN (!pll,
  968. "asserting PCH PLL %s with no PLL\n", state_string(state)))
  969. return;
  970. val = I915_READ(pll->pll_reg);
  971. cur_state = !!(val & DPLL_VCO_ENABLE);
  972. WARN(cur_state != state,
  973. "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
  974. pll->pll_reg, state_string(state), state_string(cur_state), val);
  975. /* Make sure the selected PLL is correctly attached to the transcoder */
  976. if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
  977. u32 pch_dpll;
  978. pch_dpll = I915_READ(PCH_DPLL_SEL);
  979. cur_state = pll->pll_reg == _PCH_DPLL_B;
  980. if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
  981. "PLL[%d] not attached to this transcoder %d: %08x\n",
  982. cur_state, crtc->pipe, pch_dpll)) {
  983. cur_state = !!(val >> (4*crtc->pipe + 3));
  984. WARN(cur_state != state,
  985. "PLL[%d] not %s on this transcoder %d: %08x\n",
  986. pll->pll_reg == _PCH_DPLL_B,
  987. state_string(state),
  988. crtc->pipe,
  989. val);
  990. }
  991. }
  992. }
  993. #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
  994. #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
  995. static void assert_fdi_tx(struct drm_i915_private *dev_priv,
  996. enum pipe pipe, bool state)
  997. {
  998. int reg;
  999. u32 val;
  1000. bool cur_state;
  1001. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1002. pipe);
  1003. if (HAS_DDI(dev_priv->dev)) {
  1004. /* DDI does not have a specific FDI_TX register */
  1005. reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
  1006. val = I915_READ(reg);
  1007. cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
  1008. } else {
  1009. reg = FDI_TX_CTL(pipe);
  1010. val = I915_READ(reg);
  1011. cur_state = !!(val & FDI_TX_ENABLE);
  1012. }
  1013. WARN(cur_state != state,
  1014. "FDI TX state assertion failure (expected %s, current %s)\n",
  1015. state_string(state), state_string(cur_state));
  1016. }
  1017. #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
  1018. #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
  1019. static void assert_fdi_rx(struct drm_i915_private *dev_priv,
  1020. enum pipe pipe, bool state)
  1021. {
  1022. int reg;
  1023. u32 val;
  1024. bool cur_state;
  1025. reg = FDI_RX_CTL(pipe);
  1026. val = I915_READ(reg);
  1027. cur_state = !!(val & FDI_RX_ENABLE);
  1028. WARN(cur_state != state,
  1029. "FDI RX state assertion failure (expected %s, current %s)\n",
  1030. state_string(state), state_string(cur_state));
  1031. }
  1032. #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
  1033. #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
  1034. static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
  1035. enum pipe pipe)
  1036. {
  1037. int reg;
  1038. u32 val;
  1039. /* ILK FDI PLL is always enabled */
  1040. if (dev_priv->info->gen == 5)
  1041. return;
  1042. /* On Haswell, DDI ports are responsible for the FDI PLL setup */
  1043. if (HAS_DDI(dev_priv->dev))
  1044. return;
  1045. reg = FDI_TX_CTL(pipe);
  1046. val = I915_READ(reg);
  1047. WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
  1048. }
  1049. static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
  1050. enum pipe pipe)
  1051. {
  1052. int reg;
  1053. u32 val;
  1054. reg = FDI_RX_CTL(pipe);
  1055. val = I915_READ(reg);
  1056. WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
  1057. }
  1058. static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
  1059. enum pipe pipe)
  1060. {
  1061. int pp_reg, lvds_reg;
  1062. u32 val;
  1063. enum pipe panel_pipe = PIPE_A;
  1064. bool locked = true;
  1065. if (HAS_PCH_SPLIT(dev_priv->dev)) {
  1066. pp_reg = PCH_PP_CONTROL;
  1067. lvds_reg = PCH_LVDS;
  1068. } else {
  1069. pp_reg = PP_CONTROL;
  1070. lvds_reg = LVDS;
  1071. }
  1072. val = I915_READ(pp_reg);
  1073. if (!(val & PANEL_POWER_ON) ||
  1074. ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
  1075. locked = false;
  1076. if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
  1077. panel_pipe = PIPE_B;
  1078. WARN(panel_pipe == pipe && locked,
  1079. "panel assertion failure, pipe %c regs locked\n",
  1080. pipe_name(pipe));
  1081. }
  1082. void assert_pipe(struct drm_i915_private *dev_priv,
  1083. enum pipe pipe, bool state)
  1084. {
  1085. int reg;
  1086. u32 val;
  1087. bool cur_state;
  1088. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1089. pipe);
  1090. /* if we need the pipe A quirk it must be always on */
  1091. if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
  1092. state = true;
  1093. reg = PIPECONF(cpu_transcoder);
  1094. val = I915_READ(reg);
  1095. cur_state = !!(val & PIPECONF_ENABLE);
  1096. WARN(cur_state != state,
  1097. "pipe %c assertion failure (expected %s, current %s)\n",
  1098. pipe_name(pipe), state_string(state), state_string(cur_state));
  1099. }
  1100. static void assert_plane(struct drm_i915_private *dev_priv,
  1101. enum plane plane, bool state)
  1102. {
  1103. int reg;
  1104. u32 val;
  1105. bool cur_state;
  1106. reg = DSPCNTR(plane);
  1107. val = I915_READ(reg);
  1108. cur_state = !!(val & DISPLAY_PLANE_ENABLE);
  1109. WARN(cur_state != state,
  1110. "plane %c assertion failure (expected %s, current %s)\n",
  1111. plane_name(plane), state_string(state), state_string(cur_state));
  1112. }
  1113. #define assert_plane_enabled(d, p) assert_plane(d, p, true)
  1114. #define assert_plane_disabled(d, p) assert_plane(d, p, false)
  1115. static void assert_planes_disabled(struct drm_i915_private *dev_priv,
  1116. enum pipe pipe)
  1117. {
  1118. int reg, i;
  1119. u32 val;
  1120. int cur_pipe;
  1121. /* Planes are fixed to pipes on ILK+ */
  1122. if (HAS_PCH_SPLIT(dev_priv->dev)) {
  1123. reg = DSPCNTR(pipe);
  1124. val = I915_READ(reg);
  1125. WARN((val & DISPLAY_PLANE_ENABLE),
  1126. "plane %c assertion failure, should be disabled but not\n",
  1127. plane_name(pipe));
  1128. return;
  1129. }
  1130. /* Need to check both planes against the pipe */
  1131. for (i = 0; i < 2; i++) {
  1132. reg = DSPCNTR(i);
  1133. val = I915_READ(reg);
  1134. cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
  1135. DISPPLANE_SEL_PIPE_SHIFT;
  1136. WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
  1137. "plane %c assertion failure, should be off on pipe %c but is still active\n",
  1138. plane_name(i), pipe_name(pipe));
  1139. }
  1140. }
  1141. static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
  1142. {
  1143. u32 val;
  1144. bool enabled;
  1145. if (HAS_PCH_LPT(dev_priv->dev)) {
  1146. DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
  1147. return;
  1148. }
  1149. val = I915_READ(PCH_DREF_CONTROL);
  1150. enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
  1151. DREF_SUPERSPREAD_SOURCE_MASK));
  1152. WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
  1153. }
  1154. static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
  1155. enum pipe pipe)
  1156. {
  1157. int reg;
  1158. u32 val;
  1159. bool enabled;
  1160. reg = TRANSCONF(pipe);
  1161. val = I915_READ(reg);
  1162. enabled = !!(val & TRANS_ENABLE);
  1163. WARN(enabled,
  1164. "transcoder assertion failed, should be off on pipe %c but is still active\n",
  1165. pipe_name(pipe));
  1166. }
  1167. static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
  1168. enum pipe pipe, u32 port_sel, u32 val)
  1169. {
  1170. if ((val & DP_PORT_EN) == 0)
  1171. return false;
  1172. if (HAS_PCH_CPT(dev_priv->dev)) {
  1173. u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
  1174. u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
  1175. if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
  1176. return false;
  1177. } else {
  1178. if ((val & DP_PIPE_MASK) != (pipe << 30))
  1179. return false;
  1180. }
  1181. return true;
  1182. }
  1183. static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
  1184. enum pipe pipe, u32 val)
  1185. {
  1186. if ((val & PORT_ENABLE) == 0)
  1187. return false;
  1188. if (HAS_PCH_CPT(dev_priv->dev)) {
  1189. if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1190. return false;
  1191. } else {
  1192. if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
  1193. return false;
  1194. }
  1195. return true;
  1196. }
  1197. static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
  1198. enum pipe pipe, u32 val)
  1199. {
  1200. if ((val & LVDS_PORT_EN) == 0)
  1201. return false;
  1202. if (HAS_PCH_CPT(dev_priv->dev)) {
  1203. if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1204. return false;
  1205. } else {
  1206. if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
  1207. return false;
  1208. }
  1209. return true;
  1210. }
  1211. static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
  1212. enum pipe pipe, u32 val)
  1213. {
  1214. if ((val & ADPA_DAC_ENABLE) == 0)
  1215. return false;
  1216. if (HAS_PCH_CPT(dev_priv->dev)) {
  1217. if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  1218. return false;
  1219. } else {
  1220. if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
  1221. return false;
  1222. }
  1223. return true;
  1224. }
  1225. static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
  1226. enum pipe pipe, int reg, u32 port_sel)
  1227. {
  1228. u32 val = I915_READ(reg);
  1229. WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
  1230. "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
  1231. reg, pipe_name(pipe));
  1232. WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
  1233. && (val & DP_PIPEB_SELECT),
  1234. "IBX PCH dp port still using transcoder B\n");
  1235. }
  1236. static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
  1237. enum pipe pipe, int reg)
  1238. {
  1239. u32 val = I915_READ(reg);
  1240. WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
  1241. "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
  1242. reg, pipe_name(pipe));
  1243. WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
  1244. && (val & SDVO_PIPE_B_SELECT),
  1245. "IBX PCH hdmi port still using transcoder B\n");
  1246. }
  1247. static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
  1248. enum pipe pipe)
  1249. {
  1250. int reg;
  1251. u32 val;
  1252. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
  1253. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
  1254. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
  1255. reg = PCH_ADPA;
  1256. val = I915_READ(reg);
  1257. WARN(adpa_pipe_enabled(dev_priv, pipe, val),
  1258. "PCH VGA enabled on transcoder %c, should be disabled\n",
  1259. pipe_name(pipe));
  1260. reg = PCH_LVDS;
  1261. val = I915_READ(reg);
  1262. WARN(lvds_pipe_enabled(dev_priv, pipe, val),
  1263. "PCH LVDS enabled on transcoder %c, should be disabled\n",
  1264. pipe_name(pipe));
  1265. assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
  1266. assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
  1267. assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
  1268. }
  1269. /**
  1270. * intel_enable_pll - enable a PLL
  1271. * @dev_priv: i915 private structure
  1272. * @pipe: pipe PLL to enable
  1273. *
  1274. * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
  1275. * make sure the PLL reg is writable first though, since the panel write
  1276. * protect mechanism may be enabled.
  1277. *
  1278. * Note! This is for pre-ILK only.
  1279. *
  1280. * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
  1281. */
  1282. static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  1283. {
  1284. int reg;
  1285. u32 val;
  1286. /* No really, not for ILK+ */
  1287. BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
  1288. /* PLL is protected by panel, make sure we can write it */
  1289. if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
  1290. assert_panel_unlocked(dev_priv, pipe);
  1291. reg = DPLL(pipe);
  1292. val = I915_READ(reg);
  1293. val |= DPLL_VCO_ENABLE;
  1294. /* We do this three times for luck */
  1295. I915_WRITE(reg, val);
  1296. POSTING_READ(reg);
  1297. udelay(150); /* wait for warmup */
  1298. I915_WRITE(reg, val);
  1299. POSTING_READ(reg);
  1300. udelay(150); /* wait for warmup */
  1301. I915_WRITE(reg, val);
  1302. POSTING_READ(reg);
  1303. udelay(150); /* wait for warmup */
  1304. }
  1305. /**
  1306. * intel_disable_pll - disable a PLL
  1307. * @dev_priv: i915 private structure
  1308. * @pipe: pipe PLL to disable
  1309. *
  1310. * Disable the PLL for @pipe, making sure the pipe is off first.
  1311. *
  1312. * Note! This is for pre-ILK only.
  1313. */
  1314. static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  1315. {
  1316. int reg;
  1317. u32 val;
  1318. /* Don't disable pipe A or pipe A PLLs if needed */
  1319. if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  1320. return;
  1321. /* Make sure the pipe isn't still relying on us */
  1322. assert_pipe_disabled(dev_priv, pipe);
  1323. reg = DPLL(pipe);
  1324. val = I915_READ(reg);
  1325. val &= ~DPLL_VCO_ENABLE;
  1326. I915_WRITE(reg, val);
  1327. POSTING_READ(reg);
  1328. }
  1329. /* SBI access */
  1330. static void
  1331. intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
  1332. enum intel_sbi_destination destination)
  1333. {
  1334. u32 tmp;
  1335. WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
  1336. if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
  1337. 100)) {
  1338. DRM_ERROR("timeout waiting for SBI to become ready\n");
  1339. return;
  1340. }
  1341. I915_WRITE(SBI_ADDR, (reg << 16));
  1342. I915_WRITE(SBI_DATA, value);
  1343. if (destination == SBI_ICLK)
  1344. tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
  1345. else
  1346. tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
  1347. I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
  1348. if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
  1349. 100)) {
  1350. DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
  1351. return;
  1352. }
  1353. }
  1354. static u32
  1355. intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
  1356. enum intel_sbi_destination destination)
  1357. {
  1358. u32 value = 0;
  1359. WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
  1360. if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
  1361. 100)) {
  1362. DRM_ERROR("timeout waiting for SBI to become ready\n");
  1363. return 0;
  1364. }
  1365. I915_WRITE(SBI_ADDR, (reg << 16));
  1366. if (destination == SBI_ICLK)
  1367. value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
  1368. else
  1369. value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
  1370. I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
  1371. if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
  1372. 100)) {
  1373. DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
  1374. return 0;
  1375. }
  1376. return I915_READ(SBI_DATA);
  1377. }
  1378. /**
  1379. * ironlake_enable_pch_pll - enable PCH PLL
  1380. * @dev_priv: i915 private structure
  1381. * @pipe: pipe PLL to enable
  1382. *
  1383. * The PCH PLL needs to be enabled before the PCH transcoder, since it
  1384. * drives the transcoder clock.
  1385. */
  1386. static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
  1387. {
  1388. struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
  1389. struct intel_pch_pll *pll;
  1390. int reg;
  1391. u32 val;
  1392. /* PCH PLLs only available on ILK, SNB and IVB */
  1393. BUG_ON(dev_priv->info->gen < 5);
  1394. pll = intel_crtc->pch_pll;
  1395. if (pll == NULL)
  1396. return;
  1397. if (WARN_ON(pll->refcount == 0))
  1398. return;
  1399. DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
  1400. pll->pll_reg, pll->active, pll->on,
  1401. intel_crtc->base.base.id);
  1402. /* PCH refclock must be enabled first */
  1403. assert_pch_refclk_enabled(dev_priv);
  1404. if (pll->active++ && pll->on) {
  1405. assert_pch_pll_enabled(dev_priv, pll, NULL);
  1406. return;
  1407. }
  1408. DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
  1409. reg = pll->pll_reg;
  1410. val = I915_READ(reg);
  1411. val |= DPLL_VCO_ENABLE;
  1412. I915_WRITE(reg, val);
  1413. POSTING_READ(reg);
  1414. udelay(200);
  1415. pll->on = true;
  1416. }
  1417. static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
  1418. {
  1419. struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
  1420. struct intel_pch_pll *pll = intel_crtc->pch_pll;
  1421. int reg;
  1422. u32 val;
  1423. /* PCH only available on ILK+ */
  1424. BUG_ON(dev_priv->info->gen < 5);
  1425. if (pll == NULL)
  1426. return;
  1427. if (WARN_ON(pll->refcount == 0))
  1428. return;
  1429. DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
  1430. pll->pll_reg, pll->active, pll->on,
  1431. intel_crtc->base.base.id);
  1432. if (WARN_ON(pll->active == 0)) {
  1433. assert_pch_pll_disabled(dev_priv, pll, NULL);
  1434. return;
  1435. }
  1436. if (--pll->active) {
  1437. assert_pch_pll_enabled(dev_priv, pll, NULL);
  1438. return;
  1439. }
  1440. DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
  1441. /* Make sure transcoder isn't still depending on us */
  1442. assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
  1443. reg = pll->pll_reg;
  1444. val = I915_READ(reg);
  1445. val &= ~DPLL_VCO_ENABLE;
  1446. I915_WRITE(reg, val);
  1447. POSTING_READ(reg);
  1448. udelay(200);
  1449. pll->on = false;
  1450. }
  1451. static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
  1452. enum pipe pipe)
  1453. {
  1454. struct drm_device *dev = dev_priv->dev;
  1455. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  1456. uint32_t reg, val, pipeconf_val;
  1457. /* PCH only available on ILK+ */
  1458. BUG_ON(dev_priv->info->gen < 5);
  1459. /* Make sure PCH DPLL is enabled */
  1460. assert_pch_pll_enabled(dev_priv,
  1461. to_intel_crtc(crtc)->pch_pll,
  1462. to_intel_crtc(crtc));
  1463. /* FDI must be feeding us bits for PCH ports */
  1464. assert_fdi_tx_enabled(dev_priv, pipe);
  1465. assert_fdi_rx_enabled(dev_priv, pipe);
  1466. if (HAS_PCH_CPT(dev)) {
  1467. /* Workaround: Set the timing override bit before enabling the
  1468. * pch transcoder. */
  1469. reg = TRANS_CHICKEN2(pipe);
  1470. val = I915_READ(reg);
  1471. val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
  1472. I915_WRITE(reg, val);
  1473. }
  1474. reg = TRANSCONF(pipe);
  1475. val = I915_READ(reg);
  1476. pipeconf_val = I915_READ(PIPECONF(pipe));
  1477. if (HAS_PCH_IBX(dev_priv->dev)) {
  1478. /*
  1479. * make the BPC in transcoder be consistent with
  1480. * that in pipeconf reg.
  1481. */
  1482. val &= ~PIPECONF_BPC_MASK;
  1483. val |= pipeconf_val & PIPECONF_BPC_MASK;
  1484. }
  1485. val &= ~TRANS_INTERLACE_MASK;
  1486. if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
  1487. if (HAS_PCH_IBX(dev_priv->dev) &&
  1488. intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
  1489. val |= TRANS_LEGACY_INTERLACED_ILK;
  1490. else
  1491. val |= TRANS_INTERLACED;
  1492. else
  1493. val |= TRANS_PROGRESSIVE;
  1494. I915_WRITE(reg, val | TRANS_ENABLE);
  1495. if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
  1496. DRM_ERROR("failed to enable transcoder %d\n", pipe);
  1497. }
  1498. static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
  1499. enum transcoder cpu_transcoder)
  1500. {
  1501. u32 val, pipeconf_val;
  1502. /* PCH only available on ILK+ */
  1503. BUG_ON(dev_priv->info->gen < 5);
  1504. /* FDI must be feeding us bits for PCH ports */
  1505. assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
  1506. assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
  1507. /* Workaround: set timing override bit. */
  1508. val = I915_READ(_TRANSA_CHICKEN2);
  1509. val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
  1510. I915_WRITE(_TRANSA_CHICKEN2, val);
  1511. val = TRANS_ENABLE;
  1512. pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
  1513. if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
  1514. PIPECONF_INTERLACED_ILK)
  1515. val |= TRANS_INTERLACED;
  1516. else
  1517. val |= TRANS_PROGRESSIVE;
  1518. I915_WRITE(TRANSCONF(TRANSCODER_A), val);
  1519. if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
  1520. DRM_ERROR("Failed to enable PCH transcoder\n");
  1521. }
  1522. static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
  1523. enum pipe pipe)
  1524. {
  1525. struct drm_device *dev = dev_priv->dev;
  1526. uint32_t reg, val;
  1527. /* FDI relies on the transcoder */
  1528. assert_fdi_tx_disabled(dev_priv, pipe);
  1529. assert_fdi_rx_disabled(dev_priv, pipe);
  1530. /* Ports must be off as well */
  1531. assert_pch_ports_disabled(dev_priv, pipe);
  1532. reg = TRANSCONF(pipe);
  1533. val = I915_READ(reg);
  1534. val &= ~TRANS_ENABLE;
  1535. I915_WRITE(reg, val);
  1536. /* wait for PCH transcoder off, transcoder state */
  1537. if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
  1538. DRM_ERROR("failed to disable transcoder %d\n", pipe);
  1539. if (!HAS_PCH_IBX(dev)) {
  1540. /* Workaround: Clear the timing override chicken bit again. */
  1541. reg = TRANS_CHICKEN2(pipe);
  1542. val = I915_READ(reg);
  1543. val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
  1544. I915_WRITE(reg, val);
  1545. }
  1546. }
  1547. static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
  1548. {
  1549. u32 val;
  1550. val = I915_READ(_TRANSACONF);
  1551. val &= ~TRANS_ENABLE;
  1552. I915_WRITE(_TRANSACONF, val);
  1553. /* wait for PCH transcoder off, transcoder state */
  1554. if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
  1555. DRM_ERROR("Failed to disable PCH transcoder\n");
  1556. /* Workaround: clear timing override bit. */
  1557. val = I915_READ(_TRANSA_CHICKEN2);
  1558. val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
  1559. I915_WRITE(_TRANSA_CHICKEN2, val);
  1560. }
  1561. /**
  1562. * intel_enable_pipe - enable a pipe, asserting requirements
  1563. * @dev_priv: i915 private structure
  1564. * @pipe: pipe to enable
  1565. * @pch_port: on ILK+, is this pipe driving a PCH port or not
  1566. *
  1567. * Enable @pipe, making sure that various hardware specific requirements
  1568. * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
  1569. *
  1570. * @pipe should be %PIPE_A or %PIPE_B.
  1571. *
  1572. * Will wait until the pipe is actually running (i.e. first vblank) before
  1573. * returning.
  1574. */
  1575. static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
  1576. bool pch_port)
  1577. {
  1578. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1579. pipe);
  1580. enum pipe pch_transcoder;
  1581. int reg;
  1582. u32 val;
  1583. if (HAS_PCH_LPT(dev_priv->dev))
  1584. pch_transcoder = TRANSCODER_A;
  1585. else
  1586. pch_transcoder = pipe;
  1587. /*
  1588. * A pipe without a PLL won't actually be able to drive bits from
  1589. * a plane. On ILK+ the pipe PLLs are integrated, so we don't
  1590. * need the check.
  1591. */
  1592. if (!HAS_PCH_SPLIT(dev_priv->dev))
  1593. assert_pll_enabled(dev_priv, pipe);
  1594. else {
  1595. if (pch_port) {
  1596. /* if driving the PCH, we need FDI enabled */
  1597. assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
  1598. assert_fdi_tx_pll_enabled(dev_priv,
  1599. (enum pipe) cpu_transcoder);
  1600. }
  1601. /* FIXME: assert CPU port conditions for SNB+ */
  1602. }
  1603. reg = PIPECONF(cpu_transcoder);
  1604. val = I915_READ(reg);
  1605. if (val & PIPECONF_ENABLE)
  1606. return;
  1607. I915_WRITE(reg, val | PIPECONF_ENABLE);
  1608. intel_wait_for_vblank(dev_priv->dev, pipe);
  1609. }
  1610. /**
  1611. * intel_disable_pipe - disable a pipe, asserting requirements
  1612. * @dev_priv: i915 private structure
  1613. * @pipe: pipe to disable
  1614. *
  1615. * Disable @pipe, making sure that various hardware specific requirements
  1616. * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
  1617. *
  1618. * @pipe should be %PIPE_A or %PIPE_B.
  1619. *
  1620. * Will wait until the pipe has shut down before returning.
  1621. */
  1622. static void intel_disable_pipe(struct drm_i915_private *dev_priv,
  1623. enum pipe pipe)
  1624. {
  1625. enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
  1626. pipe);
  1627. int reg;
  1628. u32 val;
  1629. /*
  1630. * Make sure planes won't keep trying to pump pixels to us,
  1631. * or we might hang the display.
  1632. */
  1633. assert_planes_disabled(dev_priv, pipe);
  1634. /* Don't disable pipe A or pipe A PLLs if needed */
  1635. if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  1636. return;
  1637. reg = PIPECONF(cpu_transcoder);
  1638. val = I915_READ(reg);
  1639. if ((val & PIPECONF_ENABLE) == 0)
  1640. return;
  1641. I915_WRITE(reg, val & ~PIPECONF_ENABLE);
  1642. intel_wait_for_pipe_off(dev_priv->dev, pipe);
  1643. }
  1644. /*
  1645. * Plane regs are double buffered, going from enabled->disabled needs a
  1646. * trigger in order to latch. The display address reg provides this.
  1647. */
  1648. void intel_flush_display_plane(struct drm_i915_private *dev_priv,
  1649. enum plane plane)
  1650. {
  1651. if (dev_priv->info->gen >= 4)
  1652. I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
  1653. else
  1654. I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
  1655. }
  1656. /**
  1657. * intel_enable_plane - enable a display plane on a given pipe
  1658. * @dev_priv: i915 private structure
  1659. * @plane: plane to enable
  1660. * @pipe: pipe being fed
  1661. *
  1662. * Enable @plane on @pipe, making sure that @pipe is running first.
  1663. */
  1664. static void intel_enable_plane(struct drm_i915_private *dev_priv,
  1665. enum plane plane, enum pipe pipe)
  1666. {
  1667. int reg;
  1668. u32 val;
  1669. /* If the pipe isn't enabled, we can't pump pixels and may hang */
  1670. assert_pipe_enabled(dev_priv, pipe);
  1671. reg = DSPCNTR(plane);
  1672. val = I915_READ(reg);
  1673. if (val & DISPLAY_PLANE_ENABLE)
  1674. return;
  1675. I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
  1676. intel_flush_display_plane(dev_priv, plane);
  1677. intel_wait_for_vblank(dev_priv->dev, pipe);
  1678. }
  1679. /**
  1680. * intel_disable_plane - disable a display plane
  1681. * @dev_priv: i915 private structure
  1682. * @plane: plane to disable
  1683. * @pipe: pipe consuming the data
  1684. *
  1685. * Disable @plane; should be an independent operation.
  1686. */
  1687. static void intel_disable_plane(struct drm_i915_private *dev_priv,
  1688. enum plane plane, enum pipe pipe)
  1689. {
  1690. int reg;
  1691. u32 val;
  1692. reg = DSPCNTR(plane);
  1693. val = I915_READ(reg);
  1694. if ((val & DISPLAY_PLANE_ENABLE) == 0)
  1695. return;
  1696. I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
  1697. intel_flush_display_plane(dev_priv, plane);
  1698. intel_wait_for_vblank(dev_priv->dev, pipe);
  1699. }
  1700. int
  1701. intel_pin_and_fence_fb_obj(struct drm_device *dev,
  1702. struct drm_i915_gem_object *obj,
  1703. struct intel_ring_buffer *pipelined)
  1704. {
  1705. struct drm_i915_private *dev_priv = dev->dev_private;
  1706. u32 alignment;
  1707. int ret;
  1708. switch (obj->tiling_mode) {
  1709. case I915_TILING_NONE:
  1710. if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
  1711. alignment = 128 * 1024;
  1712. else if (INTEL_INFO(dev)->gen >= 4)
  1713. alignment = 4 * 1024;
  1714. else
  1715. alignment = 64 * 1024;
  1716. break;
  1717. case I915_TILING_X:
  1718. /* pin() will align the object as required by fence */
  1719. alignment = 0;
  1720. break;
  1721. case I915_TILING_Y:
  1722. /* FIXME: Is this true? */
  1723. DRM_ERROR("Y tiled not allowed for scan out buffers\n");
  1724. return -EINVAL;
  1725. default:
  1726. BUG();
  1727. }
  1728. dev_priv->mm.interruptible = false;
  1729. ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
  1730. if (ret)
  1731. goto err_interruptible;
  1732. /* Install a fence for tiled scan-out. Pre-i965 always needs a
  1733. * fence, whereas 965+ only requires a fence if using
  1734. * framebuffer compression. For simplicity, we always install
  1735. * a fence as the cost is not that onerous.
  1736. */
  1737. ret = i915_gem_object_get_fence(obj);
  1738. if (ret)
  1739. goto err_unpin;
  1740. i915_gem_object_pin_fence(obj);
  1741. dev_priv->mm.interruptible = true;
  1742. return 0;
  1743. err_unpin:
  1744. i915_gem_object_unpin(obj);
  1745. err_interruptible:
  1746. dev_priv->mm.interruptible = true;
  1747. return ret;
  1748. }
  1749. void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
  1750. {
  1751. i915_gem_object_unpin_fence(obj);
  1752. i915_gem_object_unpin(obj);
  1753. }
  1754. /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
  1755. * is assumed to be a power-of-two. */
  1756. unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
  1757. unsigned int bpp,
  1758. unsigned int pitch)
  1759. {
  1760. int tile_rows, tiles;
  1761. tile_rows = *y / 8;
  1762. *y %= 8;
  1763. tiles = *x / (512/bpp);
  1764. *x %= 512/bpp;
  1765. return tile_rows * pitch * 8 + tiles * 4096;
  1766. }
  1767. static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1768. int x, int y)
  1769. {
  1770. struct drm_device *dev = crtc->dev;
  1771. struct drm_i915_private *dev_priv = dev->dev_private;
  1772. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1773. struct intel_framebuffer *intel_fb;
  1774. struct drm_i915_gem_object *obj;
  1775. int plane = intel_crtc->plane;
  1776. unsigned long linear_offset;
  1777. u32 dspcntr;
  1778. u32 reg;
  1779. switch (plane) {
  1780. case 0:
  1781. case 1:
  1782. break;
  1783. default:
  1784. DRM_ERROR("Can't update plane %d in SAREA\n", plane);
  1785. return -EINVAL;
  1786. }
  1787. intel_fb = to_intel_framebuffer(fb);
  1788. obj = intel_fb->obj;
  1789. reg = DSPCNTR(plane);
  1790. dspcntr = I915_READ(reg);
  1791. /* Mask out pixel format bits in case we change it */
  1792. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1793. switch (fb->pixel_format) {
  1794. case DRM_FORMAT_C8:
  1795. dspcntr |= DISPPLANE_8BPP;
  1796. break;
  1797. case DRM_FORMAT_XRGB1555:
  1798. case DRM_FORMAT_ARGB1555:
  1799. dspcntr |= DISPPLANE_BGRX555;
  1800. break;
  1801. case DRM_FORMAT_RGB565:
  1802. dspcntr |= DISPPLANE_BGRX565;
  1803. break;
  1804. case DRM_FORMAT_XRGB8888:
  1805. case DRM_FORMAT_ARGB8888:
  1806. dspcntr |= DISPPLANE_BGRX888;
  1807. break;
  1808. case DRM_FORMAT_XBGR8888:
  1809. case DRM_FORMAT_ABGR8888:
  1810. dspcntr |= DISPPLANE_RGBX888;
  1811. break;
  1812. case DRM_FORMAT_XRGB2101010:
  1813. case DRM_FORMAT_ARGB2101010:
  1814. dspcntr |= DISPPLANE_BGRX101010;
  1815. break;
  1816. case DRM_FORMAT_XBGR2101010:
  1817. case DRM_FORMAT_ABGR2101010:
  1818. dspcntr |= DISPPLANE_RGBX101010;
  1819. break;
  1820. default:
  1821. DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
  1822. return -EINVAL;
  1823. }
  1824. if (INTEL_INFO(dev)->gen >= 4) {
  1825. if (obj->tiling_mode != I915_TILING_NONE)
  1826. dspcntr |= DISPPLANE_TILED;
  1827. else
  1828. dspcntr &= ~DISPPLANE_TILED;
  1829. }
  1830. I915_WRITE(reg, dspcntr);
  1831. linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
  1832. if (INTEL_INFO(dev)->gen >= 4) {
  1833. intel_crtc->dspaddr_offset =
  1834. intel_gen4_compute_offset_xtiled(&x, &y,
  1835. fb->bits_per_pixel / 8,
  1836. fb->pitches[0]);
  1837. linear_offset -= intel_crtc->dspaddr_offset;
  1838. } else {
  1839. intel_crtc->dspaddr_offset = linear_offset;
  1840. }
  1841. DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
  1842. obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
  1843. I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  1844. if (INTEL_INFO(dev)->gen >= 4) {
  1845. I915_MODIFY_DISPBASE(DSPSURF(plane),
  1846. obj->gtt_offset + intel_crtc->dspaddr_offset);
  1847. I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  1848. I915_WRITE(DSPLINOFF(plane), linear_offset);
  1849. } else
  1850. I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
  1851. POSTING_READ(reg);
  1852. return 0;
  1853. }
  1854. static int ironlake_update_plane(struct drm_crtc *crtc,
  1855. struct drm_framebuffer *fb, int x, int y)
  1856. {
  1857. struct drm_device *dev = crtc->dev;
  1858. struct drm_i915_private *dev_priv = dev->dev_private;
  1859. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1860. struct intel_framebuffer *intel_fb;
  1861. struct drm_i915_gem_object *obj;
  1862. int plane = intel_crtc->plane;
  1863. unsigned long linear_offset;
  1864. u32 dspcntr;
  1865. u32 reg;
  1866. switch (plane) {
  1867. case 0:
  1868. case 1:
  1869. case 2:
  1870. break;
  1871. default:
  1872. DRM_ERROR("Can't update plane %d in SAREA\n", plane);
  1873. return -EINVAL;
  1874. }
  1875. intel_fb = to_intel_framebuffer(fb);
  1876. obj = intel_fb->obj;
  1877. reg = DSPCNTR(plane);
  1878. dspcntr = I915_READ(reg);
  1879. /* Mask out pixel format bits in case we change it */
  1880. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1881. switch (fb->pixel_format) {
  1882. case DRM_FORMAT_C8:
  1883. dspcntr |= DISPPLANE_8BPP;
  1884. break;
  1885. case DRM_FORMAT_RGB565:
  1886. dspcntr |= DISPPLANE_BGRX565;
  1887. break;
  1888. case DRM_FORMAT_XRGB8888:
  1889. case DRM_FORMAT_ARGB8888:
  1890. dspcntr |= DISPPLANE_BGRX888;
  1891. break;
  1892. case DRM_FORMAT_XBGR8888:
  1893. case DRM_FORMAT_ABGR8888:
  1894. dspcntr |= DISPPLANE_RGBX888;
  1895. break;
  1896. case DRM_FORMAT_XRGB2101010:
  1897. case DRM_FORMAT_ARGB2101010:
  1898. dspcntr |= DISPPLANE_BGRX101010;
  1899. break;
  1900. case DRM_FORMAT_XBGR2101010:
  1901. case DRM_FORMAT_ABGR2101010:
  1902. dspcntr |= DISPPLANE_RGBX101010;
  1903. break;
  1904. default:
  1905. DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
  1906. return -EINVAL;
  1907. }
  1908. if (obj->tiling_mode != I915_TILING_NONE)
  1909. dspcntr |= DISPPLANE_TILED;
  1910. else
  1911. dspcntr &= ~DISPPLANE_TILED;
  1912. /* must disable */
  1913. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1914. I915_WRITE(reg, dspcntr);
  1915. linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
  1916. intel_crtc->dspaddr_offset =
  1917. intel_gen4_compute_offset_xtiled(&x, &y,
  1918. fb->bits_per_pixel / 8,
  1919. fb->pitches[0]);
  1920. linear_offset -= intel_crtc->dspaddr_offset;
  1921. DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
  1922. obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
  1923. I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  1924. I915_MODIFY_DISPBASE(DSPSURF(plane),
  1925. obj->gtt_offset + intel_crtc->dspaddr_offset);
  1926. if (IS_HASWELL(dev)) {
  1927. I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
  1928. } else {
  1929. I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  1930. I915_WRITE(DSPLINOFF(plane), linear_offset);
  1931. }
  1932. POSTING_READ(reg);
  1933. return 0;
  1934. }
  1935. /* Assume fb object is pinned & idle & fenced and just update base pointers */
  1936. static int
  1937. intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1938. int x, int y, enum mode_set_atomic state)
  1939. {
  1940. struct drm_device *dev = crtc->dev;
  1941. struct drm_i915_private *dev_priv = dev->dev_private;
  1942. if (dev_priv->display.disable_fbc)
  1943. dev_priv->display.disable_fbc(dev);
  1944. intel_increase_pllclock(crtc);
  1945. return dev_priv->display.update_plane(crtc, fb, x, y);
  1946. }
  1947. static int
  1948. intel_finish_fb(struct drm_framebuffer *old_fb)
  1949. {
  1950. struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
  1951. struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
  1952. bool was_interruptible = dev_priv->mm.interruptible;
  1953. int ret;
  1954. WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
  1955. wait_event(dev_priv->pending_flip_queue,
  1956. i915_reset_in_progress(&dev_priv->gpu_error) ||
  1957. atomic_read(&obj->pending_flip) == 0);
  1958. /* Big Hammer, we also need to ensure that any pending
  1959. * MI_WAIT_FOR_EVENT inside a user batch buffer on the
  1960. * current scanout is retired before unpinning the old
  1961. * framebuffer.
  1962. *
  1963. * This should only fail upon a hung GPU, in which case we
  1964. * can safely continue.
  1965. */
  1966. dev_priv->mm.interruptible = false;
  1967. ret = i915_gem_object_finish_gpu(obj);
  1968. dev_priv->mm.interruptible = was_interruptible;
  1969. return ret;
  1970. }
  1971. static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
  1972. {
  1973. struct drm_device *dev = crtc->dev;
  1974. struct drm_i915_master_private *master_priv;
  1975. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1976. if (!dev->primary->master)
  1977. return;
  1978. master_priv = dev->primary->master->driver_priv;
  1979. if (!master_priv->sarea_priv)
  1980. return;
  1981. switch (intel_crtc->pipe) {
  1982. case 0:
  1983. master_priv->sarea_priv->pipeA_x = x;
  1984. master_priv->sarea_priv->pipeA_y = y;
  1985. break;
  1986. case 1:
  1987. master_priv->sarea_priv->pipeB_x = x;
  1988. master_priv->sarea_priv->pipeB_y = y;
  1989. break;
  1990. default:
  1991. break;
  1992. }
  1993. }
  1994. static int
  1995. intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  1996. struct drm_framebuffer *fb)
  1997. {
  1998. struct drm_device *dev = crtc->dev;
  1999. struct drm_i915_private *dev_priv = dev->dev_private;
  2000. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2001. struct drm_framebuffer *old_fb;
  2002. int ret;
  2003. /* no fb bound */
  2004. if (!fb) {
  2005. DRM_ERROR("No FB bound\n");
  2006. return 0;
  2007. }
  2008. if(intel_crtc->plane > dev_priv->num_pipe) {
  2009. DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
  2010. intel_crtc->plane,
  2011. dev_priv->num_pipe);
  2012. return -EINVAL;
  2013. }
  2014. mutex_lock(&dev->struct_mutex);
  2015. ret = intel_pin_and_fence_fb_obj(dev,
  2016. to_intel_framebuffer(fb)->obj,
  2017. NULL);
  2018. if (ret != 0) {
  2019. mutex_unlock(&dev->struct_mutex);
  2020. DRM_ERROR("pin & fence failed\n");
  2021. return ret;
  2022. }
  2023. if (crtc->fb)
  2024. intel_finish_fb(crtc->fb);
  2025. ret = dev_priv->display.update_plane(crtc, fb, x, y);
  2026. if (ret) {
  2027. intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
  2028. mutex_unlock(&dev->struct_mutex);
  2029. DRM_ERROR("failed to update base address\n");
  2030. return ret;
  2031. }
  2032. old_fb = crtc->fb;
  2033. crtc->fb = fb;
  2034. crtc->x = x;
  2035. crtc->y = y;
  2036. if (old_fb) {
  2037. intel_wait_for_vblank(dev, intel_crtc->pipe);
  2038. intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
  2039. }
  2040. intel_update_fbc(dev);
  2041. mutex_unlock(&dev->struct_mutex);
  2042. intel_crtc_update_sarea_pos(crtc, x, y);
  2043. return 0;
  2044. }
  2045. static void intel_fdi_normal_train(struct drm_crtc *crtc)
  2046. {
  2047. struct drm_device *dev = crtc->dev;
  2048. struct drm_i915_private *dev_priv = dev->dev_private;
  2049. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2050. int pipe = intel_crtc->pipe;
  2051. u32 reg, temp;
  2052. /* enable normal train */
  2053. reg = FDI_TX_CTL(pipe);
  2054. temp = I915_READ(reg);
  2055. if (IS_IVYBRIDGE(dev)) {
  2056. temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  2057. temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
  2058. } else {
  2059. temp &= ~FDI_LINK_TRAIN_NONE;
  2060. temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
  2061. }
  2062. I915_WRITE(reg, temp);
  2063. reg = FDI_RX_CTL(pipe);
  2064. temp = I915_READ(reg);
  2065. if (HAS_PCH_CPT(dev)) {
  2066. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2067. temp |= FDI_LINK_TRAIN_NORMAL_CPT;
  2068. } else {
  2069. temp &= ~FDI_LINK_TRAIN_NONE;
  2070. temp |= FDI_LINK_TRAIN_NONE;
  2071. }
  2072. I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
  2073. /* wait one idle pattern time */
  2074. POSTING_READ(reg);
  2075. udelay(1000);
  2076. /* IVB wants error correction enabled */
  2077. if (IS_IVYBRIDGE(dev))
  2078. I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
  2079. FDI_FE_ERRC_ENABLE);
  2080. }
  2081. static void ivb_modeset_global_resources(struct drm_device *dev)
  2082. {
  2083. struct drm_i915_private *dev_priv = dev->dev_private;
  2084. struct intel_crtc *pipe_B_crtc =
  2085. to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
  2086. struct intel_crtc *pipe_C_crtc =
  2087. to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
  2088. uint32_t temp;
  2089. /* When everything is off disable fdi C so that we could enable fdi B
  2090. * with all lanes. XXX: This misses the case where a pipe is not using
  2091. * any pch resources and so doesn't need any fdi lanes. */
  2092. if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
  2093. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
  2094. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
  2095. temp = I915_READ(SOUTH_CHICKEN1);
  2096. temp &= ~FDI_BC_BIFURCATION_SELECT;
  2097. DRM_DEBUG_KMS("disabling fdi C rx\n");
  2098. I915_WRITE(SOUTH_CHICKEN1, temp);
  2099. }
  2100. }
  2101. /* The FDI link training functions for ILK/Ibexpeak. */
  2102. static void ironlake_fdi_link_train(struct drm_crtc *crtc)
  2103. {
  2104. struct drm_device *dev = crtc->dev;
  2105. struct drm_i915_private *dev_priv = dev->dev_private;
  2106. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2107. int pipe = intel_crtc->pipe;
  2108. int plane = intel_crtc->plane;
  2109. u32 reg, temp, tries;
  2110. /* FDI needs bits from pipe & plane first */
  2111. assert_pipe_enabled(dev_priv, pipe);
  2112. assert_plane_enabled(dev_priv, plane);
  2113. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2114. for train result */
  2115. reg = FDI_RX_IMR(pipe);
  2116. temp = I915_READ(reg);
  2117. temp &= ~FDI_RX_SYMBOL_LOCK;
  2118. temp &= ~FDI_RX_BIT_LOCK;
  2119. I915_WRITE(reg, temp);
  2120. I915_READ(reg);
  2121. udelay(150);
  2122. /* enable CPU FDI TX and PCH FDI RX */
  2123. reg = FDI_TX_CTL(pipe);
  2124. temp = I915_READ(reg);
  2125. temp &= ~(7 << 19);
  2126. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2127. temp &= ~FDI_LINK_TRAIN_NONE;
  2128. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2129. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2130. reg = FDI_RX_CTL(pipe);
  2131. temp = I915_READ(reg);
  2132. temp &= ~FDI_LINK_TRAIN_NONE;
  2133. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2134. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2135. POSTING_READ(reg);
  2136. udelay(150);
  2137. /* Ironlake workaround, enable clock pointer after FDI enable*/
  2138. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2139. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
  2140. FDI_RX_PHASE_SYNC_POINTER_EN);
  2141. reg = FDI_RX_IIR(pipe);
  2142. for (tries = 0; tries < 5; tries++) {
  2143. temp = I915_READ(reg);
  2144. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2145. if ((temp & FDI_RX_BIT_LOCK)) {
  2146. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2147. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2148. break;
  2149. }
  2150. }
  2151. if (tries == 5)
  2152. DRM_ERROR("FDI train 1 fail!\n");
  2153. /* Train 2 */
  2154. reg = FDI_TX_CTL(pipe);
  2155. temp = I915_READ(reg);
  2156. temp &= ~FDI_LINK_TRAIN_NONE;
  2157. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2158. I915_WRITE(reg, temp);
  2159. reg = FDI_RX_CTL(pipe);
  2160. temp = I915_READ(reg);
  2161. temp &= ~FDI_LINK_TRAIN_NONE;
  2162. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2163. I915_WRITE(reg, temp);
  2164. POSTING_READ(reg);
  2165. udelay(150);
  2166. reg = FDI_RX_IIR(pipe);
  2167. for (tries = 0; tries < 5; tries++) {
  2168. temp = I915_READ(reg);
  2169. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2170. if (temp & FDI_RX_SYMBOL_LOCK) {
  2171. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2172. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2173. break;
  2174. }
  2175. }
  2176. if (tries == 5)
  2177. DRM_ERROR("FDI train 2 fail!\n");
  2178. DRM_DEBUG_KMS("FDI train done\n");
  2179. }
  2180. static const int snb_b_fdi_train_param[] = {
  2181. FDI_LINK_TRAIN_400MV_0DB_SNB_B,
  2182. FDI_LINK_TRAIN_400MV_6DB_SNB_B,
  2183. FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
  2184. FDI_LINK_TRAIN_800MV_0DB_SNB_B,
  2185. };
  2186. /* The FDI link training functions for SNB/Cougarpoint. */
  2187. static void gen6_fdi_link_train(struct drm_crtc *crtc)
  2188. {
  2189. struct drm_device *dev = crtc->dev;
  2190. struct drm_i915_private *dev_priv = dev->dev_private;
  2191. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2192. int pipe = intel_crtc->pipe;
  2193. u32 reg, temp, i, retry;
  2194. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2195. for train result */
  2196. reg = FDI_RX_IMR(pipe);
  2197. temp = I915_READ(reg);
  2198. temp &= ~FDI_RX_SYMBOL_LOCK;
  2199. temp &= ~FDI_RX_BIT_LOCK;
  2200. I915_WRITE(reg, temp);
  2201. POSTING_READ(reg);
  2202. udelay(150);
  2203. /* enable CPU FDI TX and PCH FDI RX */
  2204. reg = FDI_TX_CTL(pipe);
  2205. temp = I915_READ(reg);
  2206. temp &= ~(7 << 19);
  2207. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2208. temp &= ~FDI_LINK_TRAIN_NONE;
  2209. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2210. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2211. /* SNB-B */
  2212. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2213. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2214. I915_WRITE(FDI_RX_MISC(pipe),
  2215. FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
  2216. reg = FDI_RX_CTL(pipe);
  2217. temp = I915_READ(reg);
  2218. if (HAS_PCH_CPT(dev)) {
  2219. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2220. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2221. } else {
  2222. temp &= ~FDI_LINK_TRAIN_NONE;
  2223. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2224. }
  2225. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2226. POSTING_READ(reg);
  2227. udelay(150);
  2228. for (i = 0; i < 4; i++) {
  2229. reg = FDI_TX_CTL(pipe);
  2230. temp = I915_READ(reg);
  2231. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2232. temp |= snb_b_fdi_train_param[i];
  2233. I915_WRITE(reg, temp);
  2234. POSTING_READ(reg);
  2235. udelay(500);
  2236. for (retry = 0; retry < 5; retry++) {
  2237. reg = FDI_RX_IIR(pipe);
  2238. temp = I915_READ(reg);
  2239. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2240. if (temp & FDI_RX_BIT_LOCK) {
  2241. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2242. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2243. break;
  2244. }
  2245. udelay(50);
  2246. }
  2247. if (retry < 5)
  2248. break;
  2249. }
  2250. if (i == 4)
  2251. DRM_ERROR("FDI train 1 fail!\n");
  2252. /* Train 2 */
  2253. reg = FDI_TX_CTL(pipe);
  2254. temp = I915_READ(reg);
  2255. temp &= ~FDI_LINK_TRAIN_NONE;
  2256. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2257. if (IS_GEN6(dev)) {
  2258. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2259. /* SNB-B */
  2260. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2261. }
  2262. I915_WRITE(reg, temp);
  2263. reg = FDI_RX_CTL(pipe);
  2264. temp = I915_READ(reg);
  2265. if (HAS_PCH_CPT(dev)) {
  2266. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2267. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2268. } else {
  2269. temp &= ~FDI_LINK_TRAIN_NONE;
  2270. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2271. }
  2272. I915_WRITE(reg, temp);
  2273. POSTING_READ(reg);
  2274. udelay(150);
  2275. for (i = 0; i < 4; i++) {
  2276. reg = FDI_TX_CTL(pipe);
  2277. temp = I915_READ(reg);
  2278. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2279. temp |= snb_b_fdi_train_param[i];
  2280. I915_WRITE(reg, temp);
  2281. POSTING_READ(reg);
  2282. udelay(500);
  2283. for (retry = 0; retry < 5; retry++) {
  2284. reg = FDI_RX_IIR(pipe);
  2285. temp = I915_READ(reg);
  2286. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2287. if (temp & FDI_RX_SYMBOL_LOCK) {
  2288. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2289. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2290. break;
  2291. }
  2292. udelay(50);
  2293. }
  2294. if (retry < 5)
  2295. break;
  2296. }
  2297. if (i == 4)
  2298. DRM_ERROR("FDI train 2 fail!\n");
  2299. DRM_DEBUG_KMS("FDI train done.\n");
  2300. }
  2301. /* Manual link training for Ivy Bridge A0 parts */
  2302. static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
  2303. {
  2304. struct drm_device *dev = crtc->dev;
  2305. struct drm_i915_private *dev_priv = dev->dev_private;
  2306. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2307. int pipe = intel_crtc->pipe;
  2308. u32 reg, temp, i;
  2309. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2310. for train result */
  2311. reg = FDI_RX_IMR(pipe);
  2312. temp = I915_READ(reg);
  2313. temp &= ~FDI_RX_SYMBOL_LOCK;
  2314. temp &= ~FDI_RX_BIT_LOCK;
  2315. I915_WRITE(reg, temp);
  2316. POSTING_READ(reg);
  2317. udelay(150);
  2318. DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
  2319. I915_READ(FDI_RX_IIR(pipe)));
  2320. /* enable CPU FDI TX and PCH FDI RX */
  2321. reg = FDI_TX_CTL(pipe);
  2322. temp = I915_READ(reg);
  2323. temp &= ~(7 << 19);
  2324. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2325. temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
  2326. temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
  2327. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2328. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2329. temp |= FDI_COMPOSITE_SYNC;
  2330. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2331. I915_WRITE(FDI_RX_MISC(pipe),
  2332. FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
  2333. reg = FDI_RX_CTL(pipe);
  2334. temp = I915_READ(reg);
  2335. temp &= ~FDI_LINK_TRAIN_AUTO;
  2336. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2337. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2338. temp |= FDI_COMPOSITE_SYNC;
  2339. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2340. POSTING_READ(reg);
  2341. udelay(150);
  2342. for (i = 0; i < 4; i++) {
  2343. reg = FDI_TX_CTL(pipe);
  2344. temp = I915_READ(reg);
  2345. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2346. temp |= snb_b_fdi_train_param[i];
  2347. I915_WRITE(reg, temp);
  2348. POSTING_READ(reg);
  2349. udelay(500);
  2350. reg = FDI_RX_IIR(pipe);
  2351. temp = I915_READ(reg);
  2352. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2353. if (temp & FDI_RX_BIT_LOCK ||
  2354. (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
  2355. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2356. DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
  2357. break;
  2358. }
  2359. }
  2360. if (i == 4)
  2361. DRM_ERROR("FDI train 1 fail!\n");
  2362. /* Train 2 */
  2363. reg = FDI_TX_CTL(pipe);
  2364. temp = I915_READ(reg);
  2365. temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  2366. temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
  2367. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2368. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2369. I915_WRITE(reg, temp);
  2370. reg = FDI_RX_CTL(pipe);
  2371. temp = I915_READ(reg);
  2372. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2373. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2374. I915_WRITE(reg, temp);
  2375. POSTING_READ(reg);
  2376. udelay(150);
  2377. for (i = 0; i < 4; i++) {
  2378. reg = FDI_TX_CTL(pipe);
  2379. temp = I915_READ(reg);
  2380. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2381. temp |= snb_b_fdi_train_param[i];
  2382. I915_WRITE(reg, temp);
  2383. POSTING_READ(reg);
  2384. udelay(500);
  2385. reg = FDI_RX_IIR(pipe);
  2386. temp = I915_READ(reg);
  2387. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2388. if (temp & FDI_RX_SYMBOL_LOCK) {
  2389. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2390. DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
  2391. break;
  2392. }
  2393. }
  2394. if (i == 4)
  2395. DRM_ERROR("FDI train 2 fail!\n");
  2396. DRM_DEBUG_KMS("FDI train done.\n");
  2397. }
  2398. static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
  2399. {
  2400. struct drm_device *dev = intel_crtc->base.dev;
  2401. struct drm_i915_private *dev_priv = dev->dev_private;
  2402. int pipe = intel_crtc->pipe;
  2403. u32 reg, temp;
  2404. /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
  2405. reg = FDI_RX_CTL(pipe);
  2406. temp = I915_READ(reg);
  2407. temp &= ~((0x7 << 19) | (0x7 << 16));
  2408. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2409. temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  2410. I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
  2411. POSTING_READ(reg);
  2412. udelay(200);
  2413. /* Switch from Rawclk to PCDclk */
  2414. temp = I915_READ(reg);
  2415. I915_WRITE(reg, temp | FDI_PCDCLK);
  2416. POSTING_READ(reg);
  2417. udelay(200);
  2418. /* Enable CPU FDI TX PLL, always on for Ironlake */
  2419. reg = FDI_TX_CTL(pipe);
  2420. temp = I915_READ(reg);
  2421. if ((temp & FDI_TX_PLL_ENABLE) == 0) {
  2422. I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
  2423. POSTING_READ(reg);
  2424. udelay(100);
  2425. }
  2426. }
  2427. static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
  2428. {
  2429. struct drm_device *dev = intel_crtc->base.dev;
  2430. struct drm_i915_private *dev_priv = dev->dev_private;
  2431. int pipe = intel_crtc->pipe;
  2432. u32 reg, temp;
  2433. /* Switch from PCDclk to Rawclk */
  2434. reg = FDI_RX_CTL(pipe);
  2435. temp = I915_READ(reg);
  2436. I915_WRITE(reg, temp & ~FDI_PCDCLK);
  2437. /* Disable CPU FDI TX PLL */
  2438. reg = FDI_TX_CTL(pipe);
  2439. temp = I915_READ(reg);
  2440. I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
  2441. POSTING_READ(reg);
  2442. udelay(100);
  2443. reg = FDI_RX_CTL(pipe);
  2444. temp = I915_READ(reg);
  2445. I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
  2446. /* Wait for the clocks to turn off. */
  2447. POSTING_READ(reg);
  2448. udelay(100);
  2449. }
  2450. static void ironlake_fdi_disable(struct drm_crtc *crtc)
  2451. {
  2452. struct drm_device *dev = crtc->dev;
  2453. struct drm_i915_private *dev_priv = dev->dev_private;
  2454. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2455. int pipe = intel_crtc->pipe;
  2456. u32 reg, temp;
  2457. /* disable CPU FDI tx and PCH FDI rx */
  2458. reg = FDI_TX_CTL(pipe);
  2459. temp = I915_READ(reg);
  2460. I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
  2461. POSTING_READ(reg);
  2462. reg = FDI_RX_CTL(pipe);
  2463. temp = I915_READ(reg);
  2464. temp &= ~(0x7 << 16);
  2465. temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  2466. I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
  2467. POSTING_READ(reg);
  2468. udelay(100);
  2469. /* Ironlake workaround, disable clock pointer after downing FDI */
  2470. if (HAS_PCH_IBX(dev)) {
  2471. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2472. }
  2473. /* still set train pattern 1 */
  2474. reg = FDI_TX_CTL(pipe);
  2475. temp = I915_READ(reg);
  2476. temp &= ~FDI_LINK_TRAIN_NONE;
  2477. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2478. I915_WRITE(reg, temp);
  2479. reg = FDI_RX_CTL(pipe);
  2480. temp = I915_READ(reg);
  2481. if (HAS_PCH_CPT(dev)) {
  2482. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2483. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2484. } else {
  2485. temp &= ~FDI_LINK_TRAIN_NONE;
  2486. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2487. }
  2488. /* BPC in FDI rx is consistent with that in PIPECONF */
  2489. temp &= ~(0x07 << 16);
  2490. temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
  2491. I915_WRITE(reg, temp);
  2492. POSTING_READ(reg);
  2493. udelay(100);
  2494. }
  2495. static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
  2496. {
  2497. struct drm_device *dev = crtc->dev;
  2498. struct drm_i915_private *dev_priv = dev->dev_private;
  2499. unsigned long flags;
  2500. bool pending;
  2501. if (i915_reset_in_progress(&dev_priv->gpu_error))
  2502. return false;
  2503. spin_lock_irqsave(&dev->event_lock, flags);
  2504. pending = to_intel_crtc(crtc)->unpin_work != NULL;
  2505. spin_unlock_irqrestore(&dev->event_lock, flags);
  2506. return pending;
  2507. }
  2508. static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
  2509. {
  2510. struct drm_device *dev = crtc->dev;
  2511. struct drm_i915_private *dev_priv = dev->dev_private;
  2512. if (crtc->fb == NULL)
  2513. return;
  2514. WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
  2515. wait_event(dev_priv->pending_flip_queue,
  2516. !intel_crtc_has_pending_flip(crtc));
  2517. mutex_lock(&dev->struct_mutex);
  2518. intel_finish_fb(crtc->fb);
  2519. mutex_unlock(&dev->struct_mutex);
  2520. }
  2521. static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
  2522. {
  2523. struct drm_device *dev = crtc->dev;
  2524. struct intel_encoder *intel_encoder;
  2525. /*
  2526. * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
  2527. * must be driven by its own crtc; no sharing is possible.
  2528. */
  2529. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  2530. switch (intel_encoder->type) {
  2531. case INTEL_OUTPUT_EDP:
  2532. if (!intel_encoder_is_pch_edp(&intel_encoder->base))
  2533. return false;
  2534. continue;
  2535. }
  2536. }
  2537. return true;
  2538. }
  2539. static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
  2540. {
  2541. return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
  2542. }
  2543. /* Program iCLKIP clock to the desired frequency */
  2544. static void lpt_program_iclkip(struct drm_crtc *crtc)
  2545. {
  2546. struct drm_device *dev = crtc->dev;
  2547. struct drm_i915_private *dev_priv = dev->dev_private;
  2548. u32 divsel, phaseinc, auxdiv, phasedir = 0;
  2549. u32 temp;
  2550. mutex_lock(&dev_priv->dpio_lock);
  2551. /* It is necessary to ungate the pixclk gate prior to programming
  2552. * the divisors, and gate it back when it is done.
  2553. */
  2554. I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
  2555. /* Disable SSCCTL */
  2556. intel_sbi_write(dev_priv, SBI_SSCCTL6,
  2557. intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
  2558. SBI_SSCCTL_DISABLE,
  2559. SBI_ICLK);
  2560. /* 20MHz is a corner case which is out of range for the 7-bit divisor */
  2561. if (crtc->mode.clock == 20000) {
  2562. auxdiv = 1;
  2563. divsel = 0x41;
  2564. phaseinc = 0x20;
  2565. } else {
  2566. /* The iCLK virtual clock root frequency is in MHz,
  2567. * but the crtc->mode.clock in in KHz. To get the divisors,
  2568. * it is necessary to divide one by another, so we
  2569. * convert the virtual clock precision to KHz here for higher
  2570. * precision.
  2571. */
  2572. u32 iclk_virtual_root_freq = 172800 * 1000;
  2573. u32 iclk_pi_range = 64;
  2574. u32 desired_divisor, msb_divisor_value, pi_value;
  2575. desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
  2576. msb_divisor_value = desired_divisor / iclk_pi_range;
  2577. pi_value = desired_divisor % iclk_pi_range;
  2578. auxdiv = 0;
  2579. divsel = msb_divisor_value - 2;
  2580. phaseinc = pi_value;
  2581. }
  2582. /* This should not happen with any sane values */
  2583. WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
  2584. ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
  2585. WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
  2586. ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
  2587. DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
  2588. crtc->mode.clock,
  2589. auxdiv,
  2590. divsel,
  2591. phasedir,
  2592. phaseinc);
  2593. /* Program SSCDIVINTPHASE6 */
  2594. temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
  2595. temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
  2596. temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
  2597. temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
  2598. temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
  2599. temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
  2600. temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
  2601. intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
  2602. /* Program SSCAUXDIV */
  2603. temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
  2604. temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
  2605. temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
  2606. intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
  2607. /* Enable modulator and associated divider */
  2608. temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
  2609. temp &= ~SBI_SSCCTL_DISABLE;
  2610. intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
  2611. /* Wait for initialization time */
  2612. udelay(24);
  2613. I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
  2614. mutex_unlock(&dev_priv->dpio_lock);
  2615. }
  2616. /*
  2617. * Enable PCH resources required for PCH ports:
  2618. * - PCH PLLs
  2619. * - FDI training & RX/TX
  2620. * - update transcoder timings
  2621. * - DP transcoding bits
  2622. * - transcoder
  2623. */
  2624. static void ironlake_pch_enable(struct drm_crtc *crtc)
  2625. {
  2626. struct drm_device *dev = crtc->dev;
  2627. struct drm_i915_private *dev_priv = dev->dev_private;
  2628. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2629. int pipe = intel_crtc->pipe;
  2630. u32 reg, temp;
  2631. assert_transcoder_disabled(dev_priv, pipe);
  2632. /* Write the TU size bits before fdi link training, so that error
  2633. * detection works. */
  2634. I915_WRITE(FDI_RX_TUSIZE1(pipe),
  2635. I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
  2636. /* For PCH output, training FDI link */
  2637. dev_priv->display.fdi_link_train(crtc);
  2638. /* XXX: pch pll's can be enabled any time before we enable the PCH
  2639. * transcoder, and we actually should do this to not upset any PCH
  2640. * transcoder that already use the clock when we share it.
  2641. *
  2642. * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
  2643. * unconditionally resets the pll - we need that to have the right LVDS
  2644. * enable sequence. */
  2645. ironlake_enable_pch_pll(intel_crtc);
  2646. if (HAS_PCH_CPT(dev)) {
  2647. u32 sel;
  2648. temp = I915_READ(PCH_DPLL_SEL);
  2649. switch (pipe) {
  2650. default:
  2651. case 0:
  2652. temp |= TRANSA_DPLL_ENABLE;
  2653. sel = TRANSA_DPLLB_SEL;
  2654. break;
  2655. case 1:
  2656. temp |= TRANSB_DPLL_ENABLE;
  2657. sel = TRANSB_DPLLB_SEL;
  2658. break;
  2659. case 2:
  2660. temp |= TRANSC_DPLL_ENABLE;
  2661. sel = TRANSC_DPLLB_SEL;
  2662. break;
  2663. }
  2664. if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
  2665. temp |= sel;
  2666. else
  2667. temp &= ~sel;
  2668. I915_WRITE(PCH_DPLL_SEL, temp);
  2669. }
  2670. /* set transcoder timing, panel must allow it */
  2671. assert_panel_unlocked(dev_priv, pipe);
  2672. I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
  2673. I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
  2674. I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
  2675. I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
  2676. I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
  2677. I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
  2678. I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
  2679. intel_fdi_normal_train(crtc);
  2680. /* For PCH DP, enable TRANS_DP_CTL */
  2681. if (HAS_PCH_CPT(dev) &&
  2682. (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
  2683. intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
  2684. u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
  2685. reg = TRANS_DP_CTL(pipe);
  2686. temp = I915_READ(reg);
  2687. temp &= ~(TRANS_DP_PORT_SEL_MASK |
  2688. TRANS_DP_SYNC_MASK |
  2689. TRANS_DP_BPC_MASK);
  2690. temp |= (TRANS_DP_OUTPUT_ENABLE |
  2691. TRANS_DP_ENH_FRAMING);
  2692. temp |= bpc << 9; /* same format but at 11:9 */
  2693. if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
  2694. temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
  2695. if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
  2696. temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
  2697. switch (intel_trans_dp_port_sel(crtc)) {
  2698. case PCH_DP_B:
  2699. temp |= TRANS_DP_PORT_SEL_B;
  2700. break;
  2701. case PCH_DP_C:
  2702. temp |= TRANS_DP_PORT_SEL_C;
  2703. break;
  2704. case PCH_DP_D:
  2705. temp |= TRANS_DP_PORT_SEL_D;
  2706. break;
  2707. default:
  2708. BUG();
  2709. }
  2710. I915_WRITE(reg, temp);
  2711. }
  2712. ironlake_enable_pch_transcoder(dev_priv, pipe);
  2713. }
  2714. static void lpt_pch_enable(struct drm_crtc *crtc)
  2715. {
  2716. struct drm_device *dev = crtc->dev;
  2717. struct drm_i915_private *dev_priv = dev->dev_private;
  2718. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2719. enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
  2720. assert_transcoder_disabled(dev_priv, TRANSCODER_A);
  2721. lpt_program_iclkip(crtc);
  2722. /* Set transcoder timing. */
  2723. I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
  2724. I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
  2725. I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
  2726. I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
  2727. I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
  2728. I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
  2729. I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
  2730. lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
  2731. }
  2732. static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
  2733. {
  2734. struct intel_pch_pll *pll = intel_crtc->pch_pll;
  2735. if (pll == NULL)
  2736. return;
  2737. if (pll->refcount == 0) {
  2738. WARN(1, "bad PCH PLL refcount\n");
  2739. return;
  2740. }
  2741. --pll->refcount;
  2742. intel_crtc->pch_pll = NULL;
  2743. }
  2744. static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
  2745. {
  2746. struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
  2747. struct intel_pch_pll *pll;
  2748. int i;
  2749. pll = intel_crtc->pch_pll;
  2750. if (pll) {
  2751. DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
  2752. intel_crtc->base.base.id, pll->pll_reg);
  2753. goto prepare;
  2754. }
  2755. if (HAS_PCH_IBX(dev_priv->dev)) {
  2756. /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
  2757. i = intel_crtc->pipe;
  2758. pll = &dev_priv->pch_plls[i];
  2759. DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
  2760. intel_crtc->base.base.id, pll->pll_reg);
  2761. goto found;
  2762. }
  2763. for (i = 0; i < dev_priv->num_pch_pll; i++) {
  2764. pll = &dev_priv->pch_plls[i];
  2765. /* Only want to check enabled timings first */
  2766. if (pll->refcount == 0)
  2767. continue;
  2768. if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
  2769. fp == I915_READ(pll->fp0_reg)) {
  2770. DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
  2771. intel_crtc->base.base.id,
  2772. pll->pll_reg, pll->refcount, pll->active);
  2773. goto found;
  2774. }
  2775. }
  2776. /* Ok no matching timings, maybe there's a free one? */
  2777. for (i = 0; i < dev_priv->num_pch_pll; i++) {
  2778. pll = &dev_priv->pch_plls[i];
  2779. if (pll->refcount == 0) {
  2780. DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
  2781. intel_crtc->base.base.id, pll->pll_reg);
  2782. goto found;
  2783. }
  2784. }
  2785. return NULL;
  2786. found:
  2787. intel_crtc->pch_pll = pll;
  2788. pll->refcount++;
  2789. DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
  2790. prepare: /* separate function? */
  2791. DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
  2792. /* Wait for the clocks to stabilize before rewriting the regs */
  2793. I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
  2794. POSTING_READ(pll->pll_reg);
  2795. udelay(150);
  2796. I915_WRITE(pll->fp0_reg, fp);
  2797. I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
  2798. pll->on = false;
  2799. return pll;
  2800. }
  2801. void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
  2802. {
  2803. struct drm_i915_private *dev_priv = dev->dev_private;
  2804. int dslreg = PIPEDSL(pipe);
  2805. u32 temp;
  2806. temp = I915_READ(dslreg);
  2807. udelay(500);
  2808. if (wait_for(I915_READ(dslreg) != temp, 5)) {
  2809. if (wait_for(I915_READ(dslreg) != temp, 5))
  2810. DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
  2811. }
  2812. }
  2813. static void ironlake_crtc_enable(struct drm_crtc *crtc)
  2814. {
  2815. struct drm_device *dev = crtc->dev;
  2816. struct drm_i915_private *dev_priv = dev->dev_private;
  2817. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2818. struct intel_encoder *encoder;
  2819. int pipe = intel_crtc->pipe;
  2820. int plane = intel_crtc->plane;
  2821. u32 temp;
  2822. bool is_pch_port;
  2823. WARN_ON(!crtc->enabled);
  2824. if (intel_crtc->active)
  2825. return;
  2826. intel_crtc->active = true;
  2827. intel_update_watermarks(dev);
  2828. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  2829. temp = I915_READ(PCH_LVDS);
  2830. if ((temp & LVDS_PORT_EN) == 0)
  2831. I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
  2832. }
  2833. is_pch_port = ironlake_crtc_driving_pch(crtc);
  2834. if (is_pch_port) {
  2835. /* Note: FDI PLL enabling _must_ be done before we enable the
  2836. * cpu pipes, hence this is separate from all the other fdi/pch
  2837. * enabling. */
  2838. ironlake_fdi_pll_enable(intel_crtc);
  2839. } else {
  2840. assert_fdi_tx_disabled(dev_priv, pipe);
  2841. assert_fdi_rx_disabled(dev_priv, pipe);
  2842. }
  2843. for_each_encoder_on_crtc(dev, crtc, encoder)
  2844. if (encoder->pre_enable)
  2845. encoder->pre_enable(encoder);
  2846. /* Enable panel fitting for LVDS */
  2847. if (dev_priv->pch_pf_size &&
  2848. (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
  2849. intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
  2850. /* Force use of hard-coded filter coefficients
  2851. * as some pre-programmed values are broken,
  2852. * e.g. x201.
  2853. */
  2854. if (IS_IVYBRIDGE(dev))
  2855. I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
  2856. PF_PIPE_SEL_IVB(pipe));
  2857. else
  2858. I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
  2859. I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
  2860. I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
  2861. }
  2862. /*
  2863. * On ILK+ LUT must be loaded before the pipe is running but with
  2864. * clocks enabled
  2865. */
  2866. intel_crtc_load_lut(crtc);
  2867. intel_enable_pipe(dev_priv, pipe, is_pch_port);
  2868. intel_enable_plane(dev_priv, plane, pipe);
  2869. if (is_pch_port)
  2870. ironlake_pch_enable(crtc);
  2871. mutex_lock(&dev->struct_mutex);
  2872. intel_update_fbc(dev);
  2873. mutex_unlock(&dev->struct_mutex);
  2874. intel_crtc_update_cursor(crtc, true);
  2875. for_each_encoder_on_crtc(dev, crtc, encoder)
  2876. encoder->enable(encoder);
  2877. if (HAS_PCH_CPT(dev))
  2878. intel_cpt_verify_modeset(dev, intel_crtc->pipe);
  2879. /*
  2880. * There seems to be a race in PCH platform hw (at least on some
  2881. * outputs) where an enabled pipe still completes any pageflip right
  2882. * away (as if the pipe is off) instead of waiting for vblank. As soon
  2883. * as the first vblank happend, everything works as expected. Hence just
  2884. * wait for one vblank before returning to avoid strange things
  2885. * happening.
  2886. */
  2887. intel_wait_for_vblank(dev, intel_crtc->pipe);
  2888. }
  2889. static void haswell_crtc_enable(struct drm_crtc *crtc)
  2890. {
  2891. struct drm_device *dev = crtc->dev;
  2892. struct drm_i915_private *dev_priv = dev->dev_private;
  2893. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2894. struct intel_encoder *encoder;
  2895. int pipe = intel_crtc->pipe;
  2896. int plane = intel_crtc->plane;
  2897. bool is_pch_port;
  2898. WARN_ON(!crtc->enabled);
  2899. if (intel_crtc->active)
  2900. return;
  2901. intel_crtc->active = true;
  2902. intel_update_watermarks(dev);
  2903. is_pch_port = haswell_crtc_driving_pch(crtc);
  2904. if (is_pch_port)
  2905. dev_priv->display.fdi_link_train(crtc);
  2906. for_each_encoder_on_crtc(dev, crtc, encoder)
  2907. if (encoder->pre_enable)
  2908. encoder->pre_enable(encoder);
  2909. intel_ddi_enable_pipe_clock(intel_crtc);
  2910. /* Enable panel fitting for eDP */
  2911. if (dev_priv->pch_pf_size &&
  2912. intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
  2913. /* Force use of hard-coded filter coefficients
  2914. * as some pre-programmed values are broken,
  2915. * e.g. x201.
  2916. */
  2917. I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
  2918. PF_PIPE_SEL_IVB(pipe));
  2919. I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
  2920. I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
  2921. }
  2922. /*
  2923. * On ILK+ LUT must be loaded before the pipe is running but with
  2924. * clocks enabled
  2925. */
  2926. intel_crtc_load_lut(crtc);
  2927. intel_ddi_set_pipe_settings(crtc);
  2928. intel_ddi_enable_pipe_func(crtc);
  2929. intel_enable_pipe(dev_priv, pipe, is_pch_port);
  2930. intel_enable_plane(dev_priv, plane, pipe);
  2931. if (is_pch_port)
  2932. lpt_pch_enable(crtc);
  2933. mutex_lock(&dev->struct_mutex);
  2934. intel_update_fbc(dev);
  2935. mutex_unlock(&dev->struct_mutex);
  2936. intel_crtc_update_cursor(crtc, true);
  2937. for_each_encoder_on_crtc(dev, crtc, encoder)
  2938. encoder->enable(encoder);
  2939. /*
  2940. * There seems to be a race in PCH platform hw (at least on some
  2941. * outputs) where an enabled pipe still completes any pageflip right
  2942. * away (as if the pipe is off) instead of waiting for vblank. As soon
  2943. * as the first vblank happend, everything works as expected. Hence just
  2944. * wait for one vblank before returning to avoid strange things
  2945. * happening.
  2946. */
  2947. intel_wait_for_vblank(dev, intel_crtc->pipe);
  2948. }
  2949. static void ironlake_crtc_disable(struct drm_crtc *crtc)
  2950. {
  2951. struct drm_device *dev = crtc->dev;
  2952. struct drm_i915_private *dev_priv = dev->dev_private;
  2953. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2954. struct intel_encoder *encoder;
  2955. int pipe = intel_crtc->pipe;
  2956. int plane = intel_crtc->plane;
  2957. u32 reg, temp;
  2958. if (!intel_crtc->active)
  2959. return;
  2960. for_each_encoder_on_crtc(dev, crtc, encoder)
  2961. encoder->disable(encoder);
  2962. intel_crtc_wait_for_pending_flips(crtc);
  2963. drm_vblank_off(dev, pipe);
  2964. intel_crtc_update_cursor(crtc, false);
  2965. intel_disable_plane(dev_priv, plane, pipe);
  2966. if (dev_priv->cfb_plane == plane)
  2967. intel_disable_fbc(dev);
  2968. intel_disable_pipe(dev_priv, pipe);
  2969. /* Disable PF */
  2970. I915_WRITE(PF_CTL(pipe), 0);
  2971. I915_WRITE(PF_WIN_SZ(pipe), 0);
  2972. for_each_encoder_on_crtc(dev, crtc, encoder)
  2973. if (encoder->post_disable)
  2974. encoder->post_disable(encoder);
  2975. ironlake_fdi_disable(crtc);
  2976. ironlake_disable_pch_transcoder(dev_priv, pipe);
  2977. if (HAS_PCH_CPT(dev)) {
  2978. /* disable TRANS_DP_CTL */
  2979. reg = TRANS_DP_CTL(pipe);
  2980. temp = I915_READ(reg);
  2981. temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
  2982. temp |= TRANS_DP_PORT_SEL_NONE;
  2983. I915_WRITE(reg, temp);
  2984. /* disable DPLL_SEL */
  2985. temp = I915_READ(PCH_DPLL_SEL);
  2986. switch (pipe) {
  2987. case 0:
  2988. temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
  2989. break;
  2990. case 1:
  2991. temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
  2992. break;
  2993. case 2:
  2994. /* C shares PLL A or B */
  2995. temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
  2996. break;
  2997. default:
  2998. BUG(); /* wtf */
  2999. }
  3000. I915_WRITE(PCH_DPLL_SEL, temp);
  3001. }
  3002. /* disable PCH DPLL */
  3003. intel_disable_pch_pll(intel_crtc);
  3004. ironlake_fdi_pll_disable(intel_crtc);
  3005. intel_crtc->active = false;
  3006. intel_update_watermarks(dev);
  3007. mutex_lock(&dev->struct_mutex);
  3008. intel_update_fbc(dev);
  3009. mutex_unlock(&dev->struct_mutex);
  3010. }
  3011. static void haswell_crtc_disable(struct drm_crtc *crtc)
  3012. {
  3013. struct drm_device *dev = crtc->dev;
  3014. struct drm_i915_private *dev_priv = dev->dev_private;
  3015. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3016. struct intel_encoder *encoder;
  3017. int pipe = intel_crtc->pipe;
  3018. int plane = intel_crtc->plane;
  3019. enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
  3020. bool is_pch_port;
  3021. if (!intel_crtc->active)
  3022. return;
  3023. is_pch_port = haswell_crtc_driving_pch(crtc);
  3024. for_each_encoder_on_crtc(dev, crtc, encoder)
  3025. encoder->disable(encoder);
  3026. intel_crtc_wait_for_pending_flips(crtc);
  3027. drm_vblank_off(dev, pipe);
  3028. intel_crtc_update_cursor(crtc, false);
  3029. intel_disable_plane(dev_priv, plane, pipe);
  3030. if (dev_priv->cfb_plane == plane)
  3031. intel_disable_fbc(dev);
  3032. intel_disable_pipe(dev_priv, pipe);
  3033. intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
  3034. /* Disable PF */
  3035. I915_WRITE(PF_CTL(pipe), 0);
  3036. I915_WRITE(PF_WIN_SZ(pipe), 0);
  3037. intel_ddi_disable_pipe_clock(intel_crtc);
  3038. for_each_encoder_on_crtc(dev, crtc, encoder)
  3039. if (encoder->post_disable)
  3040. encoder->post_disable(encoder);
  3041. if (is_pch_port) {
  3042. lpt_disable_pch_transcoder(dev_priv);
  3043. intel_ddi_fdi_disable(crtc);
  3044. }
  3045. intel_crtc->active = false;
  3046. intel_update_watermarks(dev);
  3047. mutex_lock(&dev->struct_mutex);
  3048. intel_update_fbc(dev);
  3049. mutex_unlock(&dev->struct_mutex);
  3050. }
  3051. static void ironlake_crtc_off(struct drm_crtc *crtc)
  3052. {
  3053. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3054. intel_put_pch_pll(intel_crtc);
  3055. }
  3056. static void haswell_crtc_off(struct drm_crtc *crtc)
  3057. {
  3058. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3059. /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
  3060. * start using it. */
  3061. intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
  3062. intel_ddi_put_crtc_pll(crtc);
  3063. }
  3064. static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
  3065. {
  3066. if (!enable && intel_crtc->overlay) {
  3067. struct drm_device *dev = intel_crtc->base.dev;
  3068. struct drm_i915_private *dev_priv = dev->dev_private;
  3069. mutex_lock(&dev->struct_mutex);
  3070. dev_priv->mm.interruptible = false;
  3071. (void) intel_overlay_switch_off(intel_crtc->overlay);
  3072. dev_priv->mm.interruptible = true;
  3073. mutex_unlock(&dev->struct_mutex);
  3074. }
  3075. /* Let userspace switch the overlay on again. In most cases userspace
  3076. * has to recompute where to put it anyway.
  3077. */
  3078. }
  3079. static void i9xx_crtc_enable(struct drm_crtc *crtc)
  3080. {
  3081. struct drm_device *dev = crtc->dev;
  3082. struct drm_i915_private *dev_priv = dev->dev_private;
  3083. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3084. struct intel_encoder *encoder;
  3085. int pipe = intel_crtc->pipe;
  3086. int plane = intel_crtc->plane;
  3087. WARN_ON(!crtc->enabled);
  3088. if (intel_crtc->active)
  3089. return;
  3090. intel_crtc->active = true;
  3091. intel_update_watermarks(dev);
  3092. intel_enable_pll(dev_priv, pipe);
  3093. intel_enable_pipe(dev_priv, pipe, false);
  3094. intel_enable_plane(dev_priv, plane, pipe);
  3095. intel_crtc_load_lut(crtc);
  3096. intel_update_fbc(dev);
  3097. /* Give the overlay scaler a chance to enable if it's on this pipe */
  3098. intel_crtc_dpms_overlay(intel_crtc, true);
  3099. intel_crtc_update_cursor(crtc, true);
  3100. for_each_encoder_on_crtc(dev, crtc, encoder)
  3101. encoder->enable(encoder);
  3102. }
  3103. static void i9xx_crtc_disable(struct drm_crtc *crtc)
  3104. {
  3105. struct drm_device *dev = crtc->dev;
  3106. struct drm_i915_private *dev_priv = dev->dev_private;
  3107. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3108. struct intel_encoder *encoder;
  3109. int pipe = intel_crtc->pipe;
  3110. int plane = intel_crtc->plane;
  3111. if (!intel_crtc->active)
  3112. return;
  3113. for_each_encoder_on_crtc(dev, crtc, encoder)
  3114. encoder->disable(encoder);
  3115. /* Give the overlay scaler a chance to disable if it's on this pipe */
  3116. intel_crtc_wait_for_pending_flips(crtc);
  3117. drm_vblank_off(dev, pipe);
  3118. intel_crtc_dpms_overlay(intel_crtc, false);
  3119. intel_crtc_update_cursor(crtc, false);
  3120. if (dev_priv->cfb_plane == plane)
  3121. intel_disable_fbc(dev);
  3122. intel_disable_plane(dev_priv, plane, pipe);
  3123. intel_disable_pipe(dev_priv, pipe);
  3124. intel_disable_pll(dev_priv, pipe);
  3125. intel_crtc->active = false;
  3126. intel_update_fbc(dev);
  3127. intel_update_watermarks(dev);
  3128. }
  3129. static void i9xx_crtc_off(struct drm_crtc *crtc)
  3130. {
  3131. }
  3132. static void intel_crtc_update_sarea(struct drm_crtc *crtc,
  3133. bool enabled)
  3134. {
  3135. struct drm_device *dev = crtc->dev;
  3136. struct drm_i915_master_private *master_priv;
  3137. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3138. int pipe = intel_crtc->pipe;
  3139. if (!dev->primary->master)
  3140. return;
  3141. master_priv = dev->primary->master->driver_priv;
  3142. if (!master_priv->sarea_priv)
  3143. return;
  3144. switch (pipe) {
  3145. case 0:
  3146. master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
  3147. master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
  3148. break;
  3149. case 1:
  3150. master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
  3151. master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
  3152. break;
  3153. default:
  3154. DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
  3155. break;
  3156. }
  3157. }
  3158. /**
  3159. * Sets the power management mode of the pipe and plane.
  3160. */
  3161. void intel_crtc_update_dpms(struct drm_crtc *crtc)
  3162. {
  3163. struct drm_device *dev = crtc->dev;
  3164. struct drm_i915_private *dev_priv = dev->dev_private;
  3165. struct intel_encoder *intel_encoder;
  3166. bool enable = false;
  3167. for_each_encoder_on_crtc(dev, crtc, intel_encoder)
  3168. enable |= intel_encoder->connectors_active;
  3169. if (enable)
  3170. dev_priv->display.crtc_enable(crtc);
  3171. else
  3172. dev_priv->display.crtc_disable(crtc);
  3173. intel_crtc_update_sarea(crtc, enable);
  3174. }
  3175. static void intel_crtc_noop(struct drm_crtc *crtc)
  3176. {
  3177. }
  3178. static void intel_crtc_disable(struct drm_crtc *crtc)
  3179. {
  3180. struct drm_device *dev = crtc->dev;
  3181. struct drm_connector *connector;
  3182. struct drm_i915_private *dev_priv = dev->dev_private;
  3183. /* crtc should still be enabled when we disable it. */
  3184. WARN_ON(!crtc->enabled);
  3185. dev_priv->display.crtc_disable(crtc);
  3186. intel_crtc_update_sarea(crtc, false);
  3187. dev_priv->display.off(crtc);
  3188. assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
  3189. assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
  3190. if (crtc->fb) {
  3191. mutex_lock(&dev->struct_mutex);
  3192. intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
  3193. mutex_unlock(&dev->struct_mutex);
  3194. crtc->fb = NULL;
  3195. }
  3196. /* Update computed state. */
  3197. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  3198. if (!connector->encoder || !connector->encoder->crtc)
  3199. continue;
  3200. if (connector->encoder->crtc != crtc)
  3201. continue;
  3202. connector->dpms = DRM_MODE_DPMS_OFF;
  3203. to_intel_encoder(connector->encoder)->connectors_active = false;
  3204. }
  3205. }
  3206. void intel_modeset_disable(struct drm_device *dev)
  3207. {
  3208. struct drm_crtc *crtc;
  3209. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  3210. if (crtc->enabled)
  3211. intel_crtc_disable(crtc);
  3212. }
  3213. }
  3214. void intel_encoder_noop(struct drm_encoder *encoder)
  3215. {
  3216. }
  3217. void intel_encoder_destroy(struct drm_encoder *encoder)
  3218. {
  3219. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  3220. drm_encoder_cleanup(encoder);
  3221. kfree(intel_encoder);
  3222. }
  3223. /* Simple dpms helper for encodres with just one connector, no cloning and only
  3224. * one kind of off state. It clamps all !ON modes to fully OFF and changes the
  3225. * state of the entire output pipe. */
  3226. void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
  3227. {
  3228. if (mode == DRM_MODE_DPMS_ON) {
  3229. encoder->connectors_active = true;
  3230. intel_crtc_update_dpms(encoder->base.crtc);
  3231. } else {
  3232. encoder->connectors_active = false;
  3233. intel_crtc_update_dpms(encoder->base.crtc);
  3234. }
  3235. }
  3236. /* Cross check the actual hw state with our own modeset state tracking (and it's
  3237. * internal consistency). */
  3238. static void intel_connector_check_state(struct intel_connector *connector)
  3239. {
  3240. if (connector->get_hw_state(connector)) {
  3241. struct intel_encoder *encoder = connector->encoder;
  3242. struct drm_crtc *crtc;
  3243. bool encoder_enabled;
  3244. enum pipe pipe;
  3245. DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
  3246. connector->base.base.id,
  3247. drm_get_connector_name(&connector->base));
  3248. WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
  3249. "wrong connector dpms state\n");
  3250. WARN(connector->base.encoder != &encoder->base,
  3251. "active connector not linked to encoder\n");
  3252. WARN(!encoder->connectors_active,
  3253. "encoder->connectors_active not set\n");
  3254. encoder_enabled = encoder->get_hw_state(encoder, &pipe);
  3255. WARN(!encoder_enabled, "encoder not enabled\n");
  3256. if (WARN_ON(!encoder->base.crtc))
  3257. return;
  3258. crtc = encoder->base.crtc;
  3259. WARN(!crtc->enabled, "crtc not enabled\n");
  3260. WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
  3261. WARN(pipe != to_intel_crtc(crtc)->pipe,
  3262. "encoder active on the wrong pipe\n");
  3263. }
  3264. }
  3265. /* Even simpler default implementation, if there's really no special case to
  3266. * consider. */
  3267. void intel_connector_dpms(struct drm_connector *connector, int mode)
  3268. {
  3269. struct intel_encoder *encoder = intel_attached_encoder(connector);
  3270. /* All the simple cases only support two dpms states. */
  3271. if (mode != DRM_MODE_DPMS_ON)
  3272. mode = DRM_MODE_DPMS_OFF;
  3273. if (mode == connector->dpms)
  3274. return;
  3275. connector->dpms = mode;
  3276. /* Only need to change hw state when actually enabled */
  3277. if (encoder->base.crtc)
  3278. intel_encoder_dpms(encoder, mode);
  3279. else
  3280. WARN_ON(encoder->connectors_active != false);
  3281. intel_modeset_check_state(connector->dev);
  3282. }
  3283. /* Simple connector->get_hw_state implementation for encoders that support only
  3284. * one connector and no cloning and hence the encoder state determines the state
  3285. * of the connector. */
  3286. bool intel_connector_get_hw_state(struct intel_connector *connector)
  3287. {
  3288. enum pipe pipe = 0;
  3289. struct intel_encoder *encoder = connector->encoder;
  3290. return encoder->get_hw_state(encoder, &pipe);
  3291. }
  3292. static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
  3293. const struct drm_display_mode *mode,
  3294. struct drm_display_mode *adjusted_mode)
  3295. {
  3296. struct drm_device *dev = crtc->dev;
  3297. if (HAS_PCH_SPLIT(dev)) {
  3298. /* FDI link clock is fixed at 2.7G */
  3299. if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
  3300. return false;
  3301. }
  3302. /* All interlaced capable intel hw wants timings in frames. Note though
  3303. * that intel_lvds_mode_fixup does some funny tricks with the crtc
  3304. * timings, so we need to be careful not to clobber these.*/
  3305. if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
  3306. drm_mode_set_crtcinfo(adjusted_mode, 0);
  3307. /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
  3308. * with a hsync front porch of 0.
  3309. */
  3310. if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
  3311. adjusted_mode->hsync_start == adjusted_mode->hdisplay)
  3312. return false;
  3313. return true;
  3314. }
  3315. static int valleyview_get_display_clock_speed(struct drm_device *dev)
  3316. {
  3317. return 400000; /* FIXME */
  3318. }
  3319. static int i945_get_display_clock_speed(struct drm_device *dev)
  3320. {
  3321. return 400000;
  3322. }
  3323. static int i915_get_display_clock_speed(struct drm_device *dev)
  3324. {
  3325. return 333000;
  3326. }
  3327. static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
  3328. {
  3329. return 200000;
  3330. }
  3331. static int i915gm_get_display_clock_speed(struct drm_device *dev)
  3332. {
  3333. u16 gcfgc = 0;
  3334. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  3335. if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
  3336. return 133000;
  3337. else {
  3338. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  3339. case GC_DISPLAY_CLOCK_333_MHZ:
  3340. return 333000;
  3341. default:
  3342. case GC_DISPLAY_CLOCK_190_200_MHZ:
  3343. return 190000;
  3344. }
  3345. }
  3346. }
  3347. static int i865_get_display_clock_speed(struct drm_device *dev)
  3348. {
  3349. return 266000;
  3350. }
  3351. static int i855_get_display_clock_speed(struct drm_device *dev)
  3352. {
  3353. u16 hpllcc = 0;
  3354. /* Assume that the hardware is in the high speed state. This
  3355. * should be the default.
  3356. */
  3357. switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
  3358. case GC_CLOCK_133_200:
  3359. case GC_CLOCK_100_200:
  3360. return 200000;
  3361. case GC_CLOCK_166_250:
  3362. return 250000;
  3363. case GC_CLOCK_100_133:
  3364. return 133000;
  3365. }
  3366. /* Shouldn't happen */
  3367. return 0;
  3368. }
  3369. static int i830_get_display_clock_speed(struct drm_device *dev)
  3370. {
  3371. return 133000;
  3372. }
  3373. static void
  3374. intel_reduce_ratio(uint32_t *num, uint32_t *den)
  3375. {
  3376. while (*num > 0xffffff || *den > 0xffffff) {
  3377. *num >>= 1;
  3378. *den >>= 1;
  3379. }
  3380. }
  3381. void
  3382. intel_link_compute_m_n(int bits_per_pixel, int nlanes,
  3383. int pixel_clock, int link_clock,
  3384. struct intel_link_m_n *m_n)
  3385. {
  3386. m_n->tu = 64;
  3387. m_n->gmch_m = bits_per_pixel * pixel_clock;
  3388. m_n->gmch_n = link_clock * nlanes * 8;
  3389. intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
  3390. m_n->link_m = pixel_clock;
  3391. m_n->link_n = link_clock;
  3392. intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
  3393. }
  3394. static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
  3395. {
  3396. if (i915_panel_use_ssc >= 0)
  3397. return i915_panel_use_ssc != 0;
  3398. return dev_priv->lvds_use_ssc
  3399. && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
  3400. }
  3401. /**
  3402. * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
  3403. * @crtc: CRTC structure
  3404. * @mode: requested mode
  3405. *
  3406. * A pipe may be connected to one or more outputs. Based on the depth of the
  3407. * attached framebuffer, choose a good color depth to use on the pipe.
  3408. *
  3409. * If possible, match the pipe depth to the fb depth. In some cases, this
  3410. * isn't ideal, because the connected output supports a lesser or restricted
  3411. * set of depths. Resolve that here:
  3412. * LVDS typically supports only 6bpc, so clamp down in that case
  3413. * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
  3414. * Displays may support a restricted set as well, check EDID and clamp as
  3415. * appropriate.
  3416. * DP may want to dither down to 6bpc to fit larger modes
  3417. *
  3418. * RETURNS:
  3419. * Dithering requirement (i.e. false if display bpc and pipe bpc match,
  3420. * true if they don't match).
  3421. */
  3422. static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
  3423. struct drm_framebuffer *fb,
  3424. unsigned int *pipe_bpp,
  3425. struct drm_display_mode *mode)
  3426. {
  3427. struct drm_device *dev = crtc->dev;
  3428. struct drm_i915_private *dev_priv = dev->dev_private;
  3429. struct drm_connector *connector;
  3430. struct intel_encoder *intel_encoder;
  3431. unsigned int display_bpc = UINT_MAX, bpc;
  3432. /* Walk the encoders & connectors on this crtc, get min bpc */
  3433. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  3434. if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
  3435. unsigned int lvds_bpc;
  3436. if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
  3437. LVDS_A3_POWER_UP)
  3438. lvds_bpc = 8;
  3439. else
  3440. lvds_bpc = 6;
  3441. if (lvds_bpc < display_bpc) {
  3442. DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
  3443. display_bpc = lvds_bpc;
  3444. }
  3445. continue;
  3446. }
  3447. /* Not one of the known troublemakers, check the EDID */
  3448. list_for_each_entry(connector, &dev->mode_config.connector_list,
  3449. head) {
  3450. if (connector->encoder != &intel_encoder->base)
  3451. continue;
  3452. /* Don't use an invalid EDID bpc value */
  3453. if (connector->display_info.bpc &&
  3454. connector->display_info.bpc < display_bpc) {
  3455. DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
  3456. display_bpc = connector->display_info.bpc;
  3457. }
  3458. }
  3459. if (intel_encoder->type == INTEL_OUTPUT_EDP) {
  3460. /* Use VBT settings if we have an eDP panel */
  3461. unsigned int edp_bpc = dev_priv->edp.bpp / 3;
  3462. if (edp_bpc && edp_bpc < display_bpc) {
  3463. DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
  3464. display_bpc = edp_bpc;
  3465. }
  3466. continue;
  3467. }
  3468. /*
  3469. * HDMI is either 12 or 8, so if the display lets 10bpc sneak
  3470. * through, clamp it down. (Note: >12bpc will be caught below.)
  3471. */
  3472. if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
  3473. if (display_bpc > 8 && display_bpc < 12) {
  3474. DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
  3475. display_bpc = 12;
  3476. } else {
  3477. DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
  3478. display_bpc = 8;
  3479. }
  3480. }
  3481. }
  3482. if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
  3483. DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
  3484. display_bpc = 6;
  3485. }
  3486. /*
  3487. * We could just drive the pipe at the highest bpc all the time and
  3488. * enable dithering as needed, but that costs bandwidth. So choose
  3489. * the minimum value that expresses the full color range of the fb but
  3490. * also stays within the max display bpc discovered above.
  3491. */
  3492. switch (fb->depth) {
  3493. case 8:
  3494. bpc = 8; /* since we go through a colormap */
  3495. break;
  3496. case 15:
  3497. case 16:
  3498. bpc = 6; /* min is 18bpp */
  3499. break;
  3500. case 24:
  3501. bpc = 8;
  3502. break;
  3503. case 30:
  3504. bpc = 10;
  3505. break;
  3506. case 48:
  3507. bpc = 12;
  3508. break;
  3509. default:
  3510. DRM_DEBUG("unsupported depth, assuming 24 bits\n");
  3511. bpc = min((unsigned int)8, display_bpc);
  3512. break;
  3513. }
  3514. display_bpc = min(display_bpc, bpc);
  3515. DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
  3516. bpc, display_bpc);
  3517. *pipe_bpp = display_bpc * 3;
  3518. return display_bpc != bpc;
  3519. }
  3520. static int vlv_get_refclk(struct drm_crtc *crtc)
  3521. {
  3522. struct drm_device *dev = crtc->dev;
  3523. struct drm_i915_private *dev_priv = dev->dev_private;
  3524. int refclk = 27000; /* for DP & HDMI */
  3525. return 100000; /* only one validated so far */
  3526. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  3527. refclk = 96000;
  3528. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  3529. if (intel_panel_use_ssc(dev_priv))
  3530. refclk = 100000;
  3531. else
  3532. refclk = 96000;
  3533. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
  3534. refclk = 100000;
  3535. }
  3536. return refclk;
  3537. }
  3538. static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
  3539. {
  3540. struct drm_device *dev = crtc->dev;
  3541. struct drm_i915_private *dev_priv = dev->dev_private;
  3542. int refclk;
  3543. if (IS_VALLEYVIEW(dev)) {
  3544. refclk = vlv_get_refclk(crtc);
  3545. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  3546. intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  3547. refclk = dev_priv->lvds_ssc_freq * 1000;
  3548. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  3549. refclk / 1000);
  3550. } else if (!IS_GEN2(dev)) {
  3551. refclk = 96000;
  3552. } else {
  3553. refclk = 48000;
  3554. }
  3555. return refclk;
  3556. }
  3557. static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
  3558. intel_clock_t *clock)
  3559. {
  3560. /* SDVO TV has fixed PLL values depend on its clock range,
  3561. this mirrors vbios setting. */
  3562. if (adjusted_mode->clock >= 100000
  3563. && adjusted_mode->clock < 140500) {
  3564. clock->p1 = 2;
  3565. clock->p2 = 10;
  3566. clock->n = 3;
  3567. clock->m1 = 16;
  3568. clock->m2 = 8;
  3569. } else if (adjusted_mode->clock >= 140500
  3570. && adjusted_mode->clock <= 200000) {
  3571. clock->p1 = 1;
  3572. clock->p2 = 10;
  3573. clock->n = 6;
  3574. clock->m1 = 12;
  3575. clock->m2 = 8;
  3576. }
  3577. }
  3578. static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
  3579. intel_clock_t *clock,
  3580. intel_clock_t *reduced_clock)
  3581. {
  3582. struct drm_device *dev = crtc->dev;
  3583. struct drm_i915_private *dev_priv = dev->dev_private;
  3584. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3585. int pipe = intel_crtc->pipe;
  3586. u32 fp, fp2 = 0;
  3587. if (IS_PINEVIEW(dev)) {
  3588. fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
  3589. if (reduced_clock)
  3590. fp2 = (1 << reduced_clock->n) << 16 |
  3591. reduced_clock->m1 << 8 | reduced_clock->m2;
  3592. } else {
  3593. fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
  3594. if (reduced_clock)
  3595. fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
  3596. reduced_clock->m2;
  3597. }
  3598. I915_WRITE(FP0(pipe), fp);
  3599. intel_crtc->lowfreq_avail = false;
  3600. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  3601. reduced_clock && i915_powersave) {
  3602. I915_WRITE(FP1(pipe), fp2);
  3603. intel_crtc->lowfreq_avail = true;
  3604. } else {
  3605. I915_WRITE(FP1(pipe), fp);
  3606. }
  3607. }
  3608. static void vlv_update_pll(struct drm_crtc *crtc,
  3609. struct drm_display_mode *mode,
  3610. struct drm_display_mode *adjusted_mode,
  3611. intel_clock_t *clock, intel_clock_t *reduced_clock,
  3612. int num_connectors)
  3613. {
  3614. struct drm_device *dev = crtc->dev;
  3615. struct drm_i915_private *dev_priv = dev->dev_private;
  3616. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3617. int pipe = intel_crtc->pipe;
  3618. u32 dpll, mdiv, pdiv;
  3619. u32 bestn, bestm1, bestm2, bestp1, bestp2;
  3620. bool is_sdvo;
  3621. u32 temp;
  3622. mutex_lock(&dev_priv->dpio_lock);
  3623. is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
  3624. intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
  3625. dpll = DPLL_VGA_MODE_DIS;
  3626. dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
  3627. dpll |= DPLL_REFA_CLK_ENABLE_VLV;
  3628. dpll |= DPLL_INTEGRATED_CLOCK_VLV;
  3629. I915_WRITE(DPLL(pipe), dpll);
  3630. POSTING_READ(DPLL(pipe));
  3631. bestn = clock->n;
  3632. bestm1 = clock->m1;
  3633. bestm2 = clock->m2;
  3634. bestp1 = clock->p1;
  3635. bestp2 = clock->p2;
  3636. /*
  3637. * In Valleyview PLL and program lane counter registers are exposed
  3638. * through DPIO interface
  3639. */
  3640. mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
  3641. mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
  3642. mdiv |= ((bestn << DPIO_N_SHIFT));
  3643. mdiv |= (1 << DPIO_POST_DIV_SHIFT);
  3644. mdiv |= (1 << DPIO_K_SHIFT);
  3645. mdiv |= DPIO_ENABLE_CALIBRATION;
  3646. intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
  3647. intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
  3648. pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
  3649. (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
  3650. (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
  3651. (5 << DPIO_CLK_BIAS_CTL_SHIFT);
  3652. intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
  3653. intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
  3654. dpll |= DPLL_VCO_ENABLE;
  3655. I915_WRITE(DPLL(pipe), dpll);
  3656. POSTING_READ(DPLL(pipe));
  3657. if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
  3658. DRM_ERROR("DPLL %d failed to lock\n", pipe);
  3659. intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
  3660. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
  3661. intel_dp_set_m_n(crtc, mode, adjusted_mode);
  3662. I915_WRITE(DPLL(pipe), dpll);
  3663. /* Wait for the clocks to stabilize. */
  3664. POSTING_READ(DPLL(pipe));
  3665. udelay(150);
  3666. temp = 0;
  3667. if (is_sdvo) {
  3668. temp = intel_mode_get_pixel_multiplier(adjusted_mode);
  3669. if (temp > 1)
  3670. temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  3671. else
  3672. temp = 0;
  3673. }
  3674. I915_WRITE(DPLL_MD(pipe), temp);
  3675. POSTING_READ(DPLL_MD(pipe));
  3676. /* Now program lane control registers */
  3677. if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
  3678. || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
  3679. {
  3680. temp = 0x1000C4;
  3681. if(pipe == 1)
  3682. temp |= (1 << 21);
  3683. intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
  3684. }
  3685. if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
  3686. {
  3687. temp = 0x1000C4;
  3688. if(pipe == 1)
  3689. temp |= (1 << 21);
  3690. intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
  3691. }
  3692. mutex_unlock(&dev_priv->dpio_lock);
  3693. }
  3694. static void i9xx_update_pll(struct drm_crtc *crtc,
  3695. struct drm_display_mode *mode,
  3696. struct drm_display_mode *adjusted_mode,
  3697. intel_clock_t *clock, intel_clock_t *reduced_clock,
  3698. int num_connectors)
  3699. {
  3700. struct drm_device *dev = crtc->dev;
  3701. struct drm_i915_private *dev_priv = dev->dev_private;
  3702. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3703. struct intel_encoder *encoder;
  3704. int pipe = intel_crtc->pipe;
  3705. u32 dpll;
  3706. bool is_sdvo;
  3707. i9xx_update_pll_dividers(crtc, clock, reduced_clock);
  3708. is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
  3709. intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
  3710. dpll = DPLL_VGA_MODE_DIS;
  3711. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  3712. dpll |= DPLLB_MODE_LVDS;
  3713. else
  3714. dpll |= DPLLB_MODE_DAC_SERIAL;
  3715. if (is_sdvo) {
  3716. int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  3717. if (pixel_multiplier > 1) {
  3718. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
  3719. dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
  3720. }
  3721. dpll |= DPLL_DVO_HIGH_SPEED;
  3722. }
  3723. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
  3724. dpll |= DPLL_DVO_HIGH_SPEED;
  3725. /* compute bitmask from p1 value */
  3726. if (IS_PINEVIEW(dev))
  3727. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
  3728. else {
  3729. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3730. if (IS_G4X(dev) && reduced_clock)
  3731. dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  3732. }
  3733. switch (clock->p2) {
  3734. case 5:
  3735. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  3736. break;
  3737. case 7:
  3738. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  3739. break;
  3740. case 10:
  3741. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  3742. break;
  3743. case 14:
  3744. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  3745. break;
  3746. }
  3747. if (INTEL_INFO(dev)->gen >= 4)
  3748. dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
  3749. if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
  3750. dpll |= PLL_REF_INPUT_TVCLKINBC;
  3751. else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
  3752. /* XXX: just matching BIOS for now */
  3753. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  3754. dpll |= 3;
  3755. else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  3756. intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  3757. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  3758. else
  3759. dpll |= PLL_REF_INPUT_DREFCLK;
  3760. dpll |= DPLL_VCO_ENABLE;
  3761. I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
  3762. POSTING_READ(DPLL(pipe));
  3763. udelay(150);
  3764. for_each_encoder_on_crtc(dev, crtc, encoder)
  3765. if (encoder->pre_pll_enable)
  3766. encoder->pre_pll_enable(encoder);
  3767. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
  3768. intel_dp_set_m_n(crtc, mode, adjusted_mode);
  3769. I915_WRITE(DPLL(pipe), dpll);
  3770. /* Wait for the clocks to stabilize. */
  3771. POSTING_READ(DPLL(pipe));
  3772. udelay(150);
  3773. if (INTEL_INFO(dev)->gen >= 4) {
  3774. u32 temp = 0;
  3775. if (is_sdvo) {
  3776. temp = intel_mode_get_pixel_multiplier(adjusted_mode);
  3777. if (temp > 1)
  3778. temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  3779. else
  3780. temp = 0;
  3781. }
  3782. I915_WRITE(DPLL_MD(pipe), temp);
  3783. } else {
  3784. /* The pixel multiplier can only be updated once the
  3785. * DPLL is enabled and the clocks are stable.
  3786. *
  3787. * So write it again.
  3788. */
  3789. I915_WRITE(DPLL(pipe), dpll);
  3790. }
  3791. }
  3792. static void i8xx_update_pll(struct drm_crtc *crtc,
  3793. struct drm_display_mode *adjusted_mode,
  3794. intel_clock_t *clock, intel_clock_t *reduced_clock,
  3795. int num_connectors)
  3796. {
  3797. struct drm_device *dev = crtc->dev;
  3798. struct drm_i915_private *dev_priv = dev->dev_private;
  3799. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3800. struct intel_encoder *encoder;
  3801. int pipe = intel_crtc->pipe;
  3802. u32 dpll;
  3803. i9xx_update_pll_dividers(crtc, clock, reduced_clock);
  3804. dpll = DPLL_VGA_MODE_DIS;
  3805. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  3806. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3807. } else {
  3808. if (clock->p1 == 2)
  3809. dpll |= PLL_P1_DIVIDE_BY_TWO;
  3810. else
  3811. dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  3812. if (clock->p2 == 4)
  3813. dpll |= PLL_P2_DIVIDE_BY_4;
  3814. }
  3815. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
  3816. /* XXX: just matching BIOS for now */
  3817. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  3818. dpll |= 3;
  3819. else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  3820. intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  3821. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  3822. else
  3823. dpll |= PLL_REF_INPUT_DREFCLK;
  3824. dpll |= DPLL_VCO_ENABLE;
  3825. I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
  3826. POSTING_READ(DPLL(pipe));
  3827. udelay(150);
  3828. for_each_encoder_on_crtc(dev, crtc, encoder)
  3829. if (encoder->pre_pll_enable)
  3830. encoder->pre_pll_enable(encoder);
  3831. I915_WRITE(DPLL(pipe), dpll);
  3832. /* Wait for the clocks to stabilize. */
  3833. POSTING_READ(DPLL(pipe));
  3834. udelay(150);
  3835. /* The pixel multiplier can only be updated once the
  3836. * DPLL is enabled and the clocks are stable.
  3837. *
  3838. * So write it again.
  3839. */
  3840. I915_WRITE(DPLL(pipe), dpll);
  3841. }
  3842. static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
  3843. struct drm_display_mode *mode,
  3844. struct drm_display_mode *adjusted_mode)
  3845. {
  3846. struct drm_device *dev = intel_crtc->base.dev;
  3847. struct drm_i915_private *dev_priv = dev->dev_private;
  3848. enum pipe pipe = intel_crtc->pipe;
  3849. enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
  3850. uint32_t vsyncshift;
  3851. if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
  3852. /* the chip adds 2 halflines automatically */
  3853. adjusted_mode->crtc_vtotal -= 1;
  3854. adjusted_mode->crtc_vblank_end -= 1;
  3855. vsyncshift = adjusted_mode->crtc_hsync_start
  3856. - adjusted_mode->crtc_htotal / 2;
  3857. } else {
  3858. vsyncshift = 0;
  3859. }
  3860. if (INTEL_INFO(dev)->gen > 3)
  3861. I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
  3862. I915_WRITE(HTOTAL(cpu_transcoder),
  3863. (adjusted_mode->crtc_hdisplay - 1) |
  3864. ((adjusted_mode->crtc_htotal - 1) << 16));
  3865. I915_WRITE(HBLANK(cpu_transcoder),
  3866. (adjusted_mode->crtc_hblank_start - 1) |
  3867. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  3868. I915_WRITE(HSYNC(cpu_transcoder),
  3869. (adjusted_mode->crtc_hsync_start - 1) |
  3870. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  3871. I915_WRITE(VTOTAL(cpu_transcoder),
  3872. (adjusted_mode->crtc_vdisplay - 1) |
  3873. ((adjusted_mode->crtc_vtotal - 1) << 16));
  3874. I915_WRITE(VBLANK(cpu_transcoder),
  3875. (adjusted_mode->crtc_vblank_start - 1) |
  3876. ((adjusted_mode->crtc_vblank_end - 1) << 16));
  3877. I915_WRITE(VSYNC(cpu_transcoder),
  3878. (adjusted_mode->crtc_vsync_start - 1) |
  3879. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  3880. /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
  3881. * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
  3882. * documented on the DDI_FUNC_CTL register description, EDP Input Select
  3883. * bits. */
  3884. if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
  3885. (pipe == PIPE_B || pipe == PIPE_C))
  3886. I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
  3887. /* pipesrc controls the size that is scaled from, which should
  3888. * always be the user's requested size.
  3889. */
  3890. I915_WRITE(PIPESRC(pipe),
  3891. ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  3892. }
  3893. static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
  3894. struct drm_display_mode *mode,
  3895. struct drm_display_mode *adjusted_mode,
  3896. int x, int y,
  3897. struct drm_framebuffer *fb)
  3898. {
  3899. struct drm_device *dev = crtc->dev;
  3900. struct drm_i915_private *dev_priv = dev->dev_private;
  3901. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  3902. int pipe = intel_crtc->pipe;
  3903. int plane = intel_crtc->plane;
  3904. int refclk, num_connectors = 0;
  3905. intel_clock_t clock, reduced_clock;
  3906. u32 dspcntr, pipeconf;
  3907. bool ok, has_reduced_clock = false, is_sdvo = false;
  3908. bool is_lvds = false, is_tv = false, is_dp = false;
  3909. struct intel_encoder *encoder;
  3910. const intel_limit_t *limit;
  3911. int ret;
  3912. for_each_encoder_on_crtc(dev, crtc, encoder) {
  3913. switch (encoder->type) {
  3914. case INTEL_OUTPUT_LVDS:
  3915. is_lvds = true;
  3916. break;
  3917. case INTEL_OUTPUT_SDVO:
  3918. case INTEL_OUTPUT_HDMI:
  3919. is_sdvo = true;
  3920. if (encoder->needs_tv_clock)
  3921. is_tv = true;
  3922. break;
  3923. case INTEL_OUTPUT_TVOUT:
  3924. is_tv = true;
  3925. break;
  3926. case INTEL_OUTPUT_DISPLAYPORT:
  3927. is_dp = true;
  3928. break;
  3929. }
  3930. num_connectors++;
  3931. }
  3932. refclk = i9xx_get_refclk(crtc, num_connectors);
  3933. /*
  3934. * Returns a set of divisors for the desired target clock with the given
  3935. * refclk, or FALSE. The returned values represent the clock equation:
  3936. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  3937. */
  3938. limit = intel_limit(crtc, refclk);
  3939. ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
  3940. &clock);
  3941. if (!ok) {
  3942. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  3943. return -EINVAL;
  3944. }
  3945. /* Ensure that the cursor is valid for the new mode before changing... */
  3946. intel_crtc_update_cursor(crtc, true);
  3947. if (is_lvds && dev_priv->lvds_downclock_avail) {
  3948. /*
  3949. * Ensure we match the reduced clock's P to the target clock.
  3950. * If the clocks don't match, we can't switch the display clock
  3951. * by using the FP0/FP1. In such case we will disable the LVDS
  3952. * downclock feature.
  3953. */
  3954. has_reduced_clock = limit->find_pll(limit, crtc,
  3955. dev_priv->lvds_downclock,
  3956. refclk,
  3957. &clock,
  3958. &reduced_clock);
  3959. }
  3960. if (is_sdvo && is_tv)
  3961. i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
  3962. if (IS_GEN2(dev))
  3963. i8xx_update_pll(crtc, adjusted_mode, &clock,
  3964. has_reduced_clock ? &reduced_clock : NULL,
  3965. num_connectors);
  3966. else if (IS_VALLEYVIEW(dev))
  3967. vlv_update_pll(crtc, mode, adjusted_mode, &clock,
  3968. has_reduced_clock ? &reduced_clock : NULL,
  3969. num_connectors);
  3970. else
  3971. i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
  3972. has_reduced_clock ? &reduced_clock : NULL,
  3973. num_connectors);
  3974. /* setup pipeconf */
  3975. pipeconf = I915_READ(PIPECONF(pipe));
  3976. /* Set up the display plane register */
  3977. dspcntr = DISPPLANE_GAMMA_ENABLE;
  3978. if (pipe == 0)
  3979. dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
  3980. else
  3981. dspcntr |= DISPPLANE_SEL_PIPE_B;
  3982. if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
  3983. /* Enable pixel doubling when the dot clock is > 90% of the (display)
  3984. * core speed.
  3985. *
  3986. * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
  3987. * pipe == 0 check?
  3988. */
  3989. if (mode->clock >
  3990. dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
  3991. pipeconf |= PIPECONF_DOUBLE_WIDE;
  3992. else
  3993. pipeconf &= ~PIPECONF_DOUBLE_WIDE;
  3994. }
  3995. /* default to 8bpc */
  3996. pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
  3997. if (is_dp) {
  3998. if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
  3999. pipeconf |= PIPECONF_6BPC |
  4000. PIPECONF_DITHER_EN |
  4001. PIPECONF_DITHER_TYPE_SP;
  4002. }
  4003. }
  4004. if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
  4005. if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
  4006. pipeconf |= PIPECONF_6BPC |
  4007. PIPECONF_ENABLE |
  4008. I965_PIPECONF_ACTIVE;
  4009. }
  4010. }
  4011. DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
  4012. drm_mode_debug_printmodeline(mode);
  4013. if (HAS_PIPE_CXSR(dev)) {
  4014. if (intel_crtc->lowfreq_avail) {
  4015. DRM_DEBUG_KMS("enabling CxSR downclocking\n");
  4016. pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
  4017. } else {
  4018. DRM_DEBUG_KMS("disabling CxSR downclocking\n");
  4019. pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
  4020. }
  4021. }
  4022. pipeconf &= ~PIPECONF_INTERLACE_MASK;
  4023. if (!IS_GEN2(dev) &&
  4024. adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  4025. pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
  4026. else
  4027. pipeconf |= PIPECONF_PROGRESSIVE;
  4028. intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
  4029. /* pipesrc and dspsize control the size that is scaled from,
  4030. * which should always be the user's requested size.
  4031. */
  4032. I915_WRITE(DSPSIZE(plane),
  4033. ((mode->vdisplay - 1) << 16) |
  4034. (mode->hdisplay - 1));
  4035. I915_WRITE(DSPPOS(plane), 0);
  4036. I915_WRITE(PIPECONF(pipe), pipeconf);
  4037. POSTING_READ(PIPECONF(pipe));
  4038. intel_enable_pipe(dev_priv, pipe, false);
  4039. intel_wait_for_vblank(dev, pipe);
  4040. I915_WRITE(DSPCNTR(plane), dspcntr);
  4041. POSTING_READ(DSPCNTR(plane));
  4042. ret = intel_pipe_set_base(crtc, x, y, fb);
  4043. intel_update_watermarks(dev);
  4044. return ret;
  4045. }
  4046. static void ironlake_init_pch_refclk(struct drm_device *dev)
  4047. {
  4048. struct drm_i915_private *dev_priv = dev->dev_private;
  4049. struct drm_mode_config *mode_config = &dev->mode_config;
  4050. struct intel_encoder *encoder;
  4051. u32 temp;
  4052. bool has_lvds = false;
  4053. bool has_cpu_edp = false;
  4054. bool has_pch_edp = false;
  4055. bool has_panel = false;
  4056. bool has_ck505 = false;
  4057. bool can_ssc = false;
  4058. /* We need to take the global config into account */
  4059. list_for_each_entry(encoder, &mode_config->encoder_list,
  4060. base.head) {
  4061. switch (encoder->type) {
  4062. case INTEL_OUTPUT_LVDS:
  4063. has_panel = true;
  4064. has_lvds = true;
  4065. break;
  4066. case INTEL_OUTPUT_EDP:
  4067. has_panel = true;
  4068. if (intel_encoder_is_pch_edp(&encoder->base))
  4069. has_pch_edp = true;
  4070. else
  4071. has_cpu_edp = true;
  4072. break;
  4073. }
  4074. }
  4075. if (HAS_PCH_IBX(dev)) {
  4076. has_ck505 = dev_priv->display_clock_mode;
  4077. can_ssc = has_ck505;
  4078. } else {
  4079. has_ck505 = false;
  4080. can_ssc = true;
  4081. }
  4082. DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
  4083. has_panel, has_lvds, has_pch_edp, has_cpu_edp,
  4084. has_ck505);
  4085. /* Ironlake: try to setup display ref clock before DPLL
  4086. * enabling. This is only under driver's control after
  4087. * PCH B stepping, previous chipset stepping should be
  4088. * ignoring this setting.
  4089. */
  4090. temp = I915_READ(PCH_DREF_CONTROL);
  4091. /* Always enable nonspread source */
  4092. temp &= ~DREF_NONSPREAD_SOURCE_MASK;
  4093. if (has_ck505)
  4094. temp |= DREF_NONSPREAD_CK505_ENABLE;
  4095. else
  4096. temp |= DREF_NONSPREAD_SOURCE_ENABLE;
  4097. if (has_panel) {
  4098. temp &= ~DREF_SSC_SOURCE_MASK;
  4099. temp |= DREF_SSC_SOURCE_ENABLE;
  4100. /* SSC must be turned on before enabling the CPU output */
  4101. if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  4102. DRM_DEBUG_KMS("Using SSC on panel\n");
  4103. temp |= DREF_SSC1_ENABLE;
  4104. } else
  4105. temp &= ~DREF_SSC1_ENABLE;
  4106. /* Get SSC going before enabling the outputs */
  4107. I915_WRITE(PCH_DREF_CONTROL, temp);
  4108. POSTING_READ(PCH_DREF_CONTROL);
  4109. udelay(200);
  4110. temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  4111. /* Enable CPU source on CPU attached eDP */
  4112. if (has_cpu_edp) {
  4113. if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  4114. DRM_DEBUG_KMS("Using SSC on eDP\n");
  4115. temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  4116. }
  4117. else
  4118. temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  4119. } else
  4120. temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  4121. I915_WRITE(PCH_DREF_CONTROL, temp);
  4122. POSTING_READ(PCH_DREF_CONTROL);
  4123. udelay(200);
  4124. } else {
  4125. DRM_DEBUG_KMS("Disabling SSC entirely\n");
  4126. temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  4127. /* Turn off CPU output */
  4128. temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  4129. I915_WRITE(PCH_DREF_CONTROL, temp);
  4130. POSTING_READ(PCH_DREF_CONTROL);
  4131. udelay(200);
  4132. /* Turn off the SSC source */
  4133. temp &= ~DREF_SSC_SOURCE_MASK;
  4134. temp |= DREF_SSC_SOURCE_DISABLE;
  4135. /* Turn off SSC1 */
  4136. temp &= ~ DREF_SSC1_ENABLE;
  4137. I915_WRITE(PCH_DREF_CONTROL, temp);
  4138. POSTING_READ(PCH_DREF_CONTROL);
  4139. udelay(200);
  4140. }
  4141. }
  4142. /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
  4143. static void lpt_init_pch_refclk(struct drm_device *dev)
  4144. {
  4145. struct drm_i915_private *dev_priv = dev->dev_private;
  4146. struct drm_mode_config *mode_config = &dev->mode_config;
  4147. struct intel_encoder *encoder;
  4148. bool has_vga = false;
  4149. bool is_sdv = false;
  4150. u32 tmp;
  4151. list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
  4152. switch (encoder->type) {
  4153. case INTEL_OUTPUT_ANALOG:
  4154. has_vga = true;
  4155. break;
  4156. }
  4157. }
  4158. if (!has_vga)
  4159. return;
  4160. /* XXX: Rip out SDV support once Haswell ships for real. */
  4161. if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
  4162. is_sdv = true;
  4163. tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  4164. tmp &= ~SBI_SSCCTL_DISABLE;
  4165. tmp |= SBI_SSCCTL_PATHALT;
  4166. intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  4167. udelay(24);
  4168. tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
  4169. tmp &= ~SBI_SSCCTL_PATHALT;
  4170. intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
  4171. if (!is_sdv) {
  4172. tmp = I915_READ(SOUTH_CHICKEN2);
  4173. tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
  4174. I915_WRITE(SOUTH_CHICKEN2, tmp);
  4175. if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
  4176. FDI_MPHY_IOSFSB_RESET_STATUS, 100))
  4177. DRM_ERROR("FDI mPHY reset assert timeout\n");
  4178. tmp = I915_READ(SOUTH_CHICKEN2);
  4179. tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
  4180. I915_WRITE(SOUTH_CHICKEN2, tmp);
  4181. if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
  4182. FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
  4183. 100))
  4184. DRM_ERROR("FDI mPHY reset de-assert timeout\n");
  4185. }
  4186. tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
  4187. tmp &= ~(0xFF << 24);
  4188. tmp |= (0x12 << 24);
  4189. intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
  4190. if (!is_sdv) {
  4191. tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
  4192. tmp &= ~(0x3 << 6);
  4193. tmp |= (1 << 6) | (1 << 0);
  4194. intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
  4195. }
  4196. if (is_sdv) {
  4197. tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
  4198. tmp |= 0x7FFF;
  4199. intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
  4200. }
  4201. tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
  4202. tmp |= (1 << 11);
  4203. intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
  4204. tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
  4205. tmp |= (1 << 11);
  4206. intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
  4207. if (is_sdv) {
  4208. tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
  4209. tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
  4210. intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
  4211. tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
  4212. tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
  4213. intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
  4214. tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
  4215. tmp |= (0x3F << 8);
  4216. intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
  4217. tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
  4218. tmp |= (0x3F << 8);
  4219. intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
  4220. }
  4221. tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
  4222. tmp |= (1 << 24) | (1 << 21) | (1 << 18);
  4223. intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
  4224. tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
  4225. tmp |= (1 << 24) | (1 << 21) | (1 << 18);
  4226. intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
  4227. if (!is_sdv) {
  4228. tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
  4229. tmp &= ~(7 << 13);
  4230. tmp |= (5 << 13);
  4231. intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
  4232. tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
  4233. tmp &= ~(7 << 13);
  4234. tmp |= (5 << 13);
  4235. intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
  4236. }
  4237. tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
  4238. tmp &= ~0xFF;
  4239. tmp |= 0x1C;
  4240. intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
  4241. tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
  4242. tmp &= ~0xFF;
  4243. tmp |= 0x1C;
  4244. intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
  4245. tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
  4246. tmp &= ~(0xFF << 16);
  4247. tmp |= (0x1C << 16);
  4248. intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
  4249. tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
  4250. tmp &= ~(0xFF << 16);
  4251. tmp |= (0x1C << 16);
  4252. intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
  4253. if (!is_sdv) {
  4254. tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
  4255. tmp |= (1 << 27);
  4256. intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
  4257. tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
  4258. tmp |= (1 << 27);
  4259. intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
  4260. tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
  4261. tmp &= ~(0xF << 28);
  4262. tmp |= (4 << 28);
  4263. intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
  4264. tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
  4265. tmp &= ~(0xF << 28);
  4266. tmp |= (4 << 28);
  4267. intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
  4268. }
  4269. /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
  4270. tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
  4271. tmp |= SBI_DBUFF0_ENABLE;
  4272. intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
  4273. }
  4274. /*
  4275. * Initialize reference clocks when the driver loads
  4276. */
  4277. void intel_init_pch_refclk(struct drm_device *dev)
  4278. {
  4279. if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
  4280. ironlake_init_pch_refclk(dev);
  4281. else if (HAS_PCH_LPT(dev))
  4282. lpt_init_pch_refclk(dev);
  4283. }
  4284. static int ironlake_get_refclk(struct drm_crtc *crtc)
  4285. {
  4286. struct drm_device *dev = crtc->dev;
  4287. struct drm_i915_private *dev_priv = dev->dev_private;
  4288. struct intel_encoder *encoder;
  4289. struct intel_encoder *edp_encoder = NULL;
  4290. int num_connectors = 0;
  4291. bool is_lvds = false;
  4292. for_each_encoder_on_crtc(dev, crtc, encoder) {
  4293. switch (encoder->type) {
  4294. case INTEL_OUTPUT_LVDS:
  4295. is_lvds = true;
  4296. break;
  4297. case INTEL_OUTPUT_EDP:
  4298. edp_encoder = encoder;
  4299. break;
  4300. }
  4301. num_connectors++;
  4302. }
  4303. if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  4304. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  4305. dev_priv->lvds_ssc_freq);
  4306. return dev_priv->lvds_ssc_freq * 1000;
  4307. }
  4308. return 120000;
  4309. }
  4310. static void ironlake_set_pipeconf(struct drm_crtc *crtc,
  4311. struct drm_display_mode *adjusted_mode,
  4312. bool dither)
  4313. {
  4314. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  4315. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4316. int pipe = intel_crtc->pipe;
  4317. uint32_t val;
  4318. val = I915_READ(PIPECONF(pipe));
  4319. val &= ~PIPECONF_BPC_MASK;
  4320. switch (intel_crtc->bpp) {
  4321. case 18:
  4322. val |= PIPECONF_6BPC;
  4323. break;
  4324. case 24:
  4325. val |= PIPECONF_8BPC;
  4326. break;
  4327. case 30:
  4328. val |= PIPECONF_10BPC;
  4329. break;
  4330. case 36:
  4331. val |= PIPECONF_12BPC;
  4332. break;
  4333. default:
  4334. /* Case prevented by intel_choose_pipe_bpp_dither. */
  4335. BUG();
  4336. }
  4337. val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
  4338. if (dither)
  4339. val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
  4340. val &= ~PIPECONF_INTERLACE_MASK;
  4341. if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  4342. val |= PIPECONF_INTERLACED_ILK;
  4343. else
  4344. val |= PIPECONF_PROGRESSIVE;
  4345. if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
  4346. val |= PIPECONF_COLOR_RANGE_SELECT;
  4347. else
  4348. val &= ~PIPECONF_COLOR_RANGE_SELECT;
  4349. I915_WRITE(PIPECONF(pipe), val);
  4350. POSTING_READ(PIPECONF(pipe));
  4351. }
  4352. static void haswell_set_pipeconf(struct drm_crtc *crtc,
  4353. struct drm_display_mode *adjusted_mode,
  4354. bool dither)
  4355. {
  4356. struct drm_i915_private *dev_priv = crtc->dev->dev_private;
  4357. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4358. enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
  4359. uint32_t val;
  4360. val = I915_READ(PIPECONF(cpu_transcoder));
  4361. val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
  4362. if (dither)
  4363. val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
  4364. val &= ~PIPECONF_INTERLACE_MASK_HSW;
  4365. if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  4366. val |= PIPECONF_INTERLACED_ILK;
  4367. else
  4368. val |= PIPECONF_PROGRESSIVE;
  4369. I915_WRITE(PIPECONF(cpu_transcoder), val);
  4370. POSTING_READ(PIPECONF(cpu_transcoder));
  4371. }
  4372. static bool ironlake_compute_clocks(struct drm_crtc *crtc,
  4373. struct drm_display_mode *adjusted_mode,
  4374. intel_clock_t *clock,
  4375. bool *has_reduced_clock,
  4376. intel_clock_t *reduced_clock)
  4377. {
  4378. struct drm_device *dev = crtc->dev;
  4379. struct drm_i915_private *dev_priv = dev->dev_private;
  4380. struct intel_encoder *intel_encoder;
  4381. int refclk;
  4382. const intel_limit_t *limit;
  4383. bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
  4384. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  4385. switch (intel_encoder->type) {
  4386. case INTEL_OUTPUT_LVDS:
  4387. is_lvds = true;
  4388. break;
  4389. case INTEL_OUTPUT_SDVO:
  4390. case INTEL_OUTPUT_HDMI:
  4391. is_sdvo = true;
  4392. if (intel_encoder->needs_tv_clock)
  4393. is_tv = true;
  4394. break;
  4395. case INTEL_OUTPUT_TVOUT:
  4396. is_tv = true;
  4397. break;
  4398. }
  4399. }
  4400. refclk = ironlake_get_refclk(crtc);
  4401. /*
  4402. * Returns a set of divisors for the desired target clock with the given
  4403. * refclk, or FALSE. The returned values represent the clock equation:
  4404. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  4405. */
  4406. limit = intel_limit(crtc, refclk);
  4407. ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
  4408. clock);
  4409. if (!ret)
  4410. return false;
  4411. if (is_lvds && dev_priv->lvds_downclock_avail) {
  4412. /*
  4413. * Ensure we match the reduced clock's P to the target clock.
  4414. * If the clocks don't match, we can't switch the display clock
  4415. * by using the FP0/FP1. In such case we will disable the LVDS
  4416. * downclock feature.
  4417. */
  4418. *has_reduced_clock = limit->find_pll(limit, crtc,
  4419. dev_priv->lvds_downclock,
  4420. refclk,
  4421. clock,
  4422. reduced_clock);
  4423. }
  4424. if (is_sdvo && is_tv)
  4425. i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
  4426. return true;
  4427. }
  4428. static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
  4429. {
  4430. struct drm_i915_private *dev_priv = dev->dev_private;
  4431. uint32_t temp;
  4432. temp = I915_READ(SOUTH_CHICKEN1);
  4433. if (temp & FDI_BC_BIFURCATION_SELECT)
  4434. return;
  4435. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
  4436. WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
  4437. temp |= FDI_BC_BIFURCATION_SELECT;
  4438. DRM_DEBUG_KMS("enabling fdi C rx\n");
  4439. I915_WRITE(SOUTH_CHICKEN1, temp);
  4440. POSTING_READ(SOUTH_CHICKEN1);
  4441. }
  4442. static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
  4443. {
  4444. struct drm_device *dev = intel_crtc->base.dev;
  4445. struct drm_i915_private *dev_priv = dev->dev_private;
  4446. struct intel_crtc *pipe_B_crtc =
  4447. to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
  4448. DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
  4449. intel_crtc->pipe, intel_crtc->fdi_lanes);
  4450. if (intel_crtc->fdi_lanes > 4) {
  4451. DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
  4452. intel_crtc->pipe, intel_crtc->fdi_lanes);
  4453. /* Clamp lanes to avoid programming the hw with bogus values. */
  4454. intel_crtc->fdi_lanes = 4;
  4455. return false;
  4456. }
  4457. if (dev_priv->num_pipe == 2)
  4458. return true;
  4459. switch (intel_crtc->pipe) {
  4460. case PIPE_A:
  4461. return true;
  4462. case PIPE_B:
  4463. if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
  4464. intel_crtc->fdi_lanes > 2) {
  4465. DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
  4466. intel_crtc->pipe, intel_crtc->fdi_lanes);
  4467. /* Clamp lanes to avoid programming the hw with bogus values. */
  4468. intel_crtc->fdi_lanes = 2;
  4469. return false;
  4470. }
  4471. if (intel_crtc->fdi_lanes > 2)
  4472. WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
  4473. else
  4474. cpt_enable_fdi_bc_bifurcation(dev);
  4475. return true;
  4476. case PIPE_C:
  4477. if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
  4478. if (intel_crtc->fdi_lanes > 2) {
  4479. DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
  4480. intel_crtc->pipe, intel_crtc->fdi_lanes);
  4481. /* Clamp lanes to avoid programming the hw with bogus values. */
  4482. intel_crtc->fdi_lanes = 2;
  4483. return false;
  4484. }
  4485. } else {
  4486. DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
  4487. return false;
  4488. }
  4489. cpt_enable_fdi_bc_bifurcation(dev);
  4490. return true;
  4491. default:
  4492. BUG();
  4493. }
  4494. }
  4495. int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
  4496. {
  4497. /*
  4498. * Account for spread spectrum to avoid
  4499. * oversubscribing the link. Max center spread
  4500. * is 2.5%; use 5% for safety's sake.
  4501. */
  4502. u32 bps = target_clock * bpp * 21 / 20;
  4503. return bps / (link_bw * 8) + 1;
  4504. }
  4505. static void ironlake_set_m_n(struct drm_crtc *crtc,
  4506. struct drm_display_mode *mode,
  4507. struct drm_display_mode *adjusted_mode)
  4508. {
  4509. struct drm_device *dev = crtc->dev;
  4510. struct drm_i915_private *dev_priv = dev->dev_private;
  4511. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4512. enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
  4513. struct intel_encoder *intel_encoder, *edp_encoder = NULL;
  4514. struct intel_link_m_n m_n = {0};
  4515. int target_clock, pixel_multiplier, lane, link_bw;
  4516. bool is_dp = false, is_cpu_edp = false;
  4517. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  4518. switch (intel_encoder->type) {
  4519. case INTEL_OUTPUT_DISPLAYPORT:
  4520. is_dp = true;
  4521. break;
  4522. case INTEL_OUTPUT_EDP:
  4523. is_dp = true;
  4524. if (!intel_encoder_is_pch_edp(&intel_encoder->base))
  4525. is_cpu_edp = true;
  4526. edp_encoder = intel_encoder;
  4527. break;
  4528. }
  4529. }
  4530. /* FDI link */
  4531. pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  4532. lane = 0;
  4533. /* CPU eDP doesn't require FDI link, so just set DP M/N
  4534. according to current link config */
  4535. if (is_cpu_edp) {
  4536. intel_edp_link_config(edp_encoder, &lane, &link_bw);
  4537. } else {
  4538. /* FDI is a binary signal running at ~2.7GHz, encoding
  4539. * each output octet as 10 bits. The actual frequency
  4540. * is stored as a divider into a 100MHz clock, and the
  4541. * mode pixel clock is stored in units of 1KHz.
  4542. * Hence the bw of each lane in terms of the mode signal
  4543. * is:
  4544. */
  4545. link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
  4546. }
  4547. /* [e]DP over FDI requires target mode clock instead of link clock. */
  4548. if (edp_encoder)
  4549. target_clock = intel_edp_target_clock(edp_encoder, mode);
  4550. else if (is_dp)
  4551. target_clock = mode->clock;
  4552. else
  4553. target_clock = adjusted_mode->clock;
  4554. if (!lane)
  4555. lane = ironlake_get_lanes_required(target_clock, link_bw,
  4556. intel_crtc->bpp);
  4557. intel_crtc->fdi_lanes = lane;
  4558. if (pixel_multiplier > 1)
  4559. link_bw *= pixel_multiplier;
  4560. intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
  4561. I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
  4562. I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
  4563. I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
  4564. I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
  4565. }
  4566. static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
  4567. struct drm_display_mode *adjusted_mode,
  4568. intel_clock_t *clock, u32 fp)
  4569. {
  4570. struct drm_crtc *crtc = &intel_crtc->base;
  4571. struct drm_device *dev = crtc->dev;
  4572. struct drm_i915_private *dev_priv = dev->dev_private;
  4573. struct intel_encoder *intel_encoder;
  4574. uint32_t dpll;
  4575. int factor, pixel_multiplier, num_connectors = 0;
  4576. bool is_lvds = false, is_sdvo = false, is_tv = false;
  4577. bool is_dp = false, is_cpu_edp = false;
  4578. for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
  4579. switch (intel_encoder->type) {
  4580. case INTEL_OUTPUT_LVDS:
  4581. is_lvds = true;
  4582. break;
  4583. case INTEL_OUTPUT_SDVO:
  4584. case INTEL_OUTPUT_HDMI:
  4585. is_sdvo = true;
  4586. if (intel_encoder->needs_tv_clock)
  4587. is_tv = true;
  4588. break;
  4589. case INTEL_OUTPUT_TVOUT:
  4590. is_tv = true;
  4591. break;
  4592. case INTEL_OUTPUT_DISPLAYPORT:
  4593. is_dp = true;
  4594. break;
  4595. case INTEL_OUTPUT_EDP:
  4596. is_dp = true;
  4597. if (!intel_encoder_is_pch_edp(&intel_encoder->base))
  4598. is_cpu_edp = true;
  4599. break;
  4600. }
  4601. num_connectors++;
  4602. }
  4603. /* Enable autotuning of the PLL clock (if permissible) */
  4604. factor = 21;
  4605. if (is_lvds) {
  4606. if ((intel_panel_use_ssc(dev_priv) &&
  4607. dev_priv->lvds_ssc_freq == 100) ||
  4608. intel_is_dual_link_lvds(dev))
  4609. factor = 25;
  4610. } else if (is_sdvo && is_tv)
  4611. factor = 20;
  4612. if (clock->m < factor * clock->n)
  4613. fp |= FP_CB_TUNE;
  4614. dpll = 0;
  4615. if (is_lvds)
  4616. dpll |= DPLLB_MODE_LVDS;
  4617. else
  4618. dpll |= DPLLB_MODE_DAC_SERIAL;
  4619. if (is_sdvo) {
  4620. pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  4621. if (pixel_multiplier > 1) {
  4622. dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
  4623. }
  4624. dpll |= DPLL_DVO_HIGH_SPEED;
  4625. }
  4626. if (is_dp && !is_cpu_edp)
  4627. dpll |= DPLL_DVO_HIGH_SPEED;
  4628. /* compute bitmask from p1 value */
  4629. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  4630. /* also FPA1 */
  4631. dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  4632. switch (clock->p2) {
  4633. case 5:
  4634. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  4635. break;
  4636. case 7:
  4637. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  4638. break;
  4639. case 10:
  4640. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  4641. break;
  4642. case 14:
  4643. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  4644. break;
  4645. }
  4646. if (is_sdvo && is_tv)
  4647. dpll |= PLL_REF_INPUT_TVCLKINBC;
  4648. else if (is_tv)
  4649. /* XXX: just matching BIOS for now */
  4650. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  4651. dpll |= 3;
  4652. else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  4653. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  4654. else
  4655. dpll |= PLL_REF_INPUT_DREFCLK;
  4656. return dpll;
  4657. }
  4658. static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
  4659. struct drm_display_mode *mode,
  4660. struct drm_display_mode *adjusted_mode,
  4661. int x, int y,
  4662. struct drm_framebuffer *fb)
  4663. {
  4664. struct drm_device *dev = crtc->dev;
  4665. struct drm_i915_private *dev_priv = dev->dev_private;
  4666. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4667. int pipe = intel_crtc->pipe;
  4668. int plane = intel_crtc->plane;
  4669. int num_connectors = 0;
  4670. intel_clock_t clock, reduced_clock;
  4671. u32 dpll, fp = 0, fp2 = 0;
  4672. bool ok, has_reduced_clock = false;
  4673. bool is_lvds = false, is_dp = false, is_cpu_edp = false;
  4674. struct intel_encoder *encoder;
  4675. int ret;
  4676. bool dither, fdi_config_ok;
  4677. for_each_encoder_on_crtc(dev, crtc, encoder) {
  4678. switch (encoder->type) {
  4679. case INTEL_OUTPUT_LVDS:
  4680. is_lvds = true;
  4681. break;
  4682. case INTEL_OUTPUT_DISPLAYPORT:
  4683. is_dp = true;
  4684. break;
  4685. case INTEL_OUTPUT_EDP:
  4686. is_dp = true;
  4687. if (!intel_encoder_is_pch_edp(&encoder->base))
  4688. is_cpu_edp = true;
  4689. break;
  4690. }
  4691. num_connectors++;
  4692. }
  4693. WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
  4694. "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
  4695. ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
  4696. &has_reduced_clock, &reduced_clock);
  4697. if (!ok) {
  4698. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  4699. return -EINVAL;
  4700. }
  4701. /* Ensure that the cursor is valid for the new mode before changing... */
  4702. intel_crtc_update_cursor(crtc, true);
  4703. /* determine panel color depth */
  4704. dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
  4705. adjusted_mode);
  4706. if (is_lvds && dev_priv->lvds_dither)
  4707. dither = true;
  4708. fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
  4709. if (has_reduced_clock)
  4710. fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
  4711. reduced_clock.m2;
  4712. dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
  4713. DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
  4714. drm_mode_debug_printmodeline(mode);
  4715. /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
  4716. if (!is_cpu_edp) {
  4717. struct intel_pch_pll *pll;
  4718. pll = intel_get_pch_pll(intel_crtc, dpll, fp);
  4719. if (pll == NULL) {
  4720. DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
  4721. pipe);
  4722. return -EINVAL;
  4723. }
  4724. } else
  4725. intel_put_pch_pll(intel_crtc);
  4726. if (is_dp && !is_cpu_edp)
  4727. intel_dp_set_m_n(crtc, mode, adjusted_mode);
  4728. for_each_encoder_on_crtc(dev, crtc, encoder)
  4729. if (encoder->pre_pll_enable)
  4730. encoder->pre_pll_enable(encoder);
  4731. if (intel_crtc->pch_pll) {
  4732. I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
  4733. /* Wait for the clocks to stabilize. */
  4734. POSTING_READ(intel_crtc->pch_pll->pll_reg);
  4735. udelay(150);
  4736. /* The pixel multiplier can only be updated once the
  4737. * DPLL is enabled and the clocks are stable.
  4738. *
  4739. * So write it again.
  4740. */
  4741. I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
  4742. }
  4743. intel_crtc->lowfreq_avail = false;
  4744. if (intel_crtc->pch_pll) {
  4745. if (is_lvds && has_reduced_clock && i915_powersave) {
  4746. I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
  4747. intel_crtc->lowfreq_avail = true;
  4748. } else {
  4749. I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
  4750. }
  4751. }
  4752. intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
  4753. /* Note, this also computes intel_crtc->fdi_lanes which is used below in
  4754. * ironlake_check_fdi_lanes. */
  4755. ironlake_set_m_n(crtc, mode, adjusted_mode);
  4756. fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
  4757. ironlake_set_pipeconf(crtc, adjusted_mode, dither);
  4758. intel_wait_for_vblank(dev, pipe);
  4759. /* Set up the display plane register */
  4760. I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
  4761. POSTING_READ(DSPCNTR(plane));
  4762. ret = intel_pipe_set_base(crtc, x, y, fb);
  4763. intel_update_watermarks(dev);
  4764. intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
  4765. return fdi_config_ok ? ret : -EINVAL;
  4766. }
  4767. static int haswell_crtc_mode_set(struct drm_crtc *crtc,
  4768. struct drm_display_mode *mode,
  4769. struct drm_display_mode *adjusted_mode,
  4770. int x, int y,
  4771. struct drm_framebuffer *fb)
  4772. {
  4773. struct drm_device *dev = crtc->dev;
  4774. struct drm_i915_private *dev_priv = dev->dev_private;
  4775. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4776. int pipe = intel_crtc->pipe;
  4777. int plane = intel_crtc->plane;
  4778. int num_connectors = 0;
  4779. bool is_dp = false, is_cpu_edp = false;
  4780. struct intel_encoder *encoder;
  4781. int ret;
  4782. bool dither;
  4783. for_each_encoder_on_crtc(dev, crtc, encoder) {
  4784. switch (encoder->type) {
  4785. case INTEL_OUTPUT_DISPLAYPORT:
  4786. is_dp = true;
  4787. break;
  4788. case INTEL_OUTPUT_EDP:
  4789. is_dp = true;
  4790. if (!intel_encoder_is_pch_edp(&encoder->base))
  4791. is_cpu_edp = true;
  4792. break;
  4793. }
  4794. num_connectors++;
  4795. }
  4796. if (is_cpu_edp)
  4797. intel_crtc->cpu_transcoder = TRANSCODER_EDP;
  4798. else
  4799. intel_crtc->cpu_transcoder = pipe;
  4800. /* We are not sure yet this won't happen. */
  4801. WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
  4802. INTEL_PCH_TYPE(dev));
  4803. WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
  4804. num_connectors, pipe_name(pipe));
  4805. WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
  4806. (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
  4807. WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
  4808. if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
  4809. return -EINVAL;
  4810. /* Ensure that the cursor is valid for the new mode before changing... */
  4811. intel_crtc_update_cursor(crtc, true);
  4812. /* determine panel color depth */
  4813. dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
  4814. adjusted_mode);
  4815. DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
  4816. drm_mode_debug_printmodeline(mode);
  4817. if (is_dp && !is_cpu_edp)
  4818. intel_dp_set_m_n(crtc, mode, adjusted_mode);
  4819. intel_crtc->lowfreq_avail = false;
  4820. intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
  4821. if (!is_dp || is_cpu_edp)
  4822. ironlake_set_m_n(crtc, mode, adjusted_mode);
  4823. haswell_set_pipeconf(crtc, adjusted_mode, dither);
  4824. /* Set up the display plane register */
  4825. I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
  4826. POSTING_READ(DSPCNTR(plane));
  4827. ret = intel_pipe_set_base(crtc, x, y, fb);
  4828. intel_update_watermarks(dev);
  4829. intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
  4830. return ret;
  4831. }
  4832. static int intel_crtc_mode_set(struct drm_crtc *crtc,
  4833. struct drm_display_mode *mode,
  4834. struct drm_display_mode *adjusted_mode,
  4835. int x, int y,
  4836. struct drm_framebuffer *fb)
  4837. {
  4838. struct drm_device *dev = crtc->dev;
  4839. struct drm_i915_private *dev_priv = dev->dev_private;
  4840. struct drm_encoder_helper_funcs *encoder_funcs;
  4841. struct intel_encoder *encoder;
  4842. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4843. int pipe = intel_crtc->pipe;
  4844. int ret;
  4845. drm_vblank_pre_modeset(dev, pipe);
  4846. ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
  4847. x, y, fb);
  4848. drm_vblank_post_modeset(dev, pipe);
  4849. if (ret != 0)
  4850. return ret;
  4851. for_each_encoder_on_crtc(dev, crtc, encoder) {
  4852. DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
  4853. encoder->base.base.id,
  4854. drm_get_encoder_name(&encoder->base),
  4855. mode->base.id, mode->name);
  4856. encoder_funcs = encoder->base.helper_private;
  4857. encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
  4858. }
  4859. return 0;
  4860. }
  4861. static bool intel_eld_uptodate(struct drm_connector *connector,
  4862. int reg_eldv, uint32_t bits_eldv,
  4863. int reg_elda, uint32_t bits_elda,
  4864. int reg_edid)
  4865. {
  4866. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  4867. uint8_t *eld = connector->eld;
  4868. uint32_t i;
  4869. i = I915_READ(reg_eldv);
  4870. i &= bits_eldv;
  4871. if (!eld[0])
  4872. return !i;
  4873. if (!i)
  4874. return false;
  4875. i = I915_READ(reg_elda);
  4876. i &= ~bits_elda;
  4877. I915_WRITE(reg_elda, i);
  4878. for (i = 0; i < eld[2]; i++)
  4879. if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
  4880. return false;
  4881. return true;
  4882. }
  4883. static void g4x_write_eld(struct drm_connector *connector,
  4884. struct drm_crtc *crtc)
  4885. {
  4886. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  4887. uint8_t *eld = connector->eld;
  4888. uint32_t eldv;
  4889. uint32_t len;
  4890. uint32_t i;
  4891. i = I915_READ(G4X_AUD_VID_DID);
  4892. if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
  4893. eldv = G4X_ELDV_DEVCL_DEVBLC;
  4894. else
  4895. eldv = G4X_ELDV_DEVCTG;
  4896. if (intel_eld_uptodate(connector,
  4897. G4X_AUD_CNTL_ST, eldv,
  4898. G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
  4899. G4X_HDMIW_HDMIEDID))
  4900. return;
  4901. i = I915_READ(G4X_AUD_CNTL_ST);
  4902. i &= ~(eldv | G4X_ELD_ADDR);
  4903. len = (i >> 9) & 0x1f; /* ELD buffer size */
  4904. I915_WRITE(G4X_AUD_CNTL_ST, i);
  4905. if (!eld[0])
  4906. return;
  4907. len = min_t(uint8_t, eld[2], len);
  4908. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  4909. for (i = 0; i < len; i++)
  4910. I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
  4911. i = I915_READ(G4X_AUD_CNTL_ST);
  4912. i |= eldv;
  4913. I915_WRITE(G4X_AUD_CNTL_ST, i);
  4914. }
  4915. static void haswell_write_eld(struct drm_connector *connector,
  4916. struct drm_crtc *crtc)
  4917. {
  4918. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  4919. uint8_t *eld = connector->eld;
  4920. struct drm_device *dev = crtc->dev;
  4921. uint32_t eldv;
  4922. uint32_t i;
  4923. int len;
  4924. int pipe = to_intel_crtc(crtc)->pipe;
  4925. int tmp;
  4926. int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
  4927. int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
  4928. int aud_config = HSW_AUD_CFG(pipe);
  4929. int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
  4930. DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
  4931. /* Audio output enable */
  4932. DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
  4933. tmp = I915_READ(aud_cntrl_st2);
  4934. tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
  4935. I915_WRITE(aud_cntrl_st2, tmp);
  4936. /* Wait for 1 vertical blank */
  4937. intel_wait_for_vblank(dev, pipe);
  4938. /* Set ELD valid state */
  4939. tmp = I915_READ(aud_cntrl_st2);
  4940. DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
  4941. tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
  4942. I915_WRITE(aud_cntrl_st2, tmp);
  4943. tmp = I915_READ(aud_cntrl_st2);
  4944. DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
  4945. /* Enable HDMI mode */
  4946. tmp = I915_READ(aud_config);
  4947. DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
  4948. /* clear N_programing_enable and N_value_index */
  4949. tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
  4950. I915_WRITE(aud_config, tmp);
  4951. DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
  4952. eldv = AUDIO_ELD_VALID_A << (pipe * 4);
  4953. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  4954. DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
  4955. eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
  4956. I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
  4957. } else
  4958. I915_WRITE(aud_config, 0);
  4959. if (intel_eld_uptodate(connector,
  4960. aud_cntrl_st2, eldv,
  4961. aud_cntl_st, IBX_ELD_ADDRESS,
  4962. hdmiw_hdmiedid))
  4963. return;
  4964. i = I915_READ(aud_cntrl_st2);
  4965. i &= ~eldv;
  4966. I915_WRITE(aud_cntrl_st2, i);
  4967. if (!eld[0])
  4968. return;
  4969. i = I915_READ(aud_cntl_st);
  4970. i &= ~IBX_ELD_ADDRESS;
  4971. I915_WRITE(aud_cntl_st, i);
  4972. i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
  4973. DRM_DEBUG_DRIVER("port num:%d\n", i);
  4974. len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
  4975. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  4976. for (i = 0; i < len; i++)
  4977. I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
  4978. i = I915_READ(aud_cntrl_st2);
  4979. i |= eldv;
  4980. I915_WRITE(aud_cntrl_st2, i);
  4981. }
  4982. static void ironlake_write_eld(struct drm_connector *connector,
  4983. struct drm_crtc *crtc)
  4984. {
  4985. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  4986. uint8_t *eld = connector->eld;
  4987. uint32_t eldv;
  4988. uint32_t i;
  4989. int len;
  4990. int hdmiw_hdmiedid;
  4991. int aud_config;
  4992. int aud_cntl_st;
  4993. int aud_cntrl_st2;
  4994. int pipe = to_intel_crtc(crtc)->pipe;
  4995. if (HAS_PCH_IBX(connector->dev)) {
  4996. hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
  4997. aud_config = IBX_AUD_CFG(pipe);
  4998. aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
  4999. aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
  5000. } else {
  5001. hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
  5002. aud_config = CPT_AUD_CFG(pipe);
  5003. aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
  5004. aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
  5005. }
  5006. DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
  5007. i = I915_READ(aud_cntl_st);
  5008. i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
  5009. if (!i) {
  5010. DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
  5011. /* operate blindly on all ports */
  5012. eldv = IBX_ELD_VALIDB;
  5013. eldv |= IBX_ELD_VALIDB << 4;
  5014. eldv |= IBX_ELD_VALIDB << 8;
  5015. } else {
  5016. DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
  5017. eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
  5018. }
  5019. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  5020. DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
  5021. eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
  5022. I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
  5023. } else
  5024. I915_WRITE(aud_config, 0);
  5025. if (intel_eld_uptodate(connector,
  5026. aud_cntrl_st2, eldv,
  5027. aud_cntl_st, IBX_ELD_ADDRESS,
  5028. hdmiw_hdmiedid))
  5029. return;
  5030. i = I915_READ(aud_cntrl_st2);
  5031. i &= ~eldv;
  5032. I915_WRITE(aud_cntrl_st2, i);
  5033. if (!eld[0])
  5034. return;
  5035. i = I915_READ(aud_cntl_st);
  5036. i &= ~IBX_ELD_ADDRESS;
  5037. I915_WRITE(aud_cntl_st, i);
  5038. len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
  5039. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  5040. for (i = 0; i < len; i++)
  5041. I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
  5042. i = I915_READ(aud_cntrl_st2);
  5043. i |= eldv;
  5044. I915_WRITE(aud_cntrl_st2, i);
  5045. }
  5046. void intel_write_eld(struct drm_encoder *encoder,
  5047. struct drm_display_mode *mode)
  5048. {
  5049. struct drm_crtc *crtc = encoder->crtc;
  5050. struct drm_connector *connector;
  5051. struct drm_device *dev = encoder->dev;
  5052. struct drm_i915_private *dev_priv = dev->dev_private;
  5053. connector = drm_select_eld(encoder, mode);
  5054. if (!connector)
  5055. return;
  5056. DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  5057. connector->base.id,
  5058. drm_get_connector_name(connector),
  5059. connector->encoder->base.id,
  5060. drm_get_encoder_name(connector->encoder));
  5061. connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
  5062. if (dev_priv->display.write_eld)
  5063. dev_priv->display.write_eld(connector, crtc);
  5064. }
  5065. /** Loads the palette/gamma unit for the CRTC with the prepared values */
  5066. void intel_crtc_load_lut(struct drm_crtc *crtc)
  5067. {
  5068. struct drm_device *dev = crtc->dev;
  5069. struct drm_i915_private *dev_priv = dev->dev_private;
  5070. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5071. int palreg = PALETTE(intel_crtc->pipe);
  5072. int i;
  5073. /* The clocks have to be on to load the palette. */
  5074. if (!crtc->enabled || !intel_crtc->active)
  5075. return;
  5076. /* use legacy palette for Ironlake */
  5077. if (HAS_PCH_SPLIT(dev))
  5078. palreg = LGC_PALETTE(intel_crtc->pipe);
  5079. for (i = 0; i < 256; i++) {
  5080. I915_WRITE(palreg + 4 * i,
  5081. (intel_crtc->lut_r[i] << 16) |
  5082. (intel_crtc->lut_g[i] << 8) |
  5083. intel_crtc->lut_b[i]);
  5084. }
  5085. }
  5086. static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
  5087. {
  5088. struct drm_device *dev = crtc->dev;
  5089. struct drm_i915_private *dev_priv = dev->dev_private;
  5090. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5091. bool visible = base != 0;
  5092. u32 cntl;
  5093. if (intel_crtc->cursor_visible == visible)
  5094. return;
  5095. cntl = I915_READ(_CURACNTR);
  5096. if (visible) {
  5097. /* On these chipsets we can only modify the base whilst
  5098. * the cursor is disabled.
  5099. */
  5100. I915_WRITE(_CURABASE, base);
  5101. cntl &= ~(CURSOR_FORMAT_MASK);
  5102. /* XXX width must be 64, stride 256 => 0x00 << 28 */
  5103. cntl |= CURSOR_ENABLE |
  5104. CURSOR_GAMMA_ENABLE |
  5105. CURSOR_FORMAT_ARGB;
  5106. } else
  5107. cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
  5108. I915_WRITE(_CURACNTR, cntl);
  5109. intel_crtc->cursor_visible = visible;
  5110. }
  5111. static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
  5112. {
  5113. struct drm_device *dev = crtc->dev;
  5114. struct drm_i915_private *dev_priv = dev->dev_private;
  5115. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5116. int pipe = intel_crtc->pipe;
  5117. bool visible = base != 0;
  5118. if (intel_crtc->cursor_visible != visible) {
  5119. uint32_t cntl = I915_READ(CURCNTR(pipe));
  5120. if (base) {
  5121. cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
  5122. cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  5123. cntl |= pipe << 28; /* Connect to correct pipe */
  5124. } else {
  5125. cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  5126. cntl |= CURSOR_MODE_DISABLE;
  5127. }
  5128. I915_WRITE(CURCNTR(pipe), cntl);
  5129. intel_crtc->cursor_visible = visible;
  5130. }
  5131. /* and commit changes on next vblank */
  5132. I915_WRITE(CURBASE(pipe), base);
  5133. }
  5134. static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
  5135. {
  5136. struct drm_device *dev = crtc->dev;
  5137. struct drm_i915_private *dev_priv = dev->dev_private;
  5138. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5139. int pipe = intel_crtc->pipe;
  5140. bool visible = base != 0;
  5141. if (intel_crtc->cursor_visible != visible) {
  5142. uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
  5143. if (base) {
  5144. cntl &= ~CURSOR_MODE;
  5145. cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  5146. } else {
  5147. cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  5148. cntl |= CURSOR_MODE_DISABLE;
  5149. }
  5150. I915_WRITE(CURCNTR_IVB(pipe), cntl);
  5151. intel_crtc->cursor_visible = visible;
  5152. }
  5153. /* and commit changes on next vblank */
  5154. I915_WRITE(CURBASE_IVB(pipe), base);
  5155. }
  5156. /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
  5157. static void intel_crtc_update_cursor(struct drm_crtc *crtc,
  5158. bool on)
  5159. {
  5160. struct drm_device *dev = crtc->dev;
  5161. struct drm_i915_private *dev_priv = dev->dev_private;
  5162. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5163. int pipe = intel_crtc->pipe;
  5164. int x = intel_crtc->cursor_x;
  5165. int y = intel_crtc->cursor_y;
  5166. u32 base, pos;
  5167. bool visible;
  5168. pos = 0;
  5169. if (on && crtc->enabled && crtc->fb) {
  5170. base = intel_crtc->cursor_addr;
  5171. if (x > (int) crtc->fb->width)
  5172. base = 0;
  5173. if (y > (int) crtc->fb->height)
  5174. base = 0;
  5175. } else
  5176. base = 0;
  5177. if (x < 0) {
  5178. if (x + intel_crtc->cursor_width < 0)
  5179. base = 0;
  5180. pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
  5181. x = -x;
  5182. }
  5183. pos |= x << CURSOR_X_SHIFT;
  5184. if (y < 0) {
  5185. if (y + intel_crtc->cursor_height < 0)
  5186. base = 0;
  5187. pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
  5188. y = -y;
  5189. }
  5190. pos |= y << CURSOR_Y_SHIFT;
  5191. visible = base != 0;
  5192. if (!visible && !intel_crtc->cursor_visible)
  5193. return;
  5194. if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
  5195. I915_WRITE(CURPOS_IVB(pipe), pos);
  5196. ivb_update_cursor(crtc, base);
  5197. } else {
  5198. I915_WRITE(CURPOS(pipe), pos);
  5199. if (IS_845G(dev) || IS_I865G(dev))
  5200. i845_update_cursor(crtc, base);
  5201. else
  5202. i9xx_update_cursor(crtc, base);
  5203. }
  5204. }
  5205. static int intel_crtc_cursor_set(struct drm_crtc *crtc,
  5206. struct drm_file *file,
  5207. uint32_t handle,
  5208. uint32_t width, uint32_t height)
  5209. {
  5210. struct drm_device *dev = crtc->dev;
  5211. struct drm_i915_private *dev_priv = dev->dev_private;
  5212. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5213. struct drm_i915_gem_object *obj;
  5214. uint32_t addr;
  5215. int ret;
  5216. /* if we want to turn off the cursor ignore width and height */
  5217. if (!handle) {
  5218. DRM_DEBUG_KMS("cursor off\n");
  5219. addr = 0;
  5220. obj = NULL;
  5221. mutex_lock(&dev->struct_mutex);
  5222. goto finish;
  5223. }
  5224. /* Currently we only support 64x64 cursors */
  5225. if (width != 64 || height != 64) {
  5226. DRM_ERROR("we currently only support 64x64 cursors\n");
  5227. return -EINVAL;
  5228. }
  5229. obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
  5230. if (&obj->base == NULL)
  5231. return -ENOENT;
  5232. if (obj->base.size < width * height * 4) {
  5233. DRM_ERROR("buffer is to small\n");
  5234. ret = -ENOMEM;
  5235. goto fail;
  5236. }
  5237. /* we only need to pin inside GTT if cursor is non-phy */
  5238. mutex_lock(&dev->struct_mutex);
  5239. if (!dev_priv->info->cursor_needs_physical) {
  5240. if (obj->tiling_mode) {
  5241. DRM_ERROR("cursor cannot be tiled\n");
  5242. ret = -EINVAL;
  5243. goto fail_locked;
  5244. }
  5245. ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
  5246. if (ret) {
  5247. DRM_ERROR("failed to move cursor bo into the GTT\n");
  5248. goto fail_locked;
  5249. }
  5250. ret = i915_gem_object_put_fence(obj);
  5251. if (ret) {
  5252. DRM_ERROR("failed to release fence for cursor");
  5253. goto fail_unpin;
  5254. }
  5255. addr = obj->gtt_offset;
  5256. } else {
  5257. int align = IS_I830(dev) ? 16 * 1024 : 256;
  5258. ret = i915_gem_attach_phys_object(dev, obj,
  5259. (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
  5260. align);
  5261. if (ret) {
  5262. DRM_ERROR("failed to attach phys object\n");
  5263. goto fail_locked;
  5264. }
  5265. addr = obj->phys_obj->handle->busaddr;
  5266. }
  5267. if (IS_GEN2(dev))
  5268. I915_WRITE(CURSIZE, (height << 12) | width);
  5269. finish:
  5270. if (intel_crtc->cursor_bo) {
  5271. if (dev_priv->info->cursor_needs_physical) {
  5272. if (intel_crtc->cursor_bo != obj)
  5273. i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
  5274. } else
  5275. i915_gem_object_unpin(intel_crtc->cursor_bo);
  5276. drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
  5277. }
  5278. mutex_unlock(&dev->struct_mutex);
  5279. intel_crtc->cursor_addr = addr;
  5280. intel_crtc->cursor_bo = obj;
  5281. intel_crtc->cursor_width = width;
  5282. intel_crtc->cursor_height = height;
  5283. intel_crtc_update_cursor(crtc, true);
  5284. return 0;
  5285. fail_unpin:
  5286. i915_gem_object_unpin(obj);
  5287. fail_locked:
  5288. mutex_unlock(&dev->struct_mutex);
  5289. fail:
  5290. drm_gem_object_unreference_unlocked(&obj->base);
  5291. return ret;
  5292. }
  5293. static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  5294. {
  5295. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5296. intel_crtc->cursor_x = x;
  5297. intel_crtc->cursor_y = y;
  5298. intel_crtc_update_cursor(crtc, true);
  5299. return 0;
  5300. }
  5301. /** Sets the color ramps on behalf of RandR */
  5302. void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  5303. u16 blue, int regno)
  5304. {
  5305. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5306. intel_crtc->lut_r[regno] = red >> 8;
  5307. intel_crtc->lut_g[regno] = green >> 8;
  5308. intel_crtc->lut_b[regno] = blue >> 8;
  5309. }
  5310. void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  5311. u16 *blue, int regno)
  5312. {
  5313. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5314. *red = intel_crtc->lut_r[regno] << 8;
  5315. *green = intel_crtc->lut_g[regno] << 8;
  5316. *blue = intel_crtc->lut_b[regno] << 8;
  5317. }
  5318. static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  5319. u16 *blue, uint32_t start, uint32_t size)
  5320. {
  5321. int end = (start + size > 256) ? 256 : start + size, i;
  5322. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5323. for (i = start; i < end; i++) {
  5324. intel_crtc->lut_r[i] = red[i] >> 8;
  5325. intel_crtc->lut_g[i] = green[i] >> 8;
  5326. intel_crtc->lut_b[i] = blue[i] >> 8;
  5327. }
  5328. intel_crtc_load_lut(crtc);
  5329. }
  5330. /**
  5331. * Get a pipe with a simple mode set on it for doing load-based monitor
  5332. * detection.
  5333. *
  5334. * It will be up to the load-detect code to adjust the pipe as appropriate for
  5335. * its requirements. The pipe will be connected to no other encoders.
  5336. *
  5337. * Currently this code will only succeed if there is a pipe with no encoders
  5338. * configured for it. In the future, it could choose to temporarily disable
  5339. * some outputs to free up a pipe for its use.
  5340. *
  5341. * \return crtc, or NULL if no pipes are available.
  5342. */
  5343. /* VESA 640x480x72Hz mode to set on the pipe */
  5344. static struct drm_display_mode load_detect_mode = {
  5345. DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
  5346. 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  5347. };
  5348. static struct drm_framebuffer *
  5349. intel_framebuffer_create(struct drm_device *dev,
  5350. struct drm_mode_fb_cmd2 *mode_cmd,
  5351. struct drm_i915_gem_object *obj)
  5352. {
  5353. struct intel_framebuffer *intel_fb;
  5354. int ret;
  5355. intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  5356. if (!intel_fb) {
  5357. drm_gem_object_unreference_unlocked(&obj->base);
  5358. return ERR_PTR(-ENOMEM);
  5359. }
  5360. ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
  5361. if (ret) {
  5362. drm_gem_object_unreference_unlocked(&obj->base);
  5363. kfree(intel_fb);
  5364. return ERR_PTR(ret);
  5365. }
  5366. return &intel_fb->base;
  5367. }
  5368. static u32
  5369. intel_framebuffer_pitch_for_width(int width, int bpp)
  5370. {
  5371. u32 pitch = DIV_ROUND_UP(width * bpp, 8);
  5372. return ALIGN(pitch, 64);
  5373. }
  5374. static u32
  5375. intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
  5376. {
  5377. u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
  5378. return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
  5379. }
  5380. static struct drm_framebuffer *
  5381. intel_framebuffer_create_for_mode(struct drm_device *dev,
  5382. struct drm_display_mode *mode,
  5383. int depth, int bpp)
  5384. {
  5385. struct drm_i915_gem_object *obj;
  5386. struct drm_mode_fb_cmd2 mode_cmd = { 0 };
  5387. obj = i915_gem_alloc_object(dev,
  5388. intel_framebuffer_size_for_mode(mode, bpp));
  5389. if (obj == NULL)
  5390. return ERR_PTR(-ENOMEM);
  5391. mode_cmd.width = mode->hdisplay;
  5392. mode_cmd.height = mode->vdisplay;
  5393. mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
  5394. bpp);
  5395. mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
  5396. return intel_framebuffer_create(dev, &mode_cmd, obj);
  5397. }
  5398. static struct drm_framebuffer *
  5399. mode_fits_in_fbdev(struct drm_device *dev,
  5400. struct drm_display_mode *mode)
  5401. {
  5402. struct drm_i915_private *dev_priv = dev->dev_private;
  5403. struct drm_i915_gem_object *obj;
  5404. struct drm_framebuffer *fb;
  5405. if (dev_priv->fbdev == NULL)
  5406. return NULL;
  5407. obj = dev_priv->fbdev->ifb.obj;
  5408. if (obj == NULL)
  5409. return NULL;
  5410. fb = &dev_priv->fbdev->ifb.base;
  5411. if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
  5412. fb->bits_per_pixel))
  5413. return NULL;
  5414. if (obj->base.size < mode->vdisplay * fb->pitches[0])
  5415. return NULL;
  5416. return fb;
  5417. }
  5418. bool intel_get_load_detect_pipe(struct drm_connector *connector,
  5419. struct drm_display_mode *mode,
  5420. struct intel_load_detect_pipe *old)
  5421. {
  5422. struct intel_crtc *intel_crtc;
  5423. struct intel_encoder *intel_encoder =
  5424. intel_attached_encoder(connector);
  5425. struct drm_crtc *possible_crtc;
  5426. struct drm_encoder *encoder = &intel_encoder->base;
  5427. struct drm_crtc *crtc = NULL;
  5428. struct drm_device *dev = encoder->dev;
  5429. struct drm_framebuffer *fb;
  5430. int i = -1;
  5431. DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  5432. connector->base.id, drm_get_connector_name(connector),
  5433. encoder->base.id, drm_get_encoder_name(encoder));
  5434. /*
  5435. * Algorithm gets a little messy:
  5436. *
  5437. * - if the connector already has an assigned crtc, use it (but make
  5438. * sure it's on first)
  5439. *
  5440. * - try to find the first unused crtc that can drive this connector,
  5441. * and use that if we find one
  5442. */
  5443. /* See if we already have a CRTC for this connector */
  5444. if (encoder->crtc) {
  5445. crtc = encoder->crtc;
  5446. old->dpms_mode = connector->dpms;
  5447. old->load_detect_temp = false;
  5448. /* Make sure the crtc and connector are running */
  5449. if (connector->dpms != DRM_MODE_DPMS_ON)
  5450. connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
  5451. return true;
  5452. }
  5453. /* Find an unused one (if possible) */
  5454. list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
  5455. i++;
  5456. if (!(encoder->possible_crtcs & (1 << i)))
  5457. continue;
  5458. if (!possible_crtc->enabled) {
  5459. crtc = possible_crtc;
  5460. break;
  5461. }
  5462. }
  5463. /*
  5464. * If we didn't find an unused CRTC, don't use any.
  5465. */
  5466. if (!crtc) {
  5467. DRM_DEBUG_KMS("no pipe available for load-detect\n");
  5468. return false;
  5469. }
  5470. intel_encoder->new_crtc = to_intel_crtc(crtc);
  5471. to_intel_connector(connector)->new_encoder = intel_encoder;
  5472. intel_crtc = to_intel_crtc(crtc);
  5473. old->dpms_mode = connector->dpms;
  5474. old->load_detect_temp = true;
  5475. old->release_fb = NULL;
  5476. if (!mode)
  5477. mode = &load_detect_mode;
  5478. /* We need a framebuffer large enough to accommodate all accesses
  5479. * that the plane may generate whilst we perform load detection.
  5480. * We can not rely on the fbcon either being present (we get called
  5481. * during its initialisation to detect all boot displays, or it may
  5482. * not even exist) or that it is large enough to satisfy the
  5483. * requested mode.
  5484. */
  5485. fb = mode_fits_in_fbdev(dev, mode);
  5486. if (fb == NULL) {
  5487. DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
  5488. fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
  5489. old->release_fb = fb;
  5490. } else
  5491. DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
  5492. if (IS_ERR(fb)) {
  5493. DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
  5494. return false;
  5495. }
  5496. if (intel_set_mode(crtc, mode, 0, 0, fb)) {
  5497. DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
  5498. if (old->release_fb)
  5499. old->release_fb->funcs->destroy(old->release_fb);
  5500. return false;
  5501. }
  5502. /* let the connector get through one full cycle before testing */
  5503. intel_wait_for_vblank(dev, intel_crtc->pipe);
  5504. return true;
  5505. }
  5506. void intel_release_load_detect_pipe(struct drm_connector *connector,
  5507. struct intel_load_detect_pipe *old)
  5508. {
  5509. struct intel_encoder *intel_encoder =
  5510. intel_attached_encoder(connector);
  5511. struct drm_encoder *encoder = &intel_encoder->base;
  5512. DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  5513. connector->base.id, drm_get_connector_name(connector),
  5514. encoder->base.id, drm_get_encoder_name(encoder));
  5515. if (old->load_detect_temp) {
  5516. struct drm_crtc *crtc = encoder->crtc;
  5517. to_intel_connector(connector)->new_encoder = NULL;
  5518. intel_encoder->new_crtc = NULL;
  5519. intel_set_mode(crtc, NULL, 0, 0, NULL);
  5520. if (old->release_fb)
  5521. old->release_fb->funcs->destroy(old->release_fb);
  5522. return;
  5523. }
  5524. /* Switch crtc and encoder back off if necessary */
  5525. if (old->dpms_mode != DRM_MODE_DPMS_ON)
  5526. connector->funcs->dpms(connector, old->dpms_mode);
  5527. }
  5528. /* Returns the clock of the currently programmed mode of the given pipe. */
  5529. static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
  5530. {
  5531. struct drm_i915_private *dev_priv = dev->dev_private;
  5532. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5533. int pipe = intel_crtc->pipe;
  5534. u32 dpll = I915_READ(DPLL(pipe));
  5535. u32 fp;
  5536. intel_clock_t clock;
  5537. if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  5538. fp = I915_READ(FP0(pipe));
  5539. else
  5540. fp = I915_READ(FP1(pipe));
  5541. clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
  5542. if (IS_PINEVIEW(dev)) {
  5543. clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
  5544. clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
  5545. } else {
  5546. clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
  5547. clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
  5548. }
  5549. if (!IS_GEN2(dev)) {
  5550. if (IS_PINEVIEW(dev))
  5551. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
  5552. DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
  5553. else
  5554. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
  5555. DPLL_FPA01_P1_POST_DIV_SHIFT);
  5556. switch (dpll & DPLL_MODE_MASK) {
  5557. case DPLLB_MODE_DAC_SERIAL:
  5558. clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
  5559. 5 : 10;
  5560. break;
  5561. case DPLLB_MODE_LVDS:
  5562. clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
  5563. 7 : 14;
  5564. break;
  5565. default:
  5566. DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
  5567. "mode\n", (int)(dpll & DPLL_MODE_MASK));
  5568. return 0;
  5569. }
  5570. /* XXX: Handle the 100Mhz refclk */
  5571. intel_clock(dev, 96000, &clock);
  5572. } else {
  5573. bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
  5574. if (is_lvds) {
  5575. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
  5576. DPLL_FPA01_P1_POST_DIV_SHIFT);
  5577. clock.p2 = 14;
  5578. if ((dpll & PLL_REF_INPUT_MASK) ==
  5579. PLLB_REF_INPUT_SPREADSPECTRUMIN) {
  5580. /* XXX: might not be 66MHz */
  5581. intel_clock(dev, 66000, &clock);
  5582. } else
  5583. intel_clock(dev, 48000, &clock);
  5584. } else {
  5585. if (dpll & PLL_P1_DIVIDE_BY_TWO)
  5586. clock.p1 = 2;
  5587. else {
  5588. clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
  5589. DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
  5590. }
  5591. if (dpll & PLL_P2_DIVIDE_BY_4)
  5592. clock.p2 = 4;
  5593. else
  5594. clock.p2 = 2;
  5595. intel_clock(dev, 48000, &clock);
  5596. }
  5597. }
  5598. /* XXX: It would be nice to validate the clocks, but we can't reuse
  5599. * i830PllIsValid() because it relies on the xf86_config connector
  5600. * configuration being accurate, which it isn't necessarily.
  5601. */
  5602. return clock.dot;
  5603. }
  5604. /** Returns the currently programmed mode of the given pipe. */
  5605. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  5606. struct drm_crtc *crtc)
  5607. {
  5608. struct drm_i915_private *dev_priv = dev->dev_private;
  5609. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5610. enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
  5611. struct drm_display_mode *mode;
  5612. int htot = I915_READ(HTOTAL(cpu_transcoder));
  5613. int hsync = I915_READ(HSYNC(cpu_transcoder));
  5614. int vtot = I915_READ(VTOTAL(cpu_transcoder));
  5615. int vsync = I915_READ(VSYNC(cpu_transcoder));
  5616. mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  5617. if (!mode)
  5618. return NULL;
  5619. mode->clock = intel_crtc_clock_get(dev, crtc);
  5620. mode->hdisplay = (htot & 0xffff) + 1;
  5621. mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
  5622. mode->hsync_start = (hsync & 0xffff) + 1;
  5623. mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
  5624. mode->vdisplay = (vtot & 0xffff) + 1;
  5625. mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
  5626. mode->vsync_start = (vsync & 0xffff) + 1;
  5627. mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
  5628. drm_mode_set_name(mode);
  5629. return mode;
  5630. }
  5631. static void intel_increase_pllclock(struct drm_crtc *crtc)
  5632. {
  5633. struct drm_device *dev = crtc->dev;
  5634. drm_i915_private_t *dev_priv = dev->dev_private;
  5635. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5636. int pipe = intel_crtc->pipe;
  5637. int dpll_reg = DPLL(pipe);
  5638. int dpll;
  5639. if (HAS_PCH_SPLIT(dev))
  5640. return;
  5641. if (!dev_priv->lvds_downclock_avail)
  5642. return;
  5643. dpll = I915_READ(dpll_reg);
  5644. if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
  5645. DRM_DEBUG_DRIVER("upclocking LVDS\n");
  5646. assert_panel_unlocked(dev_priv, pipe);
  5647. dpll &= ~DISPLAY_RATE_SELECT_FPA1;
  5648. I915_WRITE(dpll_reg, dpll);
  5649. intel_wait_for_vblank(dev, pipe);
  5650. dpll = I915_READ(dpll_reg);
  5651. if (dpll & DISPLAY_RATE_SELECT_FPA1)
  5652. DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
  5653. }
  5654. }
  5655. static void intel_decrease_pllclock(struct drm_crtc *crtc)
  5656. {
  5657. struct drm_device *dev = crtc->dev;
  5658. drm_i915_private_t *dev_priv = dev->dev_private;
  5659. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5660. if (HAS_PCH_SPLIT(dev))
  5661. return;
  5662. if (!dev_priv->lvds_downclock_avail)
  5663. return;
  5664. /*
  5665. * Since this is called by a timer, we should never get here in
  5666. * the manual case.
  5667. */
  5668. if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
  5669. int pipe = intel_crtc->pipe;
  5670. int dpll_reg = DPLL(pipe);
  5671. int dpll;
  5672. DRM_DEBUG_DRIVER("downclocking LVDS\n");
  5673. assert_panel_unlocked(dev_priv, pipe);
  5674. dpll = I915_READ(dpll_reg);
  5675. dpll |= DISPLAY_RATE_SELECT_FPA1;
  5676. I915_WRITE(dpll_reg, dpll);
  5677. intel_wait_for_vblank(dev, pipe);
  5678. dpll = I915_READ(dpll_reg);
  5679. if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
  5680. DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
  5681. }
  5682. }
  5683. void intel_mark_busy(struct drm_device *dev)
  5684. {
  5685. i915_update_gfx_val(dev->dev_private);
  5686. }
  5687. void intel_mark_idle(struct drm_device *dev)
  5688. {
  5689. }
  5690. void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
  5691. {
  5692. struct drm_device *dev = obj->base.dev;
  5693. struct drm_crtc *crtc;
  5694. if (!i915_powersave)
  5695. return;
  5696. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  5697. if (!crtc->fb)
  5698. continue;
  5699. if (to_intel_framebuffer(crtc->fb)->obj == obj)
  5700. intel_increase_pllclock(crtc);
  5701. }
  5702. }
  5703. void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
  5704. {
  5705. struct drm_device *dev = obj->base.dev;
  5706. struct drm_crtc *crtc;
  5707. if (!i915_powersave)
  5708. return;
  5709. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  5710. if (!crtc->fb)
  5711. continue;
  5712. if (to_intel_framebuffer(crtc->fb)->obj == obj)
  5713. intel_decrease_pllclock(crtc);
  5714. }
  5715. }
  5716. static void intel_crtc_destroy(struct drm_crtc *crtc)
  5717. {
  5718. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5719. struct drm_device *dev = crtc->dev;
  5720. struct intel_unpin_work *work;
  5721. unsigned long flags;
  5722. spin_lock_irqsave(&dev->event_lock, flags);
  5723. work = intel_crtc->unpin_work;
  5724. intel_crtc->unpin_work = NULL;
  5725. spin_unlock_irqrestore(&dev->event_lock, flags);
  5726. if (work) {
  5727. cancel_work_sync(&work->work);
  5728. kfree(work);
  5729. }
  5730. drm_crtc_cleanup(crtc);
  5731. kfree(intel_crtc);
  5732. }
  5733. static void intel_unpin_work_fn(struct work_struct *__work)
  5734. {
  5735. struct intel_unpin_work *work =
  5736. container_of(__work, struct intel_unpin_work, work);
  5737. struct drm_device *dev = work->crtc->dev;
  5738. mutex_lock(&dev->struct_mutex);
  5739. intel_unpin_fb_obj(work->old_fb_obj);
  5740. drm_gem_object_unreference(&work->pending_flip_obj->base);
  5741. drm_gem_object_unreference(&work->old_fb_obj->base);
  5742. intel_update_fbc(dev);
  5743. mutex_unlock(&dev->struct_mutex);
  5744. BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
  5745. atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
  5746. kfree(work);
  5747. }
  5748. static void do_intel_finish_page_flip(struct drm_device *dev,
  5749. struct drm_crtc *crtc)
  5750. {
  5751. drm_i915_private_t *dev_priv = dev->dev_private;
  5752. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5753. struct intel_unpin_work *work;
  5754. struct drm_i915_gem_object *obj;
  5755. unsigned long flags;
  5756. /* Ignore early vblank irqs */
  5757. if (intel_crtc == NULL)
  5758. return;
  5759. spin_lock_irqsave(&dev->event_lock, flags);
  5760. work = intel_crtc->unpin_work;
  5761. /* Ensure we don't miss a work->pending update ... */
  5762. smp_rmb();
  5763. if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
  5764. spin_unlock_irqrestore(&dev->event_lock, flags);
  5765. return;
  5766. }
  5767. /* and that the unpin work is consistent wrt ->pending. */
  5768. smp_rmb();
  5769. intel_crtc->unpin_work = NULL;
  5770. if (work->event)
  5771. drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
  5772. drm_vblank_put(dev, intel_crtc->pipe);
  5773. spin_unlock_irqrestore(&dev->event_lock, flags);
  5774. obj = work->old_fb_obj;
  5775. wake_up_all(&dev_priv->pending_flip_queue);
  5776. queue_work(dev_priv->wq, &work->work);
  5777. trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
  5778. }
  5779. void intel_finish_page_flip(struct drm_device *dev, int pipe)
  5780. {
  5781. drm_i915_private_t *dev_priv = dev->dev_private;
  5782. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  5783. do_intel_finish_page_flip(dev, crtc);
  5784. }
  5785. void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
  5786. {
  5787. drm_i915_private_t *dev_priv = dev->dev_private;
  5788. struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
  5789. do_intel_finish_page_flip(dev, crtc);
  5790. }
  5791. void intel_prepare_page_flip(struct drm_device *dev, int plane)
  5792. {
  5793. drm_i915_private_t *dev_priv = dev->dev_private;
  5794. struct intel_crtc *intel_crtc =
  5795. to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
  5796. unsigned long flags;
  5797. /* NB: An MMIO update of the plane base pointer will also
  5798. * generate a page-flip completion irq, i.e. every modeset
  5799. * is also accompanied by a spurious intel_prepare_page_flip().
  5800. */
  5801. spin_lock_irqsave(&dev->event_lock, flags);
  5802. if (intel_crtc->unpin_work)
  5803. atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
  5804. spin_unlock_irqrestore(&dev->event_lock, flags);
  5805. }
  5806. inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
  5807. {
  5808. /* Ensure that the work item is consistent when activating it ... */
  5809. smp_wmb();
  5810. atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
  5811. /* and that it is marked active as soon as the irq could fire. */
  5812. smp_wmb();
  5813. }
  5814. static int intel_gen2_queue_flip(struct drm_device *dev,
  5815. struct drm_crtc *crtc,
  5816. struct drm_framebuffer *fb,
  5817. struct drm_i915_gem_object *obj)
  5818. {
  5819. struct drm_i915_private *dev_priv = dev->dev_private;
  5820. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5821. u32 flip_mask;
  5822. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  5823. int ret;
  5824. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  5825. if (ret)
  5826. goto err;
  5827. ret = intel_ring_begin(ring, 6);
  5828. if (ret)
  5829. goto err_unpin;
  5830. /* Can't queue multiple flips, so wait for the previous
  5831. * one to finish before executing the next.
  5832. */
  5833. if (intel_crtc->plane)
  5834. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  5835. else
  5836. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  5837. intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
  5838. intel_ring_emit(ring, MI_NOOP);
  5839. intel_ring_emit(ring, MI_DISPLAY_FLIP |
  5840. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  5841. intel_ring_emit(ring, fb->pitches[0]);
  5842. intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
  5843. intel_ring_emit(ring, 0); /* aux display base address, unused */
  5844. intel_mark_page_flip_active(intel_crtc);
  5845. intel_ring_advance(ring);
  5846. return 0;
  5847. err_unpin:
  5848. intel_unpin_fb_obj(obj);
  5849. err:
  5850. return ret;
  5851. }
  5852. static int intel_gen3_queue_flip(struct drm_device *dev,
  5853. struct drm_crtc *crtc,
  5854. struct drm_framebuffer *fb,
  5855. struct drm_i915_gem_object *obj)
  5856. {
  5857. struct drm_i915_private *dev_priv = dev->dev_private;
  5858. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5859. u32 flip_mask;
  5860. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  5861. int ret;
  5862. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  5863. if (ret)
  5864. goto err;
  5865. ret = intel_ring_begin(ring, 6);
  5866. if (ret)
  5867. goto err_unpin;
  5868. if (intel_crtc->plane)
  5869. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  5870. else
  5871. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  5872. intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
  5873. intel_ring_emit(ring, MI_NOOP);
  5874. intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
  5875. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  5876. intel_ring_emit(ring, fb->pitches[0]);
  5877. intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
  5878. intel_ring_emit(ring, MI_NOOP);
  5879. intel_mark_page_flip_active(intel_crtc);
  5880. intel_ring_advance(ring);
  5881. return 0;
  5882. err_unpin:
  5883. intel_unpin_fb_obj(obj);
  5884. err:
  5885. return ret;
  5886. }
  5887. static int intel_gen4_queue_flip(struct drm_device *dev,
  5888. struct drm_crtc *crtc,
  5889. struct drm_framebuffer *fb,
  5890. struct drm_i915_gem_object *obj)
  5891. {
  5892. struct drm_i915_private *dev_priv = dev->dev_private;
  5893. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5894. uint32_t pf, pipesrc;
  5895. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  5896. int ret;
  5897. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  5898. if (ret)
  5899. goto err;
  5900. ret = intel_ring_begin(ring, 4);
  5901. if (ret)
  5902. goto err_unpin;
  5903. /* i965+ uses the linear or tiled offsets from the
  5904. * Display Registers (which do not change across a page-flip)
  5905. * so we need only reprogram the base address.
  5906. */
  5907. intel_ring_emit(ring, MI_DISPLAY_FLIP |
  5908. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  5909. intel_ring_emit(ring, fb->pitches[0]);
  5910. intel_ring_emit(ring,
  5911. (obj->gtt_offset + intel_crtc->dspaddr_offset) |
  5912. obj->tiling_mode);
  5913. /* XXX Enabling the panel-fitter across page-flip is so far
  5914. * untested on non-native modes, so ignore it for now.
  5915. * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
  5916. */
  5917. pf = 0;
  5918. pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  5919. intel_ring_emit(ring, pf | pipesrc);
  5920. intel_mark_page_flip_active(intel_crtc);
  5921. intel_ring_advance(ring);
  5922. return 0;
  5923. err_unpin:
  5924. intel_unpin_fb_obj(obj);
  5925. err:
  5926. return ret;
  5927. }
  5928. static int intel_gen6_queue_flip(struct drm_device *dev,
  5929. struct drm_crtc *crtc,
  5930. struct drm_framebuffer *fb,
  5931. struct drm_i915_gem_object *obj)
  5932. {
  5933. struct drm_i915_private *dev_priv = dev->dev_private;
  5934. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5935. struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
  5936. uint32_t pf, pipesrc;
  5937. int ret;
  5938. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  5939. if (ret)
  5940. goto err;
  5941. ret = intel_ring_begin(ring, 4);
  5942. if (ret)
  5943. goto err_unpin;
  5944. intel_ring_emit(ring, MI_DISPLAY_FLIP |
  5945. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  5946. intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
  5947. intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
  5948. /* Contrary to the suggestions in the documentation,
  5949. * "Enable Panel Fitter" does not seem to be required when page
  5950. * flipping with a non-native mode, and worse causes a normal
  5951. * modeset to fail.
  5952. * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
  5953. */
  5954. pf = 0;
  5955. pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  5956. intel_ring_emit(ring, pf | pipesrc);
  5957. intel_mark_page_flip_active(intel_crtc);
  5958. intel_ring_advance(ring);
  5959. return 0;
  5960. err_unpin:
  5961. intel_unpin_fb_obj(obj);
  5962. err:
  5963. return ret;
  5964. }
  5965. /*
  5966. * On gen7 we currently use the blit ring because (in early silicon at least)
  5967. * the render ring doesn't give us interrpts for page flip completion, which
  5968. * means clients will hang after the first flip is queued. Fortunately the
  5969. * blit ring generates interrupts properly, so use it instead.
  5970. */
  5971. static int intel_gen7_queue_flip(struct drm_device *dev,
  5972. struct drm_crtc *crtc,
  5973. struct drm_framebuffer *fb,
  5974. struct drm_i915_gem_object *obj)
  5975. {
  5976. struct drm_i915_private *dev_priv = dev->dev_private;
  5977. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5978. struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
  5979. uint32_t plane_bit = 0;
  5980. int ret;
  5981. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  5982. if (ret)
  5983. goto err;
  5984. switch(intel_crtc->plane) {
  5985. case PLANE_A:
  5986. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
  5987. break;
  5988. case PLANE_B:
  5989. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
  5990. break;
  5991. case PLANE_C:
  5992. plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
  5993. break;
  5994. default:
  5995. WARN_ONCE(1, "unknown plane in flip command\n");
  5996. ret = -ENODEV;
  5997. goto err_unpin;
  5998. }
  5999. ret = intel_ring_begin(ring, 4);
  6000. if (ret)
  6001. goto err_unpin;
  6002. intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
  6003. intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
  6004. intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
  6005. intel_ring_emit(ring, (MI_NOOP));
  6006. intel_mark_page_flip_active(intel_crtc);
  6007. intel_ring_advance(ring);
  6008. return 0;
  6009. err_unpin:
  6010. intel_unpin_fb_obj(obj);
  6011. err:
  6012. return ret;
  6013. }
  6014. static int intel_default_queue_flip(struct drm_device *dev,
  6015. struct drm_crtc *crtc,
  6016. struct drm_framebuffer *fb,
  6017. struct drm_i915_gem_object *obj)
  6018. {
  6019. return -ENODEV;
  6020. }
  6021. static int intel_crtc_page_flip(struct drm_crtc *crtc,
  6022. struct drm_framebuffer *fb,
  6023. struct drm_pending_vblank_event *event)
  6024. {
  6025. struct drm_device *dev = crtc->dev;
  6026. struct drm_i915_private *dev_priv = dev->dev_private;
  6027. struct intel_framebuffer *intel_fb;
  6028. struct drm_i915_gem_object *obj;
  6029. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6030. struct intel_unpin_work *work;
  6031. unsigned long flags;
  6032. int ret;
  6033. /* Can't change pixel format via MI display flips. */
  6034. if (fb->pixel_format != crtc->fb->pixel_format)
  6035. return -EINVAL;
  6036. /*
  6037. * TILEOFF/LINOFF registers can't be changed via MI display flips.
  6038. * Note that pitch changes could also affect these register.
  6039. */
  6040. if (INTEL_INFO(dev)->gen > 3 &&
  6041. (fb->offsets[0] != crtc->fb->offsets[0] ||
  6042. fb->pitches[0] != crtc->fb->pitches[0]))
  6043. return -EINVAL;
  6044. work = kzalloc(sizeof *work, GFP_KERNEL);
  6045. if (work == NULL)
  6046. return -ENOMEM;
  6047. work->event = event;
  6048. work->crtc = crtc;
  6049. intel_fb = to_intel_framebuffer(crtc->fb);
  6050. work->old_fb_obj = intel_fb->obj;
  6051. INIT_WORK(&work->work, intel_unpin_work_fn);
  6052. ret = drm_vblank_get(dev, intel_crtc->pipe);
  6053. if (ret)
  6054. goto free_work;
  6055. /* We borrow the event spin lock for protecting unpin_work */
  6056. spin_lock_irqsave(&dev->event_lock, flags);
  6057. if (intel_crtc->unpin_work) {
  6058. spin_unlock_irqrestore(&dev->event_lock, flags);
  6059. kfree(work);
  6060. drm_vblank_put(dev, intel_crtc->pipe);
  6061. DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
  6062. return -EBUSY;
  6063. }
  6064. intel_crtc->unpin_work = work;
  6065. spin_unlock_irqrestore(&dev->event_lock, flags);
  6066. intel_fb = to_intel_framebuffer(fb);
  6067. obj = intel_fb->obj;
  6068. if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
  6069. flush_workqueue(dev_priv->wq);
  6070. ret = i915_mutex_lock_interruptible(dev);
  6071. if (ret)
  6072. goto cleanup;
  6073. /* Reference the objects for the scheduled work. */
  6074. drm_gem_object_reference(&work->old_fb_obj->base);
  6075. drm_gem_object_reference(&obj->base);
  6076. crtc->fb = fb;
  6077. work->pending_flip_obj = obj;
  6078. work->enable_stall_check = true;
  6079. atomic_inc(&intel_crtc->unpin_work_count);
  6080. ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
  6081. if (ret)
  6082. goto cleanup_pending;
  6083. intel_disable_fbc(dev);
  6084. intel_mark_fb_busy(obj);
  6085. mutex_unlock(&dev->struct_mutex);
  6086. trace_i915_flip_request(intel_crtc->plane, obj);
  6087. return 0;
  6088. cleanup_pending:
  6089. atomic_dec(&intel_crtc->unpin_work_count);
  6090. drm_gem_object_unreference(&work->old_fb_obj->base);
  6091. drm_gem_object_unreference(&obj->base);
  6092. mutex_unlock(&dev->struct_mutex);
  6093. cleanup:
  6094. spin_lock_irqsave(&dev->event_lock, flags);
  6095. intel_crtc->unpin_work = NULL;
  6096. spin_unlock_irqrestore(&dev->event_lock, flags);
  6097. drm_vblank_put(dev, intel_crtc->pipe);
  6098. free_work:
  6099. kfree(work);
  6100. return ret;
  6101. }
  6102. static struct drm_crtc_helper_funcs intel_helper_funcs = {
  6103. .mode_set_base_atomic = intel_pipe_set_base_atomic,
  6104. .load_lut = intel_crtc_load_lut,
  6105. .disable = intel_crtc_noop,
  6106. };
  6107. bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
  6108. {
  6109. struct intel_encoder *other_encoder;
  6110. struct drm_crtc *crtc = &encoder->new_crtc->base;
  6111. if (WARN_ON(!crtc))
  6112. return false;
  6113. list_for_each_entry(other_encoder,
  6114. &crtc->dev->mode_config.encoder_list,
  6115. base.head) {
  6116. if (&other_encoder->new_crtc->base != crtc ||
  6117. encoder == other_encoder)
  6118. continue;
  6119. else
  6120. return true;
  6121. }
  6122. return false;
  6123. }
  6124. static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
  6125. struct drm_crtc *crtc)
  6126. {
  6127. struct drm_device *dev;
  6128. struct drm_crtc *tmp;
  6129. int crtc_mask = 1;
  6130. WARN(!crtc, "checking null crtc?\n");
  6131. dev = crtc->dev;
  6132. list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
  6133. if (tmp == crtc)
  6134. break;
  6135. crtc_mask <<= 1;
  6136. }
  6137. if (encoder->possible_crtcs & crtc_mask)
  6138. return true;
  6139. return false;
  6140. }
  6141. /**
  6142. * intel_modeset_update_staged_output_state
  6143. *
  6144. * Updates the staged output configuration state, e.g. after we've read out the
  6145. * current hw state.
  6146. */
  6147. static void intel_modeset_update_staged_output_state(struct drm_device *dev)
  6148. {
  6149. struct intel_encoder *encoder;
  6150. struct intel_connector *connector;
  6151. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6152. base.head) {
  6153. connector->new_encoder =
  6154. to_intel_encoder(connector->base.encoder);
  6155. }
  6156. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6157. base.head) {
  6158. encoder->new_crtc =
  6159. to_intel_crtc(encoder->base.crtc);
  6160. }
  6161. }
  6162. /**
  6163. * intel_modeset_commit_output_state
  6164. *
  6165. * This function copies the stage display pipe configuration to the real one.
  6166. */
  6167. static void intel_modeset_commit_output_state(struct drm_device *dev)
  6168. {
  6169. struct intel_encoder *encoder;
  6170. struct intel_connector *connector;
  6171. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6172. base.head) {
  6173. connector->base.encoder = &connector->new_encoder->base;
  6174. }
  6175. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6176. base.head) {
  6177. encoder->base.crtc = &encoder->new_crtc->base;
  6178. }
  6179. }
  6180. static struct drm_display_mode *
  6181. intel_modeset_adjusted_mode(struct drm_crtc *crtc,
  6182. struct drm_display_mode *mode)
  6183. {
  6184. struct drm_device *dev = crtc->dev;
  6185. struct drm_display_mode *adjusted_mode;
  6186. struct drm_encoder_helper_funcs *encoder_funcs;
  6187. struct intel_encoder *encoder;
  6188. adjusted_mode = drm_mode_duplicate(dev, mode);
  6189. if (!adjusted_mode)
  6190. return ERR_PTR(-ENOMEM);
  6191. /* Pass our mode to the connectors and the CRTC to give them a chance to
  6192. * adjust it according to limitations or connector properties, and also
  6193. * a chance to reject the mode entirely.
  6194. */
  6195. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6196. base.head) {
  6197. if (&encoder->new_crtc->base != crtc)
  6198. continue;
  6199. encoder_funcs = encoder->base.helper_private;
  6200. if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
  6201. adjusted_mode))) {
  6202. DRM_DEBUG_KMS("Encoder fixup failed\n");
  6203. goto fail;
  6204. }
  6205. }
  6206. if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
  6207. DRM_DEBUG_KMS("CRTC fixup failed\n");
  6208. goto fail;
  6209. }
  6210. DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
  6211. return adjusted_mode;
  6212. fail:
  6213. drm_mode_destroy(dev, adjusted_mode);
  6214. return ERR_PTR(-EINVAL);
  6215. }
  6216. /* Computes which crtcs are affected and sets the relevant bits in the mask. For
  6217. * simplicity we use the crtc's pipe number (because it's easier to obtain). */
  6218. static void
  6219. intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
  6220. unsigned *prepare_pipes, unsigned *disable_pipes)
  6221. {
  6222. struct intel_crtc *intel_crtc;
  6223. struct drm_device *dev = crtc->dev;
  6224. struct intel_encoder *encoder;
  6225. struct intel_connector *connector;
  6226. struct drm_crtc *tmp_crtc;
  6227. *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
  6228. /* Check which crtcs have changed outputs connected to them, these need
  6229. * to be part of the prepare_pipes mask. We don't (yet) support global
  6230. * modeset across multiple crtcs, so modeset_pipes will only have one
  6231. * bit set at most. */
  6232. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6233. base.head) {
  6234. if (connector->base.encoder == &connector->new_encoder->base)
  6235. continue;
  6236. if (connector->base.encoder) {
  6237. tmp_crtc = connector->base.encoder->crtc;
  6238. *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
  6239. }
  6240. if (connector->new_encoder)
  6241. *prepare_pipes |=
  6242. 1 << connector->new_encoder->new_crtc->pipe;
  6243. }
  6244. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6245. base.head) {
  6246. if (encoder->base.crtc == &encoder->new_crtc->base)
  6247. continue;
  6248. if (encoder->base.crtc) {
  6249. tmp_crtc = encoder->base.crtc;
  6250. *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
  6251. }
  6252. if (encoder->new_crtc)
  6253. *prepare_pipes |= 1 << encoder->new_crtc->pipe;
  6254. }
  6255. /* Check for any pipes that will be fully disabled ... */
  6256. list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
  6257. base.head) {
  6258. bool used = false;
  6259. /* Don't try to disable disabled crtcs. */
  6260. if (!intel_crtc->base.enabled)
  6261. continue;
  6262. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6263. base.head) {
  6264. if (encoder->new_crtc == intel_crtc)
  6265. used = true;
  6266. }
  6267. if (!used)
  6268. *disable_pipes |= 1 << intel_crtc->pipe;
  6269. }
  6270. /* set_mode is also used to update properties on life display pipes. */
  6271. intel_crtc = to_intel_crtc(crtc);
  6272. if (crtc->enabled)
  6273. *prepare_pipes |= 1 << intel_crtc->pipe;
  6274. /* We only support modeset on one single crtc, hence we need to do that
  6275. * only for the passed in crtc iff we change anything else than just
  6276. * disable crtcs.
  6277. *
  6278. * This is actually not true, to be fully compatible with the old crtc
  6279. * helper we automatically disable _any_ output (i.e. doesn't need to be
  6280. * connected to the crtc we're modesetting on) if it's disconnected.
  6281. * Which is a rather nutty api (since changed the output configuration
  6282. * without userspace's explicit request can lead to confusion), but
  6283. * alas. Hence we currently need to modeset on all pipes we prepare. */
  6284. if (*prepare_pipes)
  6285. *modeset_pipes = *prepare_pipes;
  6286. /* ... and mask these out. */
  6287. *modeset_pipes &= ~(*disable_pipes);
  6288. *prepare_pipes &= ~(*disable_pipes);
  6289. }
  6290. static bool intel_crtc_in_use(struct drm_crtc *crtc)
  6291. {
  6292. struct drm_encoder *encoder;
  6293. struct drm_device *dev = crtc->dev;
  6294. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
  6295. if (encoder->crtc == crtc)
  6296. return true;
  6297. return false;
  6298. }
  6299. static void
  6300. intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
  6301. {
  6302. struct intel_encoder *intel_encoder;
  6303. struct intel_crtc *intel_crtc;
  6304. struct drm_connector *connector;
  6305. list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
  6306. base.head) {
  6307. if (!intel_encoder->base.crtc)
  6308. continue;
  6309. intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
  6310. if (prepare_pipes & (1 << intel_crtc->pipe))
  6311. intel_encoder->connectors_active = false;
  6312. }
  6313. intel_modeset_commit_output_state(dev);
  6314. /* Update computed state. */
  6315. list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
  6316. base.head) {
  6317. intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
  6318. }
  6319. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  6320. if (!connector->encoder || !connector->encoder->crtc)
  6321. continue;
  6322. intel_crtc = to_intel_crtc(connector->encoder->crtc);
  6323. if (prepare_pipes & (1 << intel_crtc->pipe)) {
  6324. struct drm_property *dpms_property =
  6325. dev->mode_config.dpms_property;
  6326. connector->dpms = DRM_MODE_DPMS_ON;
  6327. drm_object_property_set_value(&connector->base,
  6328. dpms_property,
  6329. DRM_MODE_DPMS_ON);
  6330. intel_encoder = to_intel_encoder(connector->encoder);
  6331. intel_encoder->connectors_active = true;
  6332. }
  6333. }
  6334. }
  6335. #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
  6336. list_for_each_entry((intel_crtc), \
  6337. &(dev)->mode_config.crtc_list, \
  6338. base.head) \
  6339. if (mask & (1 <<(intel_crtc)->pipe)) \
  6340. void
  6341. intel_modeset_check_state(struct drm_device *dev)
  6342. {
  6343. struct intel_crtc *crtc;
  6344. struct intel_encoder *encoder;
  6345. struct intel_connector *connector;
  6346. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6347. base.head) {
  6348. /* This also checks the encoder/connector hw state with the
  6349. * ->get_hw_state callbacks. */
  6350. intel_connector_check_state(connector);
  6351. WARN(&connector->new_encoder->base != connector->base.encoder,
  6352. "connector's staged encoder doesn't match current encoder\n");
  6353. }
  6354. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6355. base.head) {
  6356. bool enabled = false;
  6357. bool active = false;
  6358. enum pipe pipe, tracked_pipe;
  6359. DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
  6360. encoder->base.base.id,
  6361. drm_get_encoder_name(&encoder->base));
  6362. WARN(&encoder->new_crtc->base != encoder->base.crtc,
  6363. "encoder's stage crtc doesn't match current crtc\n");
  6364. WARN(encoder->connectors_active && !encoder->base.crtc,
  6365. "encoder's active_connectors set, but no crtc\n");
  6366. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6367. base.head) {
  6368. if (connector->base.encoder != &encoder->base)
  6369. continue;
  6370. enabled = true;
  6371. if (connector->base.dpms != DRM_MODE_DPMS_OFF)
  6372. active = true;
  6373. }
  6374. WARN(!!encoder->base.crtc != enabled,
  6375. "encoder's enabled state mismatch "
  6376. "(expected %i, found %i)\n",
  6377. !!encoder->base.crtc, enabled);
  6378. WARN(active && !encoder->base.crtc,
  6379. "active encoder with no crtc\n");
  6380. WARN(encoder->connectors_active != active,
  6381. "encoder's computed active state doesn't match tracked active state "
  6382. "(expected %i, found %i)\n", active, encoder->connectors_active);
  6383. active = encoder->get_hw_state(encoder, &pipe);
  6384. WARN(active != encoder->connectors_active,
  6385. "encoder's hw state doesn't match sw tracking "
  6386. "(expected %i, found %i)\n",
  6387. encoder->connectors_active, active);
  6388. if (!encoder->base.crtc)
  6389. continue;
  6390. tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
  6391. WARN(active && pipe != tracked_pipe,
  6392. "active encoder's pipe doesn't match"
  6393. "(expected %i, found %i)\n",
  6394. tracked_pipe, pipe);
  6395. }
  6396. list_for_each_entry(crtc, &dev->mode_config.crtc_list,
  6397. base.head) {
  6398. bool enabled = false;
  6399. bool active = false;
  6400. DRM_DEBUG_KMS("[CRTC:%d]\n",
  6401. crtc->base.base.id);
  6402. WARN(crtc->active && !crtc->base.enabled,
  6403. "active crtc, but not enabled in sw tracking\n");
  6404. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6405. base.head) {
  6406. if (encoder->base.crtc != &crtc->base)
  6407. continue;
  6408. enabled = true;
  6409. if (encoder->connectors_active)
  6410. active = true;
  6411. }
  6412. WARN(active != crtc->active,
  6413. "crtc's computed active state doesn't match tracked active state "
  6414. "(expected %i, found %i)\n", active, crtc->active);
  6415. WARN(enabled != crtc->base.enabled,
  6416. "crtc's computed enabled state doesn't match tracked enabled state "
  6417. "(expected %i, found %i)\n", enabled, crtc->base.enabled);
  6418. assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
  6419. }
  6420. }
  6421. int intel_set_mode(struct drm_crtc *crtc,
  6422. struct drm_display_mode *mode,
  6423. int x, int y, struct drm_framebuffer *fb)
  6424. {
  6425. struct drm_device *dev = crtc->dev;
  6426. drm_i915_private_t *dev_priv = dev->dev_private;
  6427. struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode;
  6428. struct intel_crtc *intel_crtc;
  6429. unsigned disable_pipes, prepare_pipes, modeset_pipes;
  6430. int ret = 0;
  6431. saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
  6432. if (!saved_mode)
  6433. return -ENOMEM;
  6434. saved_hwmode = saved_mode + 1;
  6435. intel_modeset_affected_pipes(crtc, &modeset_pipes,
  6436. &prepare_pipes, &disable_pipes);
  6437. DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
  6438. modeset_pipes, prepare_pipes, disable_pipes);
  6439. for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
  6440. intel_crtc_disable(&intel_crtc->base);
  6441. *saved_hwmode = crtc->hwmode;
  6442. *saved_mode = crtc->mode;
  6443. /* Hack: Because we don't (yet) support global modeset on multiple
  6444. * crtcs, we don't keep track of the new mode for more than one crtc.
  6445. * Hence simply check whether any bit is set in modeset_pipes in all the
  6446. * pieces of code that are not yet converted to deal with mutliple crtcs
  6447. * changing their mode at the same time. */
  6448. adjusted_mode = NULL;
  6449. if (modeset_pipes) {
  6450. adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
  6451. if (IS_ERR(adjusted_mode)) {
  6452. ret = PTR_ERR(adjusted_mode);
  6453. goto out;
  6454. }
  6455. }
  6456. for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
  6457. if (intel_crtc->base.enabled)
  6458. dev_priv->display.crtc_disable(&intel_crtc->base);
  6459. }
  6460. /* crtc->mode is already used by the ->mode_set callbacks, hence we need
  6461. * to set it here already despite that we pass it down the callchain.
  6462. */
  6463. if (modeset_pipes)
  6464. crtc->mode = *mode;
  6465. /* Only after disabling all output pipelines that will be changed can we
  6466. * update the the output configuration. */
  6467. intel_modeset_update_state(dev, prepare_pipes);
  6468. if (dev_priv->display.modeset_global_resources)
  6469. dev_priv->display.modeset_global_resources(dev);
  6470. /* Set up the DPLL and any encoders state that needs to adjust or depend
  6471. * on the DPLL.
  6472. */
  6473. for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
  6474. ret = intel_crtc_mode_set(&intel_crtc->base,
  6475. mode, adjusted_mode,
  6476. x, y, fb);
  6477. if (ret)
  6478. goto done;
  6479. }
  6480. /* Now enable the clocks, plane, pipe, and connectors that we set up. */
  6481. for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
  6482. dev_priv->display.crtc_enable(&intel_crtc->base);
  6483. if (modeset_pipes) {
  6484. /* Store real post-adjustment hardware mode. */
  6485. crtc->hwmode = *adjusted_mode;
  6486. /* Calculate and store various constants which
  6487. * are later needed by vblank and swap-completion
  6488. * timestamping. They are derived from true hwmode.
  6489. */
  6490. drm_calc_timestamping_constants(crtc);
  6491. }
  6492. /* FIXME: add subpixel order */
  6493. done:
  6494. drm_mode_destroy(dev, adjusted_mode);
  6495. if (ret && crtc->enabled) {
  6496. crtc->hwmode = *saved_hwmode;
  6497. crtc->mode = *saved_mode;
  6498. } else {
  6499. intel_modeset_check_state(dev);
  6500. }
  6501. out:
  6502. kfree(saved_mode);
  6503. return ret;
  6504. }
  6505. void intel_crtc_restore_mode(struct drm_crtc *crtc)
  6506. {
  6507. intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
  6508. }
  6509. #undef for_each_intel_crtc_masked
  6510. static void intel_set_config_free(struct intel_set_config *config)
  6511. {
  6512. if (!config)
  6513. return;
  6514. kfree(config->save_connector_encoders);
  6515. kfree(config->save_encoder_crtcs);
  6516. kfree(config);
  6517. }
  6518. static int intel_set_config_save_state(struct drm_device *dev,
  6519. struct intel_set_config *config)
  6520. {
  6521. struct drm_encoder *encoder;
  6522. struct drm_connector *connector;
  6523. int count;
  6524. config->save_encoder_crtcs =
  6525. kcalloc(dev->mode_config.num_encoder,
  6526. sizeof(struct drm_crtc *), GFP_KERNEL);
  6527. if (!config->save_encoder_crtcs)
  6528. return -ENOMEM;
  6529. config->save_connector_encoders =
  6530. kcalloc(dev->mode_config.num_connector,
  6531. sizeof(struct drm_encoder *), GFP_KERNEL);
  6532. if (!config->save_connector_encoders)
  6533. return -ENOMEM;
  6534. /* Copy data. Note that driver private data is not affected.
  6535. * Should anything bad happen only the expected state is
  6536. * restored, not the drivers personal bookkeeping.
  6537. */
  6538. count = 0;
  6539. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  6540. config->save_encoder_crtcs[count++] = encoder->crtc;
  6541. }
  6542. count = 0;
  6543. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  6544. config->save_connector_encoders[count++] = connector->encoder;
  6545. }
  6546. return 0;
  6547. }
  6548. static void intel_set_config_restore_state(struct drm_device *dev,
  6549. struct intel_set_config *config)
  6550. {
  6551. struct intel_encoder *encoder;
  6552. struct intel_connector *connector;
  6553. int count;
  6554. count = 0;
  6555. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  6556. encoder->new_crtc =
  6557. to_intel_crtc(config->save_encoder_crtcs[count++]);
  6558. }
  6559. count = 0;
  6560. list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
  6561. connector->new_encoder =
  6562. to_intel_encoder(config->save_connector_encoders[count++]);
  6563. }
  6564. }
  6565. static void
  6566. intel_set_config_compute_mode_changes(struct drm_mode_set *set,
  6567. struct intel_set_config *config)
  6568. {
  6569. /* We should be able to check here if the fb has the same properties
  6570. * and then just flip_or_move it */
  6571. if (set->crtc->fb != set->fb) {
  6572. /* If we have no fb then treat it as a full mode set */
  6573. if (set->crtc->fb == NULL) {
  6574. DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
  6575. config->mode_changed = true;
  6576. } else if (set->fb == NULL) {
  6577. config->mode_changed = true;
  6578. } else if (set->fb->depth != set->crtc->fb->depth) {
  6579. config->mode_changed = true;
  6580. } else if (set->fb->bits_per_pixel !=
  6581. set->crtc->fb->bits_per_pixel) {
  6582. config->mode_changed = true;
  6583. } else
  6584. config->fb_changed = true;
  6585. }
  6586. if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
  6587. config->fb_changed = true;
  6588. if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
  6589. DRM_DEBUG_KMS("modes are different, full mode set\n");
  6590. drm_mode_debug_printmodeline(&set->crtc->mode);
  6591. drm_mode_debug_printmodeline(set->mode);
  6592. config->mode_changed = true;
  6593. }
  6594. }
  6595. static int
  6596. intel_modeset_stage_output_state(struct drm_device *dev,
  6597. struct drm_mode_set *set,
  6598. struct intel_set_config *config)
  6599. {
  6600. struct drm_crtc *new_crtc;
  6601. struct intel_connector *connector;
  6602. struct intel_encoder *encoder;
  6603. int count, ro;
  6604. /* The upper layers ensure that we either disabl a crtc or have a list
  6605. * of connectors. For paranoia, double-check this. */
  6606. WARN_ON(!set->fb && (set->num_connectors != 0));
  6607. WARN_ON(set->fb && (set->num_connectors == 0));
  6608. count = 0;
  6609. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6610. base.head) {
  6611. /* Otherwise traverse passed in connector list and get encoders
  6612. * for them. */
  6613. for (ro = 0; ro < set->num_connectors; ro++) {
  6614. if (set->connectors[ro] == &connector->base) {
  6615. connector->new_encoder = connector->encoder;
  6616. break;
  6617. }
  6618. }
  6619. /* If we disable the crtc, disable all its connectors. Also, if
  6620. * the connector is on the changing crtc but not on the new
  6621. * connector list, disable it. */
  6622. if ((!set->fb || ro == set->num_connectors) &&
  6623. connector->base.encoder &&
  6624. connector->base.encoder->crtc == set->crtc) {
  6625. connector->new_encoder = NULL;
  6626. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
  6627. connector->base.base.id,
  6628. drm_get_connector_name(&connector->base));
  6629. }
  6630. if (&connector->new_encoder->base != connector->base.encoder) {
  6631. DRM_DEBUG_KMS("encoder changed, full mode switch\n");
  6632. config->mode_changed = true;
  6633. }
  6634. }
  6635. /* connector->new_encoder is now updated for all connectors. */
  6636. /* Update crtc of enabled connectors. */
  6637. count = 0;
  6638. list_for_each_entry(connector, &dev->mode_config.connector_list,
  6639. base.head) {
  6640. if (!connector->new_encoder)
  6641. continue;
  6642. new_crtc = connector->new_encoder->base.crtc;
  6643. for (ro = 0; ro < set->num_connectors; ro++) {
  6644. if (set->connectors[ro] == &connector->base)
  6645. new_crtc = set->crtc;
  6646. }
  6647. /* Make sure the new CRTC will work with the encoder */
  6648. if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
  6649. new_crtc)) {
  6650. return -EINVAL;
  6651. }
  6652. connector->encoder->new_crtc = to_intel_crtc(new_crtc);
  6653. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
  6654. connector->base.base.id,
  6655. drm_get_connector_name(&connector->base),
  6656. new_crtc->base.id);
  6657. }
  6658. /* Check for any encoders that needs to be disabled. */
  6659. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  6660. base.head) {
  6661. list_for_each_entry(connector,
  6662. &dev->mode_config.connector_list,
  6663. base.head) {
  6664. if (connector->new_encoder == encoder) {
  6665. WARN_ON(!connector->new_encoder->new_crtc);
  6666. goto next_encoder;
  6667. }
  6668. }
  6669. encoder->new_crtc = NULL;
  6670. next_encoder:
  6671. /* Only now check for crtc changes so we don't miss encoders
  6672. * that will be disabled. */
  6673. if (&encoder->new_crtc->base != encoder->base.crtc) {
  6674. DRM_DEBUG_KMS("crtc changed, full mode switch\n");
  6675. config->mode_changed = true;
  6676. }
  6677. }
  6678. /* Now we've also updated encoder->new_crtc for all encoders. */
  6679. return 0;
  6680. }
  6681. static int intel_crtc_set_config(struct drm_mode_set *set)
  6682. {
  6683. struct drm_device *dev;
  6684. struct drm_mode_set save_set;
  6685. struct intel_set_config *config;
  6686. int ret;
  6687. BUG_ON(!set);
  6688. BUG_ON(!set->crtc);
  6689. BUG_ON(!set->crtc->helper_private);
  6690. if (!set->mode)
  6691. set->fb = NULL;
  6692. /* The fb helper likes to play gross jokes with ->mode_set_config.
  6693. * Unfortunately the crtc helper doesn't do much at all for this case,
  6694. * so we have to cope with this madness until the fb helper is fixed up. */
  6695. if (set->fb && set->num_connectors == 0)
  6696. return 0;
  6697. if (set->fb) {
  6698. DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
  6699. set->crtc->base.id, set->fb->base.id,
  6700. (int)set->num_connectors, set->x, set->y);
  6701. } else {
  6702. DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
  6703. }
  6704. dev = set->crtc->dev;
  6705. ret = -ENOMEM;
  6706. config = kzalloc(sizeof(*config), GFP_KERNEL);
  6707. if (!config)
  6708. goto out_config;
  6709. ret = intel_set_config_save_state(dev, config);
  6710. if (ret)
  6711. goto out_config;
  6712. save_set.crtc = set->crtc;
  6713. save_set.mode = &set->crtc->mode;
  6714. save_set.x = set->crtc->x;
  6715. save_set.y = set->crtc->y;
  6716. save_set.fb = set->crtc->fb;
  6717. /* Compute whether we need a full modeset, only an fb base update or no
  6718. * change at all. In the future we might also check whether only the
  6719. * mode changed, e.g. for LVDS where we only change the panel fitter in
  6720. * such cases. */
  6721. intel_set_config_compute_mode_changes(set, config);
  6722. ret = intel_modeset_stage_output_state(dev, set, config);
  6723. if (ret)
  6724. goto fail;
  6725. if (config->mode_changed) {
  6726. if (set->mode) {
  6727. DRM_DEBUG_KMS("attempting to set mode from"
  6728. " userspace\n");
  6729. drm_mode_debug_printmodeline(set->mode);
  6730. }
  6731. ret = intel_set_mode(set->crtc, set->mode,
  6732. set->x, set->y, set->fb);
  6733. if (ret) {
  6734. DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
  6735. set->crtc->base.id, ret);
  6736. goto fail;
  6737. }
  6738. } else if (config->fb_changed) {
  6739. ret = intel_pipe_set_base(set->crtc,
  6740. set->x, set->y, set->fb);
  6741. }
  6742. intel_set_config_free(config);
  6743. return 0;
  6744. fail:
  6745. intel_set_config_restore_state(dev, config);
  6746. /* Try to restore the config */
  6747. if (config->mode_changed &&
  6748. intel_set_mode(save_set.crtc, save_set.mode,
  6749. save_set.x, save_set.y, save_set.fb))
  6750. DRM_ERROR("failed to restore config after modeset failure\n");
  6751. out_config:
  6752. intel_set_config_free(config);
  6753. return ret;
  6754. }
  6755. static const struct drm_crtc_funcs intel_crtc_funcs = {
  6756. .cursor_set = intel_crtc_cursor_set,
  6757. .cursor_move = intel_crtc_cursor_move,
  6758. .gamma_set = intel_crtc_gamma_set,
  6759. .set_config = intel_crtc_set_config,
  6760. .destroy = intel_crtc_destroy,
  6761. .page_flip = intel_crtc_page_flip,
  6762. };
  6763. static void intel_cpu_pll_init(struct drm_device *dev)
  6764. {
  6765. if (HAS_DDI(dev))
  6766. intel_ddi_pll_init(dev);
  6767. }
  6768. static void intel_pch_pll_init(struct drm_device *dev)
  6769. {
  6770. drm_i915_private_t *dev_priv = dev->dev_private;
  6771. int i;
  6772. if (dev_priv->num_pch_pll == 0) {
  6773. DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
  6774. return;
  6775. }
  6776. for (i = 0; i < dev_priv->num_pch_pll; i++) {
  6777. dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
  6778. dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
  6779. dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
  6780. }
  6781. }
  6782. static void intel_crtc_init(struct drm_device *dev, int pipe)
  6783. {
  6784. drm_i915_private_t *dev_priv = dev->dev_private;
  6785. struct intel_crtc *intel_crtc;
  6786. int i;
  6787. intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
  6788. if (intel_crtc == NULL)
  6789. return;
  6790. drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
  6791. drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
  6792. for (i = 0; i < 256; i++) {
  6793. intel_crtc->lut_r[i] = i;
  6794. intel_crtc->lut_g[i] = i;
  6795. intel_crtc->lut_b[i] = i;
  6796. }
  6797. /* Swap pipes & planes for FBC on pre-965 */
  6798. intel_crtc->pipe = pipe;
  6799. intel_crtc->plane = pipe;
  6800. intel_crtc->cpu_transcoder = pipe;
  6801. if (IS_MOBILE(dev) && IS_GEN3(dev)) {
  6802. DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
  6803. intel_crtc->plane = !pipe;
  6804. }
  6805. BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
  6806. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
  6807. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
  6808. dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
  6809. intel_crtc->bpp = 24; /* default for pre-Ironlake */
  6810. drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
  6811. }
  6812. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  6813. struct drm_file *file)
  6814. {
  6815. struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
  6816. struct drm_mode_object *drmmode_obj;
  6817. struct intel_crtc *crtc;
  6818. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  6819. return -ENODEV;
  6820. drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
  6821. DRM_MODE_OBJECT_CRTC);
  6822. if (!drmmode_obj) {
  6823. DRM_ERROR("no such CRTC id\n");
  6824. return -EINVAL;
  6825. }
  6826. crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
  6827. pipe_from_crtc_id->pipe = crtc->pipe;
  6828. return 0;
  6829. }
  6830. static int intel_encoder_clones(struct intel_encoder *encoder)
  6831. {
  6832. struct drm_device *dev = encoder->base.dev;
  6833. struct intel_encoder *source_encoder;
  6834. int index_mask = 0;
  6835. int entry = 0;
  6836. list_for_each_entry(source_encoder,
  6837. &dev->mode_config.encoder_list, base.head) {
  6838. if (encoder == source_encoder)
  6839. index_mask |= (1 << entry);
  6840. /* Intel hw has only one MUX where enocoders could be cloned. */
  6841. if (encoder->cloneable && source_encoder->cloneable)
  6842. index_mask |= (1 << entry);
  6843. entry++;
  6844. }
  6845. return index_mask;
  6846. }
  6847. static bool has_edp_a(struct drm_device *dev)
  6848. {
  6849. struct drm_i915_private *dev_priv = dev->dev_private;
  6850. if (!IS_MOBILE(dev))
  6851. return false;
  6852. if ((I915_READ(DP_A) & DP_DETECTED) == 0)
  6853. return false;
  6854. if (IS_GEN5(dev) &&
  6855. (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
  6856. return false;
  6857. return true;
  6858. }
  6859. static void intel_setup_outputs(struct drm_device *dev)
  6860. {
  6861. struct drm_i915_private *dev_priv = dev->dev_private;
  6862. struct intel_encoder *encoder;
  6863. bool dpd_is_edp = false;
  6864. bool has_lvds;
  6865. has_lvds = intel_lvds_init(dev);
  6866. if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
  6867. /* disable the panel fitter on everything but LVDS */
  6868. I915_WRITE(PFIT_CONTROL, 0);
  6869. }
  6870. if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
  6871. intel_crt_init(dev);
  6872. if (HAS_DDI(dev)) {
  6873. int found;
  6874. /* Haswell uses DDI functions to detect digital outputs */
  6875. found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
  6876. /* DDI A only supports eDP */
  6877. if (found)
  6878. intel_ddi_init(dev, PORT_A);
  6879. /* DDI B, C and D detection is indicated by the SFUSE_STRAP
  6880. * register */
  6881. found = I915_READ(SFUSE_STRAP);
  6882. if (found & SFUSE_STRAP_DDIB_DETECTED)
  6883. intel_ddi_init(dev, PORT_B);
  6884. if (found & SFUSE_STRAP_DDIC_DETECTED)
  6885. intel_ddi_init(dev, PORT_C);
  6886. if (found & SFUSE_STRAP_DDID_DETECTED)
  6887. intel_ddi_init(dev, PORT_D);
  6888. } else if (HAS_PCH_SPLIT(dev)) {
  6889. int found;
  6890. dpd_is_edp = intel_dpd_is_edp(dev);
  6891. if (has_edp_a(dev))
  6892. intel_dp_init(dev, DP_A, PORT_A);
  6893. if (I915_READ(HDMIB) & PORT_DETECTED) {
  6894. /* PCH SDVOB multiplex with HDMIB */
  6895. found = intel_sdvo_init(dev, PCH_SDVOB, true);
  6896. if (!found)
  6897. intel_hdmi_init(dev, HDMIB, PORT_B);
  6898. if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
  6899. intel_dp_init(dev, PCH_DP_B, PORT_B);
  6900. }
  6901. if (I915_READ(HDMIC) & PORT_DETECTED)
  6902. intel_hdmi_init(dev, HDMIC, PORT_C);
  6903. if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
  6904. intel_hdmi_init(dev, HDMID, PORT_D);
  6905. if (I915_READ(PCH_DP_C) & DP_DETECTED)
  6906. intel_dp_init(dev, PCH_DP_C, PORT_C);
  6907. if (I915_READ(PCH_DP_D) & DP_DETECTED)
  6908. intel_dp_init(dev, PCH_DP_D, PORT_D);
  6909. } else if (IS_VALLEYVIEW(dev)) {
  6910. int found;
  6911. /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
  6912. if (I915_READ(DP_C) & DP_DETECTED)
  6913. intel_dp_init(dev, DP_C, PORT_C);
  6914. if (I915_READ(SDVOB) & PORT_DETECTED) {
  6915. /* SDVOB multiplex with HDMIB */
  6916. found = intel_sdvo_init(dev, SDVOB, true);
  6917. if (!found)
  6918. intel_hdmi_init(dev, SDVOB, PORT_B);
  6919. if (!found && (I915_READ(DP_B) & DP_DETECTED))
  6920. intel_dp_init(dev, DP_B, PORT_B);
  6921. }
  6922. if (I915_READ(SDVOC) & PORT_DETECTED)
  6923. intel_hdmi_init(dev, SDVOC, PORT_C);
  6924. } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
  6925. bool found = false;
  6926. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  6927. DRM_DEBUG_KMS("probing SDVOB\n");
  6928. found = intel_sdvo_init(dev, SDVOB, true);
  6929. if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
  6930. DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
  6931. intel_hdmi_init(dev, SDVOB, PORT_B);
  6932. }
  6933. if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
  6934. DRM_DEBUG_KMS("probing DP_B\n");
  6935. intel_dp_init(dev, DP_B, PORT_B);
  6936. }
  6937. }
  6938. /* Before G4X SDVOC doesn't have its own detect register */
  6939. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  6940. DRM_DEBUG_KMS("probing SDVOC\n");
  6941. found = intel_sdvo_init(dev, SDVOC, false);
  6942. }
  6943. if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
  6944. if (SUPPORTS_INTEGRATED_HDMI(dev)) {
  6945. DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
  6946. intel_hdmi_init(dev, SDVOC, PORT_C);
  6947. }
  6948. if (SUPPORTS_INTEGRATED_DP(dev)) {
  6949. DRM_DEBUG_KMS("probing DP_C\n");
  6950. intel_dp_init(dev, DP_C, PORT_C);
  6951. }
  6952. }
  6953. if (SUPPORTS_INTEGRATED_DP(dev) &&
  6954. (I915_READ(DP_D) & DP_DETECTED)) {
  6955. DRM_DEBUG_KMS("probing DP_D\n");
  6956. intel_dp_init(dev, DP_D, PORT_D);
  6957. }
  6958. } else if (IS_GEN2(dev))
  6959. intel_dvo_init(dev);
  6960. if (SUPPORTS_TV(dev))
  6961. intel_tv_init(dev);
  6962. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  6963. encoder->base.possible_crtcs = encoder->crtc_mask;
  6964. encoder->base.possible_clones =
  6965. intel_encoder_clones(encoder);
  6966. }
  6967. intel_init_pch_refclk(dev);
  6968. drm_helper_move_panel_connectors_to_head(dev);
  6969. }
  6970. static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
  6971. {
  6972. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  6973. drm_framebuffer_cleanup(fb);
  6974. drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
  6975. kfree(intel_fb);
  6976. }
  6977. static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
  6978. struct drm_file *file,
  6979. unsigned int *handle)
  6980. {
  6981. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  6982. struct drm_i915_gem_object *obj = intel_fb->obj;
  6983. return drm_gem_handle_create(file, &obj->base, handle);
  6984. }
  6985. static const struct drm_framebuffer_funcs intel_fb_funcs = {
  6986. .destroy = intel_user_framebuffer_destroy,
  6987. .create_handle = intel_user_framebuffer_create_handle,
  6988. };
  6989. int intel_framebuffer_init(struct drm_device *dev,
  6990. struct intel_framebuffer *intel_fb,
  6991. struct drm_mode_fb_cmd2 *mode_cmd,
  6992. struct drm_i915_gem_object *obj)
  6993. {
  6994. int ret;
  6995. if (obj->tiling_mode == I915_TILING_Y)
  6996. return -EINVAL;
  6997. if (mode_cmd->pitches[0] & 63)
  6998. return -EINVAL;
  6999. /* FIXME <= Gen4 stride limits are bit unclear */
  7000. if (mode_cmd->pitches[0] > 32768)
  7001. return -EINVAL;
  7002. if (obj->tiling_mode != I915_TILING_NONE &&
  7003. mode_cmd->pitches[0] != obj->stride)
  7004. return -EINVAL;
  7005. /* Reject formats not supported by any plane early. */
  7006. switch (mode_cmd->pixel_format) {
  7007. case DRM_FORMAT_C8:
  7008. case DRM_FORMAT_RGB565:
  7009. case DRM_FORMAT_XRGB8888:
  7010. case DRM_FORMAT_ARGB8888:
  7011. break;
  7012. case DRM_FORMAT_XRGB1555:
  7013. case DRM_FORMAT_ARGB1555:
  7014. if (INTEL_INFO(dev)->gen > 3)
  7015. return -EINVAL;
  7016. break;
  7017. case DRM_FORMAT_XBGR8888:
  7018. case DRM_FORMAT_ABGR8888:
  7019. case DRM_FORMAT_XRGB2101010:
  7020. case DRM_FORMAT_ARGB2101010:
  7021. case DRM_FORMAT_XBGR2101010:
  7022. case DRM_FORMAT_ABGR2101010:
  7023. if (INTEL_INFO(dev)->gen < 4)
  7024. return -EINVAL;
  7025. break;
  7026. case DRM_FORMAT_YUYV:
  7027. case DRM_FORMAT_UYVY:
  7028. case DRM_FORMAT_YVYU:
  7029. case DRM_FORMAT_VYUY:
  7030. if (INTEL_INFO(dev)->gen < 6)
  7031. return -EINVAL;
  7032. break;
  7033. default:
  7034. DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
  7035. return -EINVAL;
  7036. }
  7037. /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
  7038. if (mode_cmd->offsets[0] != 0)
  7039. return -EINVAL;
  7040. ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
  7041. if (ret) {
  7042. DRM_ERROR("framebuffer init failed %d\n", ret);
  7043. return ret;
  7044. }
  7045. drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
  7046. intel_fb->obj = obj;
  7047. return 0;
  7048. }
  7049. static struct drm_framebuffer *
  7050. intel_user_framebuffer_create(struct drm_device *dev,
  7051. struct drm_file *filp,
  7052. struct drm_mode_fb_cmd2 *mode_cmd)
  7053. {
  7054. struct drm_i915_gem_object *obj;
  7055. obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
  7056. mode_cmd->handles[0]));
  7057. if (&obj->base == NULL)
  7058. return ERR_PTR(-ENOENT);
  7059. return intel_framebuffer_create(dev, mode_cmd, obj);
  7060. }
  7061. static const struct drm_mode_config_funcs intel_mode_funcs = {
  7062. .fb_create = intel_user_framebuffer_create,
  7063. .output_poll_changed = intel_fb_output_poll_changed,
  7064. };
  7065. /* Set up chip specific display functions */
  7066. static void intel_init_display(struct drm_device *dev)
  7067. {
  7068. struct drm_i915_private *dev_priv = dev->dev_private;
  7069. /* We always want a DPMS function */
  7070. if (HAS_DDI(dev)) {
  7071. dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
  7072. dev_priv->display.crtc_enable = haswell_crtc_enable;
  7073. dev_priv->display.crtc_disable = haswell_crtc_disable;
  7074. dev_priv->display.off = haswell_crtc_off;
  7075. dev_priv->display.update_plane = ironlake_update_plane;
  7076. } else if (HAS_PCH_SPLIT(dev)) {
  7077. dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
  7078. dev_priv->display.crtc_enable = ironlake_crtc_enable;
  7079. dev_priv->display.crtc_disable = ironlake_crtc_disable;
  7080. dev_priv->display.off = ironlake_crtc_off;
  7081. dev_priv->display.update_plane = ironlake_update_plane;
  7082. } else {
  7083. dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
  7084. dev_priv->display.crtc_enable = i9xx_crtc_enable;
  7085. dev_priv->display.crtc_disable = i9xx_crtc_disable;
  7086. dev_priv->display.off = i9xx_crtc_off;
  7087. dev_priv->display.update_plane = i9xx_update_plane;
  7088. }
  7089. /* Returns the core display clock speed */
  7090. if (IS_VALLEYVIEW(dev))
  7091. dev_priv->display.get_display_clock_speed =
  7092. valleyview_get_display_clock_speed;
  7093. else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
  7094. dev_priv->display.get_display_clock_speed =
  7095. i945_get_display_clock_speed;
  7096. else if (IS_I915G(dev))
  7097. dev_priv->display.get_display_clock_speed =
  7098. i915_get_display_clock_speed;
  7099. else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
  7100. dev_priv->display.get_display_clock_speed =
  7101. i9xx_misc_get_display_clock_speed;
  7102. else if (IS_I915GM(dev))
  7103. dev_priv->display.get_display_clock_speed =
  7104. i915gm_get_display_clock_speed;
  7105. else if (IS_I865G(dev))
  7106. dev_priv->display.get_display_clock_speed =
  7107. i865_get_display_clock_speed;
  7108. else if (IS_I85X(dev))
  7109. dev_priv->display.get_display_clock_speed =
  7110. i855_get_display_clock_speed;
  7111. else /* 852, 830 */
  7112. dev_priv->display.get_display_clock_speed =
  7113. i830_get_display_clock_speed;
  7114. if (HAS_PCH_SPLIT(dev)) {
  7115. if (IS_GEN5(dev)) {
  7116. dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
  7117. dev_priv->display.write_eld = ironlake_write_eld;
  7118. } else if (IS_GEN6(dev)) {
  7119. dev_priv->display.fdi_link_train = gen6_fdi_link_train;
  7120. dev_priv->display.write_eld = ironlake_write_eld;
  7121. } else if (IS_IVYBRIDGE(dev)) {
  7122. /* FIXME: detect B0+ stepping and use auto training */
  7123. dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
  7124. dev_priv->display.write_eld = ironlake_write_eld;
  7125. dev_priv->display.modeset_global_resources =
  7126. ivb_modeset_global_resources;
  7127. } else if (IS_HASWELL(dev)) {
  7128. dev_priv->display.fdi_link_train = hsw_fdi_link_train;
  7129. dev_priv->display.write_eld = haswell_write_eld;
  7130. }
  7131. } else if (IS_G4X(dev)) {
  7132. dev_priv->display.write_eld = g4x_write_eld;
  7133. }
  7134. /* Default just returns -ENODEV to indicate unsupported */
  7135. dev_priv->display.queue_flip = intel_default_queue_flip;
  7136. switch (INTEL_INFO(dev)->gen) {
  7137. case 2:
  7138. dev_priv->display.queue_flip = intel_gen2_queue_flip;
  7139. break;
  7140. case 3:
  7141. dev_priv->display.queue_flip = intel_gen3_queue_flip;
  7142. break;
  7143. case 4:
  7144. case 5:
  7145. dev_priv->display.queue_flip = intel_gen4_queue_flip;
  7146. break;
  7147. case 6:
  7148. dev_priv->display.queue_flip = intel_gen6_queue_flip;
  7149. break;
  7150. case 7:
  7151. dev_priv->display.queue_flip = intel_gen7_queue_flip;
  7152. break;
  7153. }
  7154. }
  7155. /*
  7156. * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
  7157. * resume, or other times. This quirk makes sure that's the case for
  7158. * affected systems.
  7159. */
  7160. static void quirk_pipea_force(struct drm_device *dev)
  7161. {
  7162. struct drm_i915_private *dev_priv = dev->dev_private;
  7163. dev_priv->quirks |= QUIRK_PIPEA_FORCE;
  7164. DRM_INFO("applying pipe a force quirk\n");
  7165. }
  7166. /*
  7167. * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
  7168. */
  7169. static void quirk_ssc_force_disable(struct drm_device *dev)
  7170. {
  7171. struct drm_i915_private *dev_priv = dev->dev_private;
  7172. dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
  7173. DRM_INFO("applying lvds SSC disable quirk\n");
  7174. }
  7175. /*
  7176. * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
  7177. * brightness value
  7178. */
  7179. static void quirk_invert_brightness(struct drm_device *dev)
  7180. {
  7181. struct drm_i915_private *dev_priv = dev->dev_private;
  7182. dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
  7183. DRM_INFO("applying inverted panel brightness quirk\n");
  7184. }
  7185. struct intel_quirk {
  7186. int device;
  7187. int subsystem_vendor;
  7188. int subsystem_device;
  7189. void (*hook)(struct drm_device *dev);
  7190. };
  7191. /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
  7192. struct intel_dmi_quirk {
  7193. void (*hook)(struct drm_device *dev);
  7194. const struct dmi_system_id (*dmi_id_list)[];
  7195. };
  7196. static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
  7197. {
  7198. DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
  7199. return 1;
  7200. }
  7201. static const struct intel_dmi_quirk intel_dmi_quirks[] = {
  7202. {
  7203. .dmi_id_list = &(const struct dmi_system_id[]) {
  7204. {
  7205. .callback = intel_dmi_reverse_brightness,
  7206. .ident = "NCR Corporation",
  7207. .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
  7208. DMI_MATCH(DMI_PRODUCT_NAME, ""),
  7209. },
  7210. },
  7211. { } /* terminating entry */
  7212. },
  7213. .hook = quirk_invert_brightness,
  7214. },
  7215. };
  7216. static struct intel_quirk intel_quirks[] = {
  7217. /* HP Mini needs pipe A force quirk (LP: #322104) */
  7218. { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
  7219. /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
  7220. { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
  7221. /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
  7222. { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
  7223. /* 830/845 need to leave pipe A & dpll A up */
  7224. { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  7225. { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  7226. /* Lenovo U160 cannot use SSC on LVDS */
  7227. { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
  7228. /* Sony Vaio Y cannot use SSC on LVDS */
  7229. { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
  7230. /* Acer Aspire 5734Z must invert backlight brightness */
  7231. { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
  7232. /* Acer/eMachines G725 */
  7233. { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
  7234. /* Acer/eMachines e725 */
  7235. { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
  7236. /* Acer/Packard Bell NCL20 */
  7237. { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
  7238. };
  7239. static void intel_init_quirks(struct drm_device *dev)
  7240. {
  7241. struct pci_dev *d = dev->pdev;
  7242. int i;
  7243. for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
  7244. struct intel_quirk *q = &intel_quirks[i];
  7245. if (d->device == q->device &&
  7246. (d->subsystem_vendor == q->subsystem_vendor ||
  7247. q->subsystem_vendor == PCI_ANY_ID) &&
  7248. (d->subsystem_device == q->subsystem_device ||
  7249. q->subsystem_device == PCI_ANY_ID))
  7250. q->hook(dev);
  7251. }
  7252. for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
  7253. if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
  7254. intel_dmi_quirks[i].hook(dev);
  7255. }
  7256. }
  7257. /* Disable the VGA plane that we never use */
  7258. static void i915_disable_vga(struct drm_device *dev)
  7259. {
  7260. struct drm_i915_private *dev_priv = dev->dev_private;
  7261. u8 sr1;
  7262. u32 vga_reg;
  7263. if (HAS_PCH_SPLIT(dev))
  7264. vga_reg = CPU_VGACNTRL;
  7265. else
  7266. vga_reg = VGACNTRL;
  7267. vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
  7268. outb(SR01, VGA_SR_INDEX);
  7269. sr1 = inb(VGA_SR_DATA);
  7270. outb(sr1 | 1<<5, VGA_SR_DATA);
  7271. vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
  7272. udelay(300);
  7273. I915_WRITE(vga_reg, VGA_DISP_DISABLE);
  7274. POSTING_READ(vga_reg);
  7275. }
  7276. void intel_modeset_init_hw(struct drm_device *dev)
  7277. {
  7278. /* We attempt to init the necessary power wells early in the initialization
  7279. * time, so the subsystems that expect power to be enabled can work.
  7280. */
  7281. intel_init_power_wells(dev);
  7282. intel_prepare_ddi(dev);
  7283. intel_init_clock_gating(dev);
  7284. mutex_lock(&dev->struct_mutex);
  7285. intel_enable_gt_powersave(dev);
  7286. mutex_unlock(&dev->struct_mutex);
  7287. }
  7288. void intel_modeset_init(struct drm_device *dev)
  7289. {
  7290. struct drm_i915_private *dev_priv = dev->dev_private;
  7291. int i, ret;
  7292. drm_mode_config_init(dev);
  7293. dev->mode_config.min_width = 0;
  7294. dev->mode_config.min_height = 0;
  7295. dev->mode_config.preferred_depth = 24;
  7296. dev->mode_config.prefer_shadow = 1;
  7297. dev->mode_config.funcs = &intel_mode_funcs;
  7298. intel_init_quirks(dev);
  7299. intel_init_pm(dev);
  7300. intel_init_display(dev);
  7301. if (IS_GEN2(dev)) {
  7302. dev->mode_config.max_width = 2048;
  7303. dev->mode_config.max_height = 2048;
  7304. } else if (IS_GEN3(dev)) {
  7305. dev->mode_config.max_width = 4096;
  7306. dev->mode_config.max_height = 4096;
  7307. } else {
  7308. dev->mode_config.max_width = 8192;
  7309. dev->mode_config.max_height = 8192;
  7310. }
  7311. dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
  7312. DRM_DEBUG_KMS("%d display pipe%s available.\n",
  7313. dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
  7314. for (i = 0; i < dev_priv->num_pipe; i++) {
  7315. intel_crtc_init(dev, i);
  7316. ret = intel_plane_init(dev, i);
  7317. if (ret)
  7318. DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
  7319. }
  7320. intel_cpu_pll_init(dev);
  7321. intel_pch_pll_init(dev);
  7322. /* Just disable it once at startup */
  7323. i915_disable_vga(dev);
  7324. intel_setup_outputs(dev);
  7325. /* Just in case the BIOS is doing something questionable. */
  7326. intel_disable_fbc(dev);
  7327. }
  7328. static void
  7329. intel_connector_break_all_links(struct intel_connector *connector)
  7330. {
  7331. connector->base.dpms = DRM_MODE_DPMS_OFF;
  7332. connector->base.encoder = NULL;
  7333. connector->encoder->connectors_active = false;
  7334. connector->encoder->base.crtc = NULL;
  7335. }
  7336. static void intel_enable_pipe_a(struct drm_device *dev)
  7337. {
  7338. struct intel_connector *connector;
  7339. struct drm_connector *crt = NULL;
  7340. struct intel_load_detect_pipe load_detect_temp;
  7341. /* We can't just switch on the pipe A, we need to set things up with a
  7342. * proper mode and output configuration. As a gross hack, enable pipe A
  7343. * by enabling the load detect pipe once. */
  7344. list_for_each_entry(connector,
  7345. &dev->mode_config.connector_list,
  7346. base.head) {
  7347. if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
  7348. crt = &connector->base;
  7349. break;
  7350. }
  7351. }
  7352. if (!crt)
  7353. return;
  7354. if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
  7355. intel_release_load_detect_pipe(crt, &load_detect_temp);
  7356. }
  7357. static bool
  7358. intel_check_plane_mapping(struct intel_crtc *crtc)
  7359. {
  7360. struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
  7361. u32 reg, val;
  7362. if (dev_priv->num_pipe == 1)
  7363. return true;
  7364. reg = DSPCNTR(!crtc->plane);
  7365. val = I915_READ(reg);
  7366. if ((val & DISPLAY_PLANE_ENABLE) &&
  7367. (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
  7368. return false;
  7369. return true;
  7370. }
  7371. static void intel_sanitize_crtc(struct intel_crtc *crtc)
  7372. {
  7373. struct drm_device *dev = crtc->base.dev;
  7374. struct drm_i915_private *dev_priv = dev->dev_private;
  7375. u32 reg;
  7376. /* Clear any frame start delays used for debugging left by the BIOS */
  7377. reg = PIPECONF(crtc->cpu_transcoder);
  7378. I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
  7379. /* We need to sanitize the plane -> pipe mapping first because this will
  7380. * disable the crtc (and hence change the state) if it is wrong. Note
  7381. * that gen4+ has a fixed plane -> pipe mapping. */
  7382. if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
  7383. struct intel_connector *connector;
  7384. bool plane;
  7385. DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
  7386. crtc->base.base.id);
  7387. /* Pipe has the wrong plane attached and the plane is active.
  7388. * Temporarily change the plane mapping and disable everything
  7389. * ... */
  7390. plane = crtc->plane;
  7391. crtc->plane = !plane;
  7392. dev_priv->display.crtc_disable(&crtc->base);
  7393. crtc->plane = plane;
  7394. /* ... and break all links. */
  7395. list_for_each_entry(connector, &dev->mode_config.connector_list,
  7396. base.head) {
  7397. if (connector->encoder->base.crtc != &crtc->base)
  7398. continue;
  7399. intel_connector_break_all_links(connector);
  7400. }
  7401. WARN_ON(crtc->active);
  7402. crtc->base.enabled = false;
  7403. }
  7404. if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
  7405. crtc->pipe == PIPE_A && !crtc->active) {
  7406. /* BIOS forgot to enable pipe A, this mostly happens after
  7407. * resume. Force-enable the pipe to fix this, the update_dpms
  7408. * call below we restore the pipe to the right state, but leave
  7409. * the required bits on. */
  7410. intel_enable_pipe_a(dev);
  7411. }
  7412. /* Adjust the state of the output pipe according to whether we
  7413. * have active connectors/encoders. */
  7414. intel_crtc_update_dpms(&crtc->base);
  7415. if (crtc->active != crtc->base.enabled) {
  7416. struct intel_encoder *encoder;
  7417. /* This can happen either due to bugs in the get_hw_state
  7418. * functions or because the pipe is force-enabled due to the
  7419. * pipe A quirk. */
  7420. DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
  7421. crtc->base.base.id,
  7422. crtc->base.enabled ? "enabled" : "disabled",
  7423. crtc->active ? "enabled" : "disabled");
  7424. crtc->base.enabled = crtc->active;
  7425. /* Because we only establish the connector -> encoder ->
  7426. * crtc links if something is active, this means the
  7427. * crtc is now deactivated. Break the links. connector
  7428. * -> encoder links are only establish when things are
  7429. * actually up, hence no need to break them. */
  7430. WARN_ON(crtc->active);
  7431. for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
  7432. WARN_ON(encoder->connectors_active);
  7433. encoder->base.crtc = NULL;
  7434. }
  7435. }
  7436. }
  7437. static void intel_sanitize_encoder(struct intel_encoder *encoder)
  7438. {
  7439. struct intel_connector *connector;
  7440. struct drm_device *dev = encoder->base.dev;
  7441. /* We need to check both for a crtc link (meaning that the
  7442. * encoder is active and trying to read from a pipe) and the
  7443. * pipe itself being active. */
  7444. bool has_active_crtc = encoder->base.crtc &&
  7445. to_intel_crtc(encoder->base.crtc)->active;
  7446. if (encoder->connectors_active && !has_active_crtc) {
  7447. DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
  7448. encoder->base.base.id,
  7449. drm_get_encoder_name(&encoder->base));
  7450. /* Connector is active, but has no active pipe. This is
  7451. * fallout from our resume register restoring. Disable
  7452. * the encoder manually again. */
  7453. if (encoder->base.crtc) {
  7454. DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
  7455. encoder->base.base.id,
  7456. drm_get_encoder_name(&encoder->base));
  7457. encoder->disable(encoder);
  7458. }
  7459. /* Inconsistent output/port/pipe state happens presumably due to
  7460. * a bug in one of the get_hw_state functions. Or someplace else
  7461. * in our code, like the register restore mess on resume. Clamp
  7462. * things to off as a safer default. */
  7463. list_for_each_entry(connector,
  7464. &dev->mode_config.connector_list,
  7465. base.head) {
  7466. if (connector->encoder != encoder)
  7467. continue;
  7468. intel_connector_break_all_links(connector);
  7469. }
  7470. }
  7471. /* Enabled encoders without active connectors will be fixed in
  7472. * the crtc fixup. */
  7473. }
  7474. static void i915_redisable_vga(struct drm_device *dev)
  7475. {
  7476. struct drm_i915_private *dev_priv = dev->dev_private;
  7477. u32 vga_reg;
  7478. if (HAS_PCH_SPLIT(dev))
  7479. vga_reg = CPU_VGACNTRL;
  7480. else
  7481. vga_reg = VGACNTRL;
  7482. if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
  7483. DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
  7484. I915_WRITE(vga_reg, VGA_DISP_DISABLE);
  7485. POSTING_READ(vga_reg);
  7486. }
  7487. }
  7488. /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
  7489. * and i915 state tracking structures. */
  7490. void intel_modeset_setup_hw_state(struct drm_device *dev,
  7491. bool force_restore)
  7492. {
  7493. struct drm_i915_private *dev_priv = dev->dev_private;
  7494. enum pipe pipe;
  7495. u32 tmp;
  7496. struct intel_crtc *crtc;
  7497. struct intel_encoder *encoder;
  7498. struct intel_connector *connector;
  7499. if (HAS_DDI(dev)) {
  7500. tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
  7501. if (tmp & TRANS_DDI_FUNC_ENABLE) {
  7502. switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
  7503. case TRANS_DDI_EDP_INPUT_A_ON:
  7504. case TRANS_DDI_EDP_INPUT_A_ONOFF:
  7505. pipe = PIPE_A;
  7506. break;
  7507. case TRANS_DDI_EDP_INPUT_B_ONOFF:
  7508. pipe = PIPE_B;
  7509. break;
  7510. case TRANS_DDI_EDP_INPUT_C_ONOFF:
  7511. pipe = PIPE_C;
  7512. break;
  7513. }
  7514. crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  7515. crtc->cpu_transcoder = TRANSCODER_EDP;
  7516. DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
  7517. pipe_name(pipe));
  7518. }
  7519. }
  7520. for_each_pipe(pipe) {
  7521. crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  7522. tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
  7523. if (tmp & PIPECONF_ENABLE)
  7524. crtc->active = true;
  7525. else
  7526. crtc->active = false;
  7527. crtc->base.enabled = crtc->active;
  7528. DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
  7529. crtc->base.base.id,
  7530. crtc->active ? "enabled" : "disabled");
  7531. }
  7532. if (HAS_DDI(dev))
  7533. intel_ddi_setup_hw_pll_state(dev);
  7534. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7535. base.head) {
  7536. pipe = 0;
  7537. if (encoder->get_hw_state(encoder, &pipe)) {
  7538. encoder->base.crtc =
  7539. dev_priv->pipe_to_crtc_mapping[pipe];
  7540. } else {
  7541. encoder->base.crtc = NULL;
  7542. }
  7543. encoder->connectors_active = false;
  7544. DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
  7545. encoder->base.base.id,
  7546. drm_get_encoder_name(&encoder->base),
  7547. encoder->base.crtc ? "enabled" : "disabled",
  7548. pipe);
  7549. }
  7550. list_for_each_entry(connector, &dev->mode_config.connector_list,
  7551. base.head) {
  7552. if (connector->get_hw_state(connector)) {
  7553. connector->base.dpms = DRM_MODE_DPMS_ON;
  7554. connector->encoder->connectors_active = true;
  7555. connector->base.encoder = &connector->encoder->base;
  7556. } else {
  7557. connector->base.dpms = DRM_MODE_DPMS_OFF;
  7558. connector->base.encoder = NULL;
  7559. }
  7560. DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
  7561. connector->base.base.id,
  7562. drm_get_connector_name(&connector->base),
  7563. connector->base.encoder ? "enabled" : "disabled");
  7564. }
  7565. /* HW state is read out, now we need to sanitize this mess. */
  7566. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  7567. base.head) {
  7568. intel_sanitize_encoder(encoder);
  7569. }
  7570. for_each_pipe(pipe) {
  7571. crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
  7572. intel_sanitize_crtc(crtc);
  7573. }
  7574. if (force_restore) {
  7575. for_each_pipe(pipe) {
  7576. intel_crtc_restore_mode(dev_priv->pipe_to_crtc_mapping[pipe]);
  7577. }
  7578. i915_redisable_vga(dev);
  7579. } else {
  7580. intel_modeset_update_staged_output_state(dev);
  7581. }
  7582. intel_modeset_check_state(dev);
  7583. drm_mode_config_reset(dev);
  7584. }
  7585. void intel_modeset_gem_init(struct drm_device *dev)
  7586. {
  7587. intel_modeset_init_hw(dev);
  7588. intel_setup_overlay(dev);
  7589. intel_modeset_setup_hw_state(dev, false);
  7590. }
  7591. void intel_modeset_cleanup(struct drm_device *dev)
  7592. {
  7593. struct drm_i915_private *dev_priv = dev->dev_private;
  7594. struct drm_crtc *crtc;
  7595. struct intel_crtc *intel_crtc;
  7596. drm_kms_helper_poll_fini(dev);
  7597. mutex_lock(&dev->struct_mutex);
  7598. intel_unregister_dsm_handler();
  7599. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  7600. /* Skip inactive CRTCs */
  7601. if (!crtc->fb)
  7602. continue;
  7603. intel_crtc = to_intel_crtc(crtc);
  7604. intel_increase_pllclock(crtc);
  7605. }
  7606. intel_disable_fbc(dev);
  7607. intel_disable_gt_powersave(dev);
  7608. ironlake_teardown_rc6(dev);
  7609. if (IS_VALLEYVIEW(dev))
  7610. vlv_init_dpio(dev);
  7611. mutex_unlock(&dev->struct_mutex);
  7612. /* Disable the irq before mode object teardown, for the irq might
  7613. * enqueue unpin/hotplug work. */
  7614. drm_irq_uninstall(dev);
  7615. cancel_work_sync(&dev_priv->hotplug_work);
  7616. cancel_work_sync(&dev_priv->rps.work);
  7617. /* flush any delayed tasks or pending work */
  7618. flush_scheduled_work();
  7619. drm_mode_config_cleanup(dev);
  7620. intel_cleanup_overlay(dev);
  7621. }
  7622. /*
  7623. * Return which encoder is currently attached for connector.
  7624. */
  7625. struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
  7626. {
  7627. return &intel_attached_encoder(connector)->base;
  7628. }
  7629. void intel_connector_attach_encoder(struct intel_connector *connector,
  7630. struct intel_encoder *encoder)
  7631. {
  7632. connector->encoder = encoder;
  7633. drm_mode_connector_attach_encoder(&connector->base,
  7634. &encoder->base);
  7635. }
  7636. /*
  7637. * set vga decode state - true == enable VGA decode
  7638. */
  7639. int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
  7640. {
  7641. struct drm_i915_private *dev_priv = dev->dev_private;
  7642. u16 gmch_ctrl;
  7643. pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
  7644. if (state)
  7645. gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
  7646. else
  7647. gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
  7648. pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
  7649. return 0;
  7650. }
  7651. #ifdef CONFIG_DEBUG_FS
  7652. #include <linux/seq_file.h>
  7653. struct intel_display_error_state {
  7654. struct intel_cursor_error_state {
  7655. u32 control;
  7656. u32 position;
  7657. u32 base;
  7658. u32 size;
  7659. } cursor[I915_MAX_PIPES];
  7660. struct intel_pipe_error_state {
  7661. u32 conf;
  7662. u32 source;
  7663. u32 htotal;
  7664. u32 hblank;
  7665. u32 hsync;
  7666. u32 vtotal;
  7667. u32 vblank;
  7668. u32 vsync;
  7669. } pipe[I915_MAX_PIPES];
  7670. struct intel_plane_error_state {
  7671. u32 control;
  7672. u32 stride;
  7673. u32 size;
  7674. u32 pos;
  7675. u32 addr;
  7676. u32 surface;
  7677. u32 tile_offset;
  7678. } plane[I915_MAX_PIPES];
  7679. };
  7680. struct intel_display_error_state *
  7681. intel_display_capture_error_state(struct drm_device *dev)
  7682. {
  7683. drm_i915_private_t *dev_priv = dev->dev_private;
  7684. struct intel_display_error_state *error;
  7685. enum transcoder cpu_transcoder;
  7686. int i;
  7687. error = kmalloc(sizeof(*error), GFP_ATOMIC);
  7688. if (error == NULL)
  7689. return NULL;
  7690. for_each_pipe(i) {
  7691. cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
  7692. error->cursor[i].control = I915_READ(CURCNTR(i));
  7693. error->cursor[i].position = I915_READ(CURPOS(i));
  7694. error->cursor[i].base = I915_READ(CURBASE(i));
  7695. error->plane[i].control = I915_READ(DSPCNTR(i));
  7696. error->plane[i].stride = I915_READ(DSPSTRIDE(i));
  7697. error->plane[i].size = I915_READ(DSPSIZE(i));
  7698. error->plane[i].pos = I915_READ(DSPPOS(i));
  7699. error->plane[i].addr = I915_READ(DSPADDR(i));
  7700. if (INTEL_INFO(dev)->gen >= 4) {
  7701. error->plane[i].surface = I915_READ(DSPSURF(i));
  7702. error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
  7703. }
  7704. error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
  7705. error->pipe[i].source = I915_READ(PIPESRC(i));
  7706. error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
  7707. error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
  7708. error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
  7709. error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
  7710. error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
  7711. error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
  7712. }
  7713. return error;
  7714. }
  7715. void
  7716. intel_display_print_error_state(struct seq_file *m,
  7717. struct drm_device *dev,
  7718. struct intel_display_error_state *error)
  7719. {
  7720. drm_i915_private_t *dev_priv = dev->dev_private;
  7721. int i;
  7722. seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
  7723. for_each_pipe(i) {
  7724. seq_printf(m, "Pipe [%d]:\n", i);
  7725. seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
  7726. seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
  7727. seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
  7728. seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
  7729. seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
  7730. seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
  7731. seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
  7732. seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
  7733. seq_printf(m, "Plane [%d]:\n", i);
  7734. seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
  7735. seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
  7736. seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
  7737. seq_printf(m, " POS: %08x\n", error->plane[i].pos);
  7738. seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
  7739. if (INTEL_INFO(dev)->gen >= 4) {
  7740. seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
  7741. seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
  7742. }
  7743. seq_printf(m, "Cursor [%d]:\n", i);
  7744. seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
  7745. seq_printf(m, " POS: %08x\n", error->cursor[i].position);
  7746. seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
  7747. }
  7748. }
  7749. #endif