cpuidle-tegra30.c 4.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186
  1. /*
  2. * CPU idle driver for Tegra CPUs
  3. *
  4. * Copyright (c) 2010-2012, NVIDIA Corporation.
  5. * Copyright (c) 2011 Google, Inc.
  6. * Author: Colin Cross <ccross@android.com>
  7. * Gary King <gking@nvidia.com>
  8. *
  9. * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful, but WITHOUT
  17. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  19. * more details.
  20. */
  21. #include <linux/kernel.h>
  22. #include <linux/module.h>
  23. #include <linux/cpuidle.h>
  24. #include <linux/cpu_pm.h>
  25. #include <linux/clockchips.h>
  26. #include <linux/clk/tegra.h>
  27. #include <asm/cpuidle.h>
  28. #include <asm/proc-fns.h>
  29. #include <asm/suspend.h>
  30. #include <asm/smp_plat.h>
  31. #include "pm.h"
  32. #include "sleep.h"
  33. #ifdef CONFIG_PM_SLEEP
  34. static int tegra30_idle_lp2(struct cpuidle_device *dev,
  35. struct cpuidle_driver *drv,
  36. int index);
  37. #endif
  38. static struct cpuidle_driver tegra_idle_driver = {
  39. .name = "tegra_idle",
  40. .owner = THIS_MODULE,
  41. #ifdef CONFIG_PM_SLEEP
  42. .state_count = 2,
  43. #else
  44. .state_count = 1,
  45. #endif
  46. .states = {
  47. [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
  48. #ifdef CONFIG_PM_SLEEP
  49. [1] = {
  50. .enter = tegra30_idle_lp2,
  51. .exit_latency = 2000,
  52. .target_residency = 2200,
  53. .power_usage = 0,
  54. .flags = CPUIDLE_FLAG_TIME_VALID,
  55. .name = "powered-down",
  56. .desc = "CPU power gated",
  57. },
  58. #endif
  59. },
  60. };
  61. static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
  62. #ifdef CONFIG_PM_SLEEP
  63. static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
  64. struct cpuidle_driver *drv,
  65. int index)
  66. {
  67. struct cpuidle_state *state = &drv->states[index];
  68. u32 cpu_on_time = state->exit_latency;
  69. u32 cpu_off_time = state->target_residency - state->exit_latency;
  70. /* All CPUs entering LP2 is not working.
  71. * Don't let CPU0 enter LP2 when any secondary CPU is online.
  72. */
  73. if (num_online_cpus() > 1 || !tegra_cpu_rail_off_ready()) {
  74. cpu_do_idle();
  75. return false;
  76. }
  77. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
  78. tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
  79. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
  80. return true;
  81. }
  82. #ifdef CONFIG_SMP
  83. static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
  84. struct cpuidle_driver *drv,
  85. int index)
  86. {
  87. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
  88. smp_wmb();
  89. save_cpu_arch_register();
  90. cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
  91. restore_cpu_arch_register();
  92. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
  93. return true;
  94. }
  95. #else
  96. static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
  97. struct cpuidle_driver *drv,
  98. int index)
  99. {
  100. return true;
  101. }
  102. #endif
  103. static int tegra30_idle_lp2(struct cpuidle_device *dev,
  104. struct cpuidle_driver *drv,
  105. int index)
  106. {
  107. u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
  108. bool entered_lp2 = false;
  109. bool last_cpu;
  110. local_fiq_disable();
  111. last_cpu = tegra_set_cpu_in_lp2(cpu);
  112. cpu_pm_enter();
  113. if (cpu == 0) {
  114. if (last_cpu)
  115. entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv,
  116. index);
  117. else
  118. cpu_do_idle();
  119. } else {
  120. entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index);
  121. }
  122. cpu_pm_exit();
  123. tegra_clear_cpu_in_lp2(cpu);
  124. local_fiq_enable();
  125. smp_rmb();
  126. return (entered_lp2) ? index : 0;
  127. }
  128. #endif
  129. int __init tegra30_cpuidle_init(void)
  130. {
  131. int ret;
  132. unsigned int cpu;
  133. struct cpuidle_device *dev;
  134. struct cpuidle_driver *drv = &tegra_idle_driver;
  135. #ifdef CONFIG_PM_SLEEP
  136. tegra_tear_down_cpu = tegra30_tear_down_cpu;
  137. #endif
  138. ret = cpuidle_register_driver(&tegra_idle_driver);
  139. if (ret) {
  140. pr_err("CPUidle driver registration failed\n");
  141. return ret;
  142. }
  143. for_each_possible_cpu(cpu) {
  144. dev = &per_cpu(tegra_idle_device, cpu);
  145. dev->cpu = cpu;
  146. ret = cpuidle_register_device(dev);
  147. if (ret) {
  148. pr_err("CPU%u: CPUidle device registration failed\n",
  149. cpu);
  150. return ret;
  151. }
  152. }
  153. return 0;
  154. }