intel_ringbuffer.h 4.5 KB

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  1. #ifndef _INTEL_RINGBUFFER_H_
  2. #define _INTEL_RINGBUFFER_H_
  3. enum {
  4. RCS = 0x0,
  5. VCS,
  6. BCS,
  7. I915_NUM_RINGS,
  8. };
  9. struct intel_hw_status_page {
  10. u32 __iomem *page_addr;
  11. unsigned int gfx_addr;
  12. struct drm_i915_gem_object *obj;
  13. };
  14. #define I915_RING_READ(reg) i915_safe_read(dev_priv, reg)
  15. #define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL(ring->mmio_base))
  16. #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL(ring->mmio_base), val)
  17. #define I915_READ_START(ring) I915_RING_READ(RING_START(ring->mmio_base))
  18. #define I915_WRITE_START(ring, val) I915_WRITE(RING_START(ring->mmio_base), val)
  19. #define I915_READ_HEAD(ring) I915_RING_READ(RING_HEAD(ring->mmio_base))
  20. #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD(ring->mmio_base), val)
  21. #define I915_READ_CTL(ring) I915_RING_READ(RING_CTL(ring->mmio_base))
  22. #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL(ring->mmio_base), val)
  23. #define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID(ring->mmio_base))
  24. #define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0(ring->mmio_base))
  25. #define I915_READ_SYNC_1(ring) I915_RING_READ(RING_SYNC_1(ring->mmio_base))
  26. struct intel_ring_buffer {
  27. const char *name;
  28. enum intel_ring_id {
  29. RING_RENDER = 0x1,
  30. RING_BSD = 0x2,
  31. RING_BLT = 0x4,
  32. } id;
  33. u32 mmio_base;
  34. void *virtual_start;
  35. struct drm_device *dev;
  36. struct drm_i915_gem_object *obj;
  37. u32 actual_head;
  38. u32 head;
  39. u32 tail;
  40. int space;
  41. int size;
  42. int effective_size;
  43. struct intel_hw_status_page status_page;
  44. u32 irq_seqno; /* last seq seem at irq time */
  45. u32 waiting_seqno;
  46. u32 sync_seqno[I915_NUM_RINGS-1];
  47. atomic_t irq_refcount;
  48. bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
  49. void (*irq_put)(struct intel_ring_buffer *ring);
  50. int (*init)(struct intel_ring_buffer *ring);
  51. void (*write_tail)(struct intel_ring_buffer *ring,
  52. u32 value);
  53. void (*flush)(struct intel_ring_buffer *ring,
  54. u32 invalidate_domains,
  55. u32 flush_domains);
  56. int (*add_request)(struct intel_ring_buffer *ring,
  57. u32 *seqno);
  58. u32 (*get_seqno)(struct intel_ring_buffer *ring);
  59. int (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
  60. u32 offset, u32 length);
  61. void (*cleanup)(struct intel_ring_buffer *ring);
  62. /**
  63. * List of objects currently involved in rendering from the
  64. * ringbuffer.
  65. *
  66. * Includes buffers having the contents of their GPU caches
  67. * flushed, not necessarily primitives. last_rendering_seqno
  68. * represents when the rendering involved will be completed.
  69. *
  70. * A reference is held on the buffer while on this list.
  71. */
  72. struct list_head active_list;
  73. /**
  74. * List of breadcrumbs associated with GPU requests currently
  75. * outstanding.
  76. */
  77. struct list_head request_list;
  78. /**
  79. * List of objects currently pending a GPU write flush.
  80. *
  81. * All elements on this list will belong to either the
  82. * active_list or flushing_list, last_rendering_seqno can
  83. * be used to differentiate between the two elements.
  84. */
  85. struct list_head gpu_write_list;
  86. /**
  87. * Do we have some not yet emitted requests outstanding?
  88. */
  89. u32 outstanding_lazy_request;
  90. wait_queue_head_t irq_queue;
  91. drm_local_map_t map;
  92. void *private;
  93. };
  94. static inline u32
  95. intel_ring_sync_index(struct intel_ring_buffer *ring,
  96. struct intel_ring_buffer *other)
  97. {
  98. int idx;
  99. /*
  100. * cs -> 0 = vcs, 1 = bcs
  101. * vcs -> 0 = bcs, 1 = cs,
  102. * bcs -> 0 = cs, 1 = vcs.
  103. */
  104. idx = (other - ring) - 1;
  105. if (idx < 0)
  106. idx += I915_NUM_RINGS;
  107. return idx;
  108. }
  109. static inline u32
  110. intel_read_status_page(struct intel_ring_buffer *ring,
  111. int reg)
  112. {
  113. return ioread32(ring->status_page.page_addr + reg);
  114. }
  115. void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
  116. int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n);
  117. int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
  118. static inline void intel_ring_emit(struct intel_ring_buffer *ring,
  119. u32 data)
  120. {
  121. iowrite32(data, ring->virtual_start + ring->tail);
  122. ring->tail += 4;
  123. }
  124. void intel_ring_advance(struct intel_ring_buffer *ring);
  125. u32 intel_ring_get_seqno(struct intel_ring_buffer *ring);
  126. int intel_ring_sync(struct intel_ring_buffer *ring,
  127. struct intel_ring_buffer *to,
  128. u32 seqno);
  129. int intel_init_render_ring_buffer(struct drm_device *dev);
  130. int intel_init_bsd_ring_buffer(struct drm_device *dev);
  131. int intel_init_blt_ring_buffer(struct drm_device *dev);
  132. u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
  133. void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
  134. #endif /* _INTEL_RINGBUFFER_H_ */