at91sam9n12.dtsi 15 KB

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  1. /*
  2. * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC
  3. *
  4. * Copyright (C) 2012 Atmel,
  5. * 2012 Hong Xu <hong.xu@atmel.com>
  6. *
  7. * Licensed under GPLv2 or later.
  8. */
  9. #include "skeleton.dtsi"
  10. #include <dt-bindings/pinctrl/at91.h>
  11. #include <dt-bindings/interrupt-controller/irq.h>
  12. #include <dt-bindings/gpio/gpio.h>
  13. / {
  14. model = "Atmel AT91SAM9N12 SoC";
  15. compatible = "atmel,at91sam9n12";
  16. interrupt-parent = <&aic>;
  17. aliases {
  18. serial0 = &dbgu;
  19. serial1 = &usart0;
  20. serial2 = &usart1;
  21. serial3 = &usart2;
  22. serial4 = &usart3;
  23. gpio0 = &pioA;
  24. gpio1 = &pioB;
  25. gpio2 = &pioC;
  26. gpio3 = &pioD;
  27. tcb0 = &tcb0;
  28. tcb1 = &tcb1;
  29. i2c0 = &i2c0;
  30. i2c1 = &i2c1;
  31. ssc0 = &ssc0;
  32. };
  33. cpus {
  34. #address-cells = <0>;
  35. #size-cells = <0>;
  36. cpu {
  37. compatible = "arm,arm926ej-s";
  38. device_type = "cpu";
  39. };
  40. };
  41. memory {
  42. reg = <0x20000000 0x10000000>;
  43. };
  44. ahb {
  45. compatible = "simple-bus";
  46. #address-cells = <1>;
  47. #size-cells = <1>;
  48. ranges;
  49. apb {
  50. compatible = "simple-bus";
  51. #address-cells = <1>;
  52. #size-cells = <1>;
  53. ranges;
  54. aic: interrupt-controller@fffff000 {
  55. #interrupt-cells = <3>;
  56. compatible = "atmel,at91rm9200-aic";
  57. interrupt-controller;
  58. reg = <0xfffff000 0x200>;
  59. atmel,external-irqs = <31>;
  60. };
  61. ramc0: ramc@ffffe800 {
  62. compatible = "atmel,at91sam9g45-ddramc";
  63. reg = <0xffffe800 0x200>;
  64. };
  65. pmc: pmc@fffffc00 {
  66. compatible = "atmel,at91rm9200-pmc";
  67. reg = <0xfffffc00 0x100>;
  68. };
  69. rstc@fffffe00 {
  70. compatible = "atmel,at91sam9g45-rstc";
  71. reg = <0xfffffe00 0x10>;
  72. };
  73. pit: timer@fffffe30 {
  74. compatible = "atmel,at91sam9260-pit";
  75. reg = <0xfffffe30 0xf>;
  76. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  77. };
  78. shdwc@fffffe10 {
  79. compatible = "atmel,at91sam9x5-shdwc";
  80. reg = <0xfffffe10 0x10>;
  81. };
  82. mmc0: mmc@f0008000 {
  83. compatible = "atmel,hsmci";
  84. reg = <0xf0008000 0x600>;
  85. interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
  86. dmas = <&dma 1 0>;
  87. dma-names = "rxtx";
  88. #address-cells = <1>;
  89. #size-cells = <0>;
  90. status = "disabled";
  91. };
  92. tcb0: timer@f8008000 {
  93. compatible = "atmel,at91sam9x5-tcb";
  94. reg = <0xf8008000 0x100>;
  95. interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
  96. };
  97. tcb1: timer@f800c000 {
  98. compatible = "atmel,at91sam9x5-tcb";
  99. reg = <0xf800c000 0x100>;
  100. interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
  101. };
  102. dma: dma-controller@ffffec00 {
  103. compatible = "atmel,at91sam9g45-dma";
  104. reg = <0xffffec00 0x200>;
  105. interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
  106. #dma-cells = <2>;
  107. };
  108. pinctrl@fffff400 {
  109. #address-cells = <1>;
  110. #size-cells = <1>;
  111. compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
  112. ranges = <0xfffff400 0xfffff400 0x800>;
  113. atmel,mux-mask = <
  114. /* A B C */
  115. 0xffffffff 0xffe07983 0x00000000 /* pioA */
  116. 0x00040000 0x00047e0f 0x00000000 /* pioB */
  117. 0xfdffffff 0x07c00000 0xb83fffff /* pioC */
  118. 0x003fffff 0x003f8000 0x00000000 /* pioD */
  119. >;
  120. /* shared pinctrl settings */
  121. dbgu {
  122. pinctrl_dbgu: dbgu-0 {
  123. atmel,pins =
  124. <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */
  125. AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA10 periph with pullup */
  126. };
  127. };
  128. usart0 {
  129. pinctrl_usart0: usart0-0 {
  130. atmel,pins =
  131. <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
  132. AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA0 periph A */
  133. };
  134. pinctrl_usart0_rts: usart0_rts-0 {
  135. atmel,pins =
  136. <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A */
  137. };
  138. pinctrl_usart0_cts: usart0_cts-0 {
  139. atmel,pins =
  140. <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA3 periph A */
  141. };
  142. };
  143. usart1 {
  144. pinctrl_usart1: usart1-0 {
  145. atmel,pins =
  146. <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
  147. AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */
  148. };
  149. };
  150. usart2 {
  151. pinctrl_usart2: usart2-0 {
  152. atmel,pins =
  153. <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
  154. AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA7 periph A */
  155. };
  156. pinctrl_usart2_rts: usart2_rts-0 {
  157. atmel,pins =
  158. <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */
  159. };
  160. pinctrl_usart2_cts: usart2_cts-0 {
  161. atmel,pins =
  162. <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */
  163. };
  164. };
  165. usart3 {
  166. pinctrl_usart3: usart3-0 {
  167. atmel,pins =
  168. <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PC23 periph B with pullup */
  169. AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */
  170. };
  171. pinctrl_usart3_rts: usart3_rts-0 {
  172. atmel,pins =
  173. <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
  174. };
  175. pinctrl_usart3_cts: usart3_cts-0 {
  176. atmel,pins =
  177. <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
  178. };
  179. };
  180. uart0 {
  181. pinctrl_uart0: uart0-0 {
  182. atmel,pins =
  183. <AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */
  184. AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC8 periph C */
  185. };
  186. };
  187. uart1 {
  188. pinctrl_uart1: uart1-0 {
  189. atmel,pins =
  190. <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC17 periph C with pullup */
  191. AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */
  192. };
  193. };
  194. nand {
  195. pinctrl_nand: nand-0 {
  196. atmel,pins =
  197. <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PD5 gpio RDY pin pull_up*/
  198. AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD4 gpio enable pin pull_up */
  199. };
  200. };
  201. mmc0 {
  202. pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
  203. atmel,pins =
  204. <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
  205. AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
  206. AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA15 periph A with pullup */
  207. };
  208. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  209. atmel,pins =
  210. <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
  211. AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
  212. AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
  213. };
  214. pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
  215. atmel,pins =
  216. <AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */
  217. AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA12 periph B with pullup */
  218. AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA13 periph B with pullup */
  219. AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA14 periph B with pullup */
  220. };
  221. };
  222. ssc0 {
  223. pinctrl_ssc0_tx: ssc0_tx-0 {
  224. atmel,pins =
  225. <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
  226. AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
  227. AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */
  228. };
  229. pinctrl_ssc0_rx: ssc0_rx-0 {
  230. atmel,pins =
  231. <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
  232. AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
  233. AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
  234. };
  235. };
  236. spi0 {
  237. pinctrl_spi0: spi0-0 {
  238. atmel,pins =
  239. <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A SPI0_MISO pin */
  240. AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A SPI0_MOSI pin */
  241. AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */
  242. };
  243. };
  244. spi1 {
  245. pinctrl_spi1: spi1-0 {
  246. atmel,pins =
  247. <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA21 periph B SPI1_MISO pin */
  248. AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B SPI1_MOSI pin */
  249. AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */
  250. };
  251. };
  252. tcb0 {
  253. pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
  254. atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  255. };
  256. pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
  257. atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  258. };
  259. pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
  260. atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  261. };
  262. pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
  263. atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  264. };
  265. pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
  266. atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  267. };
  268. pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
  269. atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  270. };
  271. pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
  272. atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  273. };
  274. pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
  275. atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  276. };
  277. pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
  278. atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  279. };
  280. };
  281. tcb1 {
  282. pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
  283. atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  284. };
  285. pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
  286. atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  287. };
  288. pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
  289. atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  290. };
  291. pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
  292. atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  293. };
  294. pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
  295. atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  296. };
  297. pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
  298. atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  299. };
  300. pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
  301. atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  302. };
  303. pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
  304. atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  305. };
  306. pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
  307. atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
  308. };
  309. };
  310. pioA: gpio@fffff400 {
  311. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  312. reg = <0xfffff400 0x200>;
  313. interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
  314. #gpio-cells = <2>;
  315. gpio-controller;
  316. interrupt-controller;
  317. #interrupt-cells = <2>;
  318. };
  319. pioB: gpio@fffff600 {
  320. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  321. reg = <0xfffff600 0x200>;
  322. interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
  323. #gpio-cells = <2>;
  324. gpio-controller;
  325. interrupt-controller;
  326. #interrupt-cells = <2>;
  327. };
  328. pioC: gpio@fffff800 {
  329. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  330. reg = <0xfffff800 0x200>;
  331. interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
  332. #gpio-cells = <2>;
  333. gpio-controller;
  334. interrupt-controller;
  335. #interrupt-cells = <2>;
  336. };
  337. pioD: gpio@fffffa00 {
  338. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  339. reg = <0xfffffa00 0x200>;
  340. interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
  341. #gpio-cells = <2>;
  342. gpio-controller;
  343. interrupt-controller;
  344. #interrupt-cells = <2>;
  345. };
  346. };
  347. dbgu: serial@fffff200 {
  348. compatible = "atmel,at91sam9260-usart";
  349. reg = <0xfffff200 0x200>;
  350. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  351. pinctrl-names = "default";
  352. pinctrl-0 = <&pinctrl_dbgu>;
  353. status = "disabled";
  354. };
  355. ssc0: ssc@f0010000 {
  356. compatible = "atmel,at91sam9g45-ssc";
  357. reg = <0xf0010000 0x4000>;
  358. interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
  359. pinctrl-names = "default";
  360. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  361. status = "disabled";
  362. };
  363. usart0: serial@f801c000 {
  364. compatible = "atmel,at91sam9260-usart";
  365. reg = <0xf801c000 0x4000>;
  366. interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
  367. pinctrl-names = "default";
  368. pinctrl-0 = <&pinctrl_usart0>;
  369. status = "disabled";
  370. };
  371. usart1: serial@f8020000 {
  372. compatible = "atmel,at91sam9260-usart";
  373. reg = <0xf8020000 0x4000>;
  374. interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
  375. pinctrl-names = "default";
  376. pinctrl-0 = <&pinctrl_usart1>;
  377. status = "disabled";
  378. };
  379. usart2: serial@f8024000 {
  380. compatible = "atmel,at91sam9260-usart";
  381. reg = <0xf8024000 0x4000>;
  382. interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
  383. pinctrl-names = "default";
  384. pinctrl-0 = <&pinctrl_usart2>;
  385. status = "disabled";
  386. };
  387. usart3: serial@f8028000 {
  388. compatible = "atmel,at91sam9260-usart";
  389. reg = <0xf8028000 0x4000>;
  390. interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
  391. pinctrl-names = "default";
  392. pinctrl-0 = <&pinctrl_usart3>;
  393. status = "disabled";
  394. };
  395. i2c0: i2c@f8010000 {
  396. compatible = "atmel,at91sam9x5-i2c";
  397. reg = <0xf8010000 0x100>;
  398. interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
  399. dmas = <&dma 1 13>,
  400. <&dma 1 14>;
  401. dma-names = "tx", "rx";
  402. #address-cells = <1>;
  403. #size-cells = <0>;
  404. status = "disabled";
  405. };
  406. i2c1: i2c@f8014000 {
  407. compatible = "atmel,at91sam9x5-i2c";
  408. reg = <0xf8014000 0x100>;
  409. interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
  410. dmas = <&dma 1 15>,
  411. <&dma 1 16>;
  412. dma-names = "tx", "rx";
  413. #address-cells = <1>;
  414. #size-cells = <0>;
  415. status = "disabled";
  416. };
  417. spi0: spi@f0000000 {
  418. #address-cells = <1>;
  419. #size-cells = <0>;
  420. compatible = "atmel,at91rm9200-spi";
  421. reg = <0xf0000000 0x100>;
  422. interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
  423. pinctrl-names = "default";
  424. pinctrl-0 = <&pinctrl_spi0>;
  425. status = "disabled";
  426. };
  427. spi1: spi@f0004000 {
  428. #address-cells = <1>;
  429. #size-cells = <0>;
  430. compatible = "atmel,at91rm9200-spi";
  431. reg = <0xf0004000 0x100>;
  432. interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
  433. pinctrl-names = "default";
  434. pinctrl-0 = <&pinctrl_spi1>;
  435. status = "disabled";
  436. };
  437. watchdog@fffffe40 {
  438. compatible = "atmel,at91sam9260-wdt";
  439. reg = <0xfffffe40 0x10>;
  440. status = "disabled";
  441. };
  442. };
  443. nand0: nand@40000000 {
  444. compatible = "atmel,at91rm9200-nand";
  445. #address-cells = <1>;
  446. #size-cells = <1>;
  447. reg = < 0x40000000 0x10000000
  448. 0xffffe000 0x00000600
  449. 0xffffe600 0x00000200
  450. 0x00108000 0x00018000
  451. >;
  452. atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
  453. atmel,nand-addr-offset = <21>;
  454. atmel,nand-cmd-offset = <22>;
  455. pinctrl-names = "default";
  456. pinctrl-0 = <&pinctrl_nand>;
  457. gpios = <&pioD 5 GPIO_ACTIVE_HIGH
  458. &pioD 4 GPIO_ACTIVE_HIGH
  459. 0
  460. >;
  461. status = "disabled";
  462. };
  463. usb0: ohci@00500000 {
  464. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  465. reg = <0x00500000 0x00100000>;
  466. interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
  467. status = "disabled";
  468. };
  469. };
  470. i2c@0 {
  471. compatible = "i2c-gpio";
  472. gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
  473. &pioA 31 GPIO_ACTIVE_HIGH /* scl */
  474. >;
  475. i2c-gpio,sda-open-drain;
  476. i2c-gpio,scl-open-drain;
  477. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  478. #address-cells = <1>;
  479. #size-cells = <0>;
  480. status = "disabled";
  481. };
  482. };