am33xx.dtsi 9.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423
  1. /*
  2. * Device Tree Source for AM33XX SoC
  3. *
  4. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. */
  10. /include/ "skeleton.dtsi"
  11. / {
  12. compatible = "ti,am33xx";
  13. interrupt-parent = <&intc>;
  14. aliases {
  15. serial0 = &uart1;
  16. serial1 = &uart2;
  17. serial2 = &uart3;
  18. serial3 = &uart4;
  19. serial4 = &uart5;
  20. serial5 = &uart6;
  21. d_can0 = &dcan0;
  22. d_can1 = &dcan1;
  23. };
  24. cpus {
  25. #address-cells = <1>;
  26. #size-cells = <0>;
  27. cpu@0 {
  28. compatible = "arm,cortex-a8";
  29. device_type = "cpu";
  30. reg = <0>;
  31. /*
  32. * To consider voltage drop between PMIC and SoC,
  33. * tolerance value is reduced to 2% from 4% and
  34. * voltage value is increased as a precaution.
  35. */
  36. operating-points = <
  37. /* kHz uV */
  38. 720000 1285000
  39. 600000 1225000
  40. 500000 1125000
  41. 275000 1125000
  42. >;
  43. voltage-tolerance = <2>; /* 2 percentage */
  44. clock-latency = <300000>; /* From omap-cpufreq driver */
  45. };
  46. };
  47. /*
  48. * The soc node represents the soc top level view. It is uses for IPs
  49. * that are not memory mapped in the MPU view or for the MPU itself.
  50. */
  51. soc {
  52. compatible = "ti,omap-infra";
  53. mpu {
  54. compatible = "ti,omap3-mpu";
  55. ti,hwmods = "mpu";
  56. };
  57. };
  58. am33xx_pinmux: pinmux@44e10800 {
  59. compatible = "pinctrl-single";
  60. reg = <0x44e10800 0x0238>;
  61. #address-cells = <1>;
  62. #size-cells = <0>;
  63. pinctrl-single,register-width = <32>;
  64. pinctrl-single,function-mask = <0x7f>;
  65. };
  66. /*
  67. * XXX: Use a flat representation of the AM33XX interconnect.
  68. * The real AM33XX interconnect network is quite complex.Since
  69. * that will not bring real advantage to represent that in DT
  70. * for the moment, just use a fake OCP bus entry to represent
  71. * the whole bus hierarchy.
  72. */
  73. ocp {
  74. compatible = "simple-bus";
  75. #address-cells = <1>;
  76. #size-cells = <1>;
  77. ranges;
  78. ti,hwmods = "l3_main";
  79. intc: interrupt-controller@48200000 {
  80. compatible = "ti,omap2-intc";
  81. interrupt-controller;
  82. #interrupt-cells = <1>;
  83. ti,intc-size = <128>;
  84. reg = <0x48200000 0x1000>;
  85. };
  86. gpio0: gpio@44e07000 {
  87. compatible = "ti,omap4-gpio";
  88. ti,hwmods = "gpio1";
  89. gpio-controller;
  90. #gpio-cells = <2>;
  91. interrupt-controller;
  92. #interrupt-cells = <1>;
  93. reg = <0x44e07000 0x1000>;
  94. interrupts = <96>;
  95. };
  96. gpio1: gpio@4804c000 {
  97. compatible = "ti,omap4-gpio";
  98. ti,hwmods = "gpio2";
  99. gpio-controller;
  100. #gpio-cells = <2>;
  101. interrupt-controller;
  102. #interrupt-cells = <1>;
  103. reg = <0x4804c000 0x1000>;
  104. interrupts = <98>;
  105. };
  106. gpio2: gpio@481ac000 {
  107. compatible = "ti,omap4-gpio";
  108. ti,hwmods = "gpio3";
  109. gpio-controller;
  110. #gpio-cells = <2>;
  111. interrupt-controller;
  112. #interrupt-cells = <1>;
  113. reg = <0x481ac000 0x1000>;
  114. interrupts = <32>;
  115. };
  116. gpio3: gpio@481ae000 {
  117. compatible = "ti,omap4-gpio";
  118. ti,hwmods = "gpio4";
  119. gpio-controller;
  120. #gpio-cells = <2>;
  121. interrupt-controller;
  122. #interrupt-cells = <1>;
  123. reg = <0x481ae000 0x1000>;
  124. interrupts = <62>;
  125. };
  126. uart1: serial@44e09000 {
  127. compatible = "ti,omap3-uart";
  128. ti,hwmods = "uart1";
  129. clock-frequency = <48000000>;
  130. reg = <0x44e09000 0x2000>;
  131. interrupts = <72>;
  132. status = "disabled";
  133. };
  134. uart2: serial@48022000 {
  135. compatible = "ti,omap3-uart";
  136. ti,hwmods = "uart2";
  137. clock-frequency = <48000000>;
  138. reg = <0x48022000 0x2000>;
  139. interrupts = <73>;
  140. status = "disabled";
  141. };
  142. uart3: serial@48024000 {
  143. compatible = "ti,omap3-uart";
  144. ti,hwmods = "uart3";
  145. clock-frequency = <48000000>;
  146. reg = <0x48024000 0x2000>;
  147. interrupts = <74>;
  148. status = "disabled";
  149. };
  150. uart4: serial@481a6000 {
  151. compatible = "ti,omap3-uart";
  152. ti,hwmods = "uart4";
  153. clock-frequency = <48000000>;
  154. reg = <0x481a6000 0x2000>;
  155. interrupts = <44>;
  156. status = "disabled";
  157. };
  158. uart5: serial@481a8000 {
  159. compatible = "ti,omap3-uart";
  160. ti,hwmods = "uart5";
  161. clock-frequency = <48000000>;
  162. reg = <0x481a8000 0x2000>;
  163. interrupts = <45>;
  164. status = "disabled";
  165. };
  166. uart6: serial@481aa000 {
  167. compatible = "ti,omap3-uart";
  168. ti,hwmods = "uart6";
  169. clock-frequency = <48000000>;
  170. reg = <0x481aa000 0x2000>;
  171. interrupts = <46>;
  172. status = "disabled";
  173. };
  174. i2c0: i2c@44e0b000 {
  175. compatible = "ti,omap4-i2c";
  176. #address-cells = <1>;
  177. #size-cells = <0>;
  178. ti,hwmods = "i2c1";
  179. reg = <0x44e0b000 0x1000>;
  180. interrupts = <70>;
  181. status = "disabled";
  182. };
  183. i2c1: i2c@4802a000 {
  184. compatible = "ti,omap4-i2c";
  185. #address-cells = <1>;
  186. #size-cells = <0>;
  187. ti,hwmods = "i2c2";
  188. reg = <0x4802a000 0x1000>;
  189. interrupts = <71>;
  190. status = "disabled";
  191. };
  192. i2c2: i2c@4819c000 {
  193. compatible = "ti,omap4-i2c";
  194. #address-cells = <1>;
  195. #size-cells = <0>;
  196. ti,hwmods = "i2c3";
  197. reg = <0x4819c000 0x1000>;
  198. interrupts = <30>;
  199. status = "disabled";
  200. };
  201. wdt2: wdt@44e35000 {
  202. compatible = "ti,omap3-wdt";
  203. ti,hwmods = "wd_timer2";
  204. reg = <0x44e35000 0x1000>;
  205. interrupts = <91>;
  206. };
  207. dcan0: d_can@481cc000 {
  208. compatible = "bosch,d_can";
  209. ti,hwmods = "d_can0";
  210. reg = <0x481cc000 0x2000
  211. 0x44e10644 0x4>;
  212. interrupts = <52>;
  213. status = "disabled";
  214. };
  215. dcan1: d_can@481d0000 {
  216. compatible = "bosch,d_can";
  217. ti,hwmods = "d_can1";
  218. reg = <0x481d0000 0x2000
  219. 0x44e10644 0x4>;
  220. interrupts = <55>;
  221. status = "disabled";
  222. };
  223. timer1: timer@44e31000 {
  224. compatible = "ti,am335x-timer-1ms";
  225. reg = <0x44e31000 0x400>;
  226. interrupts = <67>;
  227. ti,hwmods = "timer1";
  228. ti,timer-alwon;
  229. };
  230. timer2: timer@48040000 {
  231. compatible = "ti,am335x-timer";
  232. reg = <0x48040000 0x400>;
  233. interrupts = <68>;
  234. ti,hwmods = "timer2";
  235. };
  236. timer3: timer@48042000 {
  237. compatible = "ti,am335x-timer";
  238. reg = <0x48042000 0x400>;
  239. interrupts = <69>;
  240. ti,hwmods = "timer3";
  241. };
  242. timer4: timer@48044000 {
  243. compatible = "ti,am335x-timer";
  244. reg = <0x48044000 0x400>;
  245. interrupts = <92>;
  246. ti,hwmods = "timer4";
  247. ti,timer-pwm;
  248. };
  249. timer5: timer@48046000 {
  250. compatible = "ti,am335x-timer";
  251. reg = <0x48046000 0x400>;
  252. interrupts = <93>;
  253. ti,hwmods = "timer5";
  254. ti,timer-pwm;
  255. };
  256. timer6: timer@48048000 {
  257. compatible = "ti,am335x-timer";
  258. reg = <0x48048000 0x400>;
  259. interrupts = <94>;
  260. ti,hwmods = "timer6";
  261. ti,timer-pwm;
  262. };
  263. timer7: timer@4804a000 {
  264. compatible = "ti,am335x-timer";
  265. reg = <0x4804a000 0x400>;
  266. interrupts = <95>;
  267. ti,hwmods = "timer7";
  268. ti,timer-pwm;
  269. };
  270. rtc@44e3e000 {
  271. compatible = "ti,da830-rtc";
  272. reg = <0x44e3e000 0x1000>;
  273. interrupts = <75
  274. 76>;
  275. ti,hwmods = "rtc";
  276. };
  277. spi0: spi@48030000 {
  278. compatible = "ti,omap4-mcspi";
  279. #address-cells = <1>;
  280. #size-cells = <0>;
  281. reg = <0x48030000 0x400>;
  282. interrupts = <65>;
  283. ti,spi-num-cs = <2>;
  284. ti,hwmods = "spi0";
  285. status = "disabled";
  286. };
  287. spi1: spi@481a0000 {
  288. compatible = "ti,omap4-mcspi";
  289. #address-cells = <1>;
  290. #size-cells = <0>;
  291. reg = <0x481a0000 0x400>;
  292. interrupts = <125>;
  293. ti,spi-num-cs = <2>;
  294. ti,hwmods = "spi1";
  295. status = "disabled";
  296. };
  297. usb@47400000 {
  298. compatible = "ti,musb-am33xx";
  299. reg = <0x47400000 0x1000 /* usbss */
  300. 0x47401000 0x800 /* musb instance 0 */
  301. 0x47401800 0x800>; /* musb instance 1 */
  302. interrupts = <17 /* usbss */
  303. 18 /* musb instance 0 */
  304. 19>; /* musb instance 1 */
  305. multipoint = <1>;
  306. num-eps = <16>;
  307. ram-bits = <12>;
  308. port0-mode = <3>;
  309. port1-mode = <3>;
  310. power = <250>;
  311. ti,hwmods = "usb_otg_hs";
  312. };
  313. mac: ethernet@4a100000 {
  314. compatible = "ti,cpsw";
  315. ti,hwmods = "cpgmac0";
  316. cpdma_channels = <8>;
  317. ale_entries = <1024>;
  318. bd_ram_size = <0x2000>;
  319. no_bd_ram = <0>;
  320. rx_descs = <64>;
  321. mac_control = <0x20>;
  322. slaves = <2>;
  323. active_slave = <0>;
  324. cpts_clock_mult = <0x80000000>;
  325. cpts_clock_shift = <29>;
  326. reg = <0x4a100000 0x800
  327. 0x4a101200 0x100>;
  328. #address-cells = <1>;
  329. #size-cells = <1>;
  330. interrupt-parent = <&intc>;
  331. /*
  332. * c0_rx_thresh_pend
  333. * c0_rx_pend
  334. * c0_tx_pend
  335. * c0_misc_pend
  336. */
  337. interrupts = <40 41 42 43>;
  338. ranges;
  339. davinci_mdio: mdio@4a101000 {
  340. compatible = "ti,davinci_mdio";
  341. #address-cells = <1>;
  342. #size-cells = <0>;
  343. ti,hwmods = "davinci_mdio";
  344. bus_freq = <1000000>;
  345. reg = <0x4a101000 0x100>;
  346. };
  347. cpsw_emac0: slave@4a100200 {
  348. /* Filled in by U-Boot */
  349. mac-address = [ 00 00 00 00 00 00 ];
  350. };
  351. cpsw_emac1: slave@4a100300 {
  352. /* Filled in by U-Boot */
  353. mac-address = [ 00 00 00 00 00 00 ];
  354. };
  355. };
  356. ocmcram: ocmcram@40300000 {
  357. compatible = "ti,am3352-ocmcram";
  358. reg = <0x40300000 0x10000>;
  359. ti,hwmods = "ocmcram";
  360. ti,no_idle_on_suspend;
  361. };
  362. wkup_m3: wkup_m3@44d00000 {
  363. compatible = "ti,am3353-wkup-m3";
  364. reg = <0x44d00000 0x4000 /* M3 UMEM */
  365. 0x44d80000 0x2000>; /* M3 DMEM */
  366. ti,hwmods = "wkup_m3";
  367. };
  368. gpmc: gpmc@50000000 {
  369. compatible = "ti,am3352-gpmc";
  370. ti,hwmods = "gpmc";
  371. reg = <0x50000000 0x2000>;
  372. interrupts = <100>;
  373. num-cs = <7>;
  374. num-waitpins = <2>;
  375. #address-cells = <2>;
  376. #size-cells = <1>;
  377. status = "disabled";
  378. };
  379. };
  380. };