board-3430sdp.c 15 KB

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  1. /*
  2. * linux/arch/arm/mach-omap2/board-3430sdp.c
  3. *
  4. * Copyright (C) 2007 Texas Instruments
  5. *
  6. * Modified from mach-omap2/board-generic.c
  7. *
  8. * Initial code: Syed Mohammed Khasim
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/delay.h>
  18. #include <linux/input.h>
  19. #include <linux/input/matrix_keypad.h>
  20. #include <linux/spi/spi.h>
  21. #include <linux/i2c/twl.h>
  22. #include <linux/regulator/machine.h>
  23. #include <linux/io.h>
  24. #include <linux/gpio.h>
  25. #include <linux/mmc/host.h>
  26. #include <linux/platform_data/spi-omap2-mcspi.h>
  27. #include <asm/mach-types.h>
  28. #include <asm/mach/arch.h>
  29. #include <asm/mach/map.h>
  30. #include "common.h"
  31. #include <plat/dma.h>
  32. #include <plat/gpmc.h>
  33. #include <video/omapdss.h>
  34. #include <video/omap-panel-tfp410.h>
  35. #include "gpmc-smc91x.h"
  36. #include "board-flash.h"
  37. #include "mux.h"
  38. #include "sdram-qimonda-hyb18m512160af-6.h"
  39. #include "hsmmc.h"
  40. #include "pm.h"
  41. #include "control.h"
  42. #include "common-board-devices.h"
  43. #define CONFIG_DISABLE_HFCLK 1
  44. #define SDP3430_TS_GPIO_IRQ_SDPV1 3
  45. #define SDP3430_TS_GPIO_IRQ_SDPV2 2
  46. #define ENABLE_VAUX3_DEDICATED 0x03
  47. #define ENABLE_VAUX3_DEV_GRP 0x20
  48. #define TWL4030_MSECURE_GPIO 22
  49. static uint32_t board_keymap[] = {
  50. KEY(0, 0, KEY_LEFT),
  51. KEY(0, 1, KEY_RIGHT),
  52. KEY(0, 2, KEY_A),
  53. KEY(0, 3, KEY_B),
  54. KEY(0, 4, KEY_C),
  55. KEY(1, 0, KEY_DOWN),
  56. KEY(1, 1, KEY_UP),
  57. KEY(1, 2, KEY_E),
  58. KEY(1, 3, KEY_F),
  59. KEY(1, 4, KEY_G),
  60. KEY(2, 0, KEY_ENTER),
  61. KEY(2, 1, KEY_I),
  62. KEY(2, 2, KEY_J),
  63. KEY(2, 3, KEY_K),
  64. KEY(2, 4, KEY_3),
  65. KEY(3, 0, KEY_M),
  66. KEY(3, 1, KEY_N),
  67. KEY(3, 2, KEY_O),
  68. KEY(3, 3, KEY_P),
  69. KEY(3, 4, KEY_Q),
  70. KEY(4, 0, KEY_R),
  71. KEY(4, 1, KEY_4),
  72. KEY(4, 2, KEY_T),
  73. KEY(4, 3, KEY_U),
  74. KEY(4, 4, KEY_D),
  75. KEY(5, 0, KEY_V),
  76. KEY(5, 1, KEY_W),
  77. KEY(5, 2, KEY_L),
  78. KEY(5, 3, KEY_S),
  79. KEY(5, 4, KEY_H),
  80. 0
  81. };
  82. static struct matrix_keymap_data board_map_data = {
  83. .keymap = board_keymap,
  84. .keymap_size = ARRAY_SIZE(board_keymap),
  85. };
  86. static struct twl4030_keypad_data sdp3430_kp_data = {
  87. .keymap_data = &board_map_data,
  88. .rows = 5,
  89. .cols = 6,
  90. .rep = 1,
  91. };
  92. #define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 8
  93. #define SDP3430_LCD_PANEL_ENABLE_GPIO 5
  94. static struct gpio sdp3430_dss_gpios[] __initdata = {
  95. {SDP3430_LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW, "LCD reset" },
  96. {SDP3430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW, "LCD Backlight"},
  97. };
  98. static void __init sdp3430_display_init(void)
  99. {
  100. int r;
  101. r = gpio_request_array(sdp3430_dss_gpios,
  102. ARRAY_SIZE(sdp3430_dss_gpios));
  103. if (r)
  104. printk(KERN_ERR "failed to get LCD control GPIOs\n");
  105. }
  106. static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev)
  107. {
  108. gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 1);
  109. gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 1);
  110. return 0;
  111. }
  112. static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev)
  113. {
  114. gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 0);
  115. gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 0);
  116. }
  117. static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev)
  118. {
  119. return 0;
  120. }
  121. static void sdp3430_panel_disable_tv(struct omap_dss_device *dssdev)
  122. {
  123. }
  124. static struct omap_dss_device sdp3430_lcd_device = {
  125. .name = "lcd",
  126. .driver_name = "sharp_ls_panel",
  127. .type = OMAP_DISPLAY_TYPE_DPI,
  128. .phy.dpi.data_lines = 16,
  129. .platform_enable = sdp3430_panel_enable_lcd,
  130. .platform_disable = sdp3430_panel_disable_lcd,
  131. };
  132. static struct tfp410_platform_data dvi_panel = {
  133. .power_down_gpio = -1,
  134. };
  135. static struct omap_dss_device sdp3430_dvi_device = {
  136. .name = "dvi",
  137. .type = OMAP_DISPLAY_TYPE_DPI,
  138. .driver_name = "tfp410",
  139. .data = &dvi_panel,
  140. .phy.dpi.data_lines = 24,
  141. };
  142. static struct omap_dss_device sdp3430_tv_device = {
  143. .name = "tv",
  144. .driver_name = "venc",
  145. .type = OMAP_DISPLAY_TYPE_VENC,
  146. .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
  147. .platform_enable = sdp3430_panel_enable_tv,
  148. .platform_disable = sdp3430_panel_disable_tv,
  149. };
  150. static struct omap_dss_device *sdp3430_dss_devices[] = {
  151. &sdp3430_lcd_device,
  152. &sdp3430_dvi_device,
  153. &sdp3430_tv_device,
  154. };
  155. static struct omap_dss_board_info sdp3430_dss_data = {
  156. .num_devices = ARRAY_SIZE(sdp3430_dss_devices),
  157. .devices = sdp3430_dss_devices,
  158. .default_device = &sdp3430_lcd_device,
  159. };
  160. static struct omap2_hsmmc_info mmc[] = {
  161. {
  162. .mmc = 1,
  163. /* 8 bits (default) requires S6.3 == ON,
  164. * so the SIM card isn't used; else 4 bits.
  165. */
  166. .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
  167. .gpio_wp = 4,
  168. .deferred = true,
  169. },
  170. {
  171. .mmc = 2,
  172. .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
  173. .gpio_wp = 7,
  174. .deferred = true,
  175. },
  176. {} /* Terminator */
  177. };
  178. static int sdp3430_twl_gpio_setup(struct device *dev,
  179. unsigned gpio, unsigned ngpio)
  180. {
  181. /* gpio + 0 is "mmc0_cd" (input/IRQ),
  182. * gpio + 1 is "mmc1_cd" (input/IRQ)
  183. */
  184. mmc[0].gpio_cd = gpio + 0;
  185. mmc[1].gpio_cd = gpio + 1;
  186. omap_hsmmc_late_init(mmc);
  187. /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
  188. gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "sub_lcd_en_bkl");
  189. /* gpio + 15 is "sub_lcd_nRST" (output) */
  190. gpio_request_one(gpio + 15, GPIOF_OUT_INIT_LOW, "sub_lcd_nRST");
  191. return 0;
  192. }
  193. static struct twl4030_gpio_platform_data sdp3430_gpio_data = {
  194. .pulldowns = BIT(2) | BIT(6) | BIT(8) | BIT(13)
  195. | BIT(16) | BIT(17),
  196. .setup = sdp3430_twl_gpio_setup,
  197. };
  198. /* regulator consumer mappings */
  199. /* ads7846 on SPI */
  200. static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
  201. REGULATOR_SUPPLY("vcc", "spi1.0"),
  202. };
  203. static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
  204. REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
  205. };
  206. static struct regulator_consumer_supply sdp3430_vsim_supplies[] = {
  207. REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
  208. };
  209. static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = {
  210. REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
  211. };
  212. /*
  213. * Apply all the fixed voltages since most versions of U-Boot
  214. * don't bother with that initialization.
  215. */
  216. /* VAUX1 for mainboard (irda and sub-lcd) */
  217. static struct regulator_init_data sdp3430_vaux1 = {
  218. .constraints = {
  219. .min_uV = 2800000,
  220. .max_uV = 2800000,
  221. .apply_uV = true,
  222. .valid_modes_mask = REGULATOR_MODE_NORMAL
  223. | REGULATOR_MODE_STANDBY,
  224. .valid_ops_mask = REGULATOR_CHANGE_MODE
  225. | REGULATOR_CHANGE_STATUS,
  226. },
  227. };
  228. /* VAUX2 for camera module */
  229. static struct regulator_init_data sdp3430_vaux2 = {
  230. .constraints = {
  231. .min_uV = 2800000,
  232. .max_uV = 2800000,
  233. .apply_uV = true,
  234. .valid_modes_mask = REGULATOR_MODE_NORMAL
  235. | REGULATOR_MODE_STANDBY,
  236. .valid_ops_mask = REGULATOR_CHANGE_MODE
  237. | REGULATOR_CHANGE_STATUS,
  238. },
  239. };
  240. /* VAUX3 for LCD board */
  241. static struct regulator_init_data sdp3430_vaux3 = {
  242. .constraints = {
  243. .min_uV = 2800000,
  244. .max_uV = 2800000,
  245. .apply_uV = true,
  246. .valid_modes_mask = REGULATOR_MODE_NORMAL
  247. | REGULATOR_MODE_STANDBY,
  248. .valid_ops_mask = REGULATOR_CHANGE_MODE
  249. | REGULATOR_CHANGE_STATUS,
  250. },
  251. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vaux3_supplies),
  252. .consumer_supplies = sdp3430_vaux3_supplies,
  253. };
  254. /* VAUX4 for OMAP VDD_CSI2 (camera) */
  255. static struct regulator_init_data sdp3430_vaux4 = {
  256. .constraints = {
  257. .min_uV = 1800000,
  258. .max_uV = 1800000,
  259. .apply_uV = true,
  260. .valid_modes_mask = REGULATOR_MODE_NORMAL
  261. | REGULATOR_MODE_STANDBY,
  262. .valid_ops_mask = REGULATOR_CHANGE_MODE
  263. | REGULATOR_CHANGE_STATUS,
  264. },
  265. };
  266. /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
  267. static struct regulator_init_data sdp3430_vmmc1 = {
  268. .constraints = {
  269. .min_uV = 1850000,
  270. .max_uV = 3150000,
  271. .valid_modes_mask = REGULATOR_MODE_NORMAL
  272. | REGULATOR_MODE_STANDBY,
  273. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
  274. | REGULATOR_CHANGE_MODE
  275. | REGULATOR_CHANGE_STATUS,
  276. },
  277. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc1_supplies),
  278. .consumer_supplies = sdp3430_vmmc1_supplies,
  279. };
  280. /* VMMC2 for MMC2 card */
  281. static struct regulator_init_data sdp3430_vmmc2 = {
  282. .constraints = {
  283. .min_uV = 1850000,
  284. .max_uV = 1850000,
  285. .apply_uV = true,
  286. .valid_modes_mask = REGULATOR_MODE_NORMAL
  287. | REGULATOR_MODE_STANDBY,
  288. .valid_ops_mask = REGULATOR_CHANGE_MODE
  289. | REGULATOR_CHANGE_STATUS,
  290. },
  291. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc2_supplies),
  292. .consumer_supplies = sdp3430_vmmc2_supplies,
  293. };
  294. /* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
  295. static struct regulator_init_data sdp3430_vsim = {
  296. .constraints = {
  297. .min_uV = 1800000,
  298. .max_uV = 3000000,
  299. .valid_modes_mask = REGULATOR_MODE_NORMAL
  300. | REGULATOR_MODE_STANDBY,
  301. .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
  302. | REGULATOR_CHANGE_MODE
  303. | REGULATOR_CHANGE_STATUS,
  304. },
  305. .num_consumer_supplies = ARRAY_SIZE(sdp3430_vsim_supplies),
  306. .consumer_supplies = sdp3430_vsim_supplies,
  307. };
  308. static struct twl4030_platform_data sdp3430_twldata = {
  309. /* platform_data for children goes here */
  310. .gpio = &sdp3430_gpio_data,
  311. .keypad = &sdp3430_kp_data,
  312. .vaux1 = &sdp3430_vaux1,
  313. .vaux2 = &sdp3430_vaux2,
  314. .vaux3 = &sdp3430_vaux3,
  315. .vaux4 = &sdp3430_vaux4,
  316. .vmmc1 = &sdp3430_vmmc1,
  317. .vmmc2 = &sdp3430_vmmc2,
  318. .vsim = &sdp3430_vsim,
  319. };
  320. static int __init omap3430_i2c_init(void)
  321. {
  322. /* i2c1 for PMIC only */
  323. omap3_pmic_get_config(&sdp3430_twldata,
  324. TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
  325. TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO,
  326. TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
  327. sdp3430_twldata.vdac->constraints.apply_uV = true;
  328. sdp3430_twldata.vpll2->constraints.apply_uV = true;
  329. sdp3430_twldata.vpll2->constraints.name = "VDVI";
  330. omap3_pmic_init("twl4030", &sdp3430_twldata);
  331. /* i2c2 on camera connector (for sensor control) and optional isp1301 */
  332. omap_register_i2c_bus(2, 400, NULL, 0);
  333. /* i2c3 on display connector (for DVI, tfp410) */
  334. omap_register_i2c_bus(3, 400, NULL, 0);
  335. return 0;
  336. }
  337. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  338. static struct omap_smc91x_platform_data board_smc91x_data = {
  339. .cs = 3,
  340. .flags = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 |
  341. IORESOURCE_IRQ_LOWLEVEL,
  342. };
  343. static void __init board_smc91x_init(void)
  344. {
  345. if (omap_rev() > OMAP3430_REV_ES1_0)
  346. board_smc91x_data.gpio_irq = 6;
  347. else
  348. board_smc91x_data.gpio_irq = 29;
  349. gpmc_smc91x_init(&board_smc91x_data);
  350. }
  351. #else
  352. static inline void board_smc91x_init(void)
  353. {
  354. }
  355. #endif
  356. static void enable_board_wakeup_source(void)
  357. {
  358. /* T2 interrupt line (keypad) */
  359. omap_mux_init_signal("sys_nirq",
  360. OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
  361. }
  362. static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
  363. .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
  364. .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
  365. .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
  366. .phy_reset = true,
  367. .reset_gpio_port[0] = 57,
  368. .reset_gpio_port[1] = 61,
  369. .reset_gpio_port[2] = -EINVAL
  370. };
  371. #ifdef CONFIG_OMAP_MUX
  372. static struct omap_board_mux board_mux[] __initdata = {
  373. { .reg_offset = OMAP_MUX_TERMINATOR },
  374. };
  375. #else
  376. #define board_mux NULL
  377. #endif
  378. /*
  379. * SDP3430 V2 Board CS organization
  380. * Different from SDP3430 V1. Now 4 switches used to specify CS
  381. *
  382. * See also the Switch S8 settings in the comments.
  383. */
  384. static char chip_sel_3430[][GPMC_CS_NUM] = {
  385. {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */
  386. {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */
  387. {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */
  388. };
  389. static struct mtd_partition sdp_nor_partitions[] = {
  390. /* bootloader (U-Boot, etc) in first sector */
  391. {
  392. .name = "Bootloader-NOR",
  393. .offset = 0,
  394. .size = SZ_256K,
  395. .mask_flags = MTD_WRITEABLE, /* force read-only */
  396. },
  397. /* bootloader params in the next sector */
  398. {
  399. .name = "Params-NOR",
  400. .offset = MTDPART_OFS_APPEND,
  401. .size = SZ_256K,
  402. .mask_flags = 0,
  403. },
  404. /* kernel */
  405. {
  406. .name = "Kernel-NOR",
  407. .offset = MTDPART_OFS_APPEND,
  408. .size = SZ_2M,
  409. .mask_flags = 0
  410. },
  411. /* file system */
  412. {
  413. .name = "Filesystem-NOR",
  414. .offset = MTDPART_OFS_APPEND,
  415. .size = MTDPART_SIZ_FULL,
  416. .mask_flags = 0
  417. }
  418. };
  419. static struct mtd_partition sdp_onenand_partitions[] = {
  420. {
  421. .name = "X-Loader-OneNAND",
  422. .offset = 0,
  423. .size = 4 * (64 * 2048),
  424. .mask_flags = MTD_WRITEABLE /* force read-only */
  425. },
  426. {
  427. .name = "U-Boot-OneNAND",
  428. .offset = MTDPART_OFS_APPEND,
  429. .size = 2 * (64 * 2048),
  430. .mask_flags = MTD_WRITEABLE /* force read-only */
  431. },
  432. {
  433. .name = "U-Boot Environment-OneNAND",
  434. .offset = MTDPART_OFS_APPEND,
  435. .size = 1 * (64 * 2048),
  436. },
  437. {
  438. .name = "Kernel-OneNAND",
  439. .offset = MTDPART_OFS_APPEND,
  440. .size = 16 * (64 * 2048),
  441. },
  442. {
  443. .name = "File System-OneNAND",
  444. .offset = MTDPART_OFS_APPEND,
  445. .size = MTDPART_SIZ_FULL,
  446. },
  447. };
  448. static struct mtd_partition sdp_nand_partitions[] = {
  449. /* All the partition sizes are listed in terms of NAND block size */
  450. {
  451. .name = "X-Loader-NAND",
  452. .offset = 0,
  453. .size = 4 * (64 * 2048),
  454. .mask_flags = MTD_WRITEABLE, /* force read-only */
  455. },
  456. {
  457. .name = "U-Boot-NAND",
  458. .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
  459. .size = 10 * (64 * 2048),
  460. .mask_flags = MTD_WRITEABLE, /* force read-only */
  461. },
  462. {
  463. .name = "Boot Env-NAND",
  464. .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */
  465. .size = 6 * (64 * 2048),
  466. },
  467. {
  468. .name = "Kernel-NAND",
  469. .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
  470. .size = 40 * (64 * 2048),
  471. },
  472. {
  473. .name = "File System - NAND",
  474. .size = MTDPART_SIZ_FULL,
  475. .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
  476. },
  477. };
  478. static struct flash_partitions sdp_flash_partitions[] = {
  479. {
  480. .parts = sdp_nor_partitions,
  481. .nr_parts = ARRAY_SIZE(sdp_nor_partitions),
  482. },
  483. {
  484. .parts = sdp_onenand_partitions,
  485. .nr_parts = ARRAY_SIZE(sdp_onenand_partitions),
  486. },
  487. {
  488. .parts = sdp_nand_partitions,
  489. .nr_parts = ARRAY_SIZE(sdp_nand_partitions),
  490. },
  491. };
  492. static void __init omap_3430sdp_init(void)
  493. {
  494. int gpio_pendown;
  495. omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
  496. omap_hsmmc_init(mmc);
  497. omap3430_i2c_init();
  498. omap_display_init(&sdp3430_dss_data);
  499. if (omap_rev() > OMAP3430_REV_ES1_0)
  500. gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV2;
  501. else
  502. gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1;
  503. omap_ads7846_init(1, gpio_pendown, 310, NULL);
  504. omap_serial_init();
  505. omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL);
  506. usb_musb_init(NULL);
  507. board_smc91x_init();
  508. board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
  509. sdp3430_display_init();
  510. enable_board_wakeup_source();
  511. usbhs_init(&usbhs_bdata);
  512. }
  513. MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
  514. /* Maintainer: Syed Khasim - Texas Instruments Inc */
  515. .atag_offset = 0x100,
  516. .reserve = omap_reserve,
  517. .map_io = omap3_map_io,
  518. .init_early = omap3430_init_early,
  519. .init_irq = omap3_init_irq,
  520. .handle_irq = omap3_intc_handle_irq,
  521. .init_machine = omap_3430sdp_init,
  522. .init_late = omap3430_init_late,
  523. .timer = &omap3_timer,
  524. .restart = omap_prcm_restart,
  525. MACHINE_END