Kconfig 24 KB

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  1. #
  2. # For a description of the syntax of this configuration file,
  3. # see Documentation/kbuild/kconfig-language.txt.
  4. #
  5. mainmenu "Blackfin Kernel Configuration"
  6. config MMU
  7. bool
  8. default n
  9. config FPU
  10. bool
  11. default n
  12. config RWSEM_GENERIC_SPINLOCK
  13. bool
  14. default y
  15. config RWSEM_XCHGADD_ALGORITHM
  16. bool
  17. default n
  18. config BLACKFIN
  19. bool
  20. default y
  21. select HAVE_IDE
  22. select HAVE_OPROFILE
  23. config ZONE_DMA
  24. bool
  25. default y
  26. config GENERIC_FIND_NEXT_BIT
  27. bool
  28. default y
  29. config GENERIC_HWEIGHT
  30. bool
  31. default y
  32. config GENERIC_HARDIRQS
  33. bool
  34. default y
  35. config GENERIC_IRQ_PROBE
  36. bool
  37. default y
  38. config GENERIC_GPIO
  39. bool
  40. default y
  41. config FORCE_MAX_ZONEORDER
  42. int
  43. default "14"
  44. config GENERIC_CALIBRATE_DELAY
  45. bool
  46. default y
  47. config HARDWARE_PM
  48. def_bool y
  49. depends on OPROFILE
  50. source "init/Kconfig"
  51. source "kernel/Kconfig.preempt"
  52. menu "Blackfin Processor Options"
  53. comment "Processor and Board Settings"
  54. choice
  55. prompt "CPU"
  56. default BF533
  57. config BF522
  58. bool "BF522"
  59. help
  60. BF522 Processor Support.
  61. config BF523
  62. bool "BF523"
  63. help
  64. BF523 Processor Support.
  65. config BF524
  66. bool "BF524"
  67. help
  68. BF524 Processor Support.
  69. config BF525
  70. bool "BF525"
  71. help
  72. BF525 Processor Support.
  73. config BF526
  74. bool "BF526"
  75. help
  76. BF526 Processor Support.
  77. config BF527
  78. bool "BF527"
  79. help
  80. BF527 Processor Support.
  81. config BF531
  82. bool "BF531"
  83. help
  84. BF531 Processor Support.
  85. config BF532
  86. bool "BF532"
  87. help
  88. BF532 Processor Support.
  89. config BF533
  90. bool "BF533"
  91. help
  92. BF533 Processor Support.
  93. config BF534
  94. bool "BF534"
  95. help
  96. BF534 Processor Support.
  97. config BF536
  98. bool "BF536"
  99. help
  100. BF536 Processor Support.
  101. config BF537
  102. bool "BF537"
  103. help
  104. BF537 Processor Support.
  105. config BF542
  106. bool "BF542"
  107. help
  108. BF542 Processor Support.
  109. config BF544
  110. bool "BF544"
  111. help
  112. BF544 Processor Support.
  113. config BF547
  114. bool "BF547"
  115. help
  116. BF547 Processor Support.
  117. config BF548
  118. bool "BF548"
  119. help
  120. BF548 Processor Support.
  121. config BF549
  122. bool "BF549"
  123. help
  124. BF549 Processor Support.
  125. config BF561
  126. bool "BF561"
  127. help
  128. BF561 Processor Support.
  129. endchoice
  130. config BF_REV_MIN
  131. int
  132. default 0 if (BF52x || BF54x)
  133. default 2 if (BF537 || BF536 || BF534)
  134. default 3 if (BF561 ||BF533 || BF532 || BF531)
  135. config BF_REV_MAX
  136. int
  137. default 2 if (BF52x || BF54x)
  138. default 3 if (BF537 || BF536 || BF534)
  139. default 5 if (BF561)
  140. default 6 if (BF533 || BF532 || BF531)
  141. choice
  142. prompt "Silicon Rev"
  143. default BF_REV_0_1 if (BF52x || BF54x)
  144. default BF_REV_0_2 if (BF534 || BF536 || BF537)
  145. default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF561)
  146. config BF_REV_0_0
  147. bool "0.0"
  148. depends on (BF52x || BF54x)
  149. config BF_REV_0_1
  150. bool "0.1"
  151. depends on (BF52x || BF54x)
  152. config BF_REV_0_2
  153. bool "0.2"
  154. depends on (BF52x || BF537 || BF536 || BF534 || BF54x)
  155. config BF_REV_0_3
  156. bool "0.3"
  157. depends on (BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
  158. config BF_REV_0_4
  159. bool "0.4"
  160. depends on (BF561 || BF533 || BF532 || BF531)
  161. config BF_REV_0_5
  162. bool "0.5"
  163. depends on (BF561 || BF533 || BF532 || BF531)
  164. config BF_REV_0_6
  165. bool "0.6"
  166. depends on (BF533 || BF532 || BF531)
  167. config BF_REV_ANY
  168. bool "any"
  169. config BF_REV_NONE
  170. bool "none"
  171. endchoice
  172. config BF52x
  173. bool
  174. depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
  175. default y
  176. config BF53x
  177. bool
  178. depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
  179. default y
  180. config BF54x
  181. bool
  182. depends on (BF542 || BF544 || BF547 || BF548 || BF549)
  183. default y
  184. config MEM_GENERIC_BOARD
  185. bool
  186. depends on GENERIC_BOARD
  187. default y
  188. config MEM_MT48LC64M4A2FB_7E
  189. bool
  190. depends on (BFIN533_STAMP)
  191. default y
  192. config MEM_MT48LC16M16A2TG_75
  193. bool
  194. depends on (BFIN533_EZKIT || BFIN561_EZKIT \
  195. || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
  196. || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
  197. default y
  198. config MEM_MT48LC32M8A2_75
  199. bool
  200. depends on (BFIN537_STAMP || PNAV10)
  201. default y
  202. config MEM_MT48LC8M32B2B5_7
  203. bool
  204. depends on (BFIN561_BLUETECHNIX_CM)
  205. default y
  206. config MEM_MT48LC32M16A2TG_75
  207. bool
  208. depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
  209. default y
  210. source "arch/blackfin/mach-bf527/Kconfig"
  211. source "arch/blackfin/mach-bf533/Kconfig"
  212. source "arch/blackfin/mach-bf561/Kconfig"
  213. source "arch/blackfin/mach-bf537/Kconfig"
  214. source "arch/blackfin/mach-bf548/Kconfig"
  215. menu "Board customizations"
  216. config CMDLINE_BOOL
  217. bool "Default bootloader kernel arguments"
  218. config CMDLINE
  219. string "Initial kernel command string"
  220. depends on CMDLINE_BOOL
  221. default "console=ttyBF0,57600"
  222. help
  223. If you don't have a boot loader capable of passing a command line string
  224. to the kernel, you may specify one here. As a minimum, you should specify
  225. the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
  226. config BOOT_LOAD
  227. hex "Kernel load address for booting"
  228. default "0x1000"
  229. range 0x1000 0x20000000
  230. help
  231. This option allows you to set the load address of the kernel.
  232. This can be useful if you are on a board which has a small amount
  233. of memory or you wish to reserve some memory at the beginning of
  234. the address space.
  235. Note that you need to keep this value above 4k (0x1000) as this
  236. memory region is used to capture NULL pointer references as well
  237. as some core kernel functions.
  238. config ROM_BASE
  239. hex "Kernel ROM Base"
  240. default "0x20040000"
  241. range 0x20000000 0x20400000 if !(BF54x || BF561)
  242. range 0x20000000 0x30000000 if (BF54x || BF561)
  243. help
  244. comment "Clock/PLL Setup"
  245. config CLKIN_HZ
  246. int "Frequency of the crystal on the board in Hz"
  247. default "11059200" if BFIN533_STAMP
  248. default "27000000" if BFIN533_EZKIT
  249. default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
  250. default "30000000" if BFIN561_EZKIT
  251. default "24576000" if PNAV10
  252. default "10000000" if BFIN532_IP0X
  253. help
  254. The frequency of CLKIN crystal oscillator on the board in Hz.
  255. Warning: This value should match the crystal on the board. Otherwise,
  256. peripherals won't work properly.
  257. config BFIN_KERNEL_CLOCK
  258. bool "Re-program Clocks while Kernel boots?"
  259. default n
  260. help
  261. This option decides if kernel clocks are re-programed from the
  262. bootloader settings. If the clocks are not set, the SDRAM settings
  263. are also not changed, and the Bootloader does 100% of the hardware
  264. configuration.
  265. config PLL_BYPASS
  266. bool "Bypass PLL"
  267. depends on BFIN_KERNEL_CLOCK
  268. default n
  269. config CLKIN_HALF
  270. bool "Half Clock In"
  271. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  272. default n
  273. help
  274. If this is set the clock will be divided by 2, before it goes to the PLL.
  275. config VCO_MULT
  276. int "VCO Multiplier"
  277. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  278. range 1 64
  279. default "22" if BFIN533_EZKIT
  280. default "45" if BFIN533_STAMP
  281. default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM)
  282. default "22" if BFIN533_BLUETECHNIX_CM
  283. default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
  284. default "20" if BFIN561_EZKIT
  285. default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD)
  286. help
  287. This controls the frequency of the on-chip PLL. This can be between 1 and 64.
  288. PLL Frequency = (Crystal Frequency) * (this setting)
  289. choice
  290. prompt "Core Clock Divider"
  291. depends on BFIN_KERNEL_CLOCK
  292. default CCLK_DIV_1
  293. help
  294. This sets the frequency of the core. It can be 1, 2, 4 or 8
  295. Core Frequency = (PLL frequency) / (this setting)
  296. config CCLK_DIV_1
  297. bool "1"
  298. config CCLK_DIV_2
  299. bool "2"
  300. config CCLK_DIV_4
  301. bool "4"
  302. config CCLK_DIV_8
  303. bool "8"
  304. endchoice
  305. config SCLK_DIV
  306. int "System Clock Divider"
  307. depends on BFIN_KERNEL_CLOCK
  308. range 1 15
  309. default 5
  310. help
  311. This sets the frequency of the system clock (including SDRAM or DDR).
  312. This can be between 1 and 15
  313. System Clock = (PLL frequency) / (this setting)
  314. choice
  315. prompt "DDR SDRAM Chip Type"
  316. depends on BFIN_KERNEL_CLOCK
  317. depends on BF54x
  318. default MEM_MT46V32M16_5B
  319. config MEM_MT46V32M16_6T
  320. bool "MT46V32M16_6T"
  321. config MEM_MT46V32M16_5B
  322. bool "MT46V32M16_5B"
  323. endchoice
  324. config MAX_MEM_SIZE
  325. int "Max SDRAM Memory Size in MBytes"
  326. depends on !MPU
  327. default 512
  328. help
  329. This is the max memory size that the kernel will create CPLB
  330. tables for. Your system will not be able to handle any more.
  331. #
  332. # Max & Min Speeds for various Chips
  333. #
  334. config MAX_VCO_HZ
  335. int
  336. default 600000000 if BF522
  337. default 400000000 if BF523
  338. default 400000000 if BF524
  339. default 600000000 if BF525
  340. default 400000000 if BF526
  341. default 600000000 if BF527
  342. default 400000000 if BF531
  343. default 400000000 if BF532
  344. default 750000000 if BF533
  345. default 500000000 if BF534
  346. default 400000000 if BF536
  347. default 600000000 if BF537
  348. default 533333333 if BF538
  349. default 533333333 if BF539
  350. default 600000000 if BF542
  351. default 533333333 if BF544
  352. default 600000000 if BF547
  353. default 600000000 if BF548
  354. default 533333333 if BF549
  355. default 600000000 if BF561
  356. config MIN_VCO_HZ
  357. int
  358. default 50000000
  359. config MAX_SCLK_HZ
  360. int
  361. default 133333333
  362. config MIN_SCLK_HZ
  363. int
  364. default 27000000
  365. comment "Kernel Timer/Scheduler"
  366. source kernel/Kconfig.hz
  367. config GENERIC_TIME
  368. bool "Generic time"
  369. default y
  370. config GENERIC_CLOCKEVENTS
  371. bool "Generic clock events"
  372. depends on GENERIC_TIME
  373. default y
  374. config CYCLES_CLOCKSOURCE
  375. bool "Use 'CYCLES' as a clocksource (EXPERIMENTAL)"
  376. depends on EXPERIMENTAL
  377. depends on GENERIC_CLOCKEVENTS
  378. depends on !BFIN_SCRATCH_REG_CYCLES
  379. default n
  380. help
  381. If you say Y here, you will enable support for using the 'cycles'
  382. registers as a clock source. Doing so means you will be unable to
  383. safely write to the 'cycles' register during runtime. You will
  384. still be able to read it (such as for performance monitoring), but
  385. writing the registers will most likely crash the kernel.
  386. source kernel/time/Kconfig
  387. comment "Misc"
  388. choice
  389. prompt "Blackfin Exception Scratch Register"
  390. default BFIN_SCRATCH_REG_RETN
  391. help
  392. Select the resource to reserve for the Exception handler:
  393. - RETN: Non-Maskable Interrupt (NMI)
  394. - RETE: Exception Return (JTAG/ICE)
  395. - CYCLES: Performance counter
  396. If you are unsure, please select "RETN".
  397. config BFIN_SCRATCH_REG_RETN
  398. bool "RETN"
  399. help
  400. Use the RETN register in the Blackfin exception handler
  401. as a stack scratch register. This means you cannot
  402. safely use NMI on the Blackfin while running Linux, but
  403. you can debug the system with a JTAG ICE and use the
  404. CYCLES performance registers.
  405. If you are unsure, please select "RETN".
  406. config BFIN_SCRATCH_REG_RETE
  407. bool "RETE"
  408. help
  409. Use the RETE register in the Blackfin exception handler
  410. as a stack scratch register. This means you cannot
  411. safely use a JTAG ICE while debugging a Blackfin board,
  412. but you can safely use the CYCLES performance registers
  413. and the NMI.
  414. If you are unsure, please select "RETN".
  415. config BFIN_SCRATCH_REG_CYCLES
  416. bool "CYCLES"
  417. help
  418. Use the CYCLES register in the Blackfin exception handler
  419. as a stack scratch register. This means you cannot
  420. safely use the CYCLES performance registers on a Blackfin
  421. board at anytime, but you can debug the system with a JTAG
  422. ICE and use the NMI.
  423. If you are unsure, please select "RETN".
  424. endchoice
  425. endmenu
  426. menu "Blackfin Kernel Optimizations"
  427. comment "Memory Optimizations"
  428. config I_ENTRY_L1
  429. bool "Locate interrupt entry code in L1 Memory"
  430. default y
  431. help
  432. If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
  433. into L1 instruction memory. (less latency)
  434. config EXCPT_IRQ_SYSC_L1
  435. bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
  436. default y
  437. help
  438. If enabled, the entire ASM lowlevel exception and interrupt entry code
  439. (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
  440. (less latency)
  441. config DO_IRQ_L1
  442. bool "Locate frequently called do_irq dispatcher function in L1 Memory"
  443. default y
  444. help
  445. If enabled, the frequently called do_irq dispatcher function is linked
  446. into L1 instruction memory. (less latency)
  447. config CORE_TIMER_IRQ_L1
  448. bool "Locate frequently called timer_interrupt() function in L1 Memory"
  449. default y
  450. help
  451. If enabled, the frequently called timer_interrupt() function is linked
  452. into L1 instruction memory. (less latency)
  453. config IDLE_L1
  454. bool "Locate frequently idle function in L1 Memory"
  455. default y
  456. help
  457. If enabled, the frequently called idle function is linked
  458. into L1 instruction memory. (less latency)
  459. config SCHEDULE_L1
  460. bool "Locate kernel schedule function in L1 Memory"
  461. default y
  462. help
  463. If enabled, the frequently called kernel schedule is linked
  464. into L1 instruction memory. (less latency)
  465. config ARITHMETIC_OPS_L1
  466. bool "Locate kernel owned arithmetic functions in L1 Memory"
  467. default y
  468. help
  469. If enabled, arithmetic functions are linked
  470. into L1 instruction memory. (less latency)
  471. config ACCESS_OK_L1
  472. bool "Locate access_ok function in L1 Memory"
  473. default y
  474. help
  475. If enabled, the access_ok function is linked
  476. into L1 instruction memory. (less latency)
  477. config MEMSET_L1
  478. bool "Locate memset function in L1 Memory"
  479. default y
  480. help
  481. If enabled, the memset function is linked
  482. into L1 instruction memory. (less latency)
  483. config MEMCPY_L1
  484. bool "Locate memcpy function in L1 Memory"
  485. default y
  486. help
  487. If enabled, the memcpy function is linked
  488. into L1 instruction memory. (less latency)
  489. config SYS_BFIN_SPINLOCK_L1
  490. bool "Locate sys_bfin_spinlock function in L1 Memory"
  491. default y
  492. help
  493. If enabled, sys_bfin_spinlock function is linked
  494. into L1 instruction memory. (less latency)
  495. config IP_CHECKSUM_L1
  496. bool "Locate IP Checksum function in L1 Memory"
  497. default n
  498. help
  499. If enabled, the IP Checksum function is linked
  500. into L1 instruction memory. (less latency)
  501. config CACHELINE_ALIGNED_L1
  502. bool "Locate cacheline_aligned data to L1 Data Memory"
  503. default y if !BF54x
  504. default n if BF54x
  505. depends on !BF531
  506. help
  507. If enabled, cacheline_anligned data is linked
  508. into L1 data memory. (less latency)
  509. config SYSCALL_TAB_L1
  510. bool "Locate Syscall Table L1 Data Memory"
  511. default n
  512. depends on !BF531
  513. help
  514. If enabled, the Syscall LUT is linked
  515. into L1 data memory. (less latency)
  516. config CPLB_SWITCH_TAB_L1
  517. bool "Locate CPLB Switch Tables L1 Data Memory"
  518. default n
  519. depends on !BF531
  520. help
  521. If enabled, the CPLB Switch Tables are linked
  522. into L1 data memory. (less latency)
  523. config APP_STACK_L1
  524. bool "Support locating application stack in L1 Scratch Memory"
  525. default y
  526. help
  527. If enabled the application stack can be located in L1
  528. scratch memory (less latency).
  529. Currently only works with FLAT binaries.
  530. comment "Speed Optimizations"
  531. config BFIN_INS_LOWOVERHEAD
  532. bool "ins[bwl] low overhead, higher interrupt latency"
  533. default y
  534. help
  535. Reads on the Blackfin are speculative. In Blackfin terms, this means
  536. they can be interrupted at any time (even after they have been issued
  537. on to the external bus), and re-issued after the interrupt occurs.
  538. For memory - this is not a big deal, since memory does not change if
  539. it sees a read.
  540. If a FIFO is sitting on the end of the read, it will see two reads,
  541. when the core only sees one since the FIFO receives both the read
  542. which is cancelled (and not delivered to the core) and the one which
  543. is re-issued (which is delivered to the core).
  544. To solve this, interrupts are turned off before reads occur to
  545. I/O space. This option controls which the overhead/latency of
  546. controlling interrupts during this time
  547. "n" turns interrupts off every read
  548. (higher overhead, but lower interrupt latency)
  549. "y" turns interrupts off every loop
  550. (low overhead, but longer interrupt latency)
  551. default behavior is to leave this set to on (type "Y"). If you are experiencing
  552. interrupt latency issues, it is safe and OK to turn this off.
  553. endmenu
  554. choice
  555. prompt "Kernel executes from"
  556. help
  557. Choose the memory type that the kernel will be running in.
  558. config RAMKERNEL
  559. bool "RAM"
  560. help
  561. The kernel will be resident in RAM when running.
  562. config ROMKERNEL
  563. bool "ROM"
  564. help
  565. The kernel will be resident in FLASH/ROM when running.
  566. endchoice
  567. source "mm/Kconfig"
  568. config BFIN_GPTIMERS
  569. tristate "Enable Blackfin General Purpose Timers API"
  570. default n
  571. help
  572. Enable support for the General Purpose Timers API. If you
  573. are unsure, say N.
  574. To compile this driver as a module, choose M here: the module
  575. will be called gptimers.ko.
  576. config BFIN_DMA_5XX
  577. bool "Enable DMA Support"
  578. depends on (BF52x || BF53x || BF561 || BF54x)
  579. default y
  580. help
  581. DMA driver for BF5xx.
  582. choice
  583. prompt "Uncached SDRAM region"
  584. default DMA_UNCACHED_1M
  585. depends on BFIN_DMA_5XX
  586. config DMA_UNCACHED_4M
  587. bool "Enable 4M DMA region"
  588. config DMA_UNCACHED_2M
  589. bool "Enable 2M DMA region"
  590. config DMA_UNCACHED_1M
  591. bool "Enable 1M DMA region"
  592. config DMA_UNCACHED_NONE
  593. bool "Disable DMA region"
  594. endchoice
  595. comment "Cache Support"
  596. config BFIN_ICACHE
  597. bool "Enable ICACHE"
  598. config BFIN_DCACHE
  599. bool "Enable DCACHE"
  600. config BFIN_DCACHE_BANKA
  601. bool "Enable only 16k BankA DCACHE - BankB is SRAM"
  602. depends on BFIN_DCACHE && !BF531
  603. default n
  604. config BFIN_ICACHE_LOCK
  605. bool "Enable Instruction Cache Locking"
  606. choice
  607. prompt "Policy"
  608. depends on BFIN_DCACHE
  609. default BFIN_WB
  610. config BFIN_WB
  611. bool "Write back"
  612. help
  613. Write Back Policy:
  614. Cached data will be written back to SDRAM only when needed.
  615. This can give a nice increase in performance, but beware of
  616. broken drivers that do not properly invalidate/flush their
  617. cache.
  618. Write Through Policy:
  619. Cached data will always be written back to SDRAM when the
  620. cache is updated. This is a completely safe setting, but
  621. performance is worse than Write Back.
  622. If you are unsure of the options and you want to be safe,
  623. then go with Write Through.
  624. config BFIN_WT
  625. bool "Write through"
  626. help
  627. Write Back Policy:
  628. Cached data will be written back to SDRAM only when needed.
  629. This can give a nice increase in performance, but beware of
  630. broken drivers that do not properly invalidate/flush their
  631. cache.
  632. Write Through Policy:
  633. Cached data will always be written back to SDRAM when the
  634. cache is updated. This is a completely safe setting, but
  635. performance is worse than Write Back.
  636. If you are unsure of the options and you want to be safe,
  637. then go with Write Through.
  638. endchoice
  639. config BFIN_L2_CACHEABLE
  640. bool "Cache L2 SRAM"
  641. depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || BF561)
  642. default n
  643. help
  644. Select to make L2 SRAM cacheable in L1 data and instruction cache.
  645. config MPU
  646. bool "Enable the memory protection unit (EXPERIMENTAL)"
  647. default n
  648. help
  649. Use the processor's MPU to protect applications from accessing
  650. memory they do not own. This comes at a performance penalty
  651. and is recommended only for debugging.
  652. comment "Asynchonous Memory Configuration"
  653. menu "EBIU_AMGCTL Global Control"
  654. config C_AMCKEN
  655. bool "Enable CLKOUT"
  656. default y
  657. config C_CDPRIO
  658. bool "DMA has priority over core for ext. accesses"
  659. default n
  660. config C_B0PEN
  661. depends on BF561
  662. bool "Bank 0 16 bit packing enable"
  663. default y
  664. config C_B1PEN
  665. depends on BF561
  666. bool "Bank 1 16 bit packing enable"
  667. default y
  668. config C_B2PEN
  669. depends on BF561
  670. bool "Bank 2 16 bit packing enable"
  671. default y
  672. config C_B3PEN
  673. depends on BF561
  674. bool "Bank 3 16 bit packing enable"
  675. default n
  676. choice
  677. prompt"Enable Asynchonous Memory Banks"
  678. default C_AMBEN_ALL
  679. config C_AMBEN
  680. bool "Disable All Banks"
  681. config C_AMBEN_B0
  682. bool "Enable Bank 0"
  683. config C_AMBEN_B0_B1
  684. bool "Enable Bank 0 & 1"
  685. config C_AMBEN_B0_B1_B2
  686. bool "Enable Bank 0 & 1 & 2"
  687. config C_AMBEN_ALL
  688. bool "Enable All Banks"
  689. endchoice
  690. endmenu
  691. menu "EBIU_AMBCTL Control"
  692. config BANK_0
  693. hex "Bank 0"
  694. default 0x7BB0
  695. config BANK_1
  696. hex "Bank 1"
  697. default 0x7BB0
  698. default 0x5558 if BF54x
  699. config BANK_2
  700. hex "Bank 2"
  701. default 0x7BB0
  702. config BANK_3
  703. hex "Bank 3"
  704. default 0x99B3
  705. endmenu
  706. config EBIU_MBSCTLVAL
  707. hex "EBIU Bank Select Control Register"
  708. depends on BF54x
  709. default 0
  710. config EBIU_MODEVAL
  711. hex "Flash Memory Mode Control Register"
  712. depends on BF54x
  713. default 1
  714. config EBIU_FCTLVAL
  715. hex "Flash Memory Bank Control Register"
  716. depends on BF54x
  717. default 6
  718. endmenu
  719. #############################################################################
  720. menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
  721. config PCI
  722. bool "PCI support"
  723. depends on BROKEN
  724. help
  725. Support for PCI bus.
  726. source "drivers/pci/Kconfig"
  727. config HOTPLUG
  728. bool "Support for hot-pluggable device"
  729. help
  730. Say Y here if you want to plug devices into your computer while
  731. the system is running, and be able to use them quickly. In many
  732. cases, the devices can likewise be unplugged at any time too.
  733. One well known example of this is PCMCIA- or PC-cards, credit-card
  734. size devices such as network cards, modems or hard drives which are
  735. plugged into slots found on all modern laptop computers. Another
  736. example, used on modern desktops as well as laptops, is USB.
  737. Enable HOTPLUG and build a modular kernel. Get agent software
  738. (from <http://linux-hotplug.sourceforge.net/>) and install it.
  739. Then your kernel will automatically call out to a user mode "policy
  740. agent" (/sbin/hotplug) to load modules and set up software needed
  741. to use devices as you hotplug them.
  742. source "drivers/pcmcia/Kconfig"
  743. source "drivers/pci/hotplug/Kconfig"
  744. endmenu
  745. menu "Executable file formats"
  746. source "fs/Kconfig.binfmt"
  747. endmenu
  748. menu "Power management options"
  749. source "kernel/power/Kconfig"
  750. config ARCH_SUSPEND_POSSIBLE
  751. def_bool y
  752. depends on !SMP
  753. choice
  754. prompt "Standby Power Saving Mode"
  755. depends on PM
  756. default PM_BFIN_SLEEP_DEEPER
  757. config PM_BFIN_SLEEP_DEEPER
  758. bool "Sleep Deeper"
  759. help
  760. Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
  761. power dissipation by disabling the clock to the processor core (CCLK).
  762. Furthermore, Standby sets the internal power supply voltage (VDDINT)
  763. to 0.85 V to provide the greatest power savings, while preserving the
  764. processor state.
  765. The PLL and system clock (SCLK) continue to operate at a very low
  766. frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
  767. the SDRAM is put into Self Refresh Mode. Typically an external event
  768. such as GPIO interrupt or RTC activity wakes up the processor.
  769. Various Peripherals such as UART, SPORT, PPI may not function as
  770. normal during Sleep Deeper, due to the reduced SCLK frequency.
  771. When in the sleep mode, system DMA access to L1 memory is not supported.
  772. If unsure, select "Sleep Deeper".
  773. config PM_BFIN_SLEEP
  774. bool "Sleep"
  775. help
  776. Sleep Mode (High Power Savings) - The sleep mode reduces power
  777. dissipation by disabling the clock to the processor core (CCLK).
  778. The PLL and system clock (SCLK), however, continue to operate in
  779. this mode. Typically an external event or RTC activity will wake
  780. up the processor. When in the sleep mode, system DMA access to L1
  781. memory is not supported.
  782. If unsure, select "Sleep Deeper".
  783. endchoice
  784. config PM_WAKEUP_BY_GPIO
  785. bool "Allow Wakeup from Standby by GPIO"
  786. config PM_WAKEUP_GPIO_NUMBER
  787. int "GPIO number"
  788. range 0 47
  789. depends on PM_WAKEUP_BY_GPIO
  790. default 2 if BFIN537_STAMP
  791. choice
  792. prompt "GPIO Polarity"
  793. depends on PM_WAKEUP_BY_GPIO
  794. default PM_WAKEUP_GPIO_POLAR_H
  795. config PM_WAKEUP_GPIO_POLAR_H
  796. bool "Active High"
  797. config PM_WAKEUP_GPIO_POLAR_L
  798. bool "Active Low"
  799. config PM_WAKEUP_GPIO_POLAR_EDGE_F
  800. bool "Falling EDGE"
  801. config PM_WAKEUP_GPIO_POLAR_EDGE_R
  802. bool "Rising EDGE"
  803. config PM_WAKEUP_GPIO_POLAR_EDGE_B
  804. bool "Both EDGE"
  805. endchoice
  806. comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
  807. depends on PM
  808. config PM_BFIN_WAKE_PH6
  809. bool "Allow Wake-Up from on-chip PHY or PH6 GP"
  810. depends on PM && (BF52x || BF534 || BF536 || BF537)
  811. default n
  812. help
  813. Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
  814. config PM_BFIN_WAKE_GP
  815. bool "Allow Wake-Up from GPIOs"
  816. depends on PM && BF54x
  817. default n
  818. help
  819. Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
  820. endmenu
  821. menu "CPU Frequency scaling"
  822. source "drivers/cpufreq/Kconfig"
  823. config CPU_VOLTAGE
  824. bool "CPU Voltage scaling"
  825. depends on EXPERIMENTAL
  826. depends on CPU_FREQ
  827. default n
  828. help
  829. Say Y here if you want CPU voltage scaling according to the CPU frequency.
  830. This option violates the PLL BYPASS recommendation in the Blackfin Processor
  831. manuals. There is a theoretical risk that during VDDINT transitions
  832. the PLL may unlock.
  833. endmenu
  834. source "net/Kconfig"
  835. source "drivers/Kconfig"
  836. source "fs/Kconfig"
  837. source "arch/blackfin/Kconfig.debug"
  838. source "security/Kconfig"
  839. source "crypto/Kconfig"
  840. source "lib/Kconfig"