ac97c.c 31 KB

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  1. /*
  2. * Driver for Atmel AC97C
  3. *
  4. * Copyright (C) 2005-2009 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/delay.h>
  12. #include <linux/bitmap.h>
  13. #include <linux/device.h>
  14. #include <linux/dmaengine.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/atmel_pdc.h>
  17. #include <linux/init.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/module.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/mutex.h>
  22. #include <linux/gpio.h>
  23. #include <linux/types.h>
  24. #include <linux/io.h>
  25. #include <sound/core.h>
  26. #include <sound/initval.h>
  27. #include <sound/pcm.h>
  28. #include <sound/pcm_params.h>
  29. #include <sound/ac97_codec.h>
  30. #include <sound/atmel-ac97c.h>
  31. #include <sound/memalloc.h>
  32. #include <linux/dw_dmac.h>
  33. #include <mach/cpu.h>
  34. #ifdef CONFIG_ARCH_AT91
  35. #include <mach/hardware.h>
  36. #endif
  37. #include "ac97c.h"
  38. enum {
  39. DMA_TX_READY = 0,
  40. DMA_RX_READY,
  41. DMA_TX_CHAN_PRESENT,
  42. DMA_RX_CHAN_PRESENT,
  43. };
  44. /* Serialize access to opened variable */
  45. static DEFINE_MUTEX(opened_mutex);
  46. struct atmel_ac97c_dma {
  47. struct dma_chan *rx_chan;
  48. struct dma_chan *tx_chan;
  49. };
  50. struct atmel_ac97c {
  51. struct clk *pclk;
  52. struct platform_device *pdev;
  53. struct atmel_ac97c_dma dma;
  54. struct snd_pcm_substream *playback_substream;
  55. struct snd_pcm_substream *capture_substream;
  56. struct snd_card *card;
  57. struct snd_pcm *pcm;
  58. struct snd_ac97 *ac97;
  59. struct snd_ac97_bus *ac97_bus;
  60. u64 cur_format;
  61. unsigned int cur_rate;
  62. unsigned long flags;
  63. int playback_period, capture_period;
  64. /* Serialize access to opened variable */
  65. spinlock_t lock;
  66. void __iomem *regs;
  67. int irq;
  68. int opened;
  69. int reset_pin;
  70. };
  71. #define get_chip(card) ((struct atmel_ac97c *)(card)->private_data)
  72. #define ac97c_writel(chip, reg, val) \
  73. __raw_writel((val), (chip)->regs + AC97C_##reg)
  74. #define ac97c_readl(chip, reg) \
  75. __raw_readl((chip)->regs + AC97C_##reg)
  76. /* This function is called by the DMA driver. */
  77. static void atmel_ac97c_dma_playback_period_done(void *arg)
  78. {
  79. struct atmel_ac97c *chip = arg;
  80. snd_pcm_period_elapsed(chip->playback_substream);
  81. }
  82. static void atmel_ac97c_dma_capture_period_done(void *arg)
  83. {
  84. struct atmel_ac97c *chip = arg;
  85. snd_pcm_period_elapsed(chip->capture_substream);
  86. }
  87. static int atmel_ac97c_prepare_dma(struct atmel_ac97c *chip,
  88. struct snd_pcm_substream *substream,
  89. enum dma_transfer_direction direction)
  90. {
  91. struct dma_chan *chan;
  92. struct dw_cyclic_desc *cdesc;
  93. struct snd_pcm_runtime *runtime = substream->runtime;
  94. unsigned long buffer_len, period_len;
  95. /*
  96. * We don't do DMA on "complex" transfers, i.e. with
  97. * non-halfword-aligned buffers or lengths.
  98. */
  99. if (runtime->dma_addr & 1 || runtime->buffer_size & 1) {
  100. dev_dbg(&chip->pdev->dev, "too complex transfer\n");
  101. return -EINVAL;
  102. }
  103. if (direction == DMA_MEM_TO_DEV)
  104. chan = chip->dma.tx_chan;
  105. else
  106. chan = chip->dma.rx_chan;
  107. buffer_len = frames_to_bytes(runtime, runtime->buffer_size);
  108. period_len = frames_to_bytes(runtime, runtime->period_size);
  109. cdesc = dw_dma_cyclic_prep(chan, runtime->dma_addr, buffer_len,
  110. period_len, direction);
  111. if (IS_ERR(cdesc)) {
  112. dev_dbg(&chip->pdev->dev, "could not prepare cyclic DMA\n");
  113. return PTR_ERR(cdesc);
  114. }
  115. if (direction == DMA_MEM_TO_DEV) {
  116. cdesc->period_callback = atmel_ac97c_dma_playback_period_done;
  117. set_bit(DMA_TX_READY, &chip->flags);
  118. } else {
  119. cdesc->period_callback = atmel_ac97c_dma_capture_period_done;
  120. set_bit(DMA_RX_READY, &chip->flags);
  121. }
  122. cdesc->period_callback_param = chip;
  123. return 0;
  124. }
  125. static struct snd_pcm_hardware atmel_ac97c_hw = {
  126. .info = (SNDRV_PCM_INFO_MMAP
  127. | SNDRV_PCM_INFO_MMAP_VALID
  128. | SNDRV_PCM_INFO_INTERLEAVED
  129. | SNDRV_PCM_INFO_BLOCK_TRANSFER
  130. | SNDRV_PCM_INFO_JOINT_DUPLEX
  131. | SNDRV_PCM_INFO_RESUME
  132. | SNDRV_PCM_INFO_PAUSE),
  133. .formats = (SNDRV_PCM_FMTBIT_S16_BE
  134. | SNDRV_PCM_FMTBIT_S16_LE),
  135. .rates = (SNDRV_PCM_RATE_CONTINUOUS),
  136. .rate_min = 4000,
  137. .rate_max = 48000,
  138. .channels_min = 1,
  139. .channels_max = 2,
  140. .buffer_bytes_max = 2 * 2 * 64 * 2048,
  141. .period_bytes_min = 4096,
  142. .period_bytes_max = 4096,
  143. .periods_min = 6,
  144. .periods_max = 64,
  145. };
  146. static int atmel_ac97c_playback_open(struct snd_pcm_substream *substream)
  147. {
  148. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  149. struct snd_pcm_runtime *runtime = substream->runtime;
  150. mutex_lock(&opened_mutex);
  151. chip->opened++;
  152. runtime->hw = atmel_ac97c_hw;
  153. if (chip->cur_rate) {
  154. runtime->hw.rate_min = chip->cur_rate;
  155. runtime->hw.rate_max = chip->cur_rate;
  156. }
  157. if (chip->cur_format)
  158. runtime->hw.formats = pcm_format_to_bits(chip->cur_format);
  159. mutex_unlock(&opened_mutex);
  160. chip->playback_substream = substream;
  161. return 0;
  162. }
  163. static int atmel_ac97c_capture_open(struct snd_pcm_substream *substream)
  164. {
  165. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  166. struct snd_pcm_runtime *runtime = substream->runtime;
  167. mutex_lock(&opened_mutex);
  168. chip->opened++;
  169. runtime->hw = atmel_ac97c_hw;
  170. if (chip->cur_rate) {
  171. runtime->hw.rate_min = chip->cur_rate;
  172. runtime->hw.rate_max = chip->cur_rate;
  173. }
  174. if (chip->cur_format)
  175. runtime->hw.formats = pcm_format_to_bits(chip->cur_format);
  176. mutex_unlock(&opened_mutex);
  177. chip->capture_substream = substream;
  178. return 0;
  179. }
  180. static int atmel_ac97c_playback_close(struct snd_pcm_substream *substream)
  181. {
  182. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  183. mutex_lock(&opened_mutex);
  184. chip->opened--;
  185. if (!chip->opened) {
  186. chip->cur_rate = 0;
  187. chip->cur_format = 0;
  188. }
  189. mutex_unlock(&opened_mutex);
  190. chip->playback_substream = NULL;
  191. return 0;
  192. }
  193. static int atmel_ac97c_capture_close(struct snd_pcm_substream *substream)
  194. {
  195. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  196. mutex_lock(&opened_mutex);
  197. chip->opened--;
  198. if (!chip->opened) {
  199. chip->cur_rate = 0;
  200. chip->cur_format = 0;
  201. }
  202. mutex_unlock(&opened_mutex);
  203. chip->capture_substream = NULL;
  204. return 0;
  205. }
  206. static int atmel_ac97c_playback_hw_params(struct snd_pcm_substream *substream,
  207. struct snd_pcm_hw_params *hw_params)
  208. {
  209. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  210. int retval;
  211. retval = snd_pcm_lib_malloc_pages(substream,
  212. params_buffer_bytes(hw_params));
  213. if (retval < 0)
  214. return retval;
  215. /* snd_pcm_lib_malloc_pages returns 1 if buffer is changed. */
  216. if (cpu_is_at32ap7000()) {
  217. /* snd_pcm_lib_malloc_pages returns 1 if buffer is changed. */
  218. if (retval == 1)
  219. if (test_and_clear_bit(DMA_TX_READY, &chip->flags))
  220. dw_dma_cyclic_free(chip->dma.tx_chan);
  221. }
  222. /* Set restrictions to params. */
  223. mutex_lock(&opened_mutex);
  224. chip->cur_rate = params_rate(hw_params);
  225. chip->cur_format = params_format(hw_params);
  226. mutex_unlock(&opened_mutex);
  227. return retval;
  228. }
  229. static int atmel_ac97c_capture_hw_params(struct snd_pcm_substream *substream,
  230. struct snd_pcm_hw_params *hw_params)
  231. {
  232. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  233. int retval;
  234. retval = snd_pcm_lib_malloc_pages(substream,
  235. params_buffer_bytes(hw_params));
  236. if (retval < 0)
  237. return retval;
  238. /* snd_pcm_lib_malloc_pages returns 1 if buffer is changed. */
  239. if (cpu_is_at32ap7000() && retval == 1)
  240. if (test_and_clear_bit(DMA_RX_READY, &chip->flags))
  241. dw_dma_cyclic_free(chip->dma.rx_chan);
  242. /* Set restrictions to params. */
  243. mutex_lock(&opened_mutex);
  244. chip->cur_rate = params_rate(hw_params);
  245. chip->cur_format = params_format(hw_params);
  246. mutex_unlock(&opened_mutex);
  247. return retval;
  248. }
  249. static int atmel_ac97c_playback_hw_free(struct snd_pcm_substream *substream)
  250. {
  251. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  252. if (cpu_is_at32ap7000()) {
  253. if (test_and_clear_bit(DMA_TX_READY, &chip->flags))
  254. dw_dma_cyclic_free(chip->dma.tx_chan);
  255. }
  256. return snd_pcm_lib_free_pages(substream);
  257. }
  258. static int atmel_ac97c_capture_hw_free(struct snd_pcm_substream *substream)
  259. {
  260. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  261. if (cpu_is_at32ap7000()) {
  262. if (test_and_clear_bit(DMA_RX_READY, &chip->flags))
  263. dw_dma_cyclic_free(chip->dma.rx_chan);
  264. }
  265. return snd_pcm_lib_free_pages(substream);
  266. }
  267. static int atmel_ac97c_playback_prepare(struct snd_pcm_substream *substream)
  268. {
  269. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  270. struct snd_pcm_runtime *runtime = substream->runtime;
  271. int block_size = frames_to_bytes(runtime, runtime->period_size);
  272. unsigned long word = ac97c_readl(chip, OCA);
  273. int retval;
  274. chip->playback_period = 0;
  275. word &= ~(AC97C_CH_MASK(PCM_LEFT) | AC97C_CH_MASK(PCM_RIGHT));
  276. /* assign channels to AC97C channel A */
  277. switch (runtime->channels) {
  278. case 1:
  279. word |= AC97C_CH_ASSIGN(PCM_LEFT, A);
  280. break;
  281. case 2:
  282. word |= AC97C_CH_ASSIGN(PCM_LEFT, A)
  283. | AC97C_CH_ASSIGN(PCM_RIGHT, A);
  284. break;
  285. default:
  286. /* TODO: support more than two channels */
  287. return -EINVAL;
  288. }
  289. ac97c_writel(chip, OCA, word);
  290. /* configure sample format and size */
  291. word = ac97c_readl(chip, CAMR);
  292. if (chip->opened <= 1)
  293. word = AC97C_CMR_DMAEN | AC97C_CMR_SIZE_16;
  294. else
  295. word |= AC97C_CMR_DMAEN | AC97C_CMR_SIZE_16;
  296. switch (runtime->format) {
  297. case SNDRV_PCM_FORMAT_S16_LE:
  298. if (cpu_is_at32ap7000())
  299. word |= AC97C_CMR_CEM_LITTLE;
  300. break;
  301. case SNDRV_PCM_FORMAT_S16_BE: /* fall through */
  302. word &= ~(AC97C_CMR_CEM_LITTLE);
  303. break;
  304. default:
  305. word = ac97c_readl(chip, OCA);
  306. word &= ~(AC97C_CH_MASK(PCM_LEFT) | AC97C_CH_MASK(PCM_RIGHT));
  307. ac97c_writel(chip, OCA, word);
  308. return -EINVAL;
  309. }
  310. /* Enable underrun interrupt on channel A */
  311. word |= AC97C_CSR_UNRUN;
  312. ac97c_writel(chip, CAMR, word);
  313. /* Enable channel A event interrupt */
  314. word = ac97c_readl(chip, IMR);
  315. word |= AC97C_SR_CAEVT;
  316. ac97c_writel(chip, IER, word);
  317. /* set variable rate if needed */
  318. if (runtime->rate != 48000) {
  319. word = ac97c_readl(chip, MR);
  320. word |= AC97C_MR_VRA;
  321. ac97c_writel(chip, MR, word);
  322. } else {
  323. word = ac97c_readl(chip, MR);
  324. word &= ~(AC97C_MR_VRA);
  325. ac97c_writel(chip, MR, word);
  326. }
  327. retval = snd_ac97_set_rate(chip->ac97, AC97_PCM_FRONT_DAC_RATE,
  328. runtime->rate);
  329. if (retval)
  330. dev_dbg(&chip->pdev->dev, "could not set rate %d Hz\n",
  331. runtime->rate);
  332. if (cpu_is_at32ap7000()) {
  333. if (!test_bit(DMA_TX_READY, &chip->flags))
  334. retval = atmel_ac97c_prepare_dma(chip, substream,
  335. DMA_MEM_TO_DEV);
  336. } else {
  337. /* Initialize and start the PDC */
  338. writel(runtime->dma_addr, chip->regs + ATMEL_PDC_TPR);
  339. writel(block_size / 2, chip->regs + ATMEL_PDC_TCR);
  340. writel(runtime->dma_addr + block_size,
  341. chip->regs + ATMEL_PDC_TNPR);
  342. writel(block_size / 2, chip->regs + ATMEL_PDC_TNCR);
  343. }
  344. return retval;
  345. }
  346. static int atmel_ac97c_capture_prepare(struct snd_pcm_substream *substream)
  347. {
  348. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  349. struct snd_pcm_runtime *runtime = substream->runtime;
  350. int block_size = frames_to_bytes(runtime, runtime->period_size);
  351. unsigned long word = ac97c_readl(chip, ICA);
  352. int retval;
  353. chip->capture_period = 0;
  354. word &= ~(AC97C_CH_MASK(PCM_LEFT) | AC97C_CH_MASK(PCM_RIGHT));
  355. /* assign channels to AC97C channel A */
  356. switch (runtime->channels) {
  357. case 1:
  358. word |= AC97C_CH_ASSIGN(PCM_LEFT, A);
  359. break;
  360. case 2:
  361. word |= AC97C_CH_ASSIGN(PCM_LEFT, A)
  362. | AC97C_CH_ASSIGN(PCM_RIGHT, A);
  363. break;
  364. default:
  365. /* TODO: support more than two channels */
  366. return -EINVAL;
  367. }
  368. ac97c_writel(chip, ICA, word);
  369. /* configure sample format and size */
  370. word = ac97c_readl(chip, CAMR);
  371. if (chip->opened <= 1)
  372. word = AC97C_CMR_DMAEN | AC97C_CMR_SIZE_16;
  373. else
  374. word |= AC97C_CMR_DMAEN | AC97C_CMR_SIZE_16;
  375. switch (runtime->format) {
  376. case SNDRV_PCM_FORMAT_S16_LE:
  377. if (cpu_is_at32ap7000())
  378. word |= AC97C_CMR_CEM_LITTLE;
  379. break;
  380. case SNDRV_PCM_FORMAT_S16_BE: /* fall through */
  381. word &= ~(AC97C_CMR_CEM_LITTLE);
  382. break;
  383. default:
  384. word = ac97c_readl(chip, ICA);
  385. word &= ~(AC97C_CH_MASK(PCM_LEFT) | AC97C_CH_MASK(PCM_RIGHT));
  386. ac97c_writel(chip, ICA, word);
  387. return -EINVAL;
  388. }
  389. /* Enable overrun interrupt on channel A */
  390. word |= AC97C_CSR_OVRUN;
  391. ac97c_writel(chip, CAMR, word);
  392. /* Enable channel A event interrupt */
  393. word = ac97c_readl(chip, IMR);
  394. word |= AC97C_SR_CAEVT;
  395. ac97c_writel(chip, IER, word);
  396. /* set variable rate if needed */
  397. if (runtime->rate != 48000) {
  398. word = ac97c_readl(chip, MR);
  399. word |= AC97C_MR_VRA;
  400. ac97c_writel(chip, MR, word);
  401. } else {
  402. word = ac97c_readl(chip, MR);
  403. word &= ~(AC97C_MR_VRA);
  404. ac97c_writel(chip, MR, word);
  405. }
  406. retval = snd_ac97_set_rate(chip->ac97, AC97_PCM_LR_ADC_RATE,
  407. runtime->rate);
  408. if (retval)
  409. dev_dbg(&chip->pdev->dev, "could not set rate %d Hz\n",
  410. runtime->rate);
  411. if (cpu_is_at32ap7000()) {
  412. if (!test_bit(DMA_RX_READY, &chip->flags))
  413. retval = atmel_ac97c_prepare_dma(chip, substream,
  414. DMA_DEV_TO_MEM);
  415. } else {
  416. /* Initialize and start the PDC */
  417. writel(runtime->dma_addr, chip->regs + ATMEL_PDC_RPR);
  418. writel(block_size / 2, chip->regs + ATMEL_PDC_RCR);
  419. writel(runtime->dma_addr + block_size,
  420. chip->regs + ATMEL_PDC_RNPR);
  421. writel(block_size / 2, chip->regs + ATMEL_PDC_RNCR);
  422. }
  423. return retval;
  424. }
  425. static int
  426. atmel_ac97c_playback_trigger(struct snd_pcm_substream *substream, int cmd)
  427. {
  428. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  429. unsigned long camr, ptcr = 0;
  430. int retval = 0;
  431. camr = ac97c_readl(chip, CAMR);
  432. switch (cmd) {
  433. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: /* fall through */
  434. case SNDRV_PCM_TRIGGER_RESUME: /* fall through */
  435. case SNDRV_PCM_TRIGGER_START:
  436. if (cpu_is_at32ap7000()) {
  437. retval = dw_dma_cyclic_start(chip->dma.tx_chan);
  438. if (retval)
  439. goto out;
  440. } else {
  441. ptcr = ATMEL_PDC_TXTEN;
  442. }
  443. camr |= AC97C_CMR_CENA | AC97C_CSR_ENDTX;
  444. break;
  445. case SNDRV_PCM_TRIGGER_PAUSE_PUSH: /* fall through */
  446. case SNDRV_PCM_TRIGGER_SUSPEND: /* fall through */
  447. case SNDRV_PCM_TRIGGER_STOP:
  448. if (cpu_is_at32ap7000())
  449. dw_dma_cyclic_stop(chip->dma.tx_chan);
  450. else
  451. ptcr |= ATMEL_PDC_TXTDIS;
  452. if (chip->opened <= 1)
  453. camr &= ~AC97C_CMR_CENA;
  454. break;
  455. default:
  456. retval = -EINVAL;
  457. goto out;
  458. }
  459. ac97c_writel(chip, CAMR, camr);
  460. if (!cpu_is_at32ap7000())
  461. writel(ptcr, chip->regs + ATMEL_PDC_PTCR);
  462. out:
  463. return retval;
  464. }
  465. static int
  466. atmel_ac97c_capture_trigger(struct snd_pcm_substream *substream, int cmd)
  467. {
  468. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  469. unsigned long camr, ptcr = 0;
  470. int retval = 0;
  471. camr = ac97c_readl(chip, CAMR);
  472. ptcr = readl(chip->regs + ATMEL_PDC_PTSR);
  473. switch (cmd) {
  474. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: /* fall through */
  475. case SNDRV_PCM_TRIGGER_RESUME: /* fall through */
  476. case SNDRV_PCM_TRIGGER_START:
  477. if (cpu_is_at32ap7000()) {
  478. retval = dw_dma_cyclic_start(chip->dma.rx_chan);
  479. if (retval)
  480. goto out;
  481. } else {
  482. ptcr = ATMEL_PDC_RXTEN;
  483. }
  484. camr |= AC97C_CMR_CENA | AC97C_CSR_ENDRX;
  485. break;
  486. case SNDRV_PCM_TRIGGER_PAUSE_PUSH: /* fall through */
  487. case SNDRV_PCM_TRIGGER_SUSPEND: /* fall through */
  488. case SNDRV_PCM_TRIGGER_STOP:
  489. if (cpu_is_at32ap7000())
  490. dw_dma_cyclic_stop(chip->dma.rx_chan);
  491. else
  492. ptcr |= (ATMEL_PDC_RXTDIS);
  493. if (chip->opened <= 1)
  494. camr &= ~AC97C_CMR_CENA;
  495. break;
  496. default:
  497. retval = -EINVAL;
  498. break;
  499. }
  500. ac97c_writel(chip, CAMR, camr);
  501. if (!cpu_is_at32ap7000())
  502. writel(ptcr, chip->regs + ATMEL_PDC_PTCR);
  503. out:
  504. return retval;
  505. }
  506. static snd_pcm_uframes_t
  507. atmel_ac97c_playback_pointer(struct snd_pcm_substream *substream)
  508. {
  509. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  510. struct snd_pcm_runtime *runtime = substream->runtime;
  511. snd_pcm_uframes_t frames;
  512. unsigned long bytes;
  513. if (cpu_is_at32ap7000())
  514. bytes = dw_dma_get_src_addr(chip->dma.tx_chan);
  515. else
  516. bytes = readl(chip->regs + ATMEL_PDC_TPR);
  517. bytes -= runtime->dma_addr;
  518. frames = bytes_to_frames(runtime, bytes);
  519. if (frames >= runtime->buffer_size)
  520. frames -= runtime->buffer_size;
  521. return frames;
  522. }
  523. static snd_pcm_uframes_t
  524. atmel_ac97c_capture_pointer(struct snd_pcm_substream *substream)
  525. {
  526. struct atmel_ac97c *chip = snd_pcm_substream_chip(substream);
  527. struct snd_pcm_runtime *runtime = substream->runtime;
  528. snd_pcm_uframes_t frames;
  529. unsigned long bytes;
  530. if (cpu_is_at32ap7000())
  531. bytes = dw_dma_get_dst_addr(chip->dma.rx_chan);
  532. else
  533. bytes = readl(chip->regs + ATMEL_PDC_RPR);
  534. bytes -= runtime->dma_addr;
  535. frames = bytes_to_frames(runtime, bytes);
  536. if (frames >= runtime->buffer_size)
  537. frames -= runtime->buffer_size;
  538. return frames;
  539. }
  540. static struct snd_pcm_ops atmel_ac97_playback_ops = {
  541. .open = atmel_ac97c_playback_open,
  542. .close = atmel_ac97c_playback_close,
  543. .ioctl = snd_pcm_lib_ioctl,
  544. .hw_params = atmel_ac97c_playback_hw_params,
  545. .hw_free = atmel_ac97c_playback_hw_free,
  546. .prepare = atmel_ac97c_playback_prepare,
  547. .trigger = atmel_ac97c_playback_trigger,
  548. .pointer = atmel_ac97c_playback_pointer,
  549. };
  550. static struct snd_pcm_ops atmel_ac97_capture_ops = {
  551. .open = atmel_ac97c_capture_open,
  552. .close = atmel_ac97c_capture_close,
  553. .ioctl = snd_pcm_lib_ioctl,
  554. .hw_params = atmel_ac97c_capture_hw_params,
  555. .hw_free = atmel_ac97c_capture_hw_free,
  556. .prepare = atmel_ac97c_capture_prepare,
  557. .trigger = atmel_ac97c_capture_trigger,
  558. .pointer = atmel_ac97c_capture_pointer,
  559. };
  560. static irqreturn_t atmel_ac97c_interrupt(int irq, void *dev)
  561. {
  562. struct atmel_ac97c *chip = (struct atmel_ac97c *)dev;
  563. irqreturn_t retval = IRQ_NONE;
  564. u32 sr = ac97c_readl(chip, SR);
  565. u32 casr = ac97c_readl(chip, CASR);
  566. u32 cosr = ac97c_readl(chip, COSR);
  567. u32 camr = ac97c_readl(chip, CAMR);
  568. if (sr & AC97C_SR_CAEVT) {
  569. struct snd_pcm_runtime *runtime;
  570. int offset, next_period, block_size;
  571. dev_dbg(&chip->pdev->dev, "channel A event%s%s%s%s%s%s\n",
  572. casr & AC97C_CSR_OVRUN ? " OVRUN" : "",
  573. casr & AC97C_CSR_RXRDY ? " RXRDY" : "",
  574. casr & AC97C_CSR_UNRUN ? " UNRUN" : "",
  575. casr & AC97C_CSR_TXEMPTY ? " TXEMPTY" : "",
  576. casr & AC97C_CSR_TXRDY ? " TXRDY" : "",
  577. !casr ? " NONE" : "");
  578. if (!cpu_is_at32ap7000()) {
  579. if ((casr & camr) & AC97C_CSR_ENDTX) {
  580. runtime = chip->playback_substream->runtime;
  581. block_size = frames_to_bytes(runtime,
  582. runtime->period_size);
  583. chip->playback_period++;
  584. if (chip->playback_period == runtime->periods)
  585. chip->playback_period = 0;
  586. next_period = chip->playback_period + 1;
  587. if (next_period == runtime->periods)
  588. next_period = 0;
  589. offset = block_size * next_period;
  590. writel(runtime->dma_addr + offset,
  591. chip->regs + ATMEL_PDC_TNPR);
  592. writel(block_size / 2,
  593. chip->regs + ATMEL_PDC_TNCR);
  594. snd_pcm_period_elapsed(
  595. chip->playback_substream);
  596. }
  597. if ((casr & camr) & AC97C_CSR_ENDRX) {
  598. runtime = chip->capture_substream->runtime;
  599. block_size = frames_to_bytes(runtime,
  600. runtime->period_size);
  601. chip->capture_period++;
  602. if (chip->capture_period == runtime->periods)
  603. chip->capture_period = 0;
  604. next_period = chip->capture_period + 1;
  605. if (next_period == runtime->periods)
  606. next_period = 0;
  607. offset = block_size * next_period;
  608. writel(runtime->dma_addr + offset,
  609. chip->regs + ATMEL_PDC_RNPR);
  610. writel(block_size / 2,
  611. chip->regs + ATMEL_PDC_RNCR);
  612. snd_pcm_period_elapsed(chip->capture_substream);
  613. }
  614. }
  615. retval = IRQ_HANDLED;
  616. }
  617. if (sr & AC97C_SR_COEVT) {
  618. dev_info(&chip->pdev->dev, "codec channel event%s%s%s%s%s\n",
  619. cosr & AC97C_CSR_OVRUN ? " OVRUN" : "",
  620. cosr & AC97C_CSR_RXRDY ? " RXRDY" : "",
  621. cosr & AC97C_CSR_TXEMPTY ? " TXEMPTY" : "",
  622. cosr & AC97C_CSR_TXRDY ? " TXRDY" : "",
  623. !cosr ? " NONE" : "");
  624. retval = IRQ_HANDLED;
  625. }
  626. if (retval == IRQ_NONE) {
  627. dev_err(&chip->pdev->dev, "spurious interrupt sr 0x%08x "
  628. "casr 0x%08x cosr 0x%08x\n", sr, casr, cosr);
  629. }
  630. return retval;
  631. }
  632. static struct ac97_pcm at91_ac97_pcm_defs[] = {
  633. /* Playback */
  634. {
  635. .exclusive = 1,
  636. .r = { {
  637. .slots = ((1 << AC97_SLOT_PCM_LEFT)
  638. | (1 << AC97_SLOT_PCM_RIGHT)),
  639. } },
  640. },
  641. /* PCM in */
  642. {
  643. .stream = 1,
  644. .exclusive = 1,
  645. .r = { {
  646. .slots = ((1 << AC97_SLOT_PCM_LEFT)
  647. | (1 << AC97_SLOT_PCM_RIGHT)),
  648. } }
  649. },
  650. /* Mic in */
  651. {
  652. .stream = 1,
  653. .exclusive = 1,
  654. .r = { {
  655. .slots = (1<<AC97_SLOT_MIC),
  656. } }
  657. },
  658. };
  659. static int atmel_ac97c_pcm_new(struct atmel_ac97c *chip)
  660. {
  661. struct snd_pcm *pcm;
  662. struct snd_pcm_hardware hw = atmel_ac97c_hw;
  663. int capture, playback, retval, err;
  664. capture = test_bit(DMA_RX_CHAN_PRESENT, &chip->flags);
  665. playback = test_bit(DMA_TX_CHAN_PRESENT, &chip->flags);
  666. if (!cpu_is_at32ap7000()) {
  667. err = snd_ac97_pcm_assign(chip->ac97_bus,
  668. ARRAY_SIZE(at91_ac97_pcm_defs),
  669. at91_ac97_pcm_defs);
  670. if (err)
  671. return err;
  672. }
  673. retval = snd_pcm_new(chip->card, chip->card->shortname,
  674. chip->pdev->id, playback, capture, &pcm);
  675. if (retval)
  676. return retval;
  677. if (capture)
  678. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  679. &atmel_ac97_capture_ops);
  680. if (playback)
  681. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  682. &atmel_ac97_playback_ops);
  683. retval = snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  684. &chip->pdev->dev, hw.periods_min * hw.period_bytes_min,
  685. hw.buffer_bytes_max);
  686. if (retval)
  687. return retval;
  688. pcm->private_data = chip;
  689. pcm->info_flags = 0;
  690. strcpy(pcm->name, chip->card->shortname);
  691. chip->pcm = pcm;
  692. return 0;
  693. }
  694. static int atmel_ac97c_mixer_new(struct atmel_ac97c *chip)
  695. {
  696. struct snd_ac97_template template;
  697. memset(&template, 0, sizeof(template));
  698. template.private_data = chip;
  699. return snd_ac97_mixer(chip->ac97_bus, &template, &chip->ac97);
  700. }
  701. static void atmel_ac97c_write(struct snd_ac97 *ac97, unsigned short reg,
  702. unsigned short val)
  703. {
  704. struct atmel_ac97c *chip = get_chip(ac97);
  705. unsigned long word;
  706. int timeout = 40;
  707. word = (reg & 0x7f) << 16 | val;
  708. do {
  709. if (ac97c_readl(chip, COSR) & AC97C_CSR_TXRDY) {
  710. ac97c_writel(chip, COTHR, word);
  711. return;
  712. }
  713. udelay(1);
  714. } while (--timeout);
  715. dev_dbg(&chip->pdev->dev, "codec write timeout\n");
  716. }
  717. static unsigned short atmel_ac97c_read(struct snd_ac97 *ac97,
  718. unsigned short reg)
  719. {
  720. struct atmel_ac97c *chip = get_chip(ac97);
  721. unsigned long word;
  722. int timeout = 40;
  723. int write = 10;
  724. word = (0x80 | (reg & 0x7f)) << 16;
  725. if ((ac97c_readl(chip, COSR) & AC97C_CSR_RXRDY) != 0)
  726. ac97c_readl(chip, CORHR);
  727. retry_write:
  728. timeout = 40;
  729. do {
  730. if ((ac97c_readl(chip, COSR) & AC97C_CSR_TXRDY) != 0) {
  731. ac97c_writel(chip, COTHR, word);
  732. goto read_reg;
  733. }
  734. udelay(10);
  735. } while (--timeout);
  736. if (!--write)
  737. goto timed_out;
  738. goto retry_write;
  739. read_reg:
  740. do {
  741. if ((ac97c_readl(chip, COSR) & AC97C_CSR_RXRDY) != 0) {
  742. unsigned short val = ac97c_readl(chip, CORHR);
  743. return val;
  744. }
  745. udelay(10);
  746. } while (--timeout);
  747. if (!--write)
  748. goto timed_out;
  749. goto retry_write;
  750. timed_out:
  751. dev_dbg(&chip->pdev->dev, "codec read timeout\n");
  752. return 0xffff;
  753. }
  754. static bool filter(struct dma_chan *chan, void *slave)
  755. {
  756. struct dw_dma_slave *dws = slave;
  757. if (dws->dma_dev == chan->device->dev) {
  758. chan->private = dws;
  759. return true;
  760. } else
  761. return false;
  762. }
  763. static void atmel_ac97c_reset(struct atmel_ac97c *chip)
  764. {
  765. ac97c_writel(chip, MR, 0);
  766. ac97c_writel(chip, MR, AC97C_MR_ENA);
  767. ac97c_writel(chip, CAMR, 0);
  768. ac97c_writel(chip, COMR, 0);
  769. if (gpio_is_valid(chip->reset_pin)) {
  770. gpio_set_value(chip->reset_pin, 0);
  771. /* AC97 v2.2 specifications says minimum 1 us. */
  772. udelay(2);
  773. gpio_set_value(chip->reset_pin, 1);
  774. } else {
  775. ac97c_writel(chip, MR, AC97C_MR_WRST | AC97C_MR_ENA);
  776. udelay(2);
  777. ac97c_writel(chip, MR, AC97C_MR_ENA);
  778. }
  779. }
  780. static int atmel_ac97c_probe(struct platform_device *pdev)
  781. {
  782. struct snd_card *card;
  783. struct atmel_ac97c *chip;
  784. struct resource *regs;
  785. struct ac97c_platform_data *pdata;
  786. struct clk *pclk;
  787. static struct snd_ac97_bus_ops ops = {
  788. .write = atmel_ac97c_write,
  789. .read = atmel_ac97c_read,
  790. };
  791. int retval;
  792. int irq;
  793. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  794. if (!regs) {
  795. dev_dbg(&pdev->dev, "no memory resource\n");
  796. return -ENXIO;
  797. }
  798. pdata = pdev->dev.platform_data;
  799. if (!pdata) {
  800. dev_dbg(&pdev->dev, "no platform data\n");
  801. return -ENXIO;
  802. }
  803. irq = platform_get_irq(pdev, 0);
  804. if (irq < 0) {
  805. dev_dbg(&pdev->dev, "could not get irq\n");
  806. return -ENXIO;
  807. }
  808. if (cpu_is_at32ap7000()) {
  809. pclk = clk_get(&pdev->dev, "pclk");
  810. } else {
  811. pclk = clk_get(&pdev->dev, "ac97_clk");
  812. }
  813. if (IS_ERR(pclk)) {
  814. dev_dbg(&pdev->dev, "no peripheral clock\n");
  815. return PTR_ERR(pclk);
  816. }
  817. clk_enable(pclk);
  818. retval = snd_card_create(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
  819. THIS_MODULE, sizeof(struct atmel_ac97c), &card);
  820. if (retval) {
  821. dev_dbg(&pdev->dev, "could not create sound card device\n");
  822. goto err_snd_card_new;
  823. }
  824. chip = get_chip(card);
  825. retval = request_irq(irq, atmel_ac97c_interrupt, 0, "AC97C", chip);
  826. if (retval) {
  827. dev_dbg(&pdev->dev, "unable to request irq %d\n", irq);
  828. goto err_request_irq;
  829. }
  830. chip->irq = irq;
  831. spin_lock_init(&chip->lock);
  832. strcpy(card->driver, "Atmel AC97C");
  833. strcpy(card->shortname, "Atmel AC97C");
  834. sprintf(card->longname, "Atmel AC97 controller");
  835. chip->card = card;
  836. chip->pclk = pclk;
  837. chip->pdev = pdev;
  838. chip->regs = ioremap(regs->start, resource_size(regs));
  839. if (!chip->regs) {
  840. dev_dbg(&pdev->dev, "could not remap register memory\n");
  841. retval = -ENOMEM;
  842. goto err_ioremap;
  843. }
  844. if (gpio_is_valid(pdata->reset_pin)) {
  845. if (gpio_request(pdata->reset_pin, "reset_pin")) {
  846. dev_dbg(&pdev->dev, "reset pin not available\n");
  847. chip->reset_pin = -ENODEV;
  848. } else {
  849. gpio_direction_output(pdata->reset_pin, 1);
  850. chip->reset_pin = pdata->reset_pin;
  851. }
  852. } else {
  853. chip->reset_pin = -EINVAL;
  854. }
  855. snd_card_set_dev(card, &pdev->dev);
  856. atmel_ac97c_reset(chip);
  857. /* Enable overrun interrupt from codec channel */
  858. ac97c_writel(chip, COMR, AC97C_CSR_OVRUN);
  859. ac97c_writel(chip, IER, ac97c_readl(chip, IMR) | AC97C_SR_COEVT);
  860. retval = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus);
  861. if (retval) {
  862. dev_dbg(&pdev->dev, "could not register on ac97 bus\n");
  863. goto err_ac97_bus;
  864. }
  865. retval = atmel_ac97c_mixer_new(chip);
  866. if (retval) {
  867. dev_dbg(&pdev->dev, "could not register ac97 mixer\n");
  868. goto err_ac97_bus;
  869. }
  870. if (cpu_is_at32ap7000()) {
  871. if (pdata->rx_dws.dma_dev) {
  872. dma_cap_mask_t mask;
  873. dma_cap_zero(mask);
  874. dma_cap_set(DMA_SLAVE, mask);
  875. chip->dma.rx_chan = dma_request_channel(mask, filter,
  876. &pdata->rx_dws);
  877. if (chip->dma.rx_chan) {
  878. struct dma_slave_config dma_conf = {
  879. .src_addr = regs->start + AC97C_CARHR +
  880. 2,
  881. .src_addr_width =
  882. DMA_SLAVE_BUSWIDTH_2_BYTES,
  883. .src_maxburst = 1,
  884. .dst_maxburst = 1,
  885. .direction = DMA_DEV_TO_MEM,
  886. .device_fc = false,
  887. };
  888. dmaengine_slave_config(chip->dma.rx_chan,
  889. &dma_conf);
  890. }
  891. dev_info(&chip->pdev->dev, "using %s for DMA RX\n",
  892. dev_name(&chip->dma.rx_chan->dev->device));
  893. set_bit(DMA_RX_CHAN_PRESENT, &chip->flags);
  894. }
  895. if (pdata->tx_dws.dma_dev) {
  896. dma_cap_mask_t mask;
  897. dma_cap_zero(mask);
  898. dma_cap_set(DMA_SLAVE, mask);
  899. chip->dma.tx_chan = dma_request_channel(mask, filter,
  900. &pdata->tx_dws);
  901. if (chip->dma.tx_chan) {
  902. struct dma_slave_config dma_conf = {
  903. .dst_addr = regs->start + AC97C_CATHR +
  904. 2,
  905. .dst_addr_width =
  906. DMA_SLAVE_BUSWIDTH_2_BYTES,
  907. .src_maxburst = 1,
  908. .dst_maxburst = 1,
  909. .direction = DMA_MEM_TO_DEV,
  910. .device_fc = false,
  911. };
  912. dmaengine_slave_config(chip->dma.tx_chan,
  913. &dma_conf);
  914. }
  915. dev_info(&chip->pdev->dev, "using %s for DMA TX\n",
  916. dev_name(&chip->dma.tx_chan->dev->device));
  917. set_bit(DMA_TX_CHAN_PRESENT, &chip->flags);
  918. }
  919. if (!test_bit(DMA_RX_CHAN_PRESENT, &chip->flags) &&
  920. !test_bit(DMA_TX_CHAN_PRESENT, &chip->flags)) {
  921. dev_dbg(&pdev->dev, "DMA not available\n");
  922. retval = -ENODEV;
  923. goto err_dma;
  924. }
  925. } else {
  926. /* Just pretend that we have DMA channel(for at91 i is actually
  927. * the PDC) */
  928. set_bit(DMA_RX_CHAN_PRESENT, &chip->flags);
  929. set_bit(DMA_TX_CHAN_PRESENT, &chip->flags);
  930. }
  931. retval = atmel_ac97c_pcm_new(chip);
  932. if (retval) {
  933. dev_dbg(&pdev->dev, "could not register ac97 pcm device\n");
  934. goto err_dma;
  935. }
  936. retval = snd_card_register(card);
  937. if (retval) {
  938. dev_dbg(&pdev->dev, "could not register sound card\n");
  939. goto err_dma;
  940. }
  941. platform_set_drvdata(pdev, card);
  942. dev_info(&pdev->dev, "Atmel AC97 controller at 0x%p, irq = %d\n",
  943. chip->regs, irq);
  944. return 0;
  945. err_dma:
  946. if (cpu_is_at32ap7000()) {
  947. if (test_bit(DMA_RX_CHAN_PRESENT, &chip->flags))
  948. dma_release_channel(chip->dma.rx_chan);
  949. if (test_bit(DMA_TX_CHAN_PRESENT, &chip->flags))
  950. dma_release_channel(chip->dma.tx_chan);
  951. clear_bit(DMA_RX_CHAN_PRESENT, &chip->flags);
  952. clear_bit(DMA_TX_CHAN_PRESENT, &chip->flags);
  953. chip->dma.rx_chan = NULL;
  954. chip->dma.tx_chan = NULL;
  955. }
  956. err_ac97_bus:
  957. snd_card_set_dev(card, NULL);
  958. if (gpio_is_valid(chip->reset_pin))
  959. gpio_free(chip->reset_pin);
  960. iounmap(chip->regs);
  961. err_ioremap:
  962. free_irq(irq, chip);
  963. err_request_irq:
  964. snd_card_free(card);
  965. err_snd_card_new:
  966. clk_disable(pclk);
  967. clk_put(pclk);
  968. return retval;
  969. }
  970. #ifdef CONFIG_PM_SLEEP
  971. static int atmel_ac97c_suspend(struct device *pdev)
  972. {
  973. struct snd_card *card = dev_get_drvdata(pdev);
  974. struct atmel_ac97c *chip = card->private_data;
  975. if (cpu_is_at32ap7000()) {
  976. if (test_bit(DMA_RX_READY, &chip->flags))
  977. dw_dma_cyclic_stop(chip->dma.rx_chan);
  978. if (test_bit(DMA_TX_READY, &chip->flags))
  979. dw_dma_cyclic_stop(chip->dma.tx_chan);
  980. }
  981. clk_disable(chip->pclk);
  982. return 0;
  983. }
  984. static int atmel_ac97c_resume(struct device *pdev)
  985. {
  986. struct snd_card *card = dev_get_drvdata(pdev);
  987. struct atmel_ac97c *chip = card->private_data;
  988. clk_enable(chip->pclk);
  989. if (cpu_is_at32ap7000()) {
  990. if (test_bit(DMA_RX_READY, &chip->flags))
  991. dw_dma_cyclic_start(chip->dma.rx_chan);
  992. if (test_bit(DMA_TX_READY, &chip->flags))
  993. dw_dma_cyclic_start(chip->dma.tx_chan);
  994. }
  995. return 0;
  996. }
  997. static SIMPLE_DEV_PM_OPS(atmel_ac97c_pm, atmel_ac97c_suspend, atmel_ac97c_resume);
  998. #define ATMEL_AC97C_PM_OPS &atmel_ac97c_pm
  999. #else
  1000. #define ATMEL_AC97C_PM_OPS NULL
  1001. #endif
  1002. static int atmel_ac97c_remove(struct platform_device *pdev)
  1003. {
  1004. struct snd_card *card = platform_get_drvdata(pdev);
  1005. struct atmel_ac97c *chip = get_chip(card);
  1006. if (gpio_is_valid(chip->reset_pin))
  1007. gpio_free(chip->reset_pin);
  1008. ac97c_writel(chip, CAMR, 0);
  1009. ac97c_writel(chip, COMR, 0);
  1010. ac97c_writel(chip, MR, 0);
  1011. clk_disable(chip->pclk);
  1012. clk_put(chip->pclk);
  1013. iounmap(chip->regs);
  1014. free_irq(chip->irq, chip);
  1015. if (cpu_is_at32ap7000()) {
  1016. if (test_bit(DMA_RX_CHAN_PRESENT, &chip->flags))
  1017. dma_release_channel(chip->dma.rx_chan);
  1018. if (test_bit(DMA_TX_CHAN_PRESENT, &chip->flags))
  1019. dma_release_channel(chip->dma.tx_chan);
  1020. clear_bit(DMA_RX_CHAN_PRESENT, &chip->flags);
  1021. clear_bit(DMA_TX_CHAN_PRESENT, &chip->flags);
  1022. chip->dma.rx_chan = NULL;
  1023. chip->dma.tx_chan = NULL;
  1024. }
  1025. snd_card_set_dev(card, NULL);
  1026. snd_card_free(card);
  1027. return 0;
  1028. }
  1029. static struct platform_driver atmel_ac97c_driver = {
  1030. .remove = atmel_ac97c_remove,
  1031. .driver = {
  1032. .name = "atmel_ac97c",
  1033. .owner = THIS_MODULE,
  1034. .pm = ATMEL_AC97C_PM_OPS,
  1035. },
  1036. };
  1037. static int __init atmel_ac97c_init(void)
  1038. {
  1039. return platform_driver_probe(&atmel_ac97c_driver,
  1040. atmel_ac97c_probe);
  1041. }
  1042. module_init(atmel_ac97c_init);
  1043. static void __exit atmel_ac97c_exit(void)
  1044. {
  1045. platform_driver_unregister(&atmel_ac97c_driver);
  1046. }
  1047. module_exit(atmel_ac97c_exit);
  1048. MODULE_LICENSE("GPL");
  1049. MODULE_DESCRIPTION("Driver for Atmel AC97 controller");
  1050. MODULE_AUTHOR("Hans-Christian Egtvedt <egtvedt@samfundet.no>");