pm8001_hwi.c 164 KB

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  1. /*
  2. * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
  3. *
  4. * Copyright (c) 2008-2009 USI Co., Ltd.
  5. * All rights reserved.
  6. *
  7. * Redistribution and use in source and binary forms, with or without
  8. * modification, are permitted provided that the following conditions
  9. * are met:
  10. * 1. Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions, and the following disclaimer,
  12. * without modification.
  13. * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14. * substantially similar to the "NO WARRANTY" disclaimer below
  15. * ("Disclaimer") and any redistribution must be conditioned upon
  16. * including a substantially similar Disclaimer requirement for further
  17. * binary redistribution.
  18. * 3. Neither the names of the above-listed copyright holders nor the names
  19. * of any contributors may be used to endorse or promote products derived
  20. * from this software without specific prior written permission.
  21. *
  22. * Alternatively, this software may be distributed under the terms of the
  23. * GNU General Public License ("GPL") version 2 as published by the Free
  24. * Software Foundation.
  25. *
  26. * NO WARRANTY
  27. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31. * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36. * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37. * POSSIBILITY OF SUCH DAMAGES.
  38. *
  39. */
  40. #include <linux/slab.h>
  41. #include "pm8001_sas.h"
  42. #include "pm8001_hwi.h"
  43. #include "pm8001_chips.h"
  44. #include "pm8001_ctl.h"
  45. /**
  46. * read_main_config_table - read the configure table and save it.
  47. * @pm8001_ha: our hba card information
  48. */
  49. static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
  50. {
  51. void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
  52. pm8001_ha->main_cfg_tbl.pm8001_tbl.signature =
  53. pm8001_mr32(address, 0x00);
  54. pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev =
  55. pm8001_mr32(address, 0x04);
  56. pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev =
  57. pm8001_mr32(address, 0x08);
  58. pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io =
  59. pm8001_mr32(address, 0x0C);
  60. pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl =
  61. pm8001_mr32(address, 0x10);
  62. pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag =
  63. pm8001_mr32(address, 0x14);
  64. pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset =
  65. pm8001_mr32(address, 0x18);
  66. pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset =
  67. pm8001_mr32(address, MAIN_IBQ_OFFSET);
  68. pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset =
  69. pm8001_mr32(address, MAIN_OBQ_OFFSET);
  70. pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag =
  71. pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
  72. /* read analog Setting offset from the configuration table */
  73. pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset =
  74. pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
  75. /* read Error Dump Offset and Length */
  76. pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 =
  77. pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
  78. pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 =
  79. pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
  80. pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 =
  81. pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
  82. pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 =
  83. pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
  84. }
  85. /**
  86. * read_general_status_table - read the general status table and save it.
  87. * @pm8001_ha: our hba card information
  88. */
  89. static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
  90. {
  91. void __iomem *address = pm8001_ha->general_stat_tbl_addr;
  92. pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate =
  93. pm8001_mr32(address, 0x00);
  94. pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0 =
  95. pm8001_mr32(address, 0x04);
  96. pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1 =
  97. pm8001_mr32(address, 0x08);
  98. pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt =
  99. pm8001_mr32(address, 0x0C);
  100. pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt =
  101. pm8001_mr32(address, 0x10);
  102. pm8001_ha->gs_tbl.pm8001_tbl.rsvd =
  103. pm8001_mr32(address, 0x14);
  104. pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0] =
  105. pm8001_mr32(address, 0x18);
  106. pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1] =
  107. pm8001_mr32(address, 0x1C);
  108. pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2] =
  109. pm8001_mr32(address, 0x20);
  110. pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3] =
  111. pm8001_mr32(address, 0x24);
  112. pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4] =
  113. pm8001_mr32(address, 0x28);
  114. pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5] =
  115. pm8001_mr32(address, 0x2C);
  116. pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6] =
  117. pm8001_mr32(address, 0x30);
  118. pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7] =
  119. pm8001_mr32(address, 0x34);
  120. pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val =
  121. pm8001_mr32(address, 0x38);
  122. pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0] =
  123. pm8001_mr32(address, 0x3C);
  124. pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1] =
  125. pm8001_mr32(address, 0x40);
  126. pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0] =
  127. pm8001_mr32(address, 0x44);
  128. pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1] =
  129. pm8001_mr32(address, 0x48);
  130. pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2] =
  131. pm8001_mr32(address, 0x4C);
  132. pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3] =
  133. pm8001_mr32(address, 0x50);
  134. pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4] =
  135. pm8001_mr32(address, 0x54);
  136. pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5] =
  137. pm8001_mr32(address, 0x58);
  138. pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6] =
  139. pm8001_mr32(address, 0x5C);
  140. pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7] =
  141. pm8001_mr32(address, 0x60);
  142. }
  143. /**
  144. * read_inbnd_queue_table - read the inbound queue table and save it.
  145. * @pm8001_ha: our hba card information
  146. */
  147. static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
  148. {
  149. int i;
  150. void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
  151. for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
  152. u32 offset = i * 0x20;
  153. pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
  154. get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
  155. pm8001_ha->inbnd_q_tbl[i].pi_offset =
  156. pm8001_mr32(address, (offset + 0x18));
  157. }
  158. }
  159. /**
  160. * read_outbnd_queue_table - read the outbound queue table and save it.
  161. * @pm8001_ha: our hba card information
  162. */
  163. static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
  164. {
  165. int i;
  166. void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
  167. for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
  168. u32 offset = i * 0x24;
  169. pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
  170. get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
  171. pm8001_ha->outbnd_q_tbl[i].ci_offset =
  172. pm8001_mr32(address, (offset + 0x18));
  173. }
  174. }
  175. /**
  176. * init_default_table_values - init the default table.
  177. * @pm8001_ha: our hba card information
  178. */
  179. static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
  180. {
  181. int i;
  182. u32 offsetib, offsetob;
  183. void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
  184. void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
  185. pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd = 0;
  186. pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3 = 0;
  187. pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7 = 0;
  188. pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3 = 0;
  189. pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7 = 0;
  190. pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 =
  191. 0;
  192. pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 =
  193. 0;
  194. pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
  195. pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
  196. pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0;
  197. pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0;
  198. pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr =
  199. pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
  200. pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr =
  201. pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
  202. pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size =
  203. PM8001_EVENT_LOG_SIZE;
  204. pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option = 0x01;
  205. pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr =
  206. pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
  207. pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr =
  208. pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
  209. pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size =
  210. PM8001_EVENT_LOG_SIZE;
  211. pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option = 0x01;
  212. pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt = 0x01;
  213. for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
  214. pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
  215. PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
  216. pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
  217. pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
  218. pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
  219. pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
  220. pm8001_ha->inbnd_q_tbl[i].base_virt =
  221. (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
  222. pm8001_ha->inbnd_q_tbl[i].total_length =
  223. pm8001_ha->memoryMap.region[IB + i].total_len;
  224. pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
  225. pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
  226. pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
  227. pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
  228. pm8001_ha->inbnd_q_tbl[i].ci_virt =
  229. pm8001_ha->memoryMap.region[CI + i].virt_ptr;
  230. offsetib = i * 0x20;
  231. pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
  232. get_pci_bar_index(pm8001_mr32(addressib,
  233. (offsetib + 0x14)));
  234. pm8001_ha->inbnd_q_tbl[i].pi_offset =
  235. pm8001_mr32(addressib, (offsetib + 0x18));
  236. pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
  237. pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
  238. }
  239. for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
  240. pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
  241. PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
  242. pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
  243. pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
  244. pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
  245. pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
  246. pm8001_ha->outbnd_q_tbl[i].base_virt =
  247. (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
  248. pm8001_ha->outbnd_q_tbl[i].total_length =
  249. pm8001_ha->memoryMap.region[OB + i].total_len;
  250. pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
  251. pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
  252. pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
  253. pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
  254. pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay =
  255. 0 | (10 << 16) | (i << 24);
  256. pm8001_ha->outbnd_q_tbl[i].pi_virt =
  257. pm8001_ha->memoryMap.region[PI + i].virt_ptr;
  258. offsetob = i * 0x24;
  259. pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
  260. get_pci_bar_index(pm8001_mr32(addressob,
  261. offsetob + 0x14));
  262. pm8001_ha->outbnd_q_tbl[i].ci_offset =
  263. pm8001_mr32(addressob, (offsetob + 0x18));
  264. pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
  265. pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
  266. }
  267. }
  268. /**
  269. * update_main_config_table - update the main default table to the HBA.
  270. * @pm8001_ha: our hba card information
  271. */
  272. static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
  273. {
  274. void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
  275. pm8001_mw32(address, 0x24,
  276. pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd);
  277. pm8001_mw32(address, 0x28,
  278. pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3);
  279. pm8001_mw32(address, 0x2C,
  280. pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7);
  281. pm8001_mw32(address, 0x30,
  282. pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3);
  283. pm8001_mw32(address, 0x34,
  284. pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7);
  285. pm8001_mw32(address, 0x38,
  286. pm8001_ha->main_cfg_tbl.pm8001_tbl.
  287. outbound_tgt_ITNexus_event_pid0_3);
  288. pm8001_mw32(address, 0x3C,
  289. pm8001_ha->main_cfg_tbl.pm8001_tbl.
  290. outbound_tgt_ITNexus_event_pid4_7);
  291. pm8001_mw32(address, 0x40,
  292. pm8001_ha->main_cfg_tbl.pm8001_tbl.
  293. outbound_tgt_ssp_event_pid0_3);
  294. pm8001_mw32(address, 0x44,
  295. pm8001_ha->main_cfg_tbl.pm8001_tbl.
  296. outbound_tgt_ssp_event_pid4_7);
  297. pm8001_mw32(address, 0x48,
  298. pm8001_ha->main_cfg_tbl.pm8001_tbl.
  299. outbound_tgt_smp_event_pid0_3);
  300. pm8001_mw32(address, 0x4C,
  301. pm8001_ha->main_cfg_tbl.pm8001_tbl.
  302. outbound_tgt_smp_event_pid4_7);
  303. pm8001_mw32(address, 0x50,
  304. pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr);
  305. pm8001_mw32(address, 0x54,
  306. pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr);
  307. pm8001_mw32(address, 0x58,
  308. pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size);
  309. pm8001_mw32(address, 0x5C,
  310. pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option);
  311. pm8001_mw32(address, 0x60,
  312. pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr);
  313. pm8001_mw32(address, 0x64,
  314. pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr);
  315. pm8001_mw32(address, 0x68,
  316. pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size);
  317. pm8001_mw32(address, 0x6C,
  318. pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option);
  319. pm8001_mw32(address, 0x70,
  320. pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt);
  321. }
  322. /**
  323. * update_inbnd_queue_table - update the inbound queue table to the HBA.
  324. * @pm8001_ha: our hba card information
  325. */
  326. static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
  327. int number)
  328. {
  329. void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
  330. u16 offset = number * 0x20;
  331. pm8001_mw32(address, offset + 0x00,
  332. pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
  333. pm8001_mw32(address, offset + 0x04,
  334. pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
  335. pm8001_mw32(address, offset + 0x08,
  336. pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
  337. pm8001_mw32(address, offset + 0x0C,
  338. pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
  339. pm8001_mw32(address, offset + 0x10,
  340. pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
  341. }
  342. /**
  343. * update_outbnd_queue_table - update the outbound queue table to the HBA.
  344. * @pm8001_ha: our hba card information
  345. */
  346. static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
  347. int number)
  348. {
  349. void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
  350. u16 offset = number * 0x24;
  351. pm8001_mw32(address, offset + 0x00,
  352. pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
  353. pm8001_mw32(address, offset + 0x04,
  354. pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
  355. pm8001_mw32(address, offset + 0x08,
  356. pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
  357. pm8001_mw32(address, offset + 0x0C,
  358. pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
  359. pm8001_mw32(address, offset + 0x10,
  360. pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
  361. pm8001_mw32(address, offset + 0x1C,
  362. pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
  363. }
  364. /**
  365. * pm8001_bar4_shift - function is called to shift BAR base address
  366. * @pm8001_ha : our hba card infomation
  367. * @shiftValue : shifting value in memory bar.
  368. */
  369. int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
  370. {
  371. u32 regVal;
  372. unsigned long start;
  373. /* program the inbound AXI translation Lower Address */
  374. pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
  375. /* confirm the setting is written */
  376. start = jiffies + HZ; /* 1 sec */
  377. do {
  378. regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
  379. } while ((regVal != shiftValue) && time_before(jiffies, start));
  380. if (regVal != shiftValue) {
  381. PM8001_INIT_DBG(pm8001_ha,
  382. pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW"
  383. " = 0x%x\n", regVal));
  384. return -1;
  385. }
  386. return 0;
  387. }
  388. /**
  389. * mpi_set_phys_g3_with_ssc
  390. * @pm8001_ha: our hba card information
  391. * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
  392. */
  393. static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha,
  394. u32 SSCbit)
  395. {
  396. u32 value, offset, i;
  397. unsigned long flags;
  398. #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
  399. #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
  400. #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
  401. #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
  402. #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
  403. #define PHY_G3_WITH_SSC_BIT_SHIFT 13
  404. #define SNW3_PHY_CAPABILITIES_PARITY 31
  405. /*
  406. * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
  407. * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
  408. */
  409. spin_lock_irqsave(&pm8001_ha->lock, flags);
  410. if (-1 == pm8001_bar4_shift(pm8001_ha,
  411. SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
  412. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  413. return;
  414. }
  415. for (i = 0; i < 4; i++) {
  416. offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
  417. pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
  418. }
  419. /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
  420. if (-1 == pm8001_bar4_shift(pm8001_ha,
  421. SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
  422. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  423. return;
  424. }
  425. for (i = 4; i < 8; i++) {
  426. offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
  427. pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
  428. }
  429. /*************************************************************
  430. Change the SSC upspreading value to 0x0 so that upspreading is disabled.
  431. Device MABC SMOD0 Controls
  432. Address: (via MEMBASE-III):
  433. Using shifted destination address 0x0_0000: with Offset 0xD8
  434. 31:28 R/W Reserved Do not change
  435. 27:24 R/W SAS_SMOD_SPRDUP 0000
  436. 23:20 R/W SAS_SMOD_SPRDDN 0000
  437. 19:0 R/W Reserved Do not change
  438. Upon power-up this register will read as 0x8990c016,
  439. and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
  440. so that the written value will be 0x8090c016.
  441. This will ensure only down-spreading SSC is enabled on the SPC.
  442. *************************************************************/
  443. value = pm8001_cr32(pm8001_ha, 2, 0xd8);
  444. pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
  445. /*set the shifted destination address to 0x0 to avoid error operation */
  446. pm8001_bar4_shift(pm8001_ha, 0x0);
  447. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  448. return;
  449. }
  450. /**
  451. * mpi_set_open_retry_interval_reg
  452. * @pm8001_ha: our hba card information
  453. * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us.
  454. */
  455. static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
  456. u32 interval)
  457. {
  458. u32 offset;
  459. u32 value;
  460. u32 i;
  461. unsigned long flags;
  462. #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
  463. #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
  464. #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
  465. #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
  466. #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
  467. value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
  468. spin_lock_irqsave(&pm8001_ha->lock, flags);
  469. /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
  470. if (-1 == pm8001_bar4_shift(pm8001_ha,
  471. OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
  472. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  473. return;
  474. }
  475. for (i = 0; i < 4; i++) {
  476. offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
  477. pm8001_cw32(pm8001_ha, 2, offset, value);
  478. }
  479. if (-1 == pm8001_bar4_shift(pm8001_ha,
  480. OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
  481. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  482. return;
  483. }
  484. for (i = 4; i < 8; i++) {
  485. offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
  486. pm8001_cw32(pm8001_ha, 2, offset, value);
  487. }
  488. /*set the shifted destination address to 0x0 to avoid error operation */
  489. pm8001_bar4_shift(pm8001_ha, 0x0);
  490. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  491. return;
  492. }
  493. /**
  494. * mpi_init_check - check firmware initialization status.
  495. * @pm8001_ha: our hba card information
  496. */
  497. static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
  498. {
  499. u32 max_wait_count;
  500. u32 value;
  501. u32 gst_len_mpistate;
  502. /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
  503. table is updated */
  504. pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
  505. /* wait until Inbound DoorBell Clear Register toggled */
  506. max_wait_count = 1 * 1000 * 1000;/* 1 sec */
  507. do {
  508. udelay(1);
  509. value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
  510. value &= SPC_MSGU_CFG_TABLE_UPDATE;
  511. } while ((value != 0) && (--max_wait_count));
  512. if (!max_wait_count)
  513. return -1;
  514. /* check the MPI-State for initialization */
  515. gst_len_mpistate =
  516. pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
  517. GST_GSTLEN_MPIS_OFFSET);
  518. if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
  519. return -1;
  520. /* check MPI Initialization error */
  521. gst_len_mpistate = gst_len_mpistate >> 16;
  522. if (0x0000 != gst_len_mpistate)
  523. return -1;
  524. return 0;
  525. }
  526. /**
  527. * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
  528. * @pm8001_ha: our hba card information
  529. */
  530. static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
  531. {
  532. u32 value, value1;
  533. u32 max_wait_count;
  534. /* check error state */
  535. value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
  536. value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
  537. /* check AAP error */
  538. if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
  539. /* error state */
  540. value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
  541. return -1;
  542. }
  543. /* check IOP error */
  544. if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
  545. /* error state */
  546. value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
  547. return -1;
  548. }
  549. /* bit 4-31 of scratch pad1 should be zeros if it is not
  550. in error state*/
  551. if (value & SCRATCH_PAD1_STATE_MASK) {
  552. /* error case */
  553. pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
  554. return -1;
  555. }
  556. /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
  557. in error state */
  558. if (value1 & SCRATCH_PAD2_STATE_MASK) {
  559. /* error case */
  560. return -1;
  561. }
  562. max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
  563. /* wait until scratch pad 1 and 2 registers in ready state */
  564. do {
  565. udelay(1);
  566. value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
  567. & SCRATCH_PAD1_RDY;
  568. value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
  569. & SCRATCH_PAD2_RDY;
  570. if ((--max_wait_count) == 0)
  571. return -1;
  572. } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
  573. return 0;
  574. }
  575. static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
  576. {
  577. void __iomem *base_addr;
  578. u32 value;
  579. u32 offset;
  580. u32 pcibar;
  581. u32 pcilogic;
  582. value = pm8001_cr32(pm8001_ha, 0, 0x44);
  583. offset = value & 0x03FFFFFF;
  584. PM8001_INIT_DBG(pm8001_ha,
  585. pm8001_printk("Scratchpad 0 Offset: %x\n", offset));
  586. pcilogic = (value & 0xFC000000) >> 26;
  587. pcibar = get_pci_bar_index(pcilogic);
  588. PM8001_INIT_DBG(pm8001_ha,
  589. pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
  590. pm8001_ha->main_cfg_tbl_addr = base_addr =
  591. pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
  592. pm8001_ha->general_stat_tbl_addr =
  593. base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
  594. pm8001_ha->inbnd_q_tbl_addr =
  595. base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
  596. pm8001_ha->outbnd_q_tbl_addr =
  597. base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
  598. }
  599. /**
  600. * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
  601. * @pm8001_ha: our hba card information
  602. */
  603. static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
  604. {
  605. u8 i = 0;
  606. u16 deviceid;
  607. pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
  608. /* 8081 controllers need BAR shift to access MPI space
  609. * as this is shared with BIOS data */
  610. if (deviceid == 0x8081) {
  611. if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
  612. PM8001_FAIL_DBG(pm8001_ha,
  613. pm8001_printk("Shift Bar4 to 0x%x failed\n",
  614. GSM_SM_BASE));
  615. return -1;
  616. }
  617. }
  618. /* check the firmware status */
  619. if (-1 == check_fw_ready(pm8001_ha)) {
  620. PM8001_FAIL_DBG(pm8001_ha,
  621. pm8001_printk("Firmware is not ready!\n"));
  622. return -EBUSY;
  623. }
  624. /* Initialize pci space address eg: mpi offset */
  625. init_pci_device_addresses(pm8001_ha);
  626. init_default_table_values(pm8001_ha);
  627. read_main_config_table(pm8001_ha);
  628. read_general_status_table(pm8001_ha);
  629. read_inbnd_queue_table(pm8001_ha);
  630. read_outbnd_queue_table(pm8001_ha);
  631. /* update main config table ,inbound table and outbound table */
  632. update_main_config_table(pm8001_ha);
  633. for (i = 0; i < PM8001_MAX_INB_NUM; i++)
  634. update_inbnd_queue_table(pm8001_ha, i);
  635. for (i = 0; i < PM8001_MAX_OUTB_NUM; i++)
  636. update_outbnd_queue_table(pm8001_ha, i);
  637. /* 8081 controller donot require these operations */
  638. if (deviceid != 0x8081) {
  639. mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
  640. /* 7->130ms, 34->500ms, 119->1.5s */
  641. mpi_set_open_retry_interval_reg(pm8001_ha, 119);
  642. }
  643. /* notify firmware update finished and check initialization status */
  644. if (0 == mpi_init_check(pm8001_ha)) {
  645. PM8001_INIT_DBG(pm8001_ha,
  646. pm8001_printk("MPI initialize successful!\n"));
  647. } else
  648. return -EBUSY;
  649. /*This register is a 16-bit timer with a resolution of 1us. This is the
  650. timer used for interrupt delay/coalescing in the PCIe Application Layer.
  651. Zero is not a valid value. A value of 1 in the register will cause the
  652. interrupts to be normal. A value greater than 1 will cause coalescing
  653. delays.*/
  654. pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
  655. pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
  656. return 0;
  657. }
  658. static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
  659. {
  660. u32 max_wait_count;
  661. u32 value;
  662. u32 gst_len_mpistate;
  663. u16 deviceid;
  664. pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
  665. if (deviceid == 0x8081) {
  666. if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
  667. PM8001_FAIL_DBG(pm8001_ha,
  668. pm8001_printk("Shift Bar4 to 0x%x failed\n",
  669. GSM_SM_BASE));
  670. return -1;
  671. }
  672. }
  673. init_pci_device_addresses(pm8001_ha);
  674. /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
  675. table is stop */
  676. pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
  677. /* wait until Inbound DoorBell Clear Register toggled */
  678. max_wait_count = 1 * 1000 * 1000;/* 1 sec */
  679. do {
  680. udelay(1);
  681. value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
  682. value &= SPC_MSGU_CFG_TABLE_RESET;
  683. } while ((value != 0) && (--max_wait_count));
  684. if (!max_wait_count) {
  685. PM8001_FAIL_DBG(pm8001_ha,
  686. pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value));
  687. return -1;
  688. }
  689. /* check the MPI-State for termination in progress */
  690. /* wait until Inbound DoorBell Clear Register toggled */
  691. max_wait_count = 1 * 1000 * 1000; /* 1 sec */
  692. do {
  693. udelay(1);
  694. gst_len_mpistate =
  695. pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
  696. GST_GSTLEN_MPIS_OFFSET);
  697. if (GST_MPI_STATE_UNINIT ==
  698. (gst_len_mpistate & GST_MPI_STATE_MASK))
  699. break;
  700. } while (--max_wait_count);
  701. if (!max_wait_count) {
  702. PM8001_FAIL_DBG(pm8001_ha,
  703. pm8001_printk(" TIME OUT MPI State = 0x%x\n",
  704. gst_len_mpistate & GST_MPI_STATE_MASK));
  705. return -1;
  706. }
  707. return 0;
  708. }
  709. /**
  710. * soft_reset_ready_check - Function to check FW is ready for soft reset.
  711. * @pm8001_ha: our hba card information
  712. */
  713. static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
  714. {
  715. u32 regVal, regVal1, regVal2;
  716. if (mpi_uninit_check(pm8001_ha) != 0) {
  717. PM8001_FAIL_DBG(pm8001_ha,
  718. pm8001_printk("MPI state is not ready\n"));
  719. return -1;
  720. }
  721. /* read the scratch pad 2 register bit 2 */
  722. regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
  723. & SCRATCH_PAD2_FWRDY_RST;
  724. if (regVal == SCRATCH_PAD2_FWRDY_RST) {
  725. PM8001_INIT_DBG(pm8001_ha,
  726. pm8001_printk("Firmware is ready for reset .\n"));
  727. } else {
  728. unsigned long flags;
  729. /* Trigger NMI twice via RB6 */
  730. spin_lock_irqsave(&pm8001_ha->lock, flags);
  731. if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
  732. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  733. PM8001_FAIL_DBG(pm8001_ha,
  734. pm8001_printk("Shift Bar4 to 0x%x failed\n",
  735. RB6_ACCESS_REG));
  736. return -1;
  737. }
  738. pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
  739. RB6_MAGIC_NUMBER_RST);
  740. pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
  741. /* wait for 100 ms */
  742. mdelay(100);
  743. regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
  744. SCRATCH_PAD2_FWRDY_RST;
  745. if (regVal != SCRATCH_PAD2_FWRDY_RST) {
  746. regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
  747. regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
  748. PM8001_FAIL_DBG(pm8001_ha,
  749. pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1"
  750. "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
  751. regVal1, regVal2));
  752. PM8001_FAIL_DBG(pm8001_ha,
  753. pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
  754. pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
  755. PM8001_FAIL_DBG(pm8001_ha,
  756. pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
  757. pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
  758. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  759. return -1;
  760. }
  761. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  762. }
  763. return 0;
  764. }
  765. /**
  766. * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
  767. * the FW register status to the originated status.
  768. * @pm8001_ha: our hba card information
  769. */
  770. static int
  771. pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
  772. {
  773. u32 regVal, toggleVal;
  774. u32 max_wait_count;
  775. u32 regVal1, regVal2, regVal3;
  776. u32 signature = 0x252acbcd; /* for host scratch pad0 */
  777. unsigned long flags;
  778. /* step1: Check FW is ready for soft reset */
  779. if (soft_reset_ready_check(pm8001_ha) != 0) {
  780. PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n"));
  781. return -1;
  782. }
  783. /* step 2: clear NMI status register on AAP1 and IOP, write the same
  784. value to clear */
  785. /* map 0x60000 to BAR4(0x20), BAR2(win) */
  786. spin_lock_irqsave(&pm8001_ha->lock, flags);
  787. if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
  788. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  789. PM8001_FAIL_DBG(pm8001_ha,
  790. pm8001_printk("Shift Bar4 to 0x%x failed\n",
  791. MBIC_AAP1_ADDR_BASE));
  792. return -1;
  793. }
  794. regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
  795. PM8001_INIT_DBG(pm8001_ha,
  796. pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal));
  797. pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
  798. /* map 0x70000 to BAR4(0x20), BAR2(win) */
  799. if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
  800. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  801. PM8001_FAIL_DBG(pm8001_ha,
  802. pm8001_printk("Shift Bar4 to 0x%x failed\n",
  803. MBIC_IOP_ADDR_BASE));
  804. return -1;
  805. }
  806. regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
  807. PM8001_INIT_DBG(pm8001_ha,
  808. pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal));
  809. pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
  810. regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
  811. PM8001_INIT_DBG(pm8001_ha,
  812. pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal));
  813. pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
  814. regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
  815. PM8001_INIT_DBG(pm8001_ha,
  816. pm8001_printk("PCIE - Event Interrupt = 0x%x\n", regVal));
  817. pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
  818. regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
  819. PM8001_INIT_DBG(pm8001_ha,
  820. pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal));
  821. pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
  822. regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
  823. PM8001_INIT_DBG(pm8001_ha,
  824. pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal));
  825. pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
  826. /* read the scratch pad 1 register bit 2 */
  827. regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
  828. & SCRATCH_PAD1_RST;
  829. toggleVal = regVal ^ SCRATCH_PAD1_RST;
  830. /* set signature in host scratch pad0 register to tell SPC that the
  831. host performs the soft reset */
  832. pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
  833. /* read required registers for confirmming */
  834. /* map 0x0700000 to BAR4(0x20), BAR2(win) */
  835. if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
  836. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  837. PM8001_FAIL_DBG(pm8001_ha,
  838. pm8001_printk("Shift Bar4 to 0x%x failed\n",
  839. GSM_ADDR_BASE));
  840. return -1;
  841. }
  842. PM8001_INIT_DBG(pm8001_ha,
  843. pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and"
  844. " Reset = 0x%x\n",
  845. pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
  846. /* step 3: host read GSM Configuration and Reset register */
  847. regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
  848. /* Put those bits to low */
  849. /* GSM XCBI offset = 0x70 0000
  850. 0x00 Bit 13 COM_SLV_SW_RSTB 1
  851. 0x00 Bit 12 QSSP_SW_RSTB 1
  852. 0x00 Bit 11 RAAE_SW_RSTB 1
  853. 0x00 Bit 9 RB_1_SW_RSTB 1
  854. 0x00 Bit 8 SM_SW_RSTB 1
  855. */
  856. regVal &= ~(0x00003b00);
  857. /* host write GSM Configuration and Reset register */
  858. pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
  859. PM8001_INIT_DBG(pm8001_ha,
  860. pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM "
  861. "Configuration and Reset is set to = 0x%x\n",
  862. pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
  863. /* step 4: */
  864. /* disable GSM - Read Address Parity Check */
  865. regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
  866. PM8001_INIT_DBG(pm8001_ha,
  867. pm8001_printk("GSM 0x700038 - Read Address Parity Check "
  868. "Enable = 0x%x\n", regVal1));
  869. pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
  870. PM8001_INIT_DBG(pm8001_ha,
  871. pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
  872. "is set to = 0x%x\n",
  873. pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
  874. /* disable GSM - Write Address Parity Check */
  875. regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
  876. PM8001_INIT_DBG(pm8001_ha,
  877. pm8001_printk("GSM 0x700040 - Write Address Parity Check"
  878. " Enable = 0x%x\n", regVal2));
  879. pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
  880. PM8001_INIT_DBG(pm8001_ha,
  881. pm8001_printk("GSM 0x700040 - Write Address Parity Check "
  882. "Enable is set to = 0x%x\n",
  883. pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
  884. /* disable GSM - Write Data Parity Check */
  885. regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
  886. PM8001_INIT_DBG(pm8001_ha,
  887. pm8001_printk("GSM 0x300048 - Write Data Parity Check"
  888. " Enable = 0x%x\n", regVal3));
  889. pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
  890. PM8001_INIT_DBG(pm8001_ha,
  891. pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable"
  892. "is set to = 0x%x\n",
  893. pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
  894. /* step 5: delay 10 usec */
  895. udelay(10);
  896. /* step 5-b: set GPIO-0 output control to tristate anyway */
  897. if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
  898. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  899. PM8001_INIT_DBG(pm8001_ha,
  900. pm8001_printk("Shift Bar4 to 0x%x failed\n",
  901. GPIO_ADDR_BASE));
  902. return -1;
  903. }
  904. regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
  905. PM8001_INIT_DBG(pm8001_ha,
  906. pm8001_printk("GPIO Output Control Register:"
  907. " = 0x%x\n", regVal));
  908. /* set GPIO-0 output control to tri-state */
  909. regVal &= 0xFFFFFFFC;
  910. pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
  911. /* Step 6: Reset the IOP and AAP1 */
  912. /* map 0x00000 to BAR4(0x20), BAR2(win) */
  913. if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
  914. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  915. PM8001_FAIL_DBG(pm8001_ha,
  916. pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
  917. SPC_TOP_LEVEL_ADDR_BASE));
  918. return -1;
  919. }
  920. regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
  921. PM8001_INIT_DBG(pm8001_ha,
  922. pm8001_printk("Top Register before resetting IOP/AAP1"
  923. ":= 0x%x\n", regVal));
  924. regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
  925. pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
  926. /* step 7: Reset the BDMA/OSSP */
  927. regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
  928. PM8001_INIT_DBG(pm8001_ha,
  929. pm8001_printk("Top Register before resetting BDMA/OSSP"
  930. ": = 0x%x\n", regVal));
  931. regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
  932. pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
  933. /* step 8: delay 10 usec */
  934. udelay(10);
  935. /* step 9: bring the BDMA and OSSP out of reset */
  936. regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
  937. PM8001_INIT_DBG(pm8001_ha,
  938. pm8001_printk("Top Register before bringing up BDMA/OSSP"
  939. ":= 0x%x\n", regVal));
  940. regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
  941. pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
  942. /* step 10: delay 10 usec */
  943. udelay(10);
  944. /* step 11: reads and sets the GSM Configuration and Reset Register */
  945. /* map 0x0700000 to BAR4(0x20), BAR2(win) */
  946. if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
  947. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  948. PM8001_FAIL_DBG(pm8001_ha,
  949. pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
  950. GSM_ADDR_BASE));
  951. return -1;
  952. }
  953. PM8001_INIT_DBG(pm8001_ha,
  954. pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and "
  955. "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
  956. regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
  957. /* Put those bits to high */
  958. /* GSM XCBI offset = 0x70 0000
  959. 0x00 Bit 13 COM_SLV_SW_RSTB 1
  960. 0x00 Bit 12 QSSP_SW_RSTB 1
  961. 0x00 Bit 11 RAAE_SW_RSTB 1
  962. 0x00 Bit 9 RB_1_SW_RSTB 1
  963. 0x00 Bit 8 SM_SW_RSTB 1
  964. */
  965. regVal |= (GSM_CONFIG_RESET_VALUE);
  966. pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
  967. PM8001_INIT_DBG(pm8001_ha,
  968. pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM"
  969. " Configuration and Reset is set to = 0x%x\n",
  970. pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
  971. /* step 12: Restore GSM - Read Address Parity Check */
  972. regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
  973. /* just for debugging */
  974. PM8001_INIT_DBG(pm8001_ha,
  975. pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
  976. " = 0x%x\n", regVal));
  977. pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
  978. PM8001_INIT_DBG(pm8001_ha,
  979. pm8001_printk("GSM 0x700038 - Read Address Parity"
  980. " Check Enable is set to = 0x%x\n",
  981. pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
  982. /* Restore GSM - Write Address Parity Check */
  983. regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
  984. pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
  985. PM8001_INIT_DBG(pm8001_ha,
  986. pm8001_printk("GSM 0x700040 - Write Address Parity Check"
  987. " Enable is set to = 0x%x\n",
  988. pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
  989. /* Restore GSM - Write Data Parity Check */
  990. regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
  991. pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
  992. PM8001_INIT_DBG(pm8001_ha,
  993. pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable"
  994. "is set to = 0x%x\n",
  995. pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
  996. /* step 13: bring the IOP and AAP1 out of reset */
  997. /* map 0x00000 to BAR4(0x20), BAR2(win) */
  998. if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
  999. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  1000. PM8001_FAIL_DBG(pm8001_ha,
  1001. pm8001_printk("Shift Bar4 to 0x%x failed\n",
  1002. SPC_TOP_LEVEL_ADDR_BASE));
  1003. return -1;
  1004. }
  1005. regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
  1006. regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
  1007. pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
  1008. /* step 14: delay 10 usec - Normal Mode */
  1009. udelay(10);
  1010. /* check Soft Reset Normal mode or Soft Reset HDA mode */
  1011. if (signature == SPC_SOFT_RESET_SIGNATURE) {
  1012. /* step 15 (Normal Mode): wait until scratch pad1 register
  1013. bit 2 toggled */
  1014. max_wait_count = 2 * 1000 * 1000;/* 2 sec */
  1015. do {
  1016. udelay(1);
  1017. regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
  1018. SCRATCH_PAD1_RST;
  1019. } while ((regVal != toggleVal) && (--max_wait_count));
  1020. if (!max_wait_count) {
  1021. regVal = pm8001_cr32(pm8001_ha, 0,
  1022. MSGU_SCRATCH_PAD_1);
  1023. PM8001_FAIL_DBG(pm8001_ha,
  1024. pm8001_printk("TIMEOUT : ToggleVal 0x%x,"
  1025. "MSGU_SCRATCH_PAD1 = 0x%x\n",
  1026. toggleVal, regVal));
  1027. PM8001_FAIL_DBG(pm8001_ha,
  1028. pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
  1029. pm8001_cr32(pm8001_ha, 0,
  1030. MSGU_SCRATCH_PAD_0)));
  1031. PM8001_FAIL_DBG(pm8001_ha,
  1032. pm8001_printk("SCRATCH_PAD2 value = 0x%x\n",
  1033. pm8001_cr32(pm8001_ha, 0,
  1034. MSGU_SCRATCH_PAD_2)));
  1035. PM8001_FAIL_DBG(pm8001_ha,
  1036. pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
  1037. pm8001_cr32(pm8001_ha, 0,
  1038. MSGU_SCRATCH_PAD_3)));
  1039. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  1040. return -1;
  1041. }
  1042. /* step 16 (Normal) - Clear ODMR and ODCR */
  1043. pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
  1044. pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
  1045. /* step 17 (Normal Mode): wait for the FW and IOP to get
  1046. ready - 1 sec timeout */
  1047. /* Wait for the SPC Configuration Table to be ready */
  1048. if (check_fw_ready(pm8001_ha) == -1) {
  1049. regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
  1050. /* return error if MPI Configuration Table not ready */
  1051. PM8001_INIT_DBG(pm8001_ha,
  1052. pm8001_printk("FW not ready SCRATCH_PAD1"
  1053. " = 0x%x\n", regVal));
  1054. regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
  1055. /* return error if MPI Configuration Table not ready */
  1056. PM8001_INIT_DBG(pm8001_ha,
  1057. pm8001_printk("FW not ready SCRATCH_PAD2"
  1058. " = 0x%x\n", regVal));
  1059. PM8001_INIT_DBG(pm8001_ha,
  1060. pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
  1061. pm8001_cr32(pm8001_ha, 0,
  1062. MSGU_SCRATCH_PAD_0)));
  1063. PM8001_INIT_DBG(pm8001_ha,
  1064. pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
  1065. pm8001_cr32(pm8001_ha, 0,
  1066. MSGU_SCRATCH_PAD_3)));
  1067. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  1068. return -1;
  1069. }
  1070. }
  1071. pm8001_bar4_shift(pm8001_ha, 0);
  1072. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  1073. PM8001_INIT_DBG(pm8001_ha,
  1074. pm8001_printk("SPC soft reset Complete\n"));
  1075. return 0;
  1076. }
  1077. static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
  1078. {
  1079. u32 i;
  1080. u32 regVal;
  1081. PM8001_INIT_DBG(pm8001_ha,
  1082. pm8001_printk("chip reset start\n"));
  1083. /* do SPC chip reset. */
  1084. regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
  1085. regVal &= ~(SPC_REG_RESET_DEVICE);
  1086. pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
  1087. /* delay 10 usec */
  1088. udelay(10);
  1089. /* bring chip reset out of reset */
  1090. regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
  1091. regVal |= SPC_REG_RESET_DEVICE;
  1092. pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
  1093. /* delay 10 usec */
  1094. udelay(10);
  1095. /* wait for 20 msec until the firmware gets reloaded */
  1096. i = 20;
  1097. do {
  1098. mdelay(1);
  1099. } while ((--i) != 0);
  1100. PM8001_INIT_DBG(pm8001_ha,
  1101. pm8001_printk("chip reset finished\n"));
  1102. }
  1103. /**
  1104. * pm8001_chip_iounmap - which maped when initialized.
  1105. * @pm8001_ha: our hba card information
  1106. */
  1107. void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
  1108. {
  1109. s8 bar, logical = 0;
  1110. for (bar = 0; bar < 6; bar++) {
  1111. /*
  1112. ** logical BARs for SPC:
  1113. ** bar 0 and 1 - logical BAR0
  1114. ** bar 2 and 3 - logical BAR1
  1115. ** bar4 - logical BAR2
  1116. ** bar5 - logical BAR3
  1117. ** Skip the appropriate assignments:
  1118. */
  1119. if ((bar == 1) || (bar == 3))
  1120. continue;
  1121. if (pm8001_ha->io_mem[logical].memvirtaddr) {
  1122. iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
  1123. logical++;
  1124. }
  1125. }
  1126. }
  1127. /**
  1128. * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
  1129. * @pm8001_ha: our hba card information
  1130. */
  1131. static void
  1132. pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
  1133. {
  1134. pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
  1135. pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
  1136. }
  1137. /**
  1138. * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
  1139. * @pm8001_ha: our hba card information
  1140. */
  1141. static void
  1142. pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
  1143. {
  1144. pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
  1145. }
  1146. /**
  1147. * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
  1148. * @pm8001_ha: our hba card information
  1149. */
  1150. static void
  1151. pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
  1152. u32 int_vec_idx)
  1153. {
  1154. u32 msi_index;
  1155. u32 value;
  1156. msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
  1157. msi_index += MSIX_TABLE_BASE;
  1158. pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
  1159. value = (1 << int_vec_idx);
  1160. pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value);
  1161. }
  1162. /**
  1163. * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
  1164. * @pm8001_ha: our hba card information
  1165. */
  1166. static void
  1167. pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
  1168. u32 int_vec_idx)
  1169. {
  1170. u32 msi_index;
  1171. msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
  1172. msi_index += MSIX_TABLE_BASE;
  1173. pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE);
  1174. }
  1175. /**
  1176. * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
  1177. * @pm8001_ha: our hba card information
  1178. */
  1179. static void
  1180. pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
  1181. {
  1182. #ifdef PM8001_USE_MSIX
  1183. pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
  1184. return;
  1185. #endif
  1186. pm8001_chip_intx_interrupt_enable(pm8001_ha);
  1187. }
  1188. /**
  1189. * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
  1190. * @pm8001_ha: our hba card information
  1191. */
  1192. static void
  1193. pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
  1194. {
  1195. #ifdef PM8001_USE_MSIX
  1196. pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
  1197. return;
  1198. #endif
  1199. pm8001_chip_intx_interrupt_disable(pm8001_ha);
  1200. }
  1201. /**
  1202. * pm8001_mpi_msg_free_get - get the free message buffer for transfer
  1203. * inbound queue.
  1204. * @circularQ: the inbound queue we want to transfer to HBA.
  1205. * @messageSize: the message size of this transfer, normally it is 64 bytes
  1206. * @messagePtr: the pointer to message.
  1207. */
  1208. int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
  1209. u16 messageSize, void **messagePtr)
  1210. {
  1211. u32 offset, consumer_index;
  1212. struct mpi_msg_hdr *msgHeader;
  1213. u8 bcCount = 1; /* only support single buffer */
  1214. /* Checks is the requested message size can be allocated in this queue*/
  1215. if (messageSize > IOMB_SIZE_SPCV) {
  1216. *messagePtr = NULL;
  1217. return -1;
  1218. }
  1219. /* Stores the new consumer index */
  1220. consumer_index = pm8001_read_32(circularQ->ci_virt);
  1221. circularQ->consumer_index = cpu_to_le32(consumer_index);
  1222. if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) ==
  1223. le32_to_cpu(circularQ->consumer_index)) {
  1224. *messagePtr = NULL;
  1225. return -1;
  1226. }
  1227. /* get memory IOMB buffer address */
  1228. offset = circularQ->producer_idx * messageSize;
  1229. /* increment to next bcCount element */
  1230. circularQ->producer_idx = (circularQ->producer_idx + bcCount)
  1231. % PM8001_MPI_QUEUE;
  1232. /* Adds that distance to the base of the region virtual address plus
  1233. the message header size*/
  1234. msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
  1235. *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
  1236. return 0;
  1237. }
  1238. /**
  1239. * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to
  1240. * FW to tell the fw to get this message from IOMB.
  1241. * @pm8001_ha: our hba card information
  1242. * @circularQ: the inbound queue we want to transfer to HBA.
  1243. * @opCode: the operation code represents commands which LLDD and fw recognized.
  1244. * @payload: the command payload of each operation command.
  1245. */
  1246. int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
  1247. struct inbound_queue_table *circularQ,
  1248. u32 opCode, void *payload, u32 responseQueue)
  1249. {
  1250. u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
  1251. void *pMessage;
  1252. if (pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size,
  1253. &pMessage) < 0) {
  1254. PM8001_IO_DBG(pm8001_ha,
  1255. pm8001_printk("No free mpi buffer\n"));
  1256. return -1;
  1257. }
  1258. BUG_ON(!payload);
  1259. /*Copy to the payload*/
  1260. memcpy(pMessage, payload, (pm8001_ha->iomb_size -
  1261. sizeof(struct mpi_msg_hdr)));
  1262. /*Build the header*/
  1263. Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
  1264. | ((responseQueue & 0x3F) << 16)
  1265. | ((category & 0xF) << 12) | (opCode & 0xFFF));
  1266. pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
  1267. /*Update the PI to the firmware*/
  1268. pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
  1269. circularQ->pi_offset, circularQ->producer_idx);
  1270. PM8001_IO_DBG(pm8001_ha,
  1271. pm8001_printk("INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n",
  1272. responseQueue, opCode, circularQ->producer_idx,
  1273. circularQ->consumer_index));
  1274. return 0;
  1275. }
  1276. u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
  1277. struct outbound_queue_table *circularQ, u8 bc)
  1278. {
  1279. u32 producer_index;
  1280. struct mpi_msg_hdr *msgHeader;
  1281. struct mpi_msg_hdr *pOutBoundMsgHeader;
  1282. msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
  1283. pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
  1284. circularQ->consumer_idx * pm8001_ha->iomb_size);
  1285. if (pOutBoundMsgHeader != msgHeader) {
  1286. PM8001_FAIL_DBG(pm8001_ha,
  1287. pm8001_printk("consumer_idx = %d msgHeader = %p\n",
  1288. circularQ->consumer_idx, msgHeader));
  1289. /* Update the producer index from SPC */
  1290. producer_index = pm8001_read_32(circularQ->pi_virt);
  1291. circularQ->producer_index = cpu_to_le32(producer_index);
  1292. PM8001_FAIL_DBG(pm8001_ha,
  1293. pm8001_printk("consumer_idx = %d producer_index = %d"
  1294. "msgHeader = %p\n", circularQ->consumer_idx,
  1295. circularQ->producer_index, msgHeader));
  1296. return 0;
  1297. }
  1298. /* free the circular queue buffer elements associated with the message*/
  1299. circularQ->consumer_idx = (circularQ->consumer_idx + bc)
  1300. % PM8001_MPI_QUEUE;
  1301. /* update the CI of outbound queue */
  1302. pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
  1303. circularQ->consumer_idx);
  1304. /* Update the producer index from SPC*/
  1305. producer_index = pm8001_read_32(circularQ->pi_virt);
  1306. circularQ->producer_index = cpu_to_le32(producer_index);
  1307. PM8001_IO_DBG(pm8001_ha,
  1308. pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx,
  1309. circularQ->producer_index));
  1310. return 0;
  1311. }
  1312. /**
  1313. * pm8001_mpi_msg_consume- get the MPI message from outbound queue
  1314. * message table.
  1315. * @pm8001_ha: our hba card information
  1316. * @circularQ: the outbound queue table.
  1317. * @messagePtr1: the message contents of this outbound message.
  1318. * @pBC: the message size.
  1319. */
  1320. u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
  1321. struct outbound_queue_table *circularQ,
  1322. void **messagePtr1, u8 *pBC)
  1323. {
  1324. struct mpi_msg_hdr *msgHeader;
  1325. __le32 msgHeader_tmp;
  1326. u32 header_tmp;
  1327. do {
  1328. /* If there are not-yet-delivered messages ... */
  1329. if (le32_to_cpu(circularQ->producer_index)
  1330. != circularQ->consumer_idx) {
  1331. /*Get the pointer to the circular queue buffer element*/
  1332. msgHeader = (struct mpi_msg_hdr *)
  1333. (circularQ->base_virt +
  1334. circularQ->consumer_idx * pm8001_ha->iomb_size);
  1335. /* read header */
  1336. header_tmp = pm8001_read_32(msgHeader);
  1337. msgHeader_tmp = cpu_to_le32(header_tmp);
  1338. if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) {
  1339. if (OPC_OUB_SKIP_ENTRY !=
  1340. (le32_to_cpu(msgHeader_tmp) & 0xfff)) {
  1341. *messagePtr1 =
  1342. ((u8 *)msgHeader) +
  1343. sizeof(struct mpi_msg_hdr);
  1344. *pBC = (u8)((le32_to_cpu(msgHeader_tmp)
  1345. >> 24) & 0x1f);
  1346. PM8001_IO_DBG(pm8001_ha,
  1347. pm8001_printk(": CI=%d PI=%d "
  1348. "msgHeader=%x\n",
  1349. circularQ->consumer_idx,
  1350. circularQ->producer_index,
  1351. msgHeader_tmp));
  1352. return MPI_IO_STATUS_SUCCESS;
  1353. } else {
  1354. circularQ->consumer_idx =
  1355. (circularQ->consumer_idx +
  1356. ((le32_to_cpu(msgHeader_tmp)
  1357. >> 24) & 0x1f))
  1358. % PM8001_MPI_QUEUE;
  1359. msgHeader_tmp = 0;
  1360. pm8001_write_32(msgHeader, 0, 0);
  1361. /* update the CI of outbound queue */
  1362. pm8001_cw32(pm8001_ha,
  1363. circularQ->ci_pci_bar,
  1364. circularQ->ci_offset,
  1365. circularQ->consumer_idx);
  1366. }
  1367. } else {
  1368. circularQ->consumer_idx =
  1369. (circularQ->consumer_idx +
  1370. ((le32_to_cpu(msgHeader_tmp) >> 24) &
  1371. 0x1f)) % PM8001_MPI_QUEUE;
  1372. msgHeader_tmp = 0;
  1373. pm8001_write_32(msgHeader, 0, 0);
  1374. /* update the CI of outbound queue */
  1375. pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
  1376. circularQ->ci_offset,
  1377. circularQ->consumer_idx);
  1378. return MPI_IO_STATUS_FAIL;
  1379. }
  1380. } else {
  1381. u32 producer_index;
  1382. void *pi_virt = circularQ->pi_virt;
  1383. /* Update the producer index from SPC */
  1384. producer_index = pm8001_read_32(pi_virt);
  1385. circularQ->producer_index = cpu_to_le32(producer_index);
  1386. }
  1387. } while (le32_to_cpu(circularQ->producer_index) !=
  1388. circularQ->consumer_idx);
  1389. /* while we don't have any more not-yet-delivered message */
  1390. /* report empty */
  1391. return MPI_IO_STATUS_BUSY;
  1392. }
  1393. void pm8001_work_fn(struct work_struct *work)
  1394. {
  1395. struct pm8001_work *pw = container_of(work, struct pm8001_work, work);
  1396. struct pm8001_device *pm8001_dev;
  1397. struct domain_device *dev;
  1398. /*
  1399. * So far, all users of this stash an associated structure here.
  1400. * If we get here, and this pointer is null, then the action
  1401. * was cancelled. This nullification happens when the device
  1402. * goes away.
  1403. */
  1404. pm8001_dev = pw->data; /* Most stash device structure */
  1405. if ((pm8001_dev == NULL)
  1406. || ((pw->handler != IO_XFER_ERROR_BREAK)
  1407. && (pm8001_dev->dev_type == SAS_PHY_UNUSED))) {
  1408. kfree(pw);
  1409. return;
  1410. }
  1411. switch (pw->handler) {
  1412. case IO_XFER_ERROR_BREAK:
  1413. { /* This one stashes the sas_task instead */
  1414. struct sas_task *t = (struct sas_task *)pm8001_dev;
  1415. u32 tag;
  1416. struct pm8001_ccb_info *ccb;
  1417. struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
  1418. unsigned long flags, flags1;
  1419. struct task_status_struct *ts;
  1420. int i;
  1421. if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC)
  1422. break; /* Task still on lu */
  1423. spin_lock_irqsave(&pm8001_ha->lock, flags);
  1424. spin_lock_irqsave(&t->task_state_lock, flags1);
  1425. if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
  1426. spin_unlock_irqrestore(&t->task_state_lock, flags1);
  1427. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  1428. break; /* Task got completed by another */
  1429. }
  1430. spin_unlock_irqrestore(&t->task_state_lock, flags1);
  1431. /* Search for a possible ccb that matches the task */
  1432. for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
  1433. ccb = &pm8001_ha->ccb_info[i];
  1434. tag = ccb->ccb_tag;
  1435. if ((tag != 0xFFFFFFFF) && (ccb->task == t))
  1436. break;
  1437. }
  1438. if (!ccb) {
  1439. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  1440. break; /* Task got freed by another */
  1441. }
  1442. ts = &t->task_status;
  1443. ts->resp = SAS_TASK_COMPLETE;
  1444. /* Force the midlayer to retry */
  1445. ts->stat = SAS_QUEUE_FULL;
  1446. pm8001_dev = ccb->device;
  1447. if (pm8001_dev)
  1448. pm8001_dev->running_req--;
  1449. spin_lock_irqsave(&t->task_state_lock, flags1);
  1450. t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
  1451. t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
  1452. t->task_state_flags |= SAS_TASK_STATE_DONE;
  1453. if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
  1454. spin_unlock_irqrestore(&t->task_state_lock, flags1);
  1455. PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p"
  1456. " done with event 0x%x resp 0x%x stat 0x%x but"
  1457. " aborted by upper layer!\n",
  1458. t, pw->handler, ts->resp, ts->stat));
  1459. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  1460. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  1461. } else {
  1462. spin_unlock_irqrestore(&t->task_state_lock, flags1);
  1463. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  1464. mb();/* in order to force CPU ordering */
  1465. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  1466. t->task_done(t);
  1467. }
  1468. } break;
  1469. case IO_XFER_OPEN_RETRY_TIMEOUT:
  1470. { /* This one stashes the sas_task instead */
  1471. struct sas_task *t = (struct sas_task *)pm8001_dev;
  1472. u32 tag;
  1473. struct pm8001_ccb_info *ccb;
  1474. struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
  1475. unsigned long flags, flags1;
  1476. int i, ret = 0;
  1477. PM8001_IO_DBG(pm8001_ha,
  1478. pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
  1479. ret = pm8001_query_task(t);
  1480. PM8001_IO_DBG(pm8001_ha,
  1481. switch (ret) {
  1482. case TMF_RESP_FUNC_SUCC:
  1483. pm8001_printk("...Task on lu\n");
  1484. break;
  1485. case TMF_RESP_FUNC_COMPLETE:
  1486. pm8001_printk("...Task NOT on lu\n");
  1487. break;
  1488. default:
  1489. pm8001_printk("...query task failed!!!\n");
  1490. break;
  1491. });
  1492. spin_lock_irqsave(&pm8001_ha->lock, flags);
  1493. spin_lock_irqsave(&t->task_state_lock, flags1);
  1494. if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
  1495. spin_unlock_irqrestore(&t->task_state_lock, flags1);
  1496. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  1497. if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
  1498. (void)pm8001_abort_task(t);
  1499. break; /* Task got completed by another */
  1500. }
  1501. spin_unlock_irqrestore(&t->task_state_lock, flags1);
  1502. /* Search for a possible ccb that matches the task */
  1503. for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
  1504. ccb = &pm8001_ha->ccb_info[i];
  1505. tag = ccb->ccb_tag;
  1506. if ((tag != 0xFFFFFFFF) && (ccb->task == t))
  1507. break;
  1508. }
  1509. if (!ccb) {
  1510. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  1511. if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
  1512. (void)pm8001_abort_task(t);
  1513. break; /* Task got freed by another */
  1514. }
  1515. pm8001_dev = ccb->device;
  1516. dev = pm8001_dev->sas_device;
  1517. switch (ret) {
  1518. case TMF_RESP_FUNC_SUCC: /* task on lu */
  1519. ccb->open_retry = 1; /* Snub completion */
  1520. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  1521. ret = pm8001_abort_task(t);
  1522. ccb->open_retry = 0;
  1523. switch (ret) {
  1524. case TMF_RESP_FUNC_SUCC:
  1525. case TMF_RESP_FUNC_COMPLETE:
  1526. break;
  1527. default: /* device misbehavior */
  1528. ret = TMF_RESP_FUNC_FAILED;
  1529. PM8001_IO_DBG(pm8001_ha,
  1530. pm8001_printk("...Reset phy\n"));
  1531. pm8001_I_T_nexus_reset(dev);
  1532. break;
  1533. }
  1534. break;
  1535. case TMF_RESP_FUNC_COMPLETE: /* task not on lu */
  1536. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  1537. /* Do we need to abort the task locally? */
  1538. break;
  1539. default: /* device misbehavior */
  1540. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  1541. ret = TMF_RESP_FUNC_FAILED;
  1542. PM8001_IO_DBG(pm8001_ha,
  1543. pm8001_printk("...Reset phy\n"));
  1544. pm8001_I_T_nexus_reset(dev);
  1545. }
  1546. if (ret == TMF_RESP_FUNC_FAILED)
  1547. t = NULL;
  1548. pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev);
  1549. PM8001_IO_DBG(pm8001_ha, pm8001_printk("...Complete\n"));
  1550. } break;
  1551. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
  1552. dev = pm8001_dev->sas_device;
  1553. pm8001_I_T_nexus_event_handler(dev);
  1554. break;
  1555. case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
  1556. dev = pm8001_dev->sas_device;
  1557. pm8001_I_T_nexus_reset(dev);
  1558. break;
  1559. case IO_DS_IN_ERROR:
  1560. dev = pm8001_dev->sas_device;
  1561. pm8001_I_T_nexus_reset(dev);
  1562. break;
  1563. case IO_DS_NON_OPERATIONAL:
  1564. dev = pm8001_dev->sas_device;
  1565. pm8001_I_T_nexus_reset(dev);
  1566. break;
  1567. }
  1568. kfree(pw);
  1569. }
  1570. int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
  1571. int handler)
  1572. {
  1573. struct pm8001_work *pw;
  1574. int ret = 0;
  1575. pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC);
  1576. if (pw) {
  1577. pw->pm8001_ha = pm8001_ha;
  1578. pw->data = data;
  1579. pw->handler = handler;
  1580. INIT_WORK(&pw->work, pm8001_work_fn);
  1581. queue_work(pm8001_wq, &pw->work);
  1582. } else
  1583. ret = -ENOMEM;
  1584. return ret;
  1585. }
  1586. static void pm8001_send_abort_all(struct pm8001_hba_info *pm8001_ha,
  1587. struct pm8001_device *pm8001_ha_dev)
  1588. {
  1589. int res;
  1590. u32 ccb_tag;
  1591. struct pm8001_ccb_info *ccb;
  1592. struct sas_task *task = NULL;
  1593. struct task_abort_req task_abort;
  1594. struct inbound_queue_table *circularQ;
  1595. u32 opc = OPC_INB_SATA_ABORT;
  1596. int ret;
  1597. if (!pm8001_ha_dev) {
  1598. PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
  1599. return;
  1600. }
  1601. task = sas_alloc_slow_task(GFP_ATOMIC);
  1602. if (!task) {
  1603. PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
  1604. "allocate task\n"));
  1605. return;
  1606. }
  1607. task->task_done = pm8001_task_done;
  1608. res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
  1609. if (res)
  1610. return;
  1611. ccb = &pm8001_ha->ccb_info[ccb_tag];
  1612. ccb->device = pm8001_ha_dev;
  1613. ccb->ccb_tag = ccb_tag;
  1614. ccb->task = task;
  1615. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  1616. memset(&task_abort, 0, sizeof(task_abort));
  1617. task_abort.abort_all = cpu_to_le32(1);
  1618. task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
  1619. task_abort.tag = cpu_to_le32(ccb_tag);
  1620. ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
  1621. }
  1622. static void pm8001_send_read_log(struct pm8001_hba_info *pm8001_ha,
  1623. struct pm8001_device *pm8001_ha_dev)
  1624. {
  1625. struct sata_start_req sata_cmd;
  1626. int res;
  1627. u32 ccb_tag;
  1628. struct pm8001_ccb_info *ccb;
  1629. struct sas_task *task = NULL;
  1630. struct host_to_dev_fis fis;
  1631. struct domain_device *dev;
  1632. struct inbound_queue_table *circularQ;
  1633. u32 opc = OPC_INB_SATA_HOST_OPSTART;
  1634. task = sas_alloc_slow_task(GFP_ATOMIC);
  1635. if (!task) {
  1636. PM8001_FAIL_DBG(pm8001_ha,
  1637. pm8001_printk("cannot allocate task !!!\n"));
  1638. return;
  1639. }
  1640. task->task_done = pm8001_task_done;
  1641. res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
  1642. if (res) {
  1643. PM8001_FAIL_DBG(pm8001_ha,
  1644. pm8001_printk("cannot allocate tag !!!\n"));
  1645. return;
  1646. }
  1647. /* allocate domain device by ourselves as libsas
  1648. * is not going to provide any
  1649. */
  1650. dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
  1651. if (!dev) {
  1652. PM8001_FAIL_DBG(pm8001_ha,
  1653. pm8001_printk("Domain device cannot be allocated\n"));
  1654. sas_free_task(task);
  1655. return;
  1656. } else {
  1657. task->dev = dev;
  1658. task->dev->lldd_dev = pm8001_ha_dev;
  1659. }
  1660. ccb = &pm8001_ha->ccb_info[ccb_tag];
  1661. ccb->device = pm8001_ha_dev;
  1662. ccb->ccb_tag = ccb_tag;
  1663. ccb->task = task;
  1664. pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
  1665. pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
  1666. memset(&sata_cmd, 0, sizeof(sata_cmd));
  1667. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  1668. /* construct read log FIS */
  1669. memset(&fis, 0, sizeof(struct host_to_dev_fis));
  1670. fis.fis_type = 0x27;
  1671. fis.flags = 0x80;
  1672. fis.command = ATA_CMD_READ_LOG_EXT;
  1673. fis.lbal = 0x10;
  1674. fis.sector_count = 0x1;
  1675. sata_cmd.tag = cpu_to_le32(ccb_tag);
  1676. sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
  1677. sata_cmd.ncqtag_atap_dir_m |= ((0x1 << 7) | (0x5 << 9));
  1678. memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
  1679. res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
  1680. }
  1681. /**
  1682. * mpi_ssp_completion- process the event that FW response to the SSP request.
  1683. * @pm8001_ha: our hba card information
  1684. * @piomb: the message contents of this outbound message.
  1685. *
  1686. * When FW has completed a ssp request for example a IO request, after it has
  1687. * filled the SG data with the data, it will trigger this event represent
  1688. * that he has finished the job,please check the coresponding buffer.
  1689. * So we will tell the caller who maybe waiting the result to tell upper layer
  1690. * that the task has been finished.
  1691. */
  1692. static void
  1693. mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
  1694. {
  1695. struct sas_task *t;
  1696. struct pm8001_ccb_info *ccb;
  1697. unsigned long flags;
  1698. u32 status;
  1699. u32 param;
  1700. u32 tag;
  1701. struct ssp_completion_resp *psspPayload;
  1702. struct task_status_struct *ts;
  1703. struct ssp_response_iu *iu;
  1704. struct pm8001_device *pm8001_dev;
  1705. psspPayload = (struct ssp_completion_resp *)(piomb + 4);
  1706. status = le32_to_cpu(psspPayload->status);
  1707. tag = le32_to_cpu(psspPayload->tag);
  1708. ccb = &pm8001_ha->ccb_info[tag];
  1709. if ((status == IO_ABORTED) && ccb->open_retry) {
  1710. /* Being completed by another */
  1711. ccb->open_retry = 0;
  1712. return;
  1713. }
  1714. pm8001_dev = ccb->device;
  1715. param = le32_to_cpu(psspPayload->param);
  1716. t = ccb->task;
  1717. if (status && status != IO_UNDERFLOW)
  1718. PM8001_FAIL_DBG(pm8001_ha,
  1719. pm8001_printk("sas IO status 0x%x\n", status));
  1720. if (unlikely(!t || !t->lldd_task || !t->dev))
  1721. return;
  1722. ts = &t->task_status;
  1723. /* Print sas address of IO failed device */
  1724. if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
  1725. (status != IO_UNDERFLOW))
  1726. PM8001_FAIL_DBG(pm8001_ha,
  1727. pm8001_printk("SAS Address of IO Failure Drive:"
  1728. "%016llx", SAS_ADDR(t->dev->sas_addr)));
  1729. switch (status) {
  1730. case IO_SUCCESS:
  1731. PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS"
  1732. ",param = %d\n", param));
  1733. if (param == 0) {
  1734. ts->resp = SAS_TASK_COMPLETE;
  1735. ts->stat = SAM_STAT_GOOD;
  1736. } else {
  1737. ts->resp = SAS_TASK_COMPLETE;
  1738. ts->stat = SAS_PROTO_RESPONSE;
  1739. ts->residual = param;
  1740. iu = &psspPayload->ssp_resp_iu;
  1741. sas_ssp_task_response(pm8001_ha->dev, t, iu);
  1742. }
  1743. if (pm8001_dev)
  1744. pm8001_dev->running_req--;
  1745. break;
  1746. case IO_ABORTED:
  1747. PM8001_IO_DBG(pm8001_ha,
  1748. pm8001_printk("IO_ABORTED IOMB Tag\n"));
  1749. ts->resp = SAS_TASK_COMPLETE;
  1750. ts->stat = SAS_ABORTED_TASK;
  1751. break;
  1752. case IO_UNDERFLOW:
  1753. /* SSP Completion with error */
  1754. PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW"
  1755. ",param = %d\n", param));
  1756. ts->resp = SAS_TASK_COMPLETE;
  1757. ts->stat = SAS_DATA_UNDERRUN;
  1758. ts->residual = param;
  1759. if (pm8001_dev)
  1760. pm8001_dev->running_req--;
  1761. break;
  1762. case IO_NO_DEVICE:
  1763. PM8001_IO_DBG(pm8001_ha,
  1764. pm8001_printk("IO_NO_DEVICE\n"));
  1765. ts->resp = SAS_TASK_UNDELIVERED;
  1766. ts->stat = SAS_PHY_DOWN;
  1767. break;
  1768. case IO_XFER_ERROR_BREAK:
  1769. PM8001_IO_DBG(pm8001_ha,
  1770. pm8001_printk("IO_XFER_ERROR_BREAK\n"));
  1771. ts->resp = SAS_TASK_COMPLETE;
  1772. ts->stat = SAS_OPEN_REJECT;
  1773. /* Force the midlayer to retry */
  1774. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1775. break;
  1776. case IO_XFER_ERROR_PHY_NOT_READY:
  1777. PM8001_IO_DBG(pm8001_ha,
  1778. pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
  1779. ts->resp = SAS_TASK_COMPLETE;
  1780. ts->stat = SAS_OPEN_REJECT;
  1781. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1782. break;
  1783. case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
  1784. PM8001_IO_DBG(pm8001_ha,
  1785. pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
  1786. ts->resp = SAS_TASK_COMPLETE;
  1787. ts->stat = SAS_OPEN_REJECT;
  1788. ts->open_rej_reason = SAS_OREJ_EPROTO;
  1789. break;
  1790. case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
  1791. PM8001_IO_DBG(pm8001_ha,
  1792. pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
  1793. ts->resp = SAS_TASK_COMPLETE;
  1794. ts->stat = SAS_OPEN_REJECT;
  1795. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  1796. break;
  1797. case IO_OPEN_CNX_ERROR_BREAK:
  1798. PM8001_IO_DBG(pm8001_ha,
  1799. pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
  1800. ts->resp = SAS_TASK_COMPLETE;
  1801. ts->stat = SAS_OPEN_REJECT;
  1802. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1803. break;
  1804. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
  1805. PM8001_IO_DBG(pm8001_ha,
  1806. pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
  1807. ts->resp = SAS_TASK_COMPLETE;
  1808. ts->stat = SAS_OPEN_REJECT;
  1809. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  1810. if (!t->uldd_task)
  1811. pm8001_handle_event(pm8001_ha,
  1812. pm8001_dev,
  1813. IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
  1814. break;
  1815. case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
  1816. PM8001_IO_DBG(pm8001_ha,
  1817. pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
  1818. ts->resp = SAS_TASK_COMPLETE;
  1819. ts->stat = SAS_OPEN_REJECT;
  1820. ts->open_rej_reason = SAS_OREJ_BAD_DEST;
  1821. break;
  1822. case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
  1823. PM8001_IO_DBG(pm8001_ha,
  1824. pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
  1825. "NOT_SUPPORTED\n"));
  1826. ts->resp = SAS_TASK_COMPLETE;
  1827. ts->stat = SAS_OPEN_REJECT;
  1828. ts->open_rej_reason = SAS_OREJ_CONN_RATE;
  1829. break;
  1830. case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
  1831. PM8001_IO_DBG(pm8001_ha,
  1832. pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
  1833. ts->resp = SAS_TASK_UNDELIVERED;
  1834. ts->stat = SAS_OPEN_REJECT;
  1835. ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
  1836. break;
  1837. case IO_XFER_ERROR_NAK_RECEIVED:
  1838. PM8001_IO_DBG(pm8001_ha,
  1839. pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
  1840. ts->resp = SAS_TASK_COMPLETE;
  1841. ts->stat = SAS_OPEN_REJECT;
  1842. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1843. break;
  1844. case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
  1845. PM8001_IO_DBG(pm8001_ha,
  1846. pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
  1847. ts->resp = SAS_TASK_COMPLETE;
  1848. ts->stat = SAS_NAK_R_ERR;
  1849. break;
  1850. case IO_XFER_ERROR_DMA:
  1851. PM8001_IO_DBG(pm8001_ha,
  1852. pm8001_printk("IO_XFER_ERROR_DMA\n"));
  1853. ts->resp = SAS_TASK_COMPLETE;
  1854. ts->stat = SAS_OPEN_REJECT;
  1855. break;
  1856. case IO_XFER_OPEN_RETRY_TIMEOUT:
  1857. PM8001_IO_DBG(pm8001_ha,
  1858. pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
  1859. ts->resp = SAS_TASK_COMPLETE;
  1860. ts->stat = SAS_OPEN_REJECT;
  1861. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1862. break;
  1863. case IO_XFER_ERROR_OFFSET_MISMATCH:
  1864. PM8001_IO_DBG(pm8001_ha,
  1865. pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
  1866. ts->resp = SAS_TASK_COMPLETE;
  1867. ts->stat = SAS_OPEN_REJECT;
  1868. break;
  1869. case IO_PORT_IN_RESET:
  1870. PM8001_IO_DBG(pm8001_ha,
  1871. pm8001_printk("IO_PORT_IN_RESET\n"));
  1872. ts->resp = SAS_TASK_COMPLETE;
  1873. ts->stat = SAS_OPEN_REJECT;
  1874. break;
  1875. case IO_DS_NON_OPERATIONAL:
  1876. PM8001_IO_DBG(pm8001_ha,
  1877. pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
  1878. ts->resp = SAS_TASK_COMPLETE;
  1879. ts->stat = SAS_OPEN_REJECT;
  1880. if (!t->uldd_task)
  1881. pm8001_handle_event(pm8001_ha,
  1882. pm8001_dev,
  1883. IO_DS_NON_OPERATIONAL);
  1884. break;
  1885. case IO_DS_IN_RECOVERY:
  1886. PM8001_IO_DBG(pm8001_ha,
  1887. pm8001_printk("IO_DS_IN_RECOVERY\n"));
  1888. ts->resp = SAS_TASK_COMPLETE;
  1889. ts->stat = SAS_OPEN_REJECT;
  1890. break;
  1891. case IO_TM_TAG_NOT_FOUND:
  1892. PM8001_IO_DBG(pm8001_ha,
  1893. pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
  1894. ts->resp = SAS_TASK_COMPLETE;
  1895. ts->stat = SAS_OPEN_REJECT;
  1896. break;
  1897. case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
  1898. PM8001_IO_DBG(pm8001_ha,
  1899. pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
  1900. ts->resp = SAS_TASK_COMPLETE;
  1901. ts->stat = SAS_OPEN_REJECT;
  1902. break;
  1903. case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
  1904. PM8001_IO_DBG(pm8001_ha,
  1905. pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
  1906. ts->resp = SAS_TASK_COMPLETE;
  1907. ts->stat = SAS_OPEN_REJECT;
  1908. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1909. break;
  1910. default:
  1911. PM8001_IO_DBG(pm8001_ha,
  1912. pm8001_printk("Unknown status 0x%x\n", status));
  1913. /* not allowed case. Therefore, return failed status */
  1914. ts->resp = SAS_TASK_COMPLETE;
  1915. ts->stat = SAS_OPEN_REJECT;
  1916. break;
  1917. }
  1918. PM8001_IO_DBG(pm8001_ha,
  1919. pm8001_printk("scsi_status = %x\n ",
  1920. psspPayload->ssp_resp_iu.status));
  1921. spin_lock_irqsave(&t->task_state_lock, flags);
  1922. t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
  1923. t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
  1924. t->task_state_flags |= SAS_TASK_STATE_DONE;
  1925. if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
  1926. spin_unlock_irqrestore(&t->task_state_lock, flags);
  1927. PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
  1928. " io_status 0x%x resp 0x%x "
  1929. "stat 0x%x but aborted by upper layer!\n",
  1930. t, status, ts->resp, ts->stat));
  1931. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  1932. } else {
  1933. spin_unlock_irqrestore(&t->task_state_lock, flags);
  1934. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  1935. mb();/* in order to force CPU ordering */
  1936. t->task_done(t);
  1937. }
  1938. }
  1939. /*See the comments for mpi_ssp_completion */
  1940. static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
  1941. {
  1942. struct sas_task *t;
  1943. unsigned long flags;
  1944. struct task_status_struct *ts;
  1945. struct pm8001_ccb_info *ccb;
  1946. struct pm8001_device *pm8001_dev;
  1947. struct ssp_event_resp *psspPayload =
  1948. (struct ssp_event_resp *)(piomb + 4);
  1949. u32 event = le32_to_cpu(psspPayload->event);
  1950. u32 tag = le32_to_cpu(psspPayload->tag);
  1951. u32 port_id = le32_to_cpu(psspPayload->port_id);
  1952. u32 dev_id = le32_to_cpu(psspPayload->device_id);
  1953. ccb = &pm8001_ha->ccb_info[tag];
  1954. t = ccb->task;
  1955. pm8001_dev = ccb->device;
  1956. if (event)
  1957. PM8001_FAIL_DBG(pm8001_ha,
  1958. pm8001_printk("sas IO status 0x%x\n", event));
  1959. if (unlikely(!t || !t->lldd_task || !t->dev))
  1960. return;
  1961. ts = &t->task_status;
  1962. PM8001_IO_DBG(pm8001_ha,
  1963. pm8001_printk("port_id = %x,device_id = %x\n",
  1964. port_id, dev_id));
  1965. switch (event) {
  1966. case IO_OVERFLOW:
  1967. PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
  1968. ts->resp = SAS_TASK_COMPLETE;
  1969. ts->stat = SAS_DATA_OVERRUN;
  1970. ts->residual = 0;
  1971. if (pm8001_dev)
  1972. pm8001_dev->running_req--;
  1973. break;
  1974. case IO_XFER_ERROR_BREAK:
  1975. PM8001_IO_DBG(pm8001_ha,
  1976. pm8001_printk("IO_XFER_ERROR_BREAK\n"));
  1977. pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
  1978. return;
  1979. case IO_XFER_ERROR_PHY_NOT_READY:
  1980. PM8001_IO_DBG(pm8001_ha,
  1981. pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
  1982. ts->resp = SAS_TASK_COMPLETE;
  1983. ts->stat = SAS_OPEN_REJECT;
  1984. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1985. break;
  1986. case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
  1987. PM8001_IO_DBG(pm8001_ha,
  1988. pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
  1989. "_SUPPORTED\n"));
  1990. ts->resp = SAS_TASK_COMPLETE;
  1991. ts->stat = SAS_OPEN_REJECT;
  1992. ts->open_rej_reason = SAS_OREJ_EPROTO;
  1993. break;
  1994. case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
  1995. PM8001_IO_DBG(pm8001_ha,
  1996. pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
  1997. ts->resp = SAS_TASK_COMPLETE;
  1998. ts->stat = SAS_OPEN_REJECT;
  1999. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  2000. break;
  2001. case IO_OPEN_CNX_ERROR_BREAK:
  2002. PM8001_IO_DBG(pm8001_ha,
  2003. pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
  2004. ts->resp = SAS_TASK_COMPLETE;
  2005. ts->stat = SAS_OPEN_REJECT;
  2006. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2007. break;
  2008. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
  2009. PM8001_IO_DBG(pm8001_ha,
  2010. pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
  2011. ts->resp = SAS_TASK_COMPLETE;
  2012. ts->stat = SAS_OPEN_REJECT;
  2013. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  2014. if (!t->uldd_task)
  2015. pm8001_handle_event(pm8001_ha,
  2016. pm8001_dev,
  2017. IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
  2018. break;
  2019. case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
  2020. PM8001_IO_DBG(pm8001_ha,
  2021. pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
  2022. ts->resp = SAS_TASK_COMPLETE;
  2023. ts->stat = SAS_OPEN_REJECT;
  2024. ts->open_rej_reason = SAS_OREJ_BAD_DEST;
  2025. break;
  2026. case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
  2027. PM8001_IO_DBG(pm8001_ha,
  2028. pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
  2029. "NOT_SUPPORTED\n"));
  2030. ts->resp = SAS_TASK_COMPLETE;
  2031. ts->stat = SAS_OPEN_REJECT;
  2032. ts->open_rej_reason = SAS_OREJ_CONN_RATE;
  2033. break;
  2034. case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
  2035. PM8001_IO_DBG(pm8001_ha,
  2036. pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
  2037. ts->resp = SAS_TASK_COMPLETE;
  2038. ts->stat = SAS_OPEN_REJECT;
  2039. ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
  2040. break;
  2041. case IO_XFER_ERROR_NAK_RECEIVED:
  2042. PM8001_IO_DBG(pm8001_ha,
  2043. pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
  2044. ts->resp = SAS_TASK_COMPLETE;
  2045. ts->stat = SAS_OPEN_REJECT;
  2046. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2047. break;
  2048. case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
  2049. PM8001_IO_DBG(pm8001_ha,
  2050. pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
  2051. ts->resp = SAS_TASK_COMPLETE;
  2052. ts->stat = SAS_NAK_R_ERR;
  2053. break;
  2054. case IO_XFER_OPEN_RETRY_TIMEOUT:
  2055. PM8001_IO_DBG(pm8001_ha,
  2056. pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
  2057. pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
  2058. return;
  2059. case IO_XFER_ERROR_UNEXPECTED_PHASE:
  2060. PM8001_IO_DBG(pm8001_ha,
  2061. pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
  2062. ts->resp = SAS_TASK_COMPLETE;
  2063. ts->stat = SAS_DATA_OVERRUN;
  2064. break;
  2065. case IO_XFER_ERROR_XFER_RDY_OVERRUN:
  2066. PM8001_IO_DBG(pm8001_ha,
  2067. pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
  2068. ts->resp = SAS_TASK_COMPLETE;
  2069. ts->stat = SAS_DATA_OVERRUN;
  2070. break;
  2071. case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
  2072. PM8001_IO_DBG(pm8001_ha,
  2073. pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
  2074. ts->resp = SAS_TASK_COMPLETE;
  2075. ts->stat = SAS_DATA_OVERRUN;
  2076. break;
  2077. case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
  2078. PM8001_IO_DBG(pm8001_ha,
  2079. pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
  2080. ts->resp = SAS_TASK_COMPLETE;
  2081. ts->stat = SAS_DATA_OVERRUN;
  2082. break;
  2083. case IO_XFER_ERROR_OFFSET_MISMATCH:
  2084. PM8001_IO_DBG(pm8001_ha,
  2085. pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
  2086. ts->resp = SAS_TASK_COMPLETE;
  2087. ts->stat = SAS_DATA_OVERRUN;
  2088. break;
  2089. case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
  2090. PM8001_IO_DBG(pm8001_ha,
  2091. pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
  2092. ts->resp = SAS_TASK_COMPLETE;
  2093. ts->stat = SAS_DATA_OVERRUN;
  2094. break;
  2095. case IO_XFER_CMD_FRAME_ISSUED:
  2096. PM8001_IO_DBG(pm8001_ha,
  2097. pm8001_printk(" IO_XFER_CMD_FRAME_ISSUED\n"));
  2098. return;
  2099. default:
  2100. PM8001_IO_DBG(pm8001_ha,
  2101. pm8001_printk("Unknown status 0x%x\n", event));
  2102. /* not allowed case. Therefore, return failed status */
  2103. ts->resp = SAS_TASK_COMPLETE;
  2104. ts->stat = SAS_DATA_OVERRUN;
  2105. break;
  2106. }
  2107. spin_lock_irqsave(&t->task_state_lock, flags);
  2108. t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
  2109. t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
  2110. t->task_state_flags |= SAS_TASK_STATE_DONE;
  2111. if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
  2112. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2113. PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
  2114. " event 0x%x resp 0x%x "
  2115. "stat 0x%x but aborted by upper layer!\n",
  2116. t, event, ts->resp, ts->stat));
  2117. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2118. } else {
  2119. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2120. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2121. mb();/* in order to force CPU ordering */
  2122. t->task_done(t);
  2123. }
  2124. }
  2125. /*See the comments for mpi_ssp_completion */
  2126. static void
  2127. mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
  2128. {
  2129. struct sas_task *t;
  2130. struct pm8001_ccb_info *ccb;
  2131. u32 param;
  2132. u32 status;
  2133. u32 tag;
  2134. int i, j;
  2135. u8 sata_addr_low[4];
  2136. u32 temp_sata_addr_low;
  2137. u8 sata_addr_hi[4];
  2138. u32 temp_sata_addr_hi;
  2139. struct sata_completion_resp *psataPayload;
  2140. struct task_status_struct *ts;
  2141. struct ata_task_resp *resp ;
  2142. u32 *sata_resp;
  2143. struct pm8001_device *pm8001_dev;
  2144. unsigned long flags;
  2145. psataPayload = (struct sata_completion_resp *)(piomb + 4);
  2146. status = le32_to_cpu(psataPayload->status);
  2147. tag = le32_to_cpu(psataPayload->tag);
  2148. if (!tag) {
  2149. PM8001_FAIL_DBG(pm8001_ha,
  2150. pm8001_printk("tag null\n"));
  2151. return;
  2152. }
  2153. ccb = &pm8001_ha->ccb_info[tag];
  2154. param = le32_to_cpu(psataPayload->param);
  2155. if (ccb) {
  2156. t = ccb->task;
  2157. pm8001_dev = ccb->device;
  2158. } else {
  2159. PM8001_FAIL_DBG(pm8001_ha,
  2160. pm8001_printk("ccb null\n"));
  2161. return;
  2162. }
  2163. if (t) {
  2164. if (t->dev && (t->dev->lldd_dev))
  2165. pm8001_dev = t->dev->lldd_dev;
  2166. } else {
  2167. PM8001_FAIL_DBG(pm8001_ha,
  2168. pm8001_printk("task null\n"));
  2169. return;
  2170. }
  2171. if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
  2172. && unlikely(!t || !t->lldd_task || !t->dev)) {
  2173. PM8001_FAIL_DBG(pm8001_ha,
  2174. pm8001_printk("task or dev null\n"));
  2175. return;
  2176. }
  2177. ts = &t->task_status;
  2178. if (!ts) {
  2179. PM8001_FAIL_DBG(pm8001_ha,
  2180. pm8001_printk("ts null\n"));
  2181. return;
  2182. }
  2183. /* Print sas address of IO failed device */
  2184. if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
  2185. (status != IO_UNDERFLOW)) {
  2186. if (!((t->dev->parent) &&
  2187. (DEV_IS_EXPANDER(t->dev->parent->dev_type)))) {
  2188. for (i = 0 , j = 4; j <= 7 && i <= 3; i++ , j++)
  2189. sata_addr_low[i] = pm8001_ha->sas_addr[j];
  2190. for (i = 0 , j = 0; j <= 3 && i <= 3; i++ , j++)
  2191. sata_addr_hi[i] = pm8001_ha->sas_addr[j];
  2192. memcpy(&temp_sata_addr_low, sata_addr_low,
  2193. sizeof(sata_addr_low));
  2194. memcpy(&temp_sata_addr_hi, sata_addr_hi,
  2195. sizeof(sata_addr_hi));
  2196. temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
  2197. |((temp_sata_addr_hi << 8) &
  2198. 0xff0000) |
  2199. ((temp_sata_addr_hi >> 8)
  2200. & 0xff00) |
  2201. ((temp_sata_addr_hi << 24) &
  2202. 0xff000000));
  2203. temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
  2204. & 0xff) |
  2205. ((temp_sata_addr_low << 8)
  2206. & 0xff0000) |
  2207. ((temp_sata_addr_low >> 8)
  2208. & 0xff00) |
  2209. ((temp_sata_addr_low << 24)
  2210. & 0xff000000)) +
  2211. pm8001_dev->attached_phy +
  2212. 0x10);
  2213. PM8001_FAIL_DBG(pm8001_ha,
  2214. pm8001_printk("SAS Address of IO Failure Drive:"
  2215. "%08x%08x", temp_sata_addr_hi,
  2216. temp_sata_addr_low));
  2217. } else {
  2218. PM8001_FAIL_DBG(pm8001_ha,
  2219. pm8001_printk("SAS Address of IO Failure Drive:"
  2220. "%016llx", SAS_ADDR(t->dev->sas_addr)));
  2221. }
  2222. }
  2223. switch (status) {
  2224. case IO_SUCCESS:
  2225. PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
  2226. if (param == 0) {
  2227. ts->resp = SAS_TASK_COMPLETE;
  2228. ts->stat = SAM_STAT_GOOD;
  2229. /* check if response is for SEND READ LOG */
  2230. if (pm8001_dev &&
  2231. (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
  2232. /* set new bit for abort_all */
  2233. pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
  2234. /* clear bit for read log */
  2235. pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
  2236. pm8001_send_abort_all(pm8001_ha, pm8001_dev);
  2237. /* Free the tag */
  2238. pm8001_tag_free(pm8001_ha, tag);
  2239. sas_free_task(t);
  2240. return;
  2241. }
  2242. } else {
  2243. u8 len;
  2244. ts->resp = SAS_TASK_COMPLETE;
  2245. ts->stat = SAS_PROTO_RESPONSE;
  2246. ts->residual = param;
  2247. PM8001_IO_DBG(pm8001_ha,
  2248. pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
  2249. param));
  2250. sata_resp = &psataPayload->sata_resp[0];
  2251. resp = (struct ata_task_resp *)ts->buf;
  2252. if (t->ata_task.dma_xfer == 0 &&
  2253. t->data_dir == PCI_DMA_FROMDEVICE) {
  2254. len = sizeof(struct pio_setup_fis);
  2255. PM8001_IO_DBG(pm8001_ha,
  2256. pm8001_printk("PIO read len = %d\n", len));
  2257. } else if (t->ata_task.use_ncq) {
  2258. len = sizeof(struct set_dev_bits_fis);
  2259. PM8001_IO_DBG(pm8001_ha,
  2260. pm8001_printk("FPDMA len = %d\n", len));
  2261. } else {
  2262. len = sizeof(struct dev_to_host_fis);
  2263. PM8001_IO_DBG(pm8001_ha,
  2264. pm8001_printk("other len = %d\n", len));
  2265. }
  2266. if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
  2267. resp->frame_len = len;
  2268. memcpy(&resp->ending_fis[0], sata_resp, len);
  2269. ts->buf_valid_size = sizeof(*resp);
  2270. } else
  2271. PM8001_IO_DBG(pm8001_ha,
  2272. pm8001_printk("response to large\n"));
  2273. }
  2274. if (pm8001_dev)
  2275. pm8001_dev->running_req--;
  2276. break;
  2277. case IO_ABORTED:
  2278. PM8001_IO_DBG(pm8001_ha,
  2279. pm8001_printk("IO_ABORTED IOMB Tag\n"));
  2280. ts->resp = SAS_TASK_COMPLETE;
  2281. ts->stat = SAS_ABORTED_TASK;
  2282. if (pm8001_dev)
  2283. pm8001_dev->running_req--;
  2284. break;
  2285. /* following cases are to do cases */
  2286. case IO_UNDERFLOW:
  2287. /* SATA Completion with error */
  2288. PM8001_IO_DBG(pm8001_ha,
  2289. pm8001_printk("IO_UNDERFLOW param = %d\n", param));
  2290. ts->resp = SAS_TASK_COMPLETE;
  2291. ts->stat = SAS_DATA_UNDERRUN;
  2292. ts->residual = param;
  2293. if (pm8001_dev)
  2294. pm8001_dev->running_req--;
  2295. break;
  2296. case IO_NO_DEVICE:
  2297. PM8001_IO_DBG(pm8001_ha,
  2298. pm8001_printk("IO_NO_DEVICE\n"));
  2299. ts->resp = SAS_TASK_UNDELIVERED;
  2300. ts->stat = SAS_PHY_DOWN;
  2301. break;
  2302. case IO_XFER_ERROR_BREAK:
  2303. PM8001_IO_DBG(pm8001_ha,
  2304. pm8001_printk("IO_XFER_ERROR_BREAK\n"));
  2305. ts->resp = SAS_TASK_COMPLETE;
  2306. ts->stat = SAS_INTERRUPTED;
  2307. break;
  2308. case IO_XFER_ERROR_PHY_NOT_READY:
  2309. PM8001_IO_DBG(pm8001_ha,
  2310. pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
  2311. ts->resp = SAS_TASK_COMPLETE;
  2312. ts->stat = SAS_OPEN_REJECT;
  2313. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2314. break;
  2315. case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
  2316. PM8001_IO_DBG(pm8001_ha,
  2317. pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
  2318. "_SUPPORTED\n"));
  2319. ts->resp = SAS_TASK_COMPLETE;
  2320. ts->stat = SAS_OPEN_REJECT;
  2321. ts->open_rej_reason = SAS_OREJ_EPROTO;
  2322. break;
  2323. case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
  2324. PM8001_IO_DBG(pm8001_ha,
  2325. pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
  2326. ts->resp = SAS_TASK_COMPLETE;
  2327. ts->stat = SAS_OPEN_REJECT;
  2328. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  2329. break;
  2330. case IO_OPEN_CNX_ERROR_BREAK:
  2331. PM8001_IO_DBG(pm8001_ha,
  2332. pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
  2333. ts->resp = SAS_TASK_COMPLETE;
  2334. ts->stat = SAS_OPEN_REJECT;
  2335. ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
  2336. break;
  2337. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
  2338. PM8001_IO_DBG(pm8001_ha,
  2339. pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
  2340. ts->resp = SAS_TASK_COMPLETE;
  2341. ts->stat = SAS_DEV_NO_RESPONSE;
  2342. if (!t->uldd_task) {
  2343. pm8001_handle_event(pm8001_ha,
  2344. pm8001_dev,
  2345. IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
  2346. ts->resp = SAS_TASK_UNDELIVERED;
  2347. ts->stat = SAS_QUEUE_FULL;
  2348. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2349. mb();/*in order to force CPU ordering*/
  2350. spin_unlock_irq(&pm8001_ha->lock);
  2351. t->task_done(t);
  2352. spin_lock_irq(&pm8001_ha->lock);
  2353. return;
  2354. }
  2355. break;
  2356. case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
  2357. PM8001_IO_DBG(pm8001_ha,
  2358. pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
  2359. ts->resp = SAS_TASK_UNDELIVERED;
  2360. ts->stat = SAS_OPEN_REJECT;
  2361. ts->open_rej_reason = SAS_OREJ_BAD_DEST;
  2362. if (!t->uldd_task) {
  2363. pm8001_handle_event(pm8001_ha,
  2364. pm8001_dev,
  2365. IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
  2366. ts->resp = SAS_TASK_UNDELIVERED;
  2367. ts->stat = SAS_QUEUE_FULL;
  2368. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2369. mb();/*ditto*/
  2370. spin_unlock_irq(&pm8001_ha->lock);
  2371. t->task_done(t);
  2372. spin_lock_irq(&pm8001_ha->lock);
  2373. return;
  2374. }
  2375. break;
  2376. case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
  2377. PM8001_IO_DBG(pm8001_ha,
  2378. pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
  2379. "NOT_SUPPORTED\n"));
  2380. ts->resp = SAS_TASK_COMPLETE;
  2381. ts->stat = SAS_OPEN_REJECT;
  2382. ts->open_rej_reason = SAS_OREJ_CONN_RATE;
  2383. break;
  2384. case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
  2385. PM8001_IO_DBG(pm8001_ha,
  2386. pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES"
  2387. "_BUSY\n"));
  2388. ts->resp = SAS_TASK_COMPLETE;
  2389. ts->stat = SAS_DEV_NO_RESPONSE;
  2390. if (!t->uldd_task) {
  2391. pm8001_handle_event(pm8001_ha,
  2392. pm8001_dev,
  2393. IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
  2394. ts->resp = SAS_TASK_UNDELIVERED;
  2395. ts->stat = SAS_QUEUE_FULL;
  2396. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2397. mb();/* ditto*/
  2398. spin_unlock_irq(&pm8001_ha->lock);
  2399. t->task_done(t);
  2400. spin_lock_irq(&pm8001_ha->lock);
  2401. return;
  2402. }
  2403. break;
  2404. case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
  2405. PM8001_IO_DBG(pm8001_ha,
  2406. pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
  2407. ts->resp = SAS_TASK_COMPLETE;
  2408. ts->stat = SAS_OPEN_REJECT;
  2409. ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
  2410. break;
  2411. case IO_XFER_ERROR_NAK_RECEIVED:
  2412. PM8001_IO_DBG(pm8001_ha,
  2413. pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
  2414. ts->resp = SAS_TASK_COMPLETE;
  2415. ts->stat = SAS_NAK_R_ERR;
  2416. break;
  2417. case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
  2418. PM8001_IO_DBG(pm8001_ha,
  2419. pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
  2420. ts->resp = SAS_TASK_COMPLETE;
  2421. ts->stat = SAS_NAK_R_ERR;
  2422. break;
  2423. case IO_XFER_ERROR_DMA:
  2424. PM8001_IO_DBG(pm8001_ha,
  2425. pm8001_printk("IO_XFER_ERROR_DMA\n"));
  2426. ts->resp = SAS_TASK_COMPLETE;
  2427. ts->stat = SAS_ABORTED_TASK;
  2428. break;
  2429. case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
  2430. PM8001_IO_DBG(pm8001_ha,
  2431. pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
  2432. ts->resp = SAS_TASK_UNDELIVERED;
  2433. ts->stat = SAS_DEV_NO_RESPONSE;
  2434. break;
  2435. case IO_XFER_ERROR_REJECTED_NCQ_MODE:
  2436. PM8001_IO_DBG(pm8001_ha,
  2437. pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
  2438. ts->resp = SAS_TASK_COMPLETE;
  2439. ts->stat = SAS_DATA_UNDERRUN;
  2440. break;
  2441. case IO_XFER_OPEN_RETRY_TIMEOUT:
  2442. PM8001_IO_DBG(pm8001_ha,
  2443. pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
  2444. ts->resp = SAS_TASK_COMPLETE;
  2445. ts->stat = SAS_OPEN_TO;
  2446. break;
  2447. case IO_PORT_IN_RESET:
  2448. PM8001_IO_DBG(pm8001_ha,
  2449. pm8001_printk("IO_PORT_IN_RESET\n"));
  2450. ts->resp = SAS_TASK_COMPLETE;
  2451. ts->stat = SAS_DEV_NO_RESPONSE;
  2452. break;
  2453. case IO_DS_NON_OPERATIONAL:
  2454. PM8001_IO_DBG(pm8001_ha,
  2455. pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
  2456. ts->resp = SAS_TASK_COMPLETE;
  2457. ts->stat = SAS_DEV_NO_RESPONSE;
  2458. if (!t->uldd_task) {
  2459. pm8001_handle_event(pm8001_ha, pm8001_dev,
  2460. IO_DS_NON_OPERATIONAL);
  2461. ts->resp = SAS_TASK_UNDELIVERED;
  2462. ts->stat = SAS_QUEUE_FULL;
  2463. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2464. mb();/*ditto*/
  2465. spin_unlock_irq(&pm8001_ha->lock);
  2466. t->task_done(t);
  2467. spin_lock_irq(&pm8001_ha->lock);
  2468. return;
  2469. }
  2470. break;
  2471. case IO_DS_IN_RECOVERY:
  2472. PM8001_IO_DBG(pm8001_ha,
  2473. pm8001_printk(" IO_DS_IN_RECOVERY\n"));
  2474. ts->resp = SAS_TASK_COMPLETE;
  2475. ts->stat = SAS_DEV_NO_RESPONSE;
  2476. break;
  2477. case IO_DS_IN_ERROR:
  2478. PM8001_IO_DBG(pm8001_ha,
  2479. pm8001_printk("IO_DS_IN_ERROR\n"));
  2480. ts->resp = SAS_TASK_COMPLETE;
  2481. ts->stat = SAS_DEV_NO_RESPONSE;
  2482. if (!t->uldd_task) {
  2483. pm8001_handle_event(pm8001_ha, pm8001_dev,
  2484. IO_DS_IN_ERROR);
  2485. ts->resp = SAS_TASK_UNDELIVERED;
  2486. ts->stat = SAS_QUEUE_FULL;
  2487. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2488. mb();/*ditto*/
  2489. spin_unlock_irq(&pm8001_ha->lock);
  2490. t->task_done(t);
  2491. spin_lock_irq(&pm8001_ha->lock);
  2492. return;
  2493. }
  2494. break;
  2495. case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
  2496. PM8001_IO_DBG(pm8001_ha,
  2497. pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
  2498. ts->resp = SAS_TASK_COMPLETE;
  2499. ts->stat = SAS_OPEN_REJECT;
  2500. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2501. default:
  2502. PM8001_IO_DBG(pm8001_ha,
  2503. pm8001_printk("Unknown status 0x%x\n", status));
  2504. /* not allowed case. Therefore, return failed status */
  2505. ts->resp = SAS_TASK_COMPLETE;
  2506. ts->stat = SAS_DEV_NO_RESPONSE;
  2507. break;
  2508. }
  2509. spin_lock_irqsave(&t->task_state_lock, flags);
  2510. t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
  2511. t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
  2512. t->task_state_flags |= SAS_TASK_STATE_DONE;
  2513. if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
  2514. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2515. PM8001_FAIL_DBG(pm8001_ha,
  2516. pm8001_printk("task 0x%p done with io_status 0x%x"
  2517. " resp 0x%x stat 0x%x but aborted by upper layer!\n",
  2518. t, status, ts->resp, ts->stat));
  2519. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2520. } else if (t->uldd_task) {
  2521. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2522. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2523. mb();/* ditto */
  2524. spin_unlock_irq(&pm8001_ha->lock);
  2525. t->task_done(t);
  2526. spin_lock_irq(&pm8001_ha->lock);
  2527. } else if (!t->uldd_task) {
  2528. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2529. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2530. mb();/*ditto*/
  2531. spin_unlock_irq(&pm8001_ha->lock);
  2532. t->task_done(t);
  2533. spin_lock_irq(&pm8001_ha->lock);
  2534. }
  2535. }
  2536. /*See the comments for mpi_ssp_completion */
  2537. static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
  2538. {
  2539. struct sas_task *t;
  2540. struct task_status_struct *ts;
  2541. struct pm8001_ccb_info *ccb;
  2542. struct pm8001_device *pm8001_dev;
  2543. struct sata_event_resp *psataPayload =
  2544. (struct sata_event_resp *)(piomb + 4);
  2545. u32 event = le32_to_cpu(psataPayload->event);
  2546. u32 tag = le32_to_cpu(psataPayload->tag);
  2547. u32 port_id = le32_to_cpu(psataPayload->port_id);
  2548. u32 dev_id = le32_to_cpu(psataPayload->device_id);
  2549. unsigned long flags;
  2550. ccb = &pm8001_ha->ccb_info[tag];
  2551. if (ccb) {
  2552. t = ccb->task;
  2553. pm8001_dev = ccb->device;
  2554. } else {
  2555. PM8001_FAIL_DBG(pm8001_ha,
  2556. pm8001_printk("No CCB !!!. returning\n"));
  2557. }
  2558. if (event)
  2559. PM8001_FAIL_DBG(pm8001_ha,
  2560. pm8001_printk("SATA EVENT 0x%x\n", event));
  2561. /* Check if this is NCQ error */
  2562. if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
  2563. /* find device using device id */
  2564. pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
  2565. /* send read log extension */
  2566. if (pm8001_dev)
  2567. pm8001_send_read_log(pm8001_ha, pm8001_dev);
  2568. return;
  2569. }
  2570. ccb = &pm8001_ha->ccb_info[tag];
  2571. t = ccb->task;
  2572. pm8001_dev = ccb->device;
  2573. if (event)
  2574. PM8001_FAIL_DBG(pm8001_ha,
  2575. pm8001_printk("sata IO status 0x%x\n", event));
  2576. if (unlikely(!t || !t->lldd_task || !t->dev))
  2577. return;
  2578. ts = &t->task_status;
  2579. PM8001_IO_DBG(pm8001_ha, pm8001_printk(
  2580. "port_id:0x%x, device_id:0x%x, tag:0x%x, event:0x%x\n",
  2581. port_id, dev_id, tag, event));
  2582. switch (event) {
  2583. case IO_OVERFLOW:
  2584. PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
  2585. ts->resp = SAS_TASK_COMPLETE;
  2586. ts->stat = SAS_DATA_OVERRUN;
  2587. ts->residual = 0;
  2588. if (pm8001_dev)
  2589. pm8001_dev->running_req--;
  2590. break;
  2591. case IO_XFER_ERROR_BREAK:
  2592. PM8001_IO_DBG(pm8001_ha,
  2593. pm8001_printk("IO_XFER_ERROR_BREAK\n"));
  2594. ts->resp = SAS_TASK_COMPLETE;
  2595. ts->stat = SAS_INTERRUPTED;
  2596. break;
  2597. case IO_XFER_ERROR_PHY_NOT_READY:
  2598. PM8001_IO_DBG(pm8001_ha,
  2599. pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
  2600. ts->resp = SAS_TASK_COMPLETE;
  2601. ts->stat = SAS_OPEN_REJECT;
  2602. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2603. break;
  2604. case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
  2605. PM8001_IO_DBG(pm8001_ha,
  2606. pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
  2607. "_SUPPORTED\n"));
  2608. ts->resp = SAS_TASK_COMPLETE;
  2609. ts->stat = SAS_OPEN_REJECT;
  2610. ts->open_rej_reason = SAS_OREJ_EPROTO;
  2611. break;
  2612. case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
  2613. PM8001_IO_DBG(pm8001_ha,
  2614. pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
  2615. ts->resp = SAS_TASK_COMPLETE;
  2616. ts->stat = SAS_OPEN_REJECT;
  2617. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  2618. break;
  2619. case IO_OPEN_CNX_ERROR_BREAK:
  2620. PM8001_IO_DBG(pm8001_ha,
  2621. pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
  2622. ts->resp = SAS_TASK_COMPLETE;
  2623. ts->stat = SAS_OPEN_REJECT;
  2624. ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
  2625. break;
  2626. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
  2627. PM8001_IO_DBG(pm8001_ha,
  2628. pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
  2629. ts->resp = SAS_TASK_UNDELIVERED;
  2630. ts->stat = SAS_DEV_NO_RESPONSE;
  2631. if (!t->uldd_task) {
  2632. pm8001_handle_event(pm8001_ha,
  2633. pm8001_dev,
  2634. IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
  2635. ts->resp = SAS_TASK_COMPLETE;
  2636. ts->stat = SAS_QUEUE_FULL;
  2637. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2638. mb();/*ditto*/
  2639. spin_unlock_irq(&pm8001_ha->lock);
  2640. t->task_done(t);
  2641. spin_lock_irq(&pm8001_ha->lock);
  2642. return;
  2643. }
  2644. break;
  2645. case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
  2646. PM8001_IO_DBG(pm8001_ha,
  2647. pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
  2648. ts->resp = SAS_TASK_UNDELIVERED;
  2649. ts->stat = SAS_OPEN_REJECT;
  2650. ts->open_rej_reason = SAS_OREJ_BAD_DEST;
  2651. break;
  2652. case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
  2653. PM8001_IO_DBG(pm8001_ha,
  2654. pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
  2655. "NOT_SUPPORTED\n"));
  2656. ts->resp = SAS_TASK_COMPLETE;
  2657. ts->stat = SAS_OPEN_REJECT;
  2658. ts->open_rej_reason = SAS_OREJ_CONN_RATE;
  2659. break;
  2660. case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
  2661. PM8001_IO_DBG(pm8001_ha,
  2662. pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
  2663. ts->resp = SAS_TASK_COMPLETE;
  2664. ts->stat = SAS_OPEN_REJECT;
  2665. ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
  2666. break;
  2667. case IO_XFER_ERROR_NAK_RECEIVED:
  2668. PM8001_IO_DBG(pm8001_ha,
  2669. pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
  2670. ts->resp = SAS_TASK_COMPLETE;
  2671. ts->stat = SAS_NAK_R_ERR;
  2672. break;
  2673. case IO_XFER_ERROR_PEER_ABORTED:
  2674. PM8001_IO_DBG(pm8001_ha,
  2675. pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
  2676. ts->resp = SAS_TASK_COMPLETE;
  2677. ts->stat = SAS_NAK_R_ERR;
  2678. break;
  2679. case IO_XFER_ERROR_REJECTED_NCQ_MODE:
  2680. PM8001_IO_DBG(pm8001_ha,
  2681. pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
  2682. ts->resp = SAS_TASK_COMPLETE;
  2683. ts->stat = SAS_DATA_UNDERRUN;
  2684. break;
  2685. case IO_XFER_OPEN_RETRY_TIMEOUT:
  2686. PM8001_IO_DBG(pm8001_ha,
  2687. pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
  2688. ts->resp = SAS_TASK_COMPLETE;
  2689. ts->stat = SAS_OPEN_TO;
  2690. break;
  2691. case IO_XFER_ERROR_UNEXPECTED_PHASE:
  2692. PM8001_IO_DBG(pm8001_ha,
  2693. pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
  2694. ts->resp = SAS_TASK_COMPLETE;
  2695. ts->stat = SAS_OPEN_TO;
  2696. break;
  2697. case IO_XFER_ERROR_XFER_RDY_OVERRUN:
  2698. PM8001_IO_DBG(pm8001_ha,
  2699. pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
  2700. ts->resp = SAS_TASK_COMPLETE;
  2701. ts->stat = SAS_OPEN_TO;
  2702. break;
  2703. case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
  2704. PM8001_IO_DBG(pm8001_ha,
  2705. pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
  2706. ts->resp = SAS_TASK_COMPLETE;
  2707. ts->stat = SAS_OPEN_TO;
  2708. break;
  2709. case IO_XFER_ERROR_OFFSET_MISMATCH:
  2710. PM8001_IO_DBG(pm8001_ha,
  2711. pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
  2712. ts->resp = SAS_TASK_COMPLETE;
  2713. ts->stat = SAS_OPEN_TO;
  2714. break;
  2715. case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
  2716. PM8001_IO_DBG(pm8001_ha,
  2717. pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
  2718. ts->resp = SAS_TASK_COMPLETE;
  2719. ts->stat = SAS_OPEN_TO;
  2720. break;
  2721. case IO_XFER_CMD_FRAME_ISSUED:
  2722. PM8001_IO_DBG(pm8001_ha,
  2723. pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
  2724. break;
  2725. case IO_XFER_PIO_SETUP_ERROR:
  2726. PM8001_IO_DBG(pm8001_ha,
  2727. pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
  2728. ts->resp = SAS_TASK_COMPLETE;
  2729. ts->stat = SAS_OPEN_TO;
  2730. break;
  2731. default:
  2732. PM8001_IO_DBG(pm8001_ha,
  2733. pm8001_printk("Unknown status 0x%x\n", event));
  2734. /* not allowed case. Therefore, return failed status */
  2735. ts->resp = SAS_TASK_COMPLETE;
  2736. ts->stat = SAS_OPEN_TO;
  2737. break;
  2738. }
  2739. spin_lock_irqsave(&t->task_state_lock, flags);
  2740. t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
  2741. t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
  2742. t->task_state_flags |= SAS_TASK_STATE_DONE;
  2743. if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
  2744. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2745. PM8001_FAIL_DBG(pm8001_ha,
  2746. pm8001_printk("task 0x%p done with io_status 0x%x"
  2747. " resp 0x%x stat 0x%x but aborted by upper layer!\n",
  2748. t, event, ts->resp, ts->stat));
  2749. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2750. } else if (t->uldd_task) {
  2751. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2752. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2753. mb();/* ditto */
  2754. spin_unlock_irq(&pm8001_ha->lock);
  2755. t->task_done(t);
  2756. spin_lock_irq(&pm8001_ha->lock);
  2757. } else if (!t->uldd_task) {
  2758. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2759. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2760. mb();/*ditto*/
  2761. spin_unlock_irq(&pm8001_ha->lock);
  2762. t->task_done(t);
  2763. spin_lock_irq(&pm8001_ha->lock);
  2764. }
  2765. }
  2766. /*See the comments for mpi_ssp_completion */
  2767. static void
  2768. mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
  2769. {
  2770. u32 param;
  2771. struct sas_task *t;
  2772. struct pm8001_ccb_info *ccb;
  2773. unsigned long flags;
  2774. u32 status;
  2775. u32 tag;
  2776. struct smp_completion_resp *psmpPayload;
  2777. struct task_status_struct *ts;
  2778. struct pm8001_device *pm8001_dev;
  2779. psmpPayload = (struct smp_completion_resp *)(piomb + 4);
  2780. status = le32_to_cpu(psmpPayload->status);
  2781. tag = le32_to_cpu(psmpPayload->tag);
  2782. ccb = &pm8001_ha->ccb_info[tag];
  2783. param = le32_to_cpu(psmpPayload->param);
  2784. t = ccb->task;
  2785. ts = &t->task_status;
  2786. pm8001_dev = ccb->device;
  2787. if (status)
  2788. PM8001_FAIL_DBG(pm8001_ha,
  2789. pm8001_printk("smp IO status 0x%x\n", status));
  2790. if (unlikely(!t || !t->lldd_task || !t->dev))
  2791. return;
  2792. switch (status) {
  2793. case IO_SUCCESS:
  2794. PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
  2795. ts->resp = SAS_TASK_COMPLETE;
  2796. ts->stat = SAM_STAT_GOOD;
  2797. if (pm8001_dev)
  2798. pm8001_dev->running_req--;
  2799. break;
  2800. case IO_ABORTED:
  2801. PM8001_IO_DBG(pm8001_ha,
  2802. pm8001_printk("IO_ABORTED IOMB\n"));
  2803. ts->resp = SAS_TASK_COMPLETE;
  2804. ts->stat = SAS_ABORTED_TASK;
  2805. if (pm8001_dev)
  2806. pm8001_dev->running_req--;
  2807. break;
  2808. case IO_OVERFLOW:
  2809. PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
  2810. ts->resp = SAS_TASK_COMPLETE;
  2811. ts->stat = SAS_DATA_OVERRUN;
  2812. ts->residual = 0;
  2813. if (pm8001_dev)
  2814. pm8001_dev->running_req--;
  2815. break;
  2816. case IO_NO_DEVICE:
  2817. PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
  2818. ts->resp = SAS_TASK_COMPLETE;
  2819. ts->stat = SAS_PHY_DOWN;
  2820. break;
  2821. case IO_ERROR_HW_TIMEOUT:
  2822. PM8001_IO_DBG(pm8001_ha,
  2823. pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
  2824. ts->resp = SAS_TASK_COMPLETE;
  2825. ts->stat = SAM_STAT_BUSY;
  2826. break;
  2827. case IO_XFER_ERROR_BREAK:
  2828. PM8001_IO_DBG(pm8001_ha,
  2829. pm8001_printk("IO_XFER_ERROR_BREAK\n"));
  2830. ts->resp = SAS_TASK_COMPLETE;
  2831. ts->stat = SAM_STAT_BUSY;
  2832. break;
  2833. case IO_XFER_ERROR_PHY_NOT_READY:
  2834. PM8001_IO_DBG(pm8001_ha,
  2835. pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
  2836. ts->resp = SAS_TASK_COMPLETE;
  2837. ts->stat = SAM_STAT_BUSY;
  2838. break;
  2839. case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
  2840. PM8001_IO_DBG(pm8001_ha,
  2841. pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
  2842. ts->resp = SAS_TASK_COMPLETE;
  2843. ts->stat = SAS_OPEN_REJECT;
  2844. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  2845. break;
  2846. case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
  2847. PM8001_IO_DBG(pm8001_ha,
  2848. pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
  2849. ts->resp = SAS_TASK_COMPLETE;
  2850. ts->stat = SAS_OPEN_REJECT;
  2851. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  2852. break;
  2853. case IO_OPEN_CNX_ERROR_BREAK:
  2854. PM8001_IO_DBG(pm8001_ha,
  2855. pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
  2856. ts->resp = SAS_TASK_COMPLETE;
  2857. ts->stat = SAS_OPEN_REJECT;
  2858. ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
  2859. break;
  2860. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
  2861. PM8001_IO_DBG(pm8001_ha,
  2862. pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
  2863. ts->resp = SAS_TASK_COMPLETE;
  2864. ts->stat = SAS_OPEN_REJECT;
  2865. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  2866. pm8001_handle_event(pm8001_ha,
  2867. pm8001_dev,
  2868. IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
  2869. break;
  2870. case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
  2871. PM8001_IO_DBG(pm8001_ha,
  2872. pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
  2873. ts->resp = SAS_TASK_COMPLETE;
  2874. ts->stat = SAS_OPEN_REJECT;
  2875. ts->open_rej_reason = SAS_OREJ_BAD_DEST;
  2876. break;
  2877. case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
  2878. PM8001_IO_DBG(pm8001_ha,
  2879. pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
  2880. "NOT_SUPPORTED\n"));
  2881. ts->resp = SAS_TASK_COMPLETE;
  2882. ts->stat = SAS_OPEN_REJECT;
  2883. ts->open_rej_reason = SAS_OREJ_CONN_RATE;
  2884. break;
  2885. case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
  2886. PM8001_IO_DBG(pm8001_ha,
  2887. pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
  2888. ts->resp = SAS_TASK_COMPLETE;
  2889. ts->stat = SAS_OPEN_REJECT;
  2890. ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
  2891. break;
  2892. case IO_XFER_ERROR_RX_FRAME:
  2893. PM8001_IO_DBG(pm8001_ha,
  2894. pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
  2895. ts->resp = SAS_TASK_COMPLETE;
  2896. ts->stat = SAS_DEV_NO_RESPONSE;
  2897. break;
  2898. case IO_XFER_OPEN_RETRY_TIMEOUT:
  2899. PM8001_IO_DBG(pm8001_ha,
  2900. pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
  2901. ts->resp = SAS_TASK_COMPLETE;
  2902. ts->stat = SAS_OPEN_REJECT;
  2903. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2904. break;
  2905. case IO_ERROR_INTERNAL_SMP_RESOURCE:
  2906. PM8001_IO_DBG(pm8001_ha,
  2907. pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
  2908. ts->resp = SAS_TASK_COMPLETE;
  2909. ts->stat = SAS_QUEUE_FULL;
  2910. break;
  2911. case IO_PORT_IN_RESET:
  2912. PM8001_IO_DBG(pm8001_ha,
  2913. pm8001_printk("IO_PORT_IN_RESET\n"));
  2914. ts->resp = SAS_TASK_COMPLETE;
  2915. ts->stat = SAS_OPEN_REJECT;
  2916. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2917. break;
  2918. case IO_DS_NON_OPERATIONAL:
  2919. PM8001_IO_DBG(pm8001_ha,
  2920. pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
  2921. ts->resp = SAS_TASK_COMPLETE;
  2922. ts->stat = SAS_DEV_NO_RESPONSE;
  2923. break;
  2924. case IO_DS_IN_RECOVERY:
  2925. PM8001_IO_DBG(pm8001_ha,
  2926. pm8001_printk("IO_DS_IN_RECOVERY\n"));
  2927. ts->resp = SAS_TASK_COMPLETE;
  2928. ts->stat = SAS_OPEN_REJECT;
  2929. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2930. break;
  2931. case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
  2932. PM8001_IO_DBG(pm8001_ha,
  2933. pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
  2934. ts->resp = SAS_TASK_COMPLETE;
  2935. ts->stat = SAS_OPEN_REJECT;
  2936. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2937. break;
  2938. default:
  2939. PM8001_IO_DBG(pm8001_ha,
  2940. pm8001_printk("Unknown status 0x%x\n", status));
  2941. ts->resp = SAS_TASK_COMPLETE;
  2942. ts->stat = SAS_DEV_NO_RESPONSE;
  2943. /* not allowed case. Therefore, return failed status */
  2944. break;
  2945. }
  2946. spin_lock_irqsave(&t->task_state_lock, flags);
  2947. t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
  2948. t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
  2949. t->task_state_flags |= SAS_TASK_STATE_DONE;
  2950. if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
  2951. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2952. PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
  2953. " io_status 0x%x resp 0x%x "
  2954. "stat 0x%x but aborted by upper layer!\n",
  2955. t, status, ts->resp, ts->stat));
  2956. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2957. } else {
  2958. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2959. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2960. mb();/* in order to force CPU ordering */
  2961. t->task_done(t);
  2962. }
  2963. }
  2964. void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
  2965. void *piomb)
  2966. {
  2967. struct set_dev_state_resp *pPayload =
  2968. (struct set_dev_state_resp *)(piomb + 4);
  2969. u32 tag = le32_to_cpu(pPayload->tag);
  2970. struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
  2971. struct pm8001_device *pm8001_dev = ccb->device;
  2972. u32 status = le32_to_cpu(pPayload->status);
  2973. u32 device_id = le32_to_cpu(pPayload->device_id);
  2974. u8 pds = le32_to_cpu(pPayload->pds_nds) & PDS_BITS;
  2975. u8 nds = le32_to_cpu(pPayload->pds_nds) & NDS_BITS;
  2976. PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state "
  2977. "from 0x%x to 0x%x status = 0x%x!\n",
  2978. device_id, pds, nds, status));
  2979. complete(pm8001_dev->setds_completion);
  2980. ccb->task = NULL;
  2981. ccb->ccb_tag = 0xFFFFFFFF;
  2982. pm8001_ccb_free(pm8001_ha, tag);
  2983. }
  2984. void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
  2985. {
  2986. struct get_nvm_data_resp *pPayload =
  2987. (struct get_nvm_data_resp *)(piomb + 4);
  2988. u32 tag = le32_to_cpu(pPayload->tag);
  2989. struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
  2990. u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
  2991. complete(pm8001_ha->nvmd_completion);
  2992. PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n"));
  2993. if ((dlen_status & NVMD_STAT) != 0) {
  2994. PM8001_FAIL_DBG(pm8001_ha,
  2995. pm8001_printk("Set nvm data error!\n"));
  2996. return;
  2997. }
  2998. ccb->task = NULL;
  2999. ccb->ccb_tag = 0xFFFFFFFF;
  3000. pm8001_ccb_free(pm8001_ha, tag);
  3001. }
  3002. void
  3003. pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
  3004. {
  3005. struct fw_control_ex *fw_control_context;
  3006. struct get_nvm_data_resp *pPayload =
  3007. (struct get_nvm_data_resp *)(piomb + 4);
  3008. u32 tag = le32_to_cpu(pPayload->tag);
  3009. struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
  3010. u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
  3011. u32 ir_tds_bn_dps_das_nvm =
  3012. le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
  3013. void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
  3014. fw_control_context = ccb->fw_control_context;
  3015. PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n"));
  3016. if ((dlen_status & NVMD_STAT) != 0) {
  3017. PM8001_FAIL_DBG(pm8001_ha,
  3018. pm8001_printk("Get nvm data error!\n"));
  3019. complete(pm8001_ha->nvmd_completion);
  3020. return;
  3021. }
  3022. if (ir_tds_bn_dps_das_nvm & IPMode) {
  3023. /* indirect mode - IR bit set */
  3024. PM8001_MSG_DBG(pm8001_ha,
  3025. pm8001_printk("Get NVMD success, IR=1\n"));
  3026. if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
  3027. if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
  3028. memcpy(pm8001_ha->sas_addr,
  3029. ((u8 *)virt_addr + 4),
  3030. SAS_ADDR_SIZE);
  3031. PM8001_MSG_DBG(pm8001_ha,
  3032. pm8001_printk("Get SAS address"
  3033. " from VPD successfully!\n"));
  3034. }
  3035. } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
  3036. || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
  3037. ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
  3038. ;
  3039. } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
  3040. || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
  3041. ;
  3042. } else {
  3043. /* Should not be happened*/
  3044. PM8001_MSG_DBG(pm8001_ha,
  3045. pm8001_printk("(IR=1)Wrong Device type 0x%x\n",
  3046. ir_tds_bn_dps_das_nvm));
  3047. }
  3048. } else /* direct mode */{
  3049. PM8001_MSG_DBG(pm8001_ha,
  3050. pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n",
  3051. (dlen_status & NVMD_LEN) >> 24));
  3052. }
  3053. memcpy(fw_control_context->usrAddr,
  3054. pm8001_ha->memoryMap.region[NVMD].virt_ptr,
  3055. fw_control_context->len);
  3056. complete(pm8001_ha->nvmd_completion);
  3057. ccb->task = NULL;
  3058. ccb->ccb_tag = 0xFFFFFFFF;
  3059. pm8001_ccb_free(pm8001_ha, tag);
  3060. }
  3061. int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
  3062. {
  3063. struct local_phy_ctl_resp *pPayload =
  3064. (struct local_phy_ctl_resp *)(piomb + 4);
  3065. u32 status = le32_to_cpu(pPayload->status);
  3066. u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
  3067. u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
  3068. if (status != 0) {
  3069. PM8001_MSG_DBG(pm8001_ha,
  3070. pm8001_printk("%x phy execute %x phy op failed!\n",
  3071. phy_id, phy_op));
  3072. } else
  3073. PM8001_MSG_DBG(pm8001_ha,
  3074. pm8001_printk("%x phy execute %x phy op success!\n",
  3075. phy_id, phy_op));
  3076. return 0;
  3077. }
  3078. /**
  3079. * pm8001_bytes_dmaed - one of the interface function communication with libsas
  3080. * @pm8001_ha: our hba card information
  3081. * @i: which phy that received the event.
  3082. *
  3083. * when HBA driver received the identify done event or initiate FIS received
  3084. * event(for SATA), it will invoke this function to notify the sas layer that
  3085. * the sas toplogy has formed, please discover the the whole sas domain,
  3086. * while receive a broadcast(change) primitive just tell the sas
  3087. * layer to discover the changed domain rather than the whole domain.
  3088. */
  3089. void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
  3090. {
  3091. struct pm8001_phy *phy = &pm8001_ha->phy[i];
  3092. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  3093. struct sas_ha_struct *sas_ha;
  3094. if (!phy->phy_attached)
  3095. return;
  3096. sas_ha = pm8001_ha->sas;
  3097. if (sas_phy->phy) {
  3098. struct sas_phy *sphy = sas_phy->phy;
  3099. sphy->negotiated_linkrate = sas_phy->linkrate;
  3100. sphy->minimum_linkrate = phy->minimum_linkrate;
  3101. sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
  3102. sphy->maximum_linkrate = phy->maximum_linkrate;
  3103. sphy->maximum_linkrate_hw = phy->maximum_linkrate;
  3104. }
  3105. if (phy->phy_type & PORT_TYPE_SAS) {
  3106. struct sas_identify_frame *id;
  3107. id = (struct sas_identify_frame *)phy->frame_rcvd;
  3108. id->dev_type = phy->identify.device_type;
  3109. id->initiator_bits = SAS_PROTOCOL_ALL;
  3110. id->target_bits = phy->identify.target_port_protocols;
  3111. } else if (phy->phy_type & PORT_TYPE_SATA) {
  3112. /*Nothing*/
  3113. }
  3114. PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i));
  3115. sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
  3116. pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED);
  3117. }
  3118. /* Get the link rate speed */
  3119. void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
  3120. {
  3121. struct sas_phy *sas_phy = phy->sas_phy.phy;
  3122. switch (link_rate) {
  3123. case PHY_SPEED_60:
  3124. phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
  3125. phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
  3126. break;
  3127. case PHY_SPEED_30:
  3128. phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
  3129. phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
  3130. break;
  3131. case PHY_SPEED_15:
  3132. phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
  3133. phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
  3134. break;
  3135. }
  3136. sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
  3137. sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
  3138. sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
  3139. sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
  3140. sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
  3141. }
  3142. /**
  3143. * asd_get_attached_sas_addr -- extract/generate attached SAS address
  3144. * @phy: pointer to asd_phy
  3145. * @sas_addr: pointer to buffer where the SAS address is to be written
  3146. *
  3147. * This function extracts the SAS address from an IDENTIFY frame
  3148. * received. If OOB is SATA, then a SAS address is generated from the
  3149. * HA tables.
  3150. *
  3151. * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
  3152. * buffer.
  3153. */
  3154. void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
  3155. u8 *sas_addr)
  3156. {
  3157. if (phy->sas_phy.frame_rcvd[0] == 0x34
  3158. && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
  3159. struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
  3160. /* FIS device-to-host */
  3161. u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
  3162. addr += phy->sas_phy.id;
  3163. *(__be64 *)sas_addr = cpu_to_be64(addr);
  3164. } else {
  3165. struct sas_identify_frame *idframe =
  3166. (void *) phy->sas_phy.frame_rcvd;
  3167. memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
  3168. }
  3169. }
  3170. /**
  3171. * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
  3172. * @pm8001_ha: our hba card information
  3173. * @Qnum: the outbound queue message number.
  3174. * @SEA: source of event to ack
  3175. * @port_id: port id.
  3176. * @phyId: phy id.
  3177. * @param0: parameter 0.
  3178. * @param1: parameter 1.
  3179. */
  3180. static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
  3181. u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
  3182. {
  3183. struct hw_event_ack_req payload;
  3184. u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
  3185. struct inbound_queue_table *circularQ;
  3186. memset((u8 *)&payload, 0, sizeof(payload));
  3187. circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
  3188. payload.tag = cpu_to_le32(1);
  3189. payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
  3190. ((phyId & 0x0F) << 4) | (port_id & 0x0F));
  3191. payload.param0 = cpu_to_le32(param0);
  3192. payload.param1 = cpu_to_le32(param1);
  3193. pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
  3194. }
  3195. static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
  3196. u32 phyId, u32 phy_op);
  3197. /**
  3198. * hw_event_sas_phy_up -FW tells me a SAS phy up event.
  3199. * @pm8001_ha: our hba card information
  3200. * @piomb: IO message buffer
  3201. */
  3202. static void
  3203. hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
  3204. {
  3205. struct hw_event_resp *pPayload =
  3206. (struct hw_event_resp *)(piomb + 4);
  3207. u32 lr_evt_status_phyid_portid =
  3208. le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
  3209. u8 link_rate =
  3210. (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
  3211. u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
  3212. u8 phy_id =
  3213. (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
  3214. u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
  3215. u8 portstate = (u8)(npip_portstate & 0x0000000F);
  3216. struct pm8001_port *port = &pm8001_ha->port[port_id];
  3217. struct sas_ha_struct *sas_ha = pm8001_ha->sas;
  3218. struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
  3219. unsigned long flags;
  3220. u8 deviceType = pPayload->sas_identify.dev_type;
  3221. port->port_state = portstate;
  3222. PM8001_MSG_DBG(pm8001_ha,
  3223. pm8001_printk("HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
  3224. port_id, phy_id));
  3225. switch (deviceType) {
  3226. case SAS_PHY_UNUSED:
  3227. PM8001_MSG_DBG(pm8001_ha,
  3228. pm8001_printk("device type no device.\n"));
  3229. break;
  3230. case SAS_END_DEVICE:
  3231. PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
  3232. pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
  3233. PHY_NOTIFY_ENABLE_SPINUP);
  3234. port->port_attached = 1;
  3235. pm8001_get_lrate_mode(phy, link_rate);
  3236. break;
  3237. case SAS_EDGE_EXPANDER_DEVICE:
  3238. PM8001_MSG_DBG(pm8001_ha,
  3239. pm8001_printk("expander device.\n"));
  3240. port->port_attached = 1;
  3241. pm8001_get_lrate_mode(phy, link_rate);
  3242. break;
  3243. case SAS_FANOUT_EXPANDER_DEVICE:
  3244. PM8001_MSG_DBG(pm8001_ha,
  3245. pm8001_printk("fanout expander device.\n"));
  3246. port->port_attached = 1;
  3247. pm8001_get_lrate_mode(phy, link_rate);
  3248. break;
  3249. default:
  3250. PM8001_MSG_DBG(pm8001_ha,
  3251. pm8001_printk("unknown device type(%x)\n", deviceType));
  3252. break;
  3253. }
  3254. phy->phy_type |= PORT_TYPE_SAS;
  3255. phy->identify.device_type = deviceType;
  3256. phy->phy_attached = 1;
  3257. if (phy->identify.device_type == SAS_END_DEVICE)
  3258. phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
  3259. else if (phy->identify.device_type != SAS_PHY_UNUSED)
  3260. phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
  3261. phy->sas_phy.oob_mode = SAS_OOB_MODE;
  3262. sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
  3263. spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
  3264. memcpy(phy->frame_rcvd, &pPayload->sas_identify,
  3265. sizeof(struct sas_identify_frame)-4);
  3266. phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
  3267. pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
  3268. spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
  3269. if (pm8001_ha->flags == PM8001F_RUN_TIME)
  3270. mdelay(200);/*delay a moment to wait disk to spinup*/
  3271. pm8001_bytes_dmaed(pm8001_ha, phy_id);
  3272. }
  3273. /**
  3274. * hw_event_sata_phy_up -FW tells me a SATA phy up event.
  3275. * @pm8001_ha: our hba card information
  3276. * @piomb: IO message buffer
  3277. */
  3278. static void
  3279. hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
  3280. {
  3281. struct hw_event_resp *pPayload =
  3282. (struct hw_event_resp *)(piomb + 4);
  3283. u32 lr_evt_status_phyid_portid =
  3284. le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
  3285. u8 link_rate =
  3286. (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
  3287. u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
  3288. u8 phy_id =
  3289. (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
  3290. u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
  3291. u8 portstate = (u8)(npip_portstate & 0x0000000F);
  3292. struct pm8001_port *port = &pm8001_ha->port[port_id];
  3293. struct sas_ha_struct *sas_ha = pm8001_ha->sas;
  3294. struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
  3295. unsigned long flags;
  3296. PM8001_MSG_DBG(pm8001_ha,
  3297. pm8001_printk("HW_EVENT_SATA_PHY_UP port id = %d,"
  3298. " phy id = %d\n", port_id, phy_id));
  3299. port->port_state = portstate;
  3300. port->port_attached = 1;
  3301. pm8001_get_lrate_mode(phy, link_rate);
  3302. phy->phy_type |= PORT_TYPE_SATA;
  3303. phy->phy_attached = 1;
  3304. phy->sas_phy.oob_mode = SATA_OOB_MODE;
  3305. sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
  3306. spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
  3307. memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
  3308. sizeof(struct dev_to_host_fis));
  3309. phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
  3310. phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
  3311. phy->identify.device_type = SAS_SATA_DEV;
  3312. pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
  3313. spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
  3314. pm8001_bytes_dmaed(pm8001_ha, phy_id);
  3315. }
  3316. /**
  3317. * hw_event_phy_down -we should notify the libsas the phy is down.
  3318. * @pm8001_ha: our hba card information
  3319. * @piomb: IO message buffer
  3320. */
  3321. static void
  3322. hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
  3323. {
  3324. struct hw_event_resp *pPayload =
  3325. (struct hw_event_resp *)(piomb + 4);
  3326. u32 lr_evt_status_phyid_portid =
  3327. le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
  3328. u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
  3329. u8 phy_id =
  3330. (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
  3331. u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
  3332. u8 portstate = (u8)(npip_portstate & 0x0000000F);
  3333. struct pm8001_port *port = &pm8001_ha->port[port_id];
  3334. struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
  3335. port->port_state = portstate;
  3336. phy->phy_type = 0;
  3337. phy->identify.device_type = 0;
  3338. phy->phy_attached = 0;
  3339. memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
  3340. switch (portstate) {
  3341. case PORT_VALID:
  3342. break;
  3343. case PORT_INVALID:
  3344. PM8001_MSG_DBG(pm8001_ha,
  3345. pm8001_printk(" PortInvalid portID %d\n", port_id));
  3346. PM8001_MSG_DBG(pm8001_ha,
  3347. pm8001_printk(" Last phy Down and port invalid\n"));
  3348. port->port_attached = 0;
  3349. pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
  3350. port_id, phy_id, 0, 0);
  3351. break;
  3352. case PORT_IN_RESET:
  3353. PM8001_MSG_DBG(pm8001_ha,
  3354. pm8001_printk(" Port In Reset portID %d\n", port_id));
  3355. break;
  3356. case PORT_NOT_ESTABLISHED:
  3357. PM8001_MSG_DBG(pm8001_ha,
  3358. pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
  3359. port->port_attached = 0;
  3360. break;
  3361. case PORT_LOSTCOMM:
  3362. PM8001_MSG_DBG(pm8001_ha,
  3363. pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
  3364. PM8001_MSG_DBG(pm8001_ha,
  3365. pm8001_printk(" Last phy Down and port invalid\n"));
  3366. port->port_attached = 0;
  3367. pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
  3368. port_id, phy_id, 0, 0);
  3369. break;
  3370. default:
  3371. port->port_attached = 0;
  3372. PM8001_MSG_DBG(pm8001_ha,
  3373. pm8001_printk(" phy Down and(default) = %x\n",
  3374. portstate));
  3375. break;
  3376. }
  3377. }
  3378. /**
  3379. * pm8001_mpi_reg_resp -process register device ID response.
  3380. * @pm8001_ha: our hba card information
  3381. * @piomb: IO message buffer
  3382. *
  3383. * when sas layer find a device it will notify LLDD, then the driver register
  3384. * the domain device to FW, this event is the return device ID which the FW
  3385. * has assigned, from now,inter-communication with FW is no longer using the
  3386. * SAS address, use device ID which FW assigned.
  3387. */
  3388. int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
  3389. {
  3390. u32 status;
  3391. u32 device_id;
  3392. u32 htag;
  3393. struct pm8001_ccb_info *ccb;
  3394. struct pm8001_device *pm8001_dev;
  3395. struct dev_reg_resp *registerRespPayload =
  3396. (struct dev_reg_resp *)(piomb + 4);
  3397. htag = le32_to_cpu(registerRespPayload->tag);
  3398. ccb = &pm8001_ha->ccb_info[htag];
  3399. pm8001_dev = ccb->device;
  3400. status = le32_to_cpu(registerRespPayload->status);
  3401. device_id = le32_to_cpu(registerRespPayload->device_id);
  3402. PM8001_MSG_DBG(pm8001_ha,
  3403. pm8001_printk(" register device is status = %d\n", status));
  3404. switch (status) {
  3405. case DEVREG_SUCCESS:
  3406. PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n"));
  3407. pm8001_dev->device_id = device_id;
  3408. break;
  3409. case DEVREG_FAILURE_OUT_OF_RESOURCE:
  3410. PM8001_MSG_DBG(pm8001_ha,
  3411. pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n"));
  3412. break;
  3413. case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
  3414. PM8001_MSG_DBG(pm8001_ha,
  3415. pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"));
  3416. break;
  3417. case DEVREG_FAILURE_INVALID_PHY_ID:
  3418. PM8001_MSG_DBG(pm8001_ha,
  3419. pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n"));
  3420. break;
  3421. case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
  3422. PM8001_MSG_DBG(pm8001_ha,
  3423. pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"));
  3424. break;
  3425. case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
  3426. PM8001_MSG_DBG(pm8001_ha,
  3427. pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"));
  3428. break;
  3429. case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
  3430. PM8001_MSG_DBG(pm8001_ha,
  3431. pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"));
  3432. break;
  3433. case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
  3434. PM8001_MSG_DBG(pm8001_ha,
  3435. pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"));
  3436. break;
  3437. default:
  3438. PM8001_MSG_DBG(pm8001_ha,
  3439. pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_UNSORPORTED\n"));
  3440. break;
  3441. }
  3442. complete(pm8001_dev->dcompletion);
  3443. ccb->task = NULL;
  3444. ccb->ccb_tag = 0xFFFFFFFF;
  3445. pm8001_ccb_free(pm8001_ha, htag);
  3446. return 0;
  3447. }
  3448. int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
  3449. {
  3450. u32 status;
  3451. u32 device_id;
  3452. struct dev_reg_resp *registerRespPayload =
  3453. (struct dev_reg_resp *)(piomb + 4);
  3454. status = le32_to_cpu(registerRespPayload->status);
  3455. device_id = le32_to_cpu(registerRespPayload->device_id);
  3456. if (status != 0)
  3457. PM8001_MSG_DBG(pm8001_ha,
  3458. pm8001_printk(" deregister device failed ,status = %x"
  3459. ", device_id = %x\n", status, device_id));
  3460. return 0;
  3461. }
  3462. /**
  3463. * fw_flash_update_resp - Response from FW for flash update command.
  3464. * @pm8001_ha: our hba card information
  3465. * @piomb: IO message buffer
  3466. */
  3467. int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
  3468. void *piomb)
  3469. {
  3470. u32 status;
  3471. struct fw_control_ex fw_control_context;
  3472. struct fw_flash_Update_resp *ppayload =
  3473. (struct fw_flash_Update_resp *)(piomb + 4);
  3474. u32 tag = le32_to_cpu(ppayload->tag);
  3475. struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
  3476. status = le32_to_cpu(ppayload->status);
  3477. memcpy(&fw_control_context,
  3478. ccb->fw_control_context,
  3479. sizeof(fw_control_context));
  3480. switch (status) {
  3481. case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
  3482. PM8001_MSG_DBG(pm8001_ha,
  3483. pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"));
  3484. break;
  3485. case FLASH_UPDATE_IN_PROGRESS:
  3486. PM8001_MSG_DBG(pm8001_ha,
  3487. pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n"));
  3488. break;
  3489. case FLASH_UPDATE_HDR_ERR:
  3490. PM8001_MSG_DBG(pm8001_ha,
  3491. pm8001_printk(": FLASH_UPDATE_HDR_ERR\n"));
  3492. break;
  3493. case FLASH_UPDATE_OFFSET_ERR:
  3494. PM8001_MSG_DBG(pm8001_ha,
  3495. pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n"));
  3496. break;
  3497. case FLASH_UPDATE_CRC_ERR:
  3498. PM8001_MSG_DBG(pm8001_ha,
  3499. pm8001_printk(": FLASH_UPDATE_CRC_ERR\n"));
  3500. break;
  3501. case FLASH_UPDATE_LENGTH_ERR:
  3502. PM8001_MSG_DBG(pm8001_ha,
  3503. pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n"));
  3504. break;
  3505. case FLASH_UPDATE_HW_ERR:
  3506. PM8001_MSG_DBG(pm8001_ha,
  3507. pm8001_printk(": FLASH_UPDATE_HW_ERR\n"));
  3508. break;
  3509. case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
  3510. PM8001_MSG_DBG(pm8001_ha,
  3511. pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"));
  3512. break;
  3513. case FLASH_UPDATE_DISABLED:
  3514. PM8001_MSG_DBG(pm8001_ha,
  3515. pm8001_printk(": FLASH_UPDATE_DISABLED\n"));
  3516. break;
  3517. default:
  3518. PM8001_MSG_DBG(pm8001_ha,
  3519. pm8001_printk("No matched status = %d\n", status));
  3520. break;
  3521. }
  3522. ccb->fw_control_context->fw_control->retcode = status;
  3523. complete(pm8001_ha->nvmd_completion);
  3524. ccb->task = NULL;
  3525. ccb->ccb_tag = 0xFFFFFFFF;
  3526. pm8001_ccb_free(pm8001_ha, tag);
  3527. return 0;
  3528. }
  3529. int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
  3530. {
  3531. u32 status;
  3532. int i;
  3533. struct general_event_resp *pPayload =
  3534. (struct general_event_resp *)(piomb + 4);
  3535. status = le32_to_cpu(pPayload->status);
  3536. PM8001_MSG_DBG(pm8001_ha,
  3537. pm8001_printk(" status = 0x%x\n", status));
  3538. for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
  3539. PM8001_MSG_DBG(pm8001_ha,
  3540. pm8001_printk("inb_IOMB_payload[0x%x] 0x%x,\n", i,
  3541. pPayload->inb_IOMB_payload[i]));
  3542. return 0;
  3543. }
  3544. int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
  3545. {
  3546. struct sas_task *t;
  3547. struct pm8001_ccb_info *ccb;
  3548. unsigned long flags;
  3549. u32 status ;
  3550. u32 tag, scp;
  3551. struct task_status_struct *ts;
  3552. struct pm8001_device *pm8001_dev;
  3553. struct task_abort_resp *pPayload =
  3554. (struct task_abort_resp *)(piomb + 4);
  3555. status = le32_to_cpu(pPayload->status);
  3556. tag = le32_to_cpu(pPayload->tag);
  3557. if (!tag) {
  3558. PM8001_FAIL_DBG(pm8001_ha,
  3559. pm8001_printk(" TAG NULL. RETURNING !!!"));
  3560. return -1;
  3561. }
  3562. scp = le32_to_cpu(pPayload->scp);
  3563. ccb = &pm8001_ha->ccb_info[tag];
  3564. t = ccb->task;
  3565. pm8001_dev = ccb->device; /* retrieve device */
  3566. if (!t) {
  3567. PM8001_FAIL_DBG(pm8001_ha,
  3568. pm8001_printk(" TASK NULL. RETURNING !!!"));
  3569. return -1;
  3570. }
  3571. ts = &t->task_status;
  3572. if (status != 0)
  3573. PM8001_FAIL_DBG(pm8001_ha,
  3574. pm8001_printk("task abort failed status 0x%x ,"
  3575. "tag = 0x%x, scp= 0x%x\n", status, tag, scp));
  3576. switch (status) {
  3577. case IO_SUCCESS:
  3578. PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
  3579. ts->resp = SAS_TASK_COMPLETE;
  3580. ts->stat = SAM_STAT_GOOD;
  3581. break;
  3582. case IO_NOT_VALID:
  3583. PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n"));
  3584. ts->resp = TMF_RESP_FUNC_FAILED;
  3585. break;
  3586. }
  3587. spin_lock_irqsave(&t->task_state_lock, flags);
  3588. t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
  3589. t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
  3590. t->task_state_flags |= SAS_TASK_STATE_DONE;
  3591. spin_unlock_irqrestore(&t->task_state_lock, flags);
  3592. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  3593. mb();
  3594. if (pm8001_dev->id & NCQ_ABORT_ALL_FLAG) {
  3595. pm8001_tag_free(pm8001_ha, tag);
  3596. sas_free_task(t);
  3597. /* clear the flag */
  3598. pm8001_dev->id &= 0xBFFFFFFF;
  3599. } else
  3600. t->task_done(t);
  3601. return 0;
  3602. }
  3603. /**
  3604. * mpi_hw_event -The hw event has come.
  3605. * @pm8001_ha: our hba card information
  3606. * @piomb: IO message buffer
  3607. */
  3608. static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb)
  3609. {
  3610. unsigned long flags;
  3611. struct hw_event_resp *pPayload =
  3612. (struct hw_event_resp *)(piomb + 4);
  3613. u32 lr_evt_status_phyid_portid =
  3614. le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
  3615. u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
  3616. u8 phy_id =
  3617. (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
  3618. u16 eventType =
  3619. (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
  3620. u8 status =
  3621. (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
  3622. struct sas_ha_struct *sas_ha = pm8001_ha->sas;
  3623. struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
  3624. struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
  3625. PM8001_MSG_DBG(pm8001_ha,
  3626. pm8001_printk("outbound queue HW event & event type : "));
  3627. switch (eventType) {
  3628. case HW_EVENT_PHY_START_STATUS:
  3629. PM8001_MSG_DBG(pm8001_ha,
  3630. pm8001_printk("HW_EVENT_PHY_START_STATUS"
  3631. " status = %x\n", status));
  3632. if (status == 0) {
  3633. phy->phy_state = 1;
  3634. if (pm8001_ha->flags == PM8001F_RUN_TIME)
  3635. complete(phy->enable_completion);
  3636. }
  3637. break;
  3638. case HW_EVENT_SAS_PHY_UP:
  3639. PM8001_MSG_DBG(pm8001_ha,
  3640. pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
  3641. hw_event_sas_phy_up(pm8001_ha, piomb);
  3642. break;
  3643. case HW_EVENT_SATA_PHY_UP:
  3644. PM8001_MSG_DBG(pm8001_ha,
  3645. pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
  3646. hw_event_sata_phy_up(pm8001_ha, piomb);
  3647. break;
  3648. case HW_EVENT_PHY_STOP_STATUS:
  3649. PM8001_MSG_DBG(pm8001_ha,
  3650. pm8001_printk("HW_EVENT_PHY_STOP_STATUS "
  3651. "status = %x\n", status));
  3652. if (status == 0)
  3653. phy->phy_state = 0;
  3654. break;
  3655. case HW_EVENT_SATA_SPINUP_HOLD:
  3656. PM8001_MSG_DBG(pm8001_ha,
  3657. pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
  3658. sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
  3659. break;
  3660. case HW_EVENT_PHY_DOWN:
  3661. PM8001_MSG_DBG(pm8001_ha,
  3662. pm8001_printk("HW_EVENT_PHY_DOWN\n"));
  3663. sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
  3664. phy->phy_attached = 0;
  3665. phy->phy_state = 0;
  3666. hw_event_phy_down(pm8001_ha, piomb);
  3667. break;
  3668. case HW_EVENT_PORT_INVALID:
  3669. PM8001_MSG_DBG(pm8001_ha,
  3670. pm8001_printk("HW_EVENT_PORT_INVALID\n"));
  3671. sas_phy_disconnected(sas_phy);
  3672. phy->phy_attached = 0;
  3673. sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
  3674. break;
  3675. /* the broadcast change primitive received, tell the LIBSAS this event
  3676. to revalidate the sas domain*/
  3677. case HW_EVENT_BROADCAST_CHANGE:
  3678. PM8001_MSG_DBG(pm8001_ha,
  3679. pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
  3680. pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
  3681. port_id, phy_id, 1, 0);
  3682. spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
  3683. sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
  3684. spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
  3685. sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
  3686. break;
  3687. case HW_EVENT_PHY_ERROR:
  3688. PM8001_MSG_DBG(pm8001_ha,
  3689. pm8001_printk("HW_EVENT_PHY_ERROR\n"));
  3690. sas_phy_disconnected(&phy->sas_phy);
  3691. phy->phy_attached = 0;
  3692. sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
  3693. break;
  3694. case HW_EVENT_BROADCAST_EXP:
  3695. PM8001_MSG_DBG(pm8001_ha,
  3696. pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
  3697. spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
  3698. sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
  3699. spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
  3700. sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
  3701. break;
  3702. case HW_EVENT_LINK_ERR_INVALID_DWORD:
  3703. PM8001_MSG_DBG(pm8001_ha,
  3704. pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
  3705. pm8001_hw_event_ack_req(pm8001_ha, 0,
  3706. HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
  3707. sas_phy_disconnected(sas_phy);
  3708. phy->phy_attached = 0;
  3709. sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
  3710. break;
  3711. case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
  3712. PM8001_MSG_DBG(pm8001_ha,
  3713. pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
  3714. pm8001_hw_event_ack_req(pm8001_ha, 0,
  3715. HW_EVENT_LINK_ERR_DISPARITY_ERROR,
  3716. port_id, phy_id, 0, 0);
  3717. sas_phy_disconnected(sas_phy);
  3718. phy->phy_attached = 0;
  3719. sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
  3720. break;
  3721. case HW_EVENT_LINK_ERR_CODE_VIOLATION:
  3722. PM8001_MSG_DBG(pm8001_ha,
  3723. pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
  3724. pm8001_hw_event_ack_req(pm8001_ha, 0,
  3725. HW_EVENT_LINK_ERR_CODE_VIOLATION,
  3726. port_id, phy_id, 0, 0);
  3727. sas_phy_disconnected(sas_phy);
  3728. phy->phy_attached = 0;
  3729. sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
  3730. break;
  3731. case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
  3732. PM8001_MSG_DBG(pm8001_ha,
  3733. pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
  3734. pm8001_hw_event_ack_req(pm8001_ha, 0,
  3735. HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
  3736. port_id, phy_id, 0, 0);
  3737. sas_phy_disconnected(sas_phy);
  3738. phy->phy_attached = 0;
  3739. sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
  3740. break;
  3741. case HW_EVENT_MALFUNCTION:
  3742. PM8001_MSG_DBG(pm8001_ha,
  3743. pm8001_printk("HW_EVENT_MALFUNCTION\n"));
  3744. break;
  3745. case HW_EVENT_BROADCAST_SES:
  3746. PM8001_MSG_DBG(pm8001_ha,
  3747. pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
  3748. spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
  3749. sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
  3750. spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
  3751. sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
  3752. break;
  3753. case HW_EVENT_INBOUND_CRC_ERROR:
  3754. PM8001_MSG_DBG(pm8001_ha,
  3755. pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
  3756. pm8001_hw_event_ack_req(pm8001_ha, 0,
  3757. HW_EVENT_INBOUND_CRC_ERROR,
  3758. port_id, phy_id, 0, 0);
  3759. break;
  3760. case HW_EVENT_HARD_RESET_RECEIVED:
  3761. PM8001_MSG_DBG(pm8001_ha,
  3762. pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
  3763. sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
  3764. break;
  3765. case HW_EVENT_ID_FRAME_TIMEOUT:
  3766. PM8001_MSG_DBG(pm8001_ha,
  3767. pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
  3768. sas_phy_disconnected(sas_phy);
  3769. phy->phy_attached = 0;
  3770. sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
  3771. break;
  3772. case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
  3773. PM8001_MSG_DBG(pm8001_ha,
  3774. pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
  3775. pm8001_hw_event_ack_req(pm8001_ha, 0,
  3776. HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
  3777. port_id, phy_id, 0, 0);
  3778. sas_phy_disconnected(sas_phy);
  3779. phy->phy_attached = 0;
  3780. sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
  3781. break;
  3782. case HW_EVENT_PORT_RESET_TIMER_TMO:
  3783. PM8001_MSG_DBG(pm8001_ha,
  3784. pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
  3785. sas_phy_disconnected(sas_phy);
  3786. phy->phy_attached = 0;
  3787. sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
  3788. break;
  3789. case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
  3790. PM8001_MSG_DBG(pm8001_ha,
  3791. pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
  3792. sas_phy_disconnected(sas_phy);
  3793. phy->phy_attached = 0;
  3794. sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
  3795. break;
  3796. case HW_EVENT_PORT_RECOVER:
  3797. PM8001_MSG_DBG(pm8001_ha,
  3798. pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
  3799. break;
  3800. case HW_EVENT_PORT_RESET_COMPLETE:
  3801. PM8001_MSG_DBG(pm8001_ha,
  3802. pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
  3803. break;
  3804. case EVENT_BROADCAST_ASYNCH_EVENT:
  3805. PM8001_MSG_DBG(pm8001_ha,
  3806. pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
  3807. break;
  3808. default:
  3809. PM8001_MSG_DBG(pm8001_ha,
  3810. pm8001_printk("Unknown event type = %x\n", eventType));
  3811. break;
  3812. }
  3813. return 0;
  3814. }
  3815. /**
  3816. * process_one_iomb - process one outbound Queue memory block
  3817. * @pm8001_ha: our hba card information
  3818. * @piomb: IO message buffer
  3819. */
  3820. static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
  3821. {
  3822. __le32 pHeader = *(__le32 *)piomb;
  3823. u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
  3824. PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:"));
  3825. switch (opc) {
  3826. case OPC_OUB_ECHO:
  3827. PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
  3828. break;
  3829. case OPC_OUB_HW_EVENT:
  3830. PM8001_MSG_DBG(pm8001_ha,
  3831. pm8001_printk("OPC_OUB_HW_EVENT\n"));
  3832. mpi_hw_event(pm8001_ha, piomb);
  3833. break;
  3834. case OPC_OUB_SSP_COMP:
  3835. PM8001_MSG_DBG(pm8001_ha,
  3836. pm8001_printk("OPC_OUB_SSP_COMP\n"));
  3837. mpi_ssp_completion(pm8001_ha, piomb);
  3838. break;
  3839. case OPC_OUB_SMP_COMP:
  3840. PM8001_MSG_DBG(pm8001_ha,
  3841. pm8001_printk("OPC_OUB_SMP_COMP\n"));
  3842. mpi_smp_completion(pm8001_ha, piomb);
  3843. break;
  3844. case OPC_OUB_LOCAL_PHY_CNTRL:
  3845. PM8001_MSG_DBG(pm8001_ha,
  3846. pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
  3847. pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
  3848. break;
  3849. case OPC_OUB_DEV_REGIST:
  3850. PM8001_MSG_DBG(pm8001_ha,
  3851. pm8001_printk("OPC_OUB_DEV_REGIST\n"));
  3852. pm8001_mpi_reg_resp(pm8001_ha, piomb);
  3853. break;
  3854. case OPC_OUB_DEREG_DEV:
  3855. PM8001_MSG_DBG(pm8001_ha,
  3856. pm8001_printk("unregister the device\n"));
  3857. pm8001_mpi_dereg_resp(pm8001_ha, piomb);
  3858. break;
  3859. case OPC_OUB_GET_DEV_HANDLE:
  3860. PM8001_MSG_DBG(pm8001_ha,
  3861. pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
  3862. break;
  3863. case OPC_OUB_SATA_COMP:
  3864. PM8001_MSG_DBG(pm8001_ha,
  3865. pm8001_printk("OPC_OUB_SATA_COMP\n"));
  3866. mpi_sata_completion(pm8001_ha, piomb);
  3867. break;
  3868. case OPC_OUB_SATA_EVENT:
  3869. PM8001_MSG_DBG(pm8001_ha,
  3870. pm8001_printk("OPC_OUB_SATA_EVENT\n"));
  3871. mpi_sata_event(pm8001_ha, piomb);
  3872. break;
  3873. case OPC_OUB_SSP_EVENT:
  3874. PM8001_MSG_DBG(pm8001_ha,
  3875. pm8001_printk("OPC_OUB_SSP_EVENT\n"));
  3876. mpi_ssp_event(pm8001_ha, piomb);
  3877. break;
  3878. case OPC_OUB_DEV_HANDLE_ARRIV:
  3879. PM8001_MSG_DBG(pm8001_ha,
  3880. pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
  3881. /*This is for target*/
  3882. break;
  3883. case OPC_OUB_SSP_RECV_EVENT:
  3884. PM8001_MSG_DBG(pm8001_ha,
  3885. pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
  3886. /*This is for target*/
  3887. break;
  3888. case OPC_OUB_DEV_INFO:
  3889. PM8001_MSG_DBG(pm8001_ha,
  3890. pm8001_printk("OPC_OUB_DEV_INFO\n"));
  3891. break;
  3892. case OPC_OUB_FW_FLASH_UPDATE:
  3893. PM8001_MSG_DBG(pm8001_ha,
  3894. pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
  3895. pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
  3896. break;
  3897. case OPC_OUB_GPIO_RESPONSE:
  3898. PM8001_MSG_DBG(pm8001_ha,
  3899. pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
  3900. break;
  3901. case OPC_OUB_GPIO_EVENT:
  3902. PM8001_MSG_DBG(pm8001_ha,
  3903. pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
  3904. break;
  3905. case OPC_OUB_GENERAL_EVENT:
  3906. PM8001_MSG_DBG(pm8001_ha,
  3907. pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
  3908. pm8001_mpi_general_event(pm8001_ha, piomb);
  3909. break;
  3910. case OPC_OUB_SSP_ABORT_RSP:
  3911. PM8001_MSG_DBG(pm8001_ha,
  3912. pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
  3913. pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
  3914. break;
  3915. case OPC_OUB_SATA_ABORT_RSP:
  3916. PM8001_MSG_DBG(pm8001_ha,
  3917. pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
  3918. pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
  3919. break;
  3920. case OPC_OUB_SAS_DIAG_MODE_START_END:
  3921. PM8001_MSG_DBG(pm8001_ha,
  3922. pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
  3923. break;
  3924. case OPC_OUB_SAS_DIAG_EXECUTE:
  3925. PM8001_MSG_DBG(pm8001_ha,
  3926. pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
  3927. break;
  3928. case OPC_OUB_GET_TIME_STAMP:
  3929. PM8001_MSG_DBG(pm8001_ha,
  3930. pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
  3931. break;
  3932. case OPC_OUB_SAS_HW_EVENT_ACK:
  3933. PM8001_MSG_DBG(pm8001_ha,
  3934. pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
  3935. break;
  3936. case OPC_OUB_PORT_CONTROL:
  3937. PM8001_MSG_DBG(pm8001_ha,
  3938. pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
  3939. break;
  3940. case OPC_OUB_SMP_ABORT_RSP:
  3941. PM8001_MSG_DBG(pm8001_ha,
  3942. pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
  3943. pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
  3944. break;
  3945. case OPC_OUB_GET_NVMD_DATA:
  3946. PM8001_MSG_DBG(pm8001_ha,
  3947. pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
  3948. pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
  3949. break;
  3950. case OPC_OUB_SET_NVMD_DATA:
  3951. PM8001_MSG_DBG(pm8001_ha,
  3952. pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
  3953. pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
  3954. break;
  3955. case OPC_OUB_DEVICE_HANDLE_REMOVAL:
  3956. PM8001_MSG_DBG(pm8001_ha,
  3957. pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
  3958. break;
  3959. case OPC_OUB_SET_DEVICE_STATE:
  3960. PM8001_MSG_DBG(pm8001_ha,
  3961. pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
  3962. pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
  3963. break;
  3964. case OPC_OUB_GET_DEVICE_STATE:
  3965. PM8001_MSG_DBG(pm8001_ha,
  3966. pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
  3967. break;
  3968. case OPC_OUB_SET_DEV_INFO:
  3969. PM8001_MSG_DBG(pm8001_ha,
  3970. pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
  3971. break;
  3972. case OPC_OUB_SAS_RE_INITIALIZE:
  3973. PM8001_MSG_DBG(pm8001_ha,
  3974. pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n"));
  3975. break;
  3976. default:
  3977. PM8001_MSG_DBG(pm8001_ha,
  3978. pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n",
  3979. opc));
  3980. break;
  3981. }
  3982. }
  3983. static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
  3984. {
  3985. struct outbound_queue_table *circularQ;
  3986. void *pMsg1 = NULL;
  3987. u8 uninitialized_var(bc);
  3988. u32 ret = MPI_IO_STATUS_FAIL;
  3989. unsigned long flags;
  3990. spin_lock_irqsave(&pm8001_ha->lock, flags);
  3991. circularQ = &pm8001_ha->outbnd_q_tbl[vec];
  3992. do {
  3993. ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
  3994. if (MPI_IO_STATUS_SUCCESS == ret) {
  3995. /* process the outbound message */
  3996. process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
  3997. /* free the message from the outbound circular buffer */
  3998. pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
  3999. circularQ, bc);
  4000. }
  4001. if (MPI_IO_STATUS_BUSY == ret) {
  4002. /* Update the producer index from SPC */
  4003. circularQ->producer_index =
  4004. cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
  4005. if (le32_to_cpu(circularQ->producer_index) ==
  4006. circularQ->consumer_idx)
  4007. /* OQ is empty */
  4008. break;
  4009. }
  4010. } while (1);
  4011. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  4012. return ret;
  4013. }
  4014. /* PCI_DMA_... to our direction translation. */
  4015. static const u8 data_dir_flags[] = {
  4016. [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
  4017. [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */
  4018. [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */
  4019. [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */
  4020. };
  4021. void
  4022. pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
  4023. {
  4024. int i;
  4025. struct scatterlist *sg;
  4026. struct pm8001_prd *buf_prd = prd;
  4027. for_each_sg(scatter, sg, nr, i) {
  4028. buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
  4029. buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
  4030. buf_prd->im_len.e = 0;
  4031. buf_prd++;
  4032. }
  4033. }
  4034. static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd)
  4035. {
  4036. psmp_cmd->tag = hTag;
  4037. psmp_cmd->device_id = cpu_to_le32(deviceID);
  4038. psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
  4039. }
  4040. /**
  4041. * pm8001_chip_smp_req - send a SMP task to FW
  4042. * @pm8001_ha: our hba card information.
  4043. * @ccb: the ccb information this request used.
  4044. */
  4045. static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
  4046. struct pm8001_ccb_info *ccb)
  4047. {
  4048. int elem, rc;
  4049. struct sas_task *task = ccb->task;
  4050. struct domain_device *dev = task->dev;
  4051. struct pm8001_device *pm8001_dev = dev->lldd_dev;
  4052. struct scatterlist *sg_req, *sg_resp;
  4053. u32 req_len, resp_len;
  4054. struct smp_req smp_cmd;
  4055. u32 opc;
  4056. struct inbound_queue_table *circularQ;
  4057. memset(&smp_cmd, 0, sizeof(smp_cmd));
  4058. /*
  4059. * DMA-map SMP request, response buffers
  4060. */
  4061. sg_req = &task->smp_task.smp_req;
  4062. elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
  4063. if (!elem)
  4064. return -ENOMEM;
  4065. req_len = sg_dma_len(sg_req);
  4066. sg_resp = &task->smp_task.smp_resp;
  4067. elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
  4068. if (!elem) {
  4069. rc = -ENOMEM;
  4070. goto err_out;
  4071. }
  4072. resp_len = sg_dma_len(sg_resp);
  4073. /* must be in dwords */
  4074. if ((req_len & 0x3) || (resp_len & 0x3)) {
  4075. rc = -EINVAL;
  4076. goto err_out_2;
  4077. }
  4078. opc = OPC_INB_SMP_REQUEST;
  4079. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4080. smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
  4081. smp_cmd.long_smp_req.long_req_addr =
  4082. cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
  4083. smp_cmd.long_smp_req.long_req_size =
  4084. cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
  4085. smp_cmd.long_smp_req.long_resp_addr =
  4086. cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
  4087. smp_cmd.long_smp_req.long_resp_size =
  4088. cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
  4089. build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
  4090. pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd, 0);
  4091. return 0;
  4092. err_out_2:
  4093. dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
  4094. PCI_DMA_FROMDEVICE);
  4095. err_out:
  4096. dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
  4097. PCI_DMA_TODEVICE);
  4098. return rc;
  4099. }
  4100. /**
  4101. * pm8001_chip_ssp_io_req - send a SSP task to FW
  4102. * @pm8001_ha: our hba card information.
  4103. * @ccb: the ccb information this request used.
  4104. */
  4105. static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
  4106. struct pm8001_ccb_info *ccb)
  4107. {
  4108. struct sas_task *task = ccb->task;
  4109. struct domain_device *dev = task->dev;
  4110. struct pm8001_device *pm8001_dev = dev->lldd_dev;
  4111. struct ssp_ini_io_start_req ssp_cmd;
  4112. u32 tag = ccb->ccb_tag;
  4113. int ret;
  4114. u64 phys_addr;
  4115. struct inbound_queue_table *circularQ;
  4116. u32 opc = OPC_INB_SSPINIIOSTART;
  4117. memset(&ssp_cmd, 0, sizeof(ssp_cmd));
  4118. memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
  4119. ssp_cmd.dir_m_tlr =
  4120. cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
  4121. SAS 1.1 compatible TLR*/
  4122. ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
  4123. ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
  4124. ssp_cmd.tag = cpu_to_le32(tag);
  4125. if (task->ssp_task.enable_first_burst)
  4126. ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
  4127. ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
  4128. ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
  4129. memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
  4130. task->ssp_task.cmd->cmd_len);
  4131. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4132. /* fill in PRD (scatter/gather) table, if any */
  4133. if (task->num_scatter > 1) {
  4134. pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
  4135. phys_addr = ccb->ccb_dma_handle +
  4136. offsetof(struct pm8001_ccb_info, buf_prd[0]);
  4137. ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr));
  4138. ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr));
  4139. ssp_cmd.esgl = cpu_to_le32(1<<31);
  4140. } else if (task->num_scatter == 1) {
  4141. u64 dma_addr = sg_dma_address(task->scatter);
  4142. ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
  4143. ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr));
  4144. ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
  4145. ssp_cmd.esgl = 0;
  4146. } else if (task->num_scatter == 0) {
  4147. ssp_cmd.addr_low = 0;
  4148. ssp_cmd.addr_high = 0;
  4149. ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
  4150. ssp_cmd.esgl = 0;
  4151. }
  4152. ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd, 0);
  4153. return ret;
  4154. }
  4155. static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
  4156. struct pm8001_ccb_info *ccb)
  4157. {
  4158. struct sas_task *task = ccb->task;
  4159. struct domain_device *dev = task->dev;
  4160. struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
  4161. u32 tag = ccb->ccb_tag;
  4162. int ret;
  4163. struct sata_start_req sata_cmd;
  4164. u32 hdr_tag, ncg_tag = 0;
  4165. u64 phys_addr;
  4166. u32 ATAP = 0x0;
  4167. u32 dir;
  4168. struct inbound_queue_table *circularQ;
  4169. unsigned long flags;
  4170. u32 opc = OPC_INB_SATA_HOST_OPSTART;
  4171. memset(&sata_cmd, 0, sizeof(sata_cmd));
  4172. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4173. if (task->data_dir == PCI_DMA_NONE) {
  4174. ATAP = 0x04; /* no data*/
  4175. PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
  4176. } else if (likely(!task->ata_task.device_control_reg_update)) {
  4177. if (task->ata_task.dma_xfer) {
  4178. ATAP = 0x06; /* DMA */
  4179. PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
  4180. } else {
  4181. ATAP = 0x05; /* PIO*/
  4182. PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
  4183. }
  4184. if (task->ata_task.use_ncq &&
  4185. dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
  4186. ATAP = 0x07; /* FPDMA */
  4187. PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
  4188. }
  4189. }
  4190. if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
  4191. task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
  4192. ncg_tag = hdr_tag;
  4193. }
  4194. dir = data_dir_flags[task->data_dir] << 8;
  4195. sata_cmd.tag = cpu_to_le32(tag);
  4196. sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
  4197. sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
  4198. sata_cmd.ncqtag_atap_dir_m =
  4199. cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
  4200. sata_cmd.sata_fis = task->ata_task.fis;
  4201. if (likely(!task->ata_task.device_control_reg_update))
  4202. sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
  4203. sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
  4204. /* fill in PRD (scatter/gather) table, if any */
  4205. if (task->num_scatter > 1) {
  4206. pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
  4207. phys_addr = ccb->ccb_dma_handle +
  4208. offsetof(struct pm8001_ccb_info, buf_prd[0]);
  4209. sata_cmd.addr_low = lower_32_bits(phys_addr);
  4210. sata_cmd.addr_high = upper_32_bits(phys_addr);
  4211. sata_cmd.esgl = cpu_to_le32(1 << 31);
  4212. } else if (task->num_scatter == 1) {
  4213. u64 dma_addr = sg_dma_address(task->scatter);
  4214. sata_cmd.addr_low = lower_32_bits(dma_addr);
  4215. sata_cmd.addr_high = upper_32_bits(dma_addr);
  4216. sata_cmd.len = cpu_to_le32(task->total_xfer_len);
  4217. sata_cmd.esgl = 0;
  4218. } else if (task->num_scatter == 0) {
  4219. sata_cmd.addr_low = 0;
  4220. sata_cmd.addr_high = 0;
  4221. sata_cmd.len = cpu_to_le32(task->total_xfer_len);
  4222. sata_cmd.esgl = 0;
  4223. }
  4224. /* Check for read log for failed drive and return */
  4225. if (sata_cmd.sata_fis.command == 0x2f) {
  4226. if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
  4227. (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
  4228. (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
  4229. struct task_status_struct *ts;
  4230. pm8001_ha_dev->id &= 0xDFFFFFFF;
  4231. ts = &task->task_status;
  4232. spin_lock_irqsave(&task->task_state_lock, flags);
  4233. ts->resp = SAS_TASK_COMPLETE;
  4234. ts->stat = SAM_STAT_GOOD;
  4235. task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
  4236. task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
  4237. task->task_state_flags |= SAS_TASK_STATE_DONE;
  4238. if (unlikely((task->task_state_flags &
  4239. SAS_TASK_STATE_ABORTED))) {
  4240. spin_unlock_irqrestore(&task->task_state_lock,
  4241. flags);
  4242. PM8001_FAIL_DBG(pm8001_ha,
  4243. pm8001_printk("task 0x%p resp 0x%x "
  4244. " stat 0x%x but aborted by upper layer "
  4245. "\n", task, ts->resp, ts->stat));
  4246. pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
  4247. } else if (task->uldd_task) {
  4248. spin_unlock_irqrestore(&task->task_state_lock,
  4249. flags);
  4250. pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
  4251. mb();/* ditto */
  4252. spin_unlock_irq(&pm8001_ha->lock);
  4253. task->task_done(task);
  4254. spin_lock_irq(&pm8001_ha->lock);
  4255. return 0;
  4256. } else if (!task->uldd_task) {
  4257. spin_unlock_irqrestore(&task->task_state_lock,
  4258. flags);
  4259. pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
  4260. mb();/*ditto*/
  4261. spin_unlock_irq(&pm8001_ha->lock);
  4262. task->task_done(task);
  4263. spin_lock_irq(&pm8001_ha->lock);
  4264. return 0;
  4265. }
  4266. }
  4267. }
  4268. ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
  4269. return ret;
  4270. }
  4271. /**
  4272. * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
  4273. * @pm8001_ha: our hba card information.
  4274. * @num: the inbound queue number
  4275. * @phy_id: the phy id which we wanted to start up.
  4276. */
  4277. static int
  4278. pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
  4279. {
  4280. struct phy_start_req payload;
  4281. struct inbound_queue_table *circularQ;
  4282. int ret;
  4283. u32 tag = 0x01;
  4284. u32 opcode = OPC_INB_PHYSTART;
  4285. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4286. memset(&payload, 0, sizeof(payload));
  4287. payload.tag = cpu_to_le32(tag);
  4288. /*
  4289. ** [0:7] PHY Identifier
  4290. ** [8:11] link rate 1.5G, 3G, 6G
  4291. ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
  4292. ** [14] 0b disable spin up hold; 1b enable spin up hold
  4293. */
  4294. payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
  4295. LINKMODE_AUTO | LINKRATE_15 |
  4296. LINKRATE_30 | LINKRATE_60 | phy_id);
  4297. payload.sas_identify.dev_type = SAS_END_DEVICE;
  4298. payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
  4299. memcpy(payload.sas_identify.sas_addr,
  4300. pm8001_ha->sas_addr, SAS_ADDR_SIZE);
  4301. payload.sas_identify.phy_id = phy_id;
  4302. ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
  4303. return ret;
  4304. }
  4305. /**
  4306. * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
  4307. * @pm8001_ha: our hba card information.
  4308. * @num: the inbound queue number
  4309. * @phy_id: the phy id which we wanted to start up.
  4310. */
  4311. int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
  4312. u8 phy_id)
  4313. {
  4314. struct phy_stop_req payload;
  4315. struct inbound_queue_table *circularQ;
  4316. int ret;
  4317. u32 tag = 0x01;
  4318. u32 opcode = OPC_INB_PHYSTOP;
  4319. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4320. memset(&payload, 0, sizeof(payload));
  4321. payload.tag = cpu_to_le32(tag);
  4322. payload.phy_id = cpu_to_le32(phy_id);
  4323. ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
  4324. return ret;
  4325. }
  4326. /**
  4327. * see comments on pm8001_mpi_reg_resp.
  4328. */
  4329. static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
  4330. struct pm8001_device *pm8001_dev, u32 flag)
  4331. {
  4332. struct reg_dev_req payload;
  4333. u32 opc;
  4334. u32 stp_sspsmp_sata = 0x4;
  4335. struct inbound_queue_table *circularQ;
  4336. u32 linkrate, phy_id;
  4337. int rc, tag = 0xdeadbeef;
  4338. struct pm8001_ccb_info *ccb;
  4339. u8 retryFlag = 0x1;
  4340. u16 firstBurstSize = 0;
  4341. u16 ITNT = 2000;
  4342. struct domain_device *dev = pm8001_dev->sas_device;
  4343. struct domain_device *parent_dev = dev->parent;
  4344. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4345. memset(&payload, 0, sizeof(payload));
  4346. rc = pm8001_tag_alloc(pm8001_ha, &tag);
  4347. if (rc)
  4348. return rc;
  4349. ccb = &pm8001_ha->ccb_info[tag];
  4350. ccb->device = pm8001_dev;
  4351. ccb->ccb_tag = tag;
  4352. payload.tag = cpu_to_le32(tag);
  4353. if (flag == 1)
  4354. stp_sspsmp_sata = 0x02; /*direct attached sata */
  4355. else {
  4356. if (pm8001_dev->dev_type == SAS_SATA_DEV)
  4357. stp_sspsmp_sata = 0x00; /* stp*/
  4358. else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
  4359. pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
  4360. pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
  4361. stp_sspsmp_sata = 0x01; /*ssp or smp*/
  4362. }
  4363. if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
  4364. phy_id = parent_dev->ex_dev.ex_phy->phy_id;
  4365. else
  4366. phy_id = pm8001_dev->attached_phy;
  4367. opc = OPC_INB_REG_DEV;
  4368. linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
  4369. pm8001_dev->sas_device->linkrate : dev->port->linkrate;
  4370. payload.phyid_portid =
  4371. cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
  4372. ((phy_id & 0x0F) << 4));
  4373. payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
  4374. ((linkrate & 0x0F) * 0x1000000) |
  4375. ((stp_sspsmp_sata & 0x03) * 0x10000000));
  4376. payload.firstburstsize_ITNexustimeout =
  4377. cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
  4378. memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
  4379. SAS_ADDR_SIZE);
  4380. rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
  4381. return rc;
  4382. }
  4383. /**
  4384. * see comments on pm8001_mpi_reg_resp.
  4385. */
  4386. int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
  4387. u32 device_id)
  4388. {
  4389. struct dereg_dev_req payload;
  4390. u32 opc = OPC_INB_DEREG_DEV_HANDLE;
  4391. int ret;
  4392. struct inbound_queue_table *circularQ;
  4393. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4394. memset(&payload, 0, sizeof(payload));
  4395. payload.tag = cpu_to_le32(1);
  4396. payload.device_id = cpu_to_le32(device_id);
  4397. PM8001_MSG_DBG(pm8001_ha,
  4398. pm8001_printk("unregister device device_id = %d\n", device_id));
  4399. ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
  4400. return ret;
  4401. }
  4402. /**
  4403. * pm8001_chip_phy_ctl_req - support the local phy operation
  4404. * @pm8001_ha: our hba card information.
  4405. * @num: the inbound queue number
  4406. * @phy_id: the phy id which we wanted to operate
  4407. * @phy_op:
  4408. */
  4409. static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
  4410. u32 phyId, u32 phy_op)
  4411. {
  4412. struct local_phy_ctl_req payload;
  4413. struct inbound_queue_table *circularQ;
  4414. int ret;
  4415. u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
  4416. memset(&payload, 0, sizeof(payload));
  4417. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4418. payload.tag = cpu_to_le32(1);
  4419. payload.phyop_phyid =
  4420. cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
  4421. ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
  4422. return ret;
  4423. }
  4424. static u32 pm8001_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
  4425. {
  4426. u32 value;
  4427. #ifdef PM8001_USE_MSIX
  4428. return 1;
  4429. #endif
  4430. value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
  4431. if (value)
  4432. return 1;
  4433. return 0;
  4434. }
  4435. /**
  4436. * pm8001_chip_isr - PM8001 isr handler.
  4437. * @pm8001_ha: our hba card information.
  4438. * @irq: irq number.
  4439. * @stat: stat.
  4440. */
  4441. static irqreturn_t
  4442. pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
  4443. {
  4444. pm8001_chip_interrupt_disable(pm8001_ha, vec);
  4445. process_oq(pm8001_ha, vec);
  4446. pm8001_chip_interrupt_enable(pm8001_ha, vec);
  4447. return IRQ_HANDLED;
  4448. }
  4449. static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
  4450. u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
  4451. {
  4452. struct task_abort_req task_abort;
  4453. struct inbound_queue_table *circularQ;
  4454. int ret;
  4455. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4456. memset(&task_abort, 0, sizeof(task_abort));
  4457. if (ABORT_SINGLE == (flag & ABORT_MASK)) {
  4458. task_abort.abort_all = 0;
  4459. task_abort.device_id = cpu_to_le32(dev_id);
  4460. task_abort.tag_to_abort = cpu_to_le32(task_tag);
  4461. task_abort.tag = cpu_to_le32(cmd_tag);
  4462. } else if (ABORT_ALL == (flag & ABORT_MASK)) {
  4463. task_abort.abort_all = cpu_to_le32(1);
  4464. task_abort.device_id = cpu_to_le32(dev_id);
  4465. task_abort.tag = cpu_to_le32(cmd_tag);
  4466. }
  4467. ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
  4468. return ret;
  4469. }
  4470. /**
  4471. * pm8001_chip_abort_task - SAS abort task when error or exception happened.
  4472. * @task: the task we wanted to aborted.
  4473. * @flag: the abort flag.
  4474. */
  4475. int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
  4476. struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
  4477. {
  4478. u32 opc, device_id;
  4479. int rc = TMF_RESP_FUNC_FAILED;
  4480. PM8001_EH_DBG(pm8001_ha,
  4481. pm8001_printk("cmd_tag = %x, abort task tag = 0x%x",
  4482. cmd_tag, task_tag));
  4483. if (pm8001_dev->dev_type == SAS_END_DEVICE)
  4484. opc = OPC_INB_SSP_ABORT;
  4485. else if (pm8001_dev->dev_type == SAS_SATA_DEV)
  4486. opc = OPC_INB_SATA_ABORT;
  4487. else
  4488. opc = OPC_INB_SMP_ABORT;/* SMP */
  4489. device_id = pm8001_dev->device_id;
  4490. rc = send_task_abort(pm8001_ha, opc, device_id, flag,
  4491. task_tag, cmd_tag);
  4492. if (rc != TMF_RESP_FUNC_COMPLETE)
  4493. PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc));
  4494. return rc;
  4495. }
  4496. /**
  4497. * pm8001_chip_ssp_tm_req - built the task management command.
  4498. * @pm8001_ha: our hba card information.
  4499. * @ccb: the ccb information.
  4500. * @tmf: task management function.
  4501. */
  4502. int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
  4503. struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
  4504. {
  4505. struct sas_task *task = ccb->task;
  4506. struct domain_device *dev = task->dev;
  4507. struct pm8001_device *pm8001_dev = dev->lldd_dev;
  4508. u32 opc = OPC_INB_SSPINITMSTART;
  4509. struct inbound_queue_table *circularQ;
  4510. struct ssp_ini_tm_start_req sspTMCmd;
  4511. int ret;
  4512. memset(&sspTMCmd, 0, sizeof(sspTMCmd));
  4513. sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
  4514. sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
  4515. sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
  4516. memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
  4517. sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
  4518. if (pm8001_ha->chip_id != chip_8001)
  4519. sspTMCmd.ds_ads_m = 0x08;
  4520. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4521. ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd, 0);
  4522. return ret;
  4523. }
  4524. int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
  4525. void *payload)
  4526. {
  4527. u32 opc = OPC_INB_GET_NVMD_DATA;
  4528. u32 nvmd_type;
  4529. int rc;
  4530. u32 tag;
  4531. struct pm8001_ccb_info *ccb;
  4532. struct inbound_queue_table *circularQ;
  4533. struct get_nvm_data_req nvmd_req;
  4534. struct fw_control_ex *fw_control_context;
  4535. struct pm8001_ioctl_payload *ioctl_payload = payload;
  4536. nvmd_type = ioctl_payload->minor_function;
  4537. fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
  4538. if (!fw_control_context)
  4539. return -ENOMEM;
  4540. fw_control_context->usrAddr = (u8 *)ioctl_payload->func_specific;
  4541. fw_control_context->len = ioctl_payload->length;
  4542. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4543. memset(&nvmd_req, 0, sizeof(nvmd_req));
  4544. rc = pm8001_tag_alloc(pm8001_ha, &tag);
  4545. if (rc) {
  4546. kfree(fw_control_context);
  4547. return rc;
  4548. }
  4549. ccb = &pm8001_ha->ccb_info[tag];
  4550. ccb->ccb_tag = tag;
  4551. ccb->fw_control_context = fw_control_context;
  4552. nvmd_req.tag = cpu_to_le32(tag);
  4553. switch (nvmd_type) {
  4554. case TWI_DEVICE: {
  4555. u32 twi_addr, twi_page_size;
  4556. twi_addr = 0xa8;
  4557. twi_page_size = 2;
  4558. nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
  4559. twi_page_size << 8 | TWI_DEVICE);
  4560. nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
  4561. nvmd_req.resp_addr_hi =
  4562. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
  4563. nvmd_req.resp_addr_lo =
  4564. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
  4565. break;
  4566. }
  4567. case C_SEEPROM: {
  4568. nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
  4569. nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
  4570. nvmd_req.resp_addr_hi =
  4571. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
  4572. nvmd_req.resp_addr_lo =
  4573. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
  4574. break;
  4575. }
  4576. case VPD_FLASH: {
  4577. nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
  4578. nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
  4579. nvmd_req.resp_addr_hi =
  4580. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
  4581. nvmd_req.resp_addr_lo =
  4582. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
  4583. break;
  4584. }
  4585. case EXPAN_ROM: {
  4586. nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
  4587. nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
  4588. nvmd_req.resp_addr_hi =
  4589. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
  4590. nvmd_req.resp_addr_lo =
  4591. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
  4592. break;
  4593. }
  4594. case IOP_RDUMP: {
  4595. nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | IOP_RDUMP);
  4596. nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
  4597. nvmd_req.vpd_offset = cpu_to_le32(ioctl_payload->offset);
  4598. nvmd_req.resp_addr_hi =
  4599. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
  4600. nvmd_req.resp_addr_lo =
  4601. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
  4602. break;
  4603. }
  4604. default:
  4605. break;
  4606. }
  4607. rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 0);
  4608. return rc;
  4609. }
  4610. int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
  4611. void *payload)
  4612. {
  4613. u32 opc = OPC_INB_SET_NVMD_DATA;
  4614. u32 nvmd_type;
  4615. int rc;
  4616. u32 tag;
  4617. struct pm8001_ccb_info *ccb;
  4618. struct inbound_queue_table *circularQ;
  4619. struct set_nvm_data_req nvmd_req;
  4620. struct fw_control_ex *fw_control_context;
  4621. struct pm8001_ioctl_payload *ioctl_payload = payload;
  4622. nvmd_type = ioctl_payload->minor_function;
  4623. fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
  4624. if (!fw_control_context)
  4625. return -ENOMEM;
  4626. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4627. memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
  4628. &ioctl_payload->func_specific,
  4629. ioctl_payload->length);
  4630. memset(&nvmd_req, 0, sizeof(nvmd_req));
  4631. rc = pm8001_tag_alloc(pm8001_ha, &tag);
  4632. if (rc) {
  4633. kfree(fw_control_context);
  4634. return rc;
  4635. }
  4636. ccb = &pm8001_ha->ccb_info[tag];
  4637. ccb->fw_control_context = fw_control_context;
  4638. ccb->ccb_tag = tag;
  4639. nvmd_req.tag = cpu_to_le32(tag);
  4640. switch (nvmd_type) {
  4641. case TWI_DEVICE: {
  4642. u32 twi_addr, twi_page_size;
  4643. twi_addr = 0xa8;
  4644. twi_page_size = 2;
  4645. nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
  4646. nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
  4647. twi_page_size << 8 | TWI_DEVICE);
  4648. nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
  4649. nvmd_req.resp_addr_hi =
  4650. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
  4651. nvmd_req.resp_addr_lo =
  4652. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
  4653. break;
  4654. }
  4655. case C_SEEPROM:
  4656. nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
  4657. nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
  4658. nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
  4659. nvmd_req.resp_addr_hi =
  4660. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
  4661. nvmd_req.resp_addr_lo =
  4662. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
  4663. break;
  4664. case VPD_FLASH:
  4665. nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
  4666. nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
  4667. nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
  4668. nvmd_req.resp_addr_hi =
  4669. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
  4670. nvmd_req.resp_addr_lo =
  4671. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
  4672. break;
  4673. case EXPAN_ROM:
  4674. nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
  4675. nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
  4676. nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
  4677. nvmd_req.resp_addr_hi =
  4678. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
  4679. nvmd_req.resp_addr_lo =
  4680. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
  4681. break;
  4682. default:
  4683. break;
  4684. }
  4685. rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req, 0);
  4686. return rc;
  4687. }
  4688. /**
  4689. * pm8001_chip_fw_flash_update_build - support the firmware update operation
  4690. * @pm8001_ha: our hba card information.
  4691. * @fw_flash_updata_info: firmware flash update param
  4692. */
  4693. int
  4694. pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
  4695. void *fw_flash_updata_info, u32 tag)
  4696. {
  4697. struct fw_flash_Update_req payload;
  4698. struct fw_flash_updata_info *info;
  4699. struct inbound_queue_table *circularQ;
  4700. int ret;
  4701. u32 opc = OPC_INB_FW_FLASH_UPDATE;
  4702. memset(&payload, 0, sizeof(struct fw_flash_Update_req));
  4703. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4704. info = fw_flash_updata_info;
  4705. payload.tag = cpu_to_le32(tag);
  4706. payload.cur_image_len = cpu_to_le32(info->cur_image_len);
  4707. payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
  4708. payload.total_image_len = cpu_to_le32(info->total_image_len);
  4709. payload.len = info->sgl.im_len.len ;
  4710. payload.sgl_addr_lo =
  4711. cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr)));
  4712. payload.sgl_addr_hi =
  4713. cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr)));
  4714. ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
  4715. return ret;
  4716. }
  4717. int
  4718. pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
  4719. void *payload)
  4720. {
  4721. struct fw_flash_updata_info flash_update_info;
  4722. struct fw_control_info *fw_control;
  4723. struct fw_control_ex *fw_control_context;
  4724. int rc;
  4725. u32 tag;
  4726. struct pm8001_ccb_info *ccb;
  4727. void *buffer = pm8001_ha->memoryMap.region[FW_FLASH].virt_ptr;
  4728. dma_addr_t phys_addr = pm8001_ha->memoryMap.region[FW_FLASH].phys_addr;
  4729. struct pm8001_ioctl_payload *ioctl_payload = payload;
  4730. fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
  4731. if (!fw_control_context)
  4732. return -ENOMEM;
  4733. fw_control = (struct fw_control_info *)&ioctl_payload->func_specific;
  4734. memcpy(buffer, fw_control->buffer, fw_control->len);
  4735. flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
  4736. flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
  4737. flash_update_info.sgl.im_len.e = 0;
  4738. flash_update_info.cur_image_offset = fw_control->offset;
  4739. flash_update_info.cur_image_len = fw_control->len;
  4740. flash_update_info.total_image_len = fw_control->size;
  4741. fw_control_context->fw_control = fw_control;
  4742. fw_control_context->virtAddr = buffer;
  4743. fw_control_context->phys_addr = phys_addr;
  4744. fw_control_context->len = fw_control->len;
  4745. rc = pm8001_tag_alloc(pm8001_ha, &tag);
  4746. if (rc) {
  4747. kfree(fw_control_context);
  4748. return rc;
  4749. }
  4750. ccb = &pm8001_ha->ccb_info[tag];
  4751. ccb->fw_control_context = fw_control_context;
  4752. ccb->ccb_tag = tag;
  4753. rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
  4754. tag);
  4755. return rc;
  4756. }
  4757. ssize_t
  4758. pm8001_get_gsm_dump(struct device *cdev, u32 length, char *buf)
  4759. {
  4760. u32 value, rem, offset = 0, bar = 0;
  4761. u32 index, work_offset, dw_length;
  4762. u32 shift_value, gsm_base, gsm_dump_offset;
  4763. char *direct_data;
  4764. struct Scsi_Host *shost = class_to_shost(cdev);
  4765. struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  4766. struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
  4767. direct_data = buf;
  4768. gsm_dump_offset = pm8001_ha->fatal_forensic_shift_offset;
  4769. /* check max is 1 Mbytes */
  4770. if ((length > 0x100000) || (gsm_dump_offset & 3) ||
  4771. ((gsm_dump_offset + length) > 0x1000000))
  4772. return 1;
  4773. if (pm8001_ha->chip_id == chip_8001)
  4774. bar = 2;
  4775. else
  4776. bar = 1;
  4777. work_offset = gsm_dump_offset & 0xFFFF0000;
  4778. offset = gsm_dump_offset & 0x0000FFFF;
  4779. gsm_dump_offset = work_offset;
  4780. /* adjust length to dword boundary */
  4781. rem = length & 3;
  4782. dw_length = length >> 2;
  4783. for (index = 0; index < dw_length; index++) {
  4784. if ((work_offset + offset) & 0xFFFF0000) {
  4785. if (pm8001_ha->chip_id == chip_8001)
  4786. shift_value = ((gsm_dump_offset + offset) &
  4787. SHIFT_REG_64K_MASK);
  4788. else
  4789. shift_value = (((gsm_dump_offset + offset) &
  4790. SHIFT_REG_64K_MASK) >>
  4791. SHIFT_REG_BIT_SHIFT);
  4792. if (pm8001_ha->chip_id == chip_8001) {
  4793. gsm_base = GSM_BASE;
  4794. if (-1 == pm8001_bar4_shift(pm8001_ha,
  4795. (gsm_base + shift_value)))
  4796. return 1;
  4797. } else {
  4798. gsm_base = 0;
  4799. if (-1 == pm80xx_bar4_shift(pm8001_ha,
  4800. (gsm_base + shift_value)))
  4801. return 1;
  4802. }
  4803. gsm_dump_offset = (gsm_dump_offset + offset) &
  4804. 0xFFFF0000;
  4805. work_offset = 0;
  4806. offset = offset & 0x0000FFFF;
  4807. }
  4808. value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
  4809. 0x0000FFFF);
  4810. direct_data += sprintf(direct_data, "%08x ", value);
  4811. offset += 4;
  4812. }
  4813. if (rem != 0) {
  4814. value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
  4815. 0x0000FFFF);
  4816. /* xfr for non_dw */
  4817. direct_data += sprintf(direct_data, "%08x ", value);
  4818. }
  4819. /* Shift back to BAR4 original address */
  4820. if (pm8001_ha->chip_id == chip_8001) {
  4821. if (-1 == pm8001_bar4_shift(pm8001_ha, 0))
  4822. return 1;
  4823. } else {
  4824. if (-1 == pm80xx_bar4_shift(pm8001_ha, 0))
  4825. return 1;
  4826. }
  4827. pm8001_ha->fatal_forensic_shift_offset += 1024;
  4828. if (pm8001_ha->fatal_forensic_shift_offset >= 0x100000)
  4829. pm8001_ha->fatal_forensic_shift_offset = 0;
  4830. return direct_data - buf;
  4831. }
  4832. int
  4833. pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
  4834. struct pm8001_device *pm8001_dev, u32 state)
  4835. {
  4836. struct set_dev_state_req payload;
  4837. struct inbound_queue_table *circularQ;
  4838. struct pm8001_ccb_info *ccb;
  4839. int rc;
  4840. u32 tag;
  4841. u32 opc = OPC_INB_SET_DEVICE_STATE;
  4842. memset(&payload, 0, sizeof(payload));
  4843. rc = pm8001_tag_alloc(pm8001_ha, &tag);
  4844. if (rc)
  4845. return -1;
  4846. ccb = &pm8001_ha->ccb_info[tag];
  4847. ccb->ccb_tag = tag;
  4848. ccb->device = pm8001_dev;
  4849. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4850. payload.tag = cpu_to_le32(tag);
  4851. payload.device_id = cpu_to_le32(pm8001_dev->device_id);
  4852. payload.nds = cpu_to_le32(state);
  4853. rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
  4854. return rc;
  4855. }
  4856. static int
  4857. pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
  4858. {
  4859. struct sas_re_initialization_req payload;
  4860. struct inbound_queue_table *circularQ;
  4861. struct pm8001_ccb_info *ccb;
  4862. int rc;
  4863. u32 tag;
  4864. u32 opc = OPC_INB_SAS_RE_INITIALIZE;
  4865. memset(&payload, 0, sizeof(payload));
  4866. rc = pm8001_tag_alloc(pm8001_ha, &tag);
  4867. if (rc)
  4868. return -1;
  4869. ccb = &pm8001_ha->ccb_info[tag];
  4870. ccb->ccb_tag = tag;
  4871. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4872. payload.tag = cpu_to_le32(tag);
  4873. payload.SSAHOLT = cpu_to_le32(0xd << 25);
  4874. payload.sata_hol_tmo = cpu_to_le32(80);
  4875. payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
  4876. rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
  4877. return rc;
  4878. }
  4879. const struct pm8001_dispatch pm8001_8001_dispatch = {
  4880. .name = "pmc8001",
  4881. .chip_init = pm8001_chip_init,
  4882. .chip_soft_rst = pm8001_chip_soft_rst,
  4883. .chip_rst = pm8001_hw_chip_rst,
  4884. .chip_iounmap = pm8001_chip_iounmap,
  4885. .isr = pm8001_chip_isr,
  4886. .is_our_interupt = pm8001_chip_is_our_interupt,
  4887. .isr_process_oq = process_oq,
  4888. .interrupt_enable = pm8001_chip_interrupt_enable,
  4889. .interrupt_disable = pm8001_chip_interrupt_disable,
  4890. .make_prd = pm8001_chip_make_sg,
  4891. .smp_req = pm8001_chip_smp_req,
  4892. .ssp_io_req = pm8001_chip_ssp_io_req,
  4893. .sata_req = pm8001_chip_sata_req,
  4894. .phy_start_req = pm8001_chip_phy_start_req,
  4895. .phy_stop_req = pm8001_chip_phy_stop_req,
  4896. .reg_dev_req = pm8001_chip_reg_dev_req,
  4897. .dereg_dev_req = pm8001_chip_dereg_dev_req,
  4898. .phy_ctl_req = pm8001_chip_phy_ctl_req,
  4899. .task_abort = pm8001_chip_abort_task,
  4900. .ssp_tm_req = pm8001_chip_ssp_tm_req,
  4901. .get_nvmd_req = pm8001_chip_get_nvmd_req,
  4902. .set_nvmd_req = pm8001_chip_set_nvmd_req,
  4903. .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
  4904. .set_dev_state_req = pm8001_chip_set_dev_state_req,
  4905. .sas_re_init_req = pm8001_chip_sas_re_initialization,
  4906. };