mpt3sas_base.c 135 KB

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  1. /*
  2. * This is the Fusion MPT base driver providing common API layer interface
  3. * for access to MPT (Message Passing Technology) firmware.
  4. *
  5. * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c
  6. * Copyright (C) 2012-2013 LSI Corporation
  7. * (mailto:DL-MPTFusionLinux@lsi.com)
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * as published by the Free Software Foundation; either version 2
  12. * of the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * NO WARRANTY
  20. * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
  21. * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
  22. * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
  23. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
  24. * solely responsible for determining the appropriateness of using and
  25. * distributing the Program and assumes all risks associated with its
  26. * exercise of rights under this Agreement, including but not limited to
  27. * the risks and costs of program errors, damage to or loss of data,
  28. * programs or equipment, and unavailability or interruption of operations.
  29. * DISCLAIMER OF LIABILITY
  30. * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
  31. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32. * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
  33. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  34. * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  35. * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
  36. * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
  37. * You should have received a copy of the GNU General Public License
  38. * along with this program; if not, write to the Free Software
  39. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
  40. * USA.
  41. */
  42. #include <linux/kernel.h>
  43. #include <linux/module.h>
  44. #include <linux/errno.h>
  45. #include <linux/init.h>
  46. #include <linux/slab.h>
  47. #include <linux/types.h>
  48. #include <linux/pci.h>
  49. #include <linux/kdev_t.h>
  50. #include <linux/blkdev.h>
  51. #include <linux/delay.h>
  52. #include <linux/interrupt.h>
  53. #include <linux/dma-mapping.h>
  54. #include <linux/io.h>
  55. #include <linux/time.h>
  56. #include <linux/kthread.h>
  57. #include <linux/aer.h>
  58. #include "mpt3sas_base.h"
  59. static MPT_CALLBACK mpt_callbacks[MPT_MAX_CALLBACKS];
  60. #define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
  61. /* maximum controller queue depth */
  62. #define MAX_HBA_QUEUE_DEPTH 30000
  63. #define MAX_CHAIN_DEPTH 100000
  64. static int max_queue_depth = -1;
  65. module_param(max_queue_depth, int, 0);
  66. MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
  67. static int max_sgl_entries = -1;
  68. module_param(max_sgl_entries, int, 0);
  69. MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
  70. static int msix_disable = -1;
  71. module_param(msix_disable, int, 0);
  72. MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
  73. static int max_msix_vectors = 8;
  74. module_param(max_msix_vectors, int, 0);
  75. MODULE_PARM_DESC(max_msix_vectors,
  76. " max msix vectors - (default=8)");
  77. static int mpt3sas_fwfault_debug;
  78. MODULE_PARM_DESC(mpt3sas_fwfault_debug,
  79. " enable detection of firmware fault and halt firmware - (default=0)");
  80. /**
  81. * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
  82. *
  83. */
  84. static int
  85. _scsih_set_fwfault_debug(const char *val, struct kernel_param *kp)
  86. {
  87. int ret = param_set_int(val, kp);
  88. struct MPT3SAS_ADAPTER *ioc;
  89. if (ret)
  90. return ret;
  91. pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug);
  92. list_for_each_entry(ioc, &mpt3sas_ioc_list, list)
  93. ioc->fwfault_debug = mpt3sas_fwfault_debug;
  94. return 0;
  95. }
  96. module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
  97. param_get_int, &mpt3sas_fwfault_debug, 0644);
  98. /**
  99. * mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc
  100. * @arg: input argument, used to derive ioc
  101. *
  102. * Return 0 if controller is removed from pci subsystem.
  103. * Return -1 for other case.
  104. */
  105. static int mpt3sas_remove_dead_ioc_func(void *arg)
  106. {
  107. struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg;
  108. struct pci_dev *pdev;
  109. if ((ioc == NULL))
  110. return -1;
  111. pdev = ioc->pdev;
  112. if ((pdev == NULL))
  113. return -1;
  114. pci_stop_and_remove_bus_device(pdev);
  115. return 0;
  116. }
  117. /**
  118. * _base_fault_reset_work - workq handling ioc fault conditions
  119. * @work: input argument, used to derive ioc
  120. * Context: sleep.
  121. *
  122. * Return nothing.
  123. */
  124. static void
  125. _base_fault_reset_work(struct work_struct *work)
  126. {
  127. struct MPT3SAS_ADAPTER *ioc =
  128. container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work);
  129. unsigned long flags;
  130. u32 doorbell;
  131. int rc;
  132. struct task_struct *p;
  133. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  134. if (ioc->shost_recovery)
  135. goto rearm_timer;
  136. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  137. doorbell = mpt3sas_base_get_iocstate(ioc, 0);
  138. if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
  139. pr_err(MPT3SAS_FMT "SAS host is non-operational !!!!\n",
  140. ioc->name);
  141. /*
  142. * Call _scsih_flush_pending_cmds callback so that we flush all
  143. * pending commands back to OS. This call is required to aovid
  144. * deadlock at block layer. Dead IOC will fail to do diag reset,
  145. * and this call is safe since dead ioc will never return any
  146. * command back from HW.
  147. */
  148. ioc->schedule_dead_ioc_flush_running_cmds(ioc);
  149. /*
  150. * Set remove_host flag early since kernel thread will
  151. * take some time to execute.
  152. */
  153. ioc->remove_host = 1;
  154. /*Remove the Dead Host */
  155. p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
  156. "mpt3sas_dead_ioc_%d", ioc->id);
  157. if (IS_ERR(p))
  158. pr_err(MPT3SAS_FMT
  159. "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
  160. ioc->name, __func__);
  161. else
  162. pr_err(MPT3SAS_FMT
  163. "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
  164. ioc->name, __func__);
  165. return; /* don't rearm timer */
  166. }
  167. if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
  168. rc = mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
  169. FORCE_BIG_HAMMER);
  170. pr_warn(MPT3SAS_FMT "%s: hard reset: %s\n", ioc->name,
  171. __func__, (rc == 0) ? "success" : "failed");
  172. doorbell = mpt3sas_base_get_iocstate(ioc, 0);
  173. if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
  174. mpt3sas_base_fault_info(ioc, doorbell &
  175. MPI2_DOORBELL_DATA_MASK);
  176. if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
  177. MPI2_IOC_STATE_OPERATIONAL)
  178. return; /* don't rearm timer */
  179. }
  180. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  181. rearm_timer:
  182. if (ioc->fault_reset_work_q)
  183. queue_delayed_work(ioc->fault_reset_work_q,
  184. &ioc->fault_reset_work,
  185. msecs_to_jiffies(FAULT_POLLING_INTERVAL));
  186. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  187. }
  188. /**
  189. * mpt3sas_base_start_watchdog - start the fault_reset_work_q
  190. * @ioc: per adapter object
  191. * Context: sleep.
  192. *
  193. * Return nothing.
  194. */
  195. void
  196. mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc)
  197. {
  198. unsigned long flags;
  199. if (ioc->fault_reset_work_q)
  200. return;
  201. /* initialize fault polling */
  202. INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
  203. snprintf(ioc->fault_reset_work_q_name,
  204. sizeof(ioc->fault_reset_work_q_name), "poll_%d_status", ioc->id);
  205. ioc->fault_reset_work_q =
  206. create_singlethread_workqueue(ioc->fault_reset_work_q_name);
  207. if (!ioc->fault_reset_work_q) {
  208. pr_err(MPT3SAS_FMT "%s: failed (line=%d)\n",
  209. ioc->name, __func__, __LINE__);
  210. return;
  211. }
  212. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  213. if (ioc->fault_reset_work_q)
  214. queue_delayed_work(ioc->fault_reset_work_q,
  215. &ioc->fault_reset_work,
  216. msecs_to_jiffies(FAULT_POLLING_INTERVAL));
  217. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  218. }
  219. /**
  220. * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q
  221. * @ioc: per adapter object
  222. * Context: sleep.
  223. *
  224. * Return nothing.
  225. */
  226. void
  227. mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc)
  228. {
  229. unsigned long flags;
  230. struct workqueue_struct *wq;
  231. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  232. wq = ioc->fault_reset_work_q;
  233. ioc->fault_reset_work_q = NULL;
  234. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  235. if (wq) {
  236. if (!cancel_delayed_work(&ioc->fault_reset_work))
  237. flush_workqueue(wq);
  238. destroy_workqueue(wq);
  239. }
  240. }
  241. /**
  242. * mpt3sas_base_fault_info - verbose translation of firmware FAULT code
  243. * @ioc: per adapter object
  244. * @fault_code: fault code
  245. *
  246. * Return nothing.
  247. */
  248. void
  249. mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code)
  250. {
  251. pr_err(MPT3SAS_FMT "fault_state(0x%04x)!\n",
  252. ioc->name, fault_code);
  253. }
  254. /**
  255. * mpt3sas_halt_firmware - halt's mpt controller firmware
  256. * @ioc: per adapter object
  257. *
  258. * For debugging timeout related issues. Writing 0xCOFFEE00
  259. * to the doorbell register will halt controller firmware. With
  260. * the purpose to stop both driver and firmware, the enduser can
  261. * obtain a ring buffer from controller UART.
  262. */
  263. void
  264. mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc)
  265. {
  266. u32 doorbell;
  267. if (!ioc->fwfault_debug)
  268. return;
  269. dump_stack();
  270. doorbell = readl(&ioc->chip->Doorbell);
  271. if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
  272. mpt3sas_base_fault_info(ioc , doorbell);
  273. else {
  274. writel(0xC0FFEE00, &ioc->chip->Doorbell);
  275. pr_err(MPT3SAS_FMT "Firmware is halted due to command timeout\n",
  276. ioc->name);
  277. }
  278. if (ioc->fwfault_debug == 2)
  279. for (;;)
  280. ;
  281. else
  282. panic("panic in %s\n", __func__);
  283. }
  284. #ifdef CONFIG_SCSI_MPT3SAS_LOGGING
  285. /**
  286. * _base_sas_ioc_info - verbose translation of the ioc status
  287. * @ioc: per adapter object
  288. * @mpi_reply: reply mf payload returned from firmware
  289. * @request_hdr: request mf
  290. *
  291. * Return nothing.
  292. */
  293. static void
  294. _base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
  295. MPI2RequestHeader_t *request_hdr)
  296. {
  297. u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
  298. MPI2_IOCSTATUS_MASK;
  299. char *desc = NULL;
  300. u16 frame_sz;
  301. char *func_str = NULL;
  302. /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
  303. if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
  304. request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
  305. request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
  306. return;
  307. if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
  308. return;
  309. switch (ioc_status) {
  310. /****************************************************************************
  311. * Common IOCStatus values for all replies
  312. ****************************************************************************/
  313. case MPI2_IOCSTATUS_INVALID_FUNCTION:
  314. desc = "invalid function";
  315. break;
  316. case MPI2_IOCSTATUS_BUSY:
  317. desc = "busy";
  318. break;
  319. case MPI2_IOCSTATUS_INVALID_SGL:
  320. desc = "invalid sgl";
  321. break;
  322. case MPI2_IOCSTATUS_INTERNAL_ERROR:
  323. desc = "internal error";
  324. break;
  325. case MPI2_IOCSTATUS_INVALID_VPID:
  326. desc = "invalid vpid";
  327. break;
  328. case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
  329. desc = "insufficient resources";
  330. break;
  331. case MPI2_IOCSTATUS_INVALID_FIELD:
  332. desc = "invalid field";
  333. break;
  334. case MPI2_IOCSTATUS_INVALID_STATE:
  335. desc = "invalid state";
  336. break;
  337. case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
  338. desc = "op state not supported";
  339. break;
  340. /****************************************************************************
  341. * Config IOCStatus values
  342. ****************************************************************************/
  343. case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
  344. desc = "config invalid action";
  345. break;
  346. case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
  347. desc = "config invalid type";
  348. break;
  349. case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
  350. desc = "config invalid page";
  351. break;
  352. case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
  353. desc = "config invalid data";
  354. break;
  355. case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
  356. desc = "config no defaults";
  357. break;
  358. case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
  359. desc = "config cant commit";
  360. break;
  361. /****************************************************************************
  362. * SCSI IO Reply
  363. ****************************************************************************/
  364. case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
  365. case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
  366. case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
  367. case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
  368. case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
  369. case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
  370. case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
  371. case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
  372. case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
  373. case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
  374. case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
  375. case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
  376. break;
  377. /****************************************************************************
  378. * For use by SCSI Initiator and SCSI Target end-to-end data protection
  379. ****************************************************************************/
  380. case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
  381. desc = "eedp guard error";
  382. break;
  383. case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
  384. desc = "eedp ref tag error";
  385. break;
  386. case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
  387. desc = "eedp app tag error";
  388. break;
  389. /****************************************************************************
  390. * SCSI Target values
  391. ****************************************************************************/
  392. case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
  393. desc = "target invalid io index";
  394. break;
  395. case MPI2_IOCSTATUS_TARGET_ABORTED:
  396. desc = "target aborted";
  397. break;
  398. case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
  399. desc = "target no conn retryable";
  400. break;
  401. case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
  402. desc = "target no connection";
  403. break;
  404. case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
  405. desc = "target xfer count mismatch";
  406. break;
  407. case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
  408. desc = "target data offset error";
  409. break;
  410. case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
  411. desc = "target too much write data";
  412. break;
  413. case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
  414. desc = "target iu too short";
  415. break;
  416. case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
  417. desc = "target ack nak timeout";
  418. break;
  419. case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
  420. desc = "target nak received";
  421. break;
  422. /****************************************************************************
  423. * Serial Attached SCSI values
  424. ****************************************************************************/
  425. case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
  426. desc = "smp request failed";
  427. break;
  428. case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
  429. desc = "smp data overrun";
  430. break;
  431. /****************************************************************************
  432. * Diagnostic Buffer Post / Diagnostic Release values
  433. ****************************************************************************/
  434. case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
  435. desc = "diagnostic released";
  436. break;
  437. default:
  438. break;
  439. }
  440. if (!desc)
  441. return;
  442. switch (request_hdr->Function) {
  443. case MPI2_FUNCTION_CONFIG:
  444. frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
  445. func_str = "config_page";
  446. break;
  447. case MPI2_FUNCTION_SCSI_TASK_MGMT:
  448. frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
  449. func_str = "task_mgmt";
  450. break;
  451. case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
  452. frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
  453. func_str = "sas_iounit_ctl";
  454. break;
  455. case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
  456. frame_sz = sizeof(Mpi2SepRequest_t);
  457. func_str = "enclosure";
  458. break;
  459. case MPI2_FUNCTION_IOC_INIT:
  460. frame_sz = sizeof(Mpi2IOCInitRequest_t);
  461. func_str = "ioc_init";
  462. break;
  463. case MPI2_FUNCTION_PORT_ENABLE:
  464. frame_sz = sizeof(Mpi2PortEnableRequest_t);
  465. func_str = "port_enable";
  466. break;
  467. case MPI2_FUNCTION_SMP_PASSTHROUGH:
  468. frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
  469. func_str = "smp_passthru";
  470. break;
  471. default:
  472. frame_sz = 32;
  473. func_str = "unknown";
  474. break;
  475. }
  476. pr_warn(MPT3SAS_FMT "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
  477. ioc->name, desc, ioc_status, request_hdr, func_str);
  478. _debug_dump_mf(request_hdr, frame_sz/4);
  479. }
  480. /**
  481. * _base_display_event_data - verbose translation of firmware asyn events
  482. * @ioc: per adapter object
  483. * @mpi_reply: reply mf payload returned from firmware
  484. *
  485. * Return nothing.
  486. */
  487. static void
  488. _base_display_event_data(struct MPT3SAS_ADAPTER *ioc,
  489. Mpi2EventNotificationReply_t *mpi_reply)
  490. {
  491. char *desc = NULL;
  492. u16 event;
  493. if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
  494. return;
  495. event = le16_to_cpu(mpi_reply->Event);
  496. switch (event) {
  497. case MPI2_EVENT_LOG_DATA:
  498. desc = "Log Data";
  499. break;
  500. case MPI2_EVENT_STATE_CHANGE:
  501. desc = "Status Change";
  502. break;
  503. case MPI2_EVENT_HARD_RESET_RECEIVED:
  504. desc = "Hard Reset Received";
  505. break;
  506. case MPI2_EVENT_EVENT_CHANGE:
  507. desc = "Event Change";
  508. break;
  509. case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
  510. desc = "Device Status Change";
  511. break;
  512. case MPI2_EVENT_IR_OPERATION_STATUS:
  513. desc = "IR Operation Status";
  514. break;
  515. case MPI2_EVENT_SAS_DISCOVERY:
  516. {
  517. Mpi2EventDataSasDiscovery_t *event_data =
  518. (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
  519. pr_info(MPT3SAS_FMT "Discovery: (%s)", ioc->name,
  520. (event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED) ?
  521. "start" : "stop");
  522. if (event_data->DiscoveryStatus)
  523. pr_info("discovery_status(0x%08x)",
  524. le32_to_cpu(event_data->DiscoveryStatus));
  525. pr_info("\n");
  526. return;
  527. }
  528. case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
  529. desc = "SAS Broadcast Primitive";
  530. break;
  531. case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
  532. desc = "SAS Init Device Status Change";
  533. break;
  534. case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
  535. desc = "SAS Init Table Overflow";
  536. break;
  537. case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
  538. desc = "SAS Topology Change List";
  539. break;
  540. case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
  541. desc = "SAS Enclosure Device Status Change";
  542. break;
  543. case MPI2_EVENT_IR_VOLUME:
  544. desc = "IR Volume";
  545. break;
  546. case MPI2_EVENT_IR_PHYSICAL_DISK:
  547. desc = "IR Physical Disk";
  548. break;
  549. case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
  550. desc = "IR Configuration Change List";
  551. break;
  552. case MPI2_EVENT_LOG_ENTRY_ADDED:
  553. desc = "Log Entry Added";
  554. break;
  555. }
  556. if (!desc)
  557. return;
  558. pr_info(MPT3SAS_FMT "%s\n", ioc->name, desc);
  559. }
  560. #endif
  561. /**
  562. * _base_sas_log_info - verbose translation of firmware log info
  563. * @ioc: per adapter object
  564. * @log_info: log info
  565. *
  566. * Return nothing.
  567. */
  568. static void
  569. _base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info)
  570. {
  571. union loginfo_type {
  572. u32 loginfo;
  573. struct {
  574. u32 subcode:16;
  575. u32 code:8;
  576. u32 originator:4;
  577. u32 bus_type:4;
  578. } dw;
  579. };
  580. union loginfo_type sas_loginfo;
  581. char *originator_str = NULL;
  582. sas_loginfo.loginfo = log_info;
  583. if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
  584. return;
  585. /* each nexus loss loginfo */
  586. if (log_info == 0x31170000)
  587. return;
  588. /* eat the loginfos associated with task aborts */
  589. if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info ==
  590. 0x31140000 || log_info == 0x31130000))
  591. return;
  592. switch (sas_loginfo.dw.originator) {
  593. case 0:
  594. originator_str = "IOP";
  595. break;
  596. case 1:
  597. originator_str = "PL";
  598. break;
  599. case 2:
  600. originator_str = "IR";
  601. break;
  602. }
  603. pr_warn(MPT3SAS_FMT
  604. "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
  605. ioc->name, log_info,
  606. originator_str, sas_loginfo.dw.code,
  607. sas_loginfo.dw.subcode);
  608. }
  609. /**
  610. * _base_display_reply_info -
  611. * @ioc: per adapter object
  612. * @smid: system request message index
  613. * @msix_index: MSIX table index supplied by the OS
  614. * @reply: reply message frame(lower 32bit addr)
  615. *
  616. * Return nothing.
  617. */
  618. static void
  619. _base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
  620. u32 reply)
  621. {
  622. MPI2DefaultReply_t *mpi_reply;
  623. u16 ioc_status;
  624. u32 loginfo = 0;
  625. mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
  626. if (unlikely(!mpi_reply)) {
  627. pr_err(MPT3SAS_FMT "mpi_reply not valid at %s:%d/%s()!\n",
  628. ioc->name, __FILE__, __LINE__, __func__);
  629. return;
  630. }
  631. ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
  632. #ifdef CONFIG_SCSI_MPT3SAS_LOGGING
  633. if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
  634. (ioc->logging_level & MPT_DEBUG_REPLY)) {
  635. _base_sas_ioc_info(ioc , mpi_reply,
  636. mpt3sas_base_get_msg_frame(ioc, smid));
  637. }
  638. #endif
  639. if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
  640. loginfo = le32_to_cpu(mpi_reply->IOCLogInfo);
  641. _base_sas_log_info(ioc, loginfo);
  642. }
  643. if (ioc_status || loginfo) {
  644. ioc_status &= MPI2_IOCSTATUS_MASK;
  645. mpt3sas_trigger_mpi(ioc, ioc_status, loginfo);
  646. }
  647. }
  648. /**
  649. * mpt3sas_base_done - base internal command completion routine
  650. * @ioc: per adapter object
  651. * @smid: system request message index
  652. * @msix_index: MSIX table index supplied by the OS
  653. * @reply: reply message frame(lower 32bit addr)
  654. *
  655. * Return 1 meaning mf should be freed from _base_interrupt
  656. * 0 means the mf is freed from this function.
  657. */
  658. u8
  659. mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
  660. u32 reply)
  661. {
  662. MPI2DefaultReply_t *mpi_reply;
  663. mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
  664. if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
  665. return 1;
  666. if (ioc->base_cmds.status == MPT3_CMD_NOT_USED)
  667. return 1;
  668. ioc->base_cmds.status |= MPT3_CMD_COMPLETE;
  669. if (mpi_reply) {
  670. ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID;
  671. memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
  672. }
  673. ioc->base_cmds.status &= ~MPT3_CMD_PENDING;
  674. complete(&ioc->base_cmds.done);
  675. return 1;
  676. }
  677. /**
  678. * _base_async_event - main callback handler for firmware asyn events
  679. * @ioc: per adapter object
  680. * @msix_index: MSIX table index supplied by the OS
  681. * @reply: reply message frame(lower 32bit addr)
  682. *
  683. * Return 1 meaning mf should be freed from _base_interrupt
  684. * 0 means the mf is freed from this function.
  685. */
  686. static u8
  687. _base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
  688. {
  689. Mpi2EventNotificationReply_t *mpi_reply;
  690. Mpi2EventAckRequest_t *ack_request;
  691. u16 smid;
  692. mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
  693. if (!mpi_reply)
  694. return 1;
  695. if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
  696. return 1;
  697. #ifdef CONFIG_SCSI_MPT3SAS_LOGGING
  698. _base_display_event_data(ioc, mpi_reply);
  699. #endif
  700. if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
  701. goto out;
  702. smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
  703. if (!smid) {
  704. pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
  705. ioc->name, __func__);
  706. goto out;
  707. }
  708. ack_request = mpt3sas_base_get_msg_frame(ioc, smid);
  709. memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
  710. ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
  711. ack_request->Event = mpi_reply->Event;
  712. ack_request->EventContext = mpi_reply->EventContext;
  713. ack_request->VF_ID = 0; /* TODO */
  714. ack_request->VP_ID = 0;
  715. mpt3sas_base_put_smid_default(ioc, smid);
  716. out:
  717. /* scsih callback handler */
  718. mpt3sas_scsih_event_callback(ioc, msix_index, reply);
  719. /* ctl callback handler */
  720. mpt3sas_ctl_event_callback(ioc, msix_index, reply);
  721. return 1;
  722. }
  723. /**
  724. * _base_get_cb_idx - obtain the callback index
  725. * @ioc: per adapter object
  726. * @smid: system request message index
  727. *
  728. * Return callback index.
  729. */
  730. static u8
  731. _base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid)
  732. {
  733. int i;
  734. u8 cb_idx;
  735. if (smid < ioc->hi_priority_smid) {
  736. i = smid - 1;
  737. cb_idx = ioc->scsi_lookup[i].cb_idx;
  738. } else if (smid < ioc->internal_smid) {
  739. i = smid - ioc->hi_priority_smid;
  740. cb_idx = ioc->hpr_lookup[i].cb_idx;
  741. } else if (smid <= ioc->hba_queue_depth) {
  742. i = smid - ioc->internal_smid;
  743. cb_idx = ioc->internal_lookup[i].cb_idx;
  744. } else
  745. cb_idx = 0xFF;
  746. return cb_idx;
  747. }
  748. /**
  749. * _base_mask_interrupts - disable interrupts
  750. * @ioc: per adapter object
  751. *
  752. * Disabling ResetIRQ, Reply and Doorbell Interrupts
  753. *
  754. * Return nothing.
  755. */
  756. static void
  757. _base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
  758. {
  759. u32 him_register;
  760. ioc->mask_interrupts = 1;
  761. him_register = readl(&ioc->chip->HostInterruptMask);
  762. him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
  763. writel(him_register, &ioc->chip->HostInterruptMask);
  764. readl(&ioc->chip->HostInterruptMask);
  765. }
  766. /**
  767. * _base_unmask_interrupts - enable interrupts
  768. * @ioc: per adapter object
  769. *
  770. * Enabling only Reply Interrupts
  771. *
  772. * Return nothing.
  773. */
  774. static void
  775. _base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
  776. {
  777. u32 him_register;
  778. him_register = readl(&ioc->chip->HostInterruptMask);
  779. him_register &= ~MPI2_HIM_RIM;
  780. writel(him_register, &ioc->chip->HostInterruptMask);
  781. ioc->mask_interrupts = 0;
  782. }
  783. union reply_descriptor {
  784. u64 word;
  785. struct {
  786. u32 low;
  787. u32 high;
  788. } u;
  789. };
  790. /**
  791. * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
  792. * @irq: irq number (not used)
  793. * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
  794. * @r: pt_regs pointer (not used)
  795. *
  796. * Return IRQ_HANDLE if processed, else IRQ_NONE.
  797. */
  798. static irqreturn_t
  799. _base_interrupt(int irq, void *bus_id)
  800. {
  801. struct adapter_reply_queue *reply_q = bus_id;
  802. union reply_descriptor rd;
  803. u32 completed_cmds;
  804. u8 request_desript_type;
  805. u16 smid;
  806. u8 cb_idx;
  807. u32 reply;
  808. u8 msix_index = reply_q->msix_index;
  809. struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
  810. Mpi2ReplyDescriptorsUnion_t *rpf;
  811. u8 rc;
  812. if (ioc->mask_interrupts)
  813. return IRQ_NONE;
  814. if (!atomic_add_unless(&reply_q->busy, 1, 1))
  815. return IRQ_NONE;
  816. rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
  817. request_desript_type = rpf->Default.ReplyFlags
  818. & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
  819. if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
  820. atomic_dec(&reply_q->busy);
  821. return IRQ_NONE;
  822. }
  823. completed_cmds = 0;
  824. cb_idx = 0xFF;
  825. do {
  826. rd.word = le64_to_cpu(rpf->Words);
  827. if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
  828. goto out;
  829. reply = 0;
  830. smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
  831. if (request_desript_type ==
  832. MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS ||
  833. request_desript_type ==
  834. MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) {
  835. cb_idx = _base_get_cb_idx(ioc, smid);
  836. if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
  837. (likely(mpt_callbacks[cb_idx] != NULL))) {
  838. rc = mpt_callbacks[cb_idx](ioc, smid,
  839. msix_index, 0);
  840. if (rc)
  841. mpt3sas_base_free_smid(ioc, smid);
  842. }
  843. } else if (request_desript_type ==
  844. MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
  845. reply = le32_to_cpu(
  846. rpf->AddressReply.ReplyFrameAddress);
  847. if (reply > ioc->reply_dma_max_address ||
  848. reply < ioc->reply_dma_min_address)
  849. reply = 0;
  850. if (smid) {
  851. cb_idx = _base_get_cb_idx(ioc, smid);
  852. if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
  853. (likely(mpt_callbacks[cb_idx] != NULL))) {
  854. rc = mpt_callbacks[cb_idx](ioc, smid,
  855. msix_index, reply);
  856. if (reply)
  857. _base_display_reply_info(ioc,
  858. smid, msix_index, reply);
  859. if (rc)
  860. mpt3sas_base_free_smid(ioc,
  861. smid);
  862. }
  863. } else {
  864. _base_async_event(ioc, msix_index, reply);
  865. }
  866. /* reply free queue handling */
  867. if (reply) {
  868. ioc->reply_free_host_index =
  869. (ioc->reply_free_host_index ==
  870. (ioc->reply_free_queue_depth - 1)) ?
  871. 0 : ioc->reply_free_host_index + 1;
  872. ioc->reply_free[ioc->reply_free_host_index] =
  873. cpu_to_le32(reply);
  874. wmb();
  875. writel(ioc->reply_free_host_index,
  876. &ioc->chip->ReplyFreeHostIndex);
  877. }
  878. }
  879. rpf->Words = cpu_to_le64(ULLONG_MAX);
  880. reply_q->reply_post_host_index =
  881. (reply_q->reply_post_host_index ==
  882. (ioc->reply_post_queue_depth - 1)) ? 0 :
  883. reply_q->reply_post_host_index + 1;
  884. request_desript_type =
  885. reply_q->reply_post_free[reply_q->reply_post_host_index].
  886. Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
  887. completed_cmds++;
  888. if (request_desript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
  889. goto out;
  890. if (!reply_q->reply_post_host_index)
  891. rpf = reply_q->reply_post_free;
  892. else
  893. rpf++;
  894. } while (1);
  895. out:
  896. if (!completed_cmds) {
  897. atomic_dec(&reply_q->busy);
  898. return IRQ_NONE;
  899. }
  900. wmb();
  901. writel(reply_q->reply_post_host_index | (msix_index <<
  902. MPI2_RPHI_MSIX_INDEX_SHIFT), &ioc->chip->ReplyPostHostIndex);
  903. atomic_dec(&reply_q->busy);
  904. return IRQ_HANDLED;
  905. }
  906. /**
  907. * _base_is_controller_msix_enabled - is controller support muli-reply queues
  908. * @ioc: per adapter object
  909. *
  910. */
  911. static inline int
  912. _base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc)
  913. {
  914. return (ioc->facts.IOCCapabilities &
  915. MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
  916. }
  917. /**
  918. * mpt3sas_base_flush_reply_queues - flushing the MSIX reply queues
  919. * @ioc: per adapter object
  920. * Context: ISR conext
  921. *
  922. * Called when a Task Management request has completed. We want
  923. * to flush the other reply queues so all the outstanding IO has been
  924. * completed back to OS before we process the TM completetion.
  925. *
  926. * Return nothing.
  927. */
  928. void
  929. mpt3sas_base_flush_reply_queues(struct MPT3SAS_ADAPTER *ioc)
  930. {
  931. struct adapter_reply_queue *reply_q;
  932. /* If MSIX capability is turned off
  933. * then multi-queues are not enabled
  934. */
  935. if (!_base_is_controller_msix_enabled(ioc))
  936. return;
  937. list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
  938. if (ioc->shost_recovery)
  939. return;
  940. /* TMs are on msix_index == 0 */
  941. if (reply_q->msix_index == 0)
  942. continue;
  943. _base_interrupt(reply_q->vector, (void *)reply_q);
  944. }
  945. }
  946. /**
  947. * mpt3sas_base_release_callback_handler - clear interrupt callback handler
  948. * @cb_idx: callback index
  949. *
  950. * Return nothing.
  951. */
  952. void
  953. mpt3sas_base_release_callback_handler(u8 cb_idx)
  954. {
  955. mpt_callbacks[cb_idx] = NULL;
  956. }
  957. /**
  958. * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler
  959. * @cb_func: callback function
  960. *
  961. * Returns cb_func.
  962. */
  963. u8
  964. mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func)
  965. {
  966. u8 cb_idx;
  967. for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
  968. if (mpt_callbacks[cb_idx] == NULL)
  969. break;
  970. mpt_callbacks[cb_idx] = cb_func;
  971. return cb_idx;
  972. }
  973. /**
  974. * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler
  975. *
  976. * Return nothing.
  977. */
  978. void
  979. mpt3sas_base_initialize_callback_handler(void)
  980. {
  981. u8 cb_idx;
  982. for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
  983. mpt3sas_base_release_callback_handler(cb_idx);
  984. }
  985. /**
  986. * _base_build_zero_len_sge - build zero length sg entry
  987. * @ioc: per adapter object
  988. * @paddr: virtual address for SGE
  989. *
  990. * Create a zero length scatter gather entry to insure the IOCs hardware has
  991. * something to use if the target device goes brain dead and tries
  992. * to send data even when none is asked for.
  993. *
  994. * Return nothing.
  995. */
  996. static void
  997. _base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr)
  998. {
  999. u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
  1000. MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
  1001. MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
  1002. MPI2_SGE_FLAGS_SHIFT);
  1003. ioc->base_add_sg_single(paddr, flags_length, -1);
  1004. }
  1005. /**
  1006. * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
  1007. * @paddr: virtual address for SGE
  1008. * @flags_length: SGE flags and data transfer length
  1009. * @dma_addr: Physical address
  1010. *
  1011. * Return nothing.
  1012. */
  1013. static void
  1014. _base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
  1015. {
  1016. Mpi2SGESimple32_t *sgel = paddr;
  1017. flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
  1018. MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
  1019. sgel->FlagsLength = cpu_to_le32(flags_length);
  1020. sgel->Address = cpu_to_le32(dma_addr);
  1021. }
  1022. /**
  1023. * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
  1024. * @paddr: virtual address for SGE
  1025. * @flags_length: SGE flags and data transfer length
  1026. * @dma_addr: Physical address
  1027. *
  1028. * Return nothing.
  1029. */
  1030. static void
  1031. _base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
  1032. {
  1033. Mpi2SGESimple64_t *sgel = paddr;
  1034. flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
  1035. MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
  1036. sgel->FlagsLength = cpu_to_le32(flags_length);
  1037. sgel->Address = cpu_to_le64(dma_addr);
  1038. }
  1039. /**
  1040. * _base_get_chain_buffer_tracker - obtain chain tracker
  1041. * @ioc: per adapter object
  1042. * @smid: smid associated to an IO request
  1043. *
  1044. * Returns chain tracker(from ioc->free_chain_list)
  1045. */
  1046. static struct chain_tracker *
  1047. _base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc, u16 smid)
  1048. {
  1049. struct chain_tracker *chain_req;
  1050. unsigned long flags;
  1051. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1052. if (list_empty(&ioc->free_chain_list)) {
  1053. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1054. dfailprintk(ioc, pr_warn(MPT3SAS_FMT
  1055. "chain buffers not available\n", ioc->name));
  1056. return NULL;
  1057. }
  1058. chain_req = list_entry(ioc->free_chain_list.next,
  1059. struct chain_tracker, tracker_list);
  1060. list_del_init(&chain_req->tracker_list);
  1061. list_add_tail(&chain_req->tracker_list,
  1062. &ioc->scsi_lookup[smid - 1].chain_list);
  1063. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1064. return chain_req;
  1065. }
  1066. /**
  1067. * _base_build_sg - build generic sg
  1068. * @ioc: per adapter object
  1069. * @psge: virtual address for SGE
  1070. * @data_out_dma: physical address for WRITES
  1071. * @data_out_sz: data xfer size for WRITES
  1072. * @data_in_dma: physical address for READS
  1073. * @data_in_sz: data xfer size for READS
  1074. *
  1075. * Return nothing.
  1076. */
  1077. static void
  1078. _base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge,
  1079. dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
  1080. size_t data_in_sz)
  1081. {
  1082. u32 sgl_flags;
  1083. if (!data_out_sz && !data_in_sz) {
  1084. _base_build_zero_len_sge(ioc, psge);
  1085. return;
  1086. }
  1087. if (data_out_sz && data_in_sz) {
  1088. /* WRITE sgel first */
  1089. sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
  1090. MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC);
  1091. sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
  1092. ioc->base_add_sg_single(psge, sgl_flags |
  1093. data_out_sz, data_out_dma);
  1094. /* incr sgel */
  1095. psge += ioc->sge_size;
  1096. /* READ sgel last */
  1097. sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
  1098. MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
  1099. MPI2_SGE_FLAGS_END_OF_LIST);
  1100. sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
  1101. ioc->base_add_sg_single(psge, sgl_flags |
  1102. data_in_sz, data_in_dma);
  1103. } else if (data_out_sz) /* WRITE */ {
  1104. sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
  1105. MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
  1106. MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC);
  1107. sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
  1108. ioc->base_add_sg_single(psge, sgl_flags |
  1109. data_out_sz, data_out_dma);
  1110. } else if (data_in_sz) /* READ */ {
  1111. sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
  1112. MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
  1113. MPI2_SGE_FLAGS_END_OF_LIST);
  1114. sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
  1115. ioc->base_add_sg_single(psge, sgl_flags |
  1116. data_in_sz, data_in_dma);
  1117. }
  1118. }
  1119. /* IEEE format sgls */
  1120. /**
  1121. * _base_add_sg_single_ieee - add sg element for IEEE format
  1122. * @paddr: virtual address for SGE
  1123. * @flags: SGE flags
  1124. * @chain_offset: number of 128 byte elements from start of segment
  1125. * @length: data transfer length
  1126. * @dma_addr: Physical address
  1127. *
  1128. * Return nothing.
  1129. */
  1130. static void
  1131. _base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length,
  1132. dma_addr_t dma_addr)
  1133. {
  1134. Mpi25IeeeSgeChain64_t *sgel = paddr;
  1135. sgel->Flags = flags;
  1136. sgel->NextChainOffset = chain_offset;
  1137. sgel->Length = cpu_to_le32(length);
  1138. sgel->Address = cpu_to_le64(dma_addr);
  1139. }
  1140. /**
  1141. * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format
  1142. * @ioc: per adapter object
  1143. * @paddr: virtual address for SGE
  1144. *
  1145. * Create a zero length scatter gather entry to insure the IOCs hardware has
  1146. * something to use if the target device goes brain dead and tries
  1147. * to send data even when none is asked for.
  1148. *
  1149. * Return nothing.
  1150. */
  1151. static void
  1152. _base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
  1153. {
  1154. u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
  1155. MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
  1156. MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
  1157. _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1);
  1158. }
  1159. /**
  1160. * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format
  1161. * @ioc: per adapter object
  1162. * @scmd: scsi command
  1163. * @smid: system request message index
  1164. * Context: none.
  1165. *
  1166. * The main routine that builds scatter gather table from a given
  1167. * scsi request sent via the .queuecommand main handler.
  1168. *
  1169. * Returns 0 success, anything else error
  1170. */
  1171. static int
  1172. _base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
  1173. struct scsi_cmnd *scmd, u16 smid)
  1174. {
  1175. Mpi2SCSIIORequest_t *mpi_request;
  1176. dma_addr_t chain_dma;
  1177. struct scatterlist *sg_scmd;
  1178. void *sg_local, *chain;
  1179. u32 chain_offset;
  1180. u32 chain_length;
  1181. int sges_left;
  1182. u32 sges_in_segment;
  1183. u8 simple_sgl_flags;
  1184. u8 simple_sgl_flags_last;
  1185. u8 chain_sgl_flags;
  1186. struct chain_tracker *chain_req;
  1187. mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
  1188. /* init scatter gather flags */
  1189. simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
  1190. MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
  1191. simple_sgl_flags_last = simple_sgl_flags |
  1192. MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
  1193. chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
  1194. MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
  1195. sg_scmd = scsi_sglist(scmd);
  1196. sges_left = scsi_dma_map(scmd);
  1197. if (!sges_left) {
  1198. sdev_printk(KERN_ERR, scmd->device,
  1199. "pci_map_sg failed: request for %d bytes!\n",
  1200. scsi_bufflen(scmd));
  1201. return -ENOMEM;
  1202. }
  1203. sg_local = &mpi_request->SGL;
  1204. sges_in_segment = (ioc->request_sz -
  1205. offsetof(Mpi2SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
  1206. if (sges_left <= sges_in_segment)
  1207. goto fill_in_last_segment;
  1208. mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) +
  1209. (offsetof(Mpi2SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
  1210. /* fill in main message segment when there is a chain following */
  1211. while (sges_in_segment > 1) {
  1212. _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
  1213. sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
  1214. sg_scmd = sg_next(sg_scmd);
  1215. sg_local += ioc->sge_size_ieee;
  1216. sges_left--;
  1217. sges_in_segment--;
  1218. }
  1219. /* initializing the pointers */
  1220. chain_req = _base_get_chain_buffer_tracker(ioc, smid);
  1221. if (!chain_req)
  1222. return -1;
  1223. chain = chain_req->chain_buffer;
  1224. chain_dma = chain_req->chain_buffer_dma;
  1225. do {
  1226. sges_in_segment = (sges_left <=
  1227. ioc->max_sges_in_chain_message) ? sges_left :
  1228. ioc->max_sges_in_chain_message;
  1229. chain_offset = (sges_left == sges_in_segment) ?
  1230. 0 : sges_in_segment;
  1231. chain_length = sges_in_segment * ioc->sge_size_ieee;
  1232. if (chain_offset)
  1233. chain_length += ioc->sge_size_ieee;
  1234. _base_add_sg_single_ieee(sg_local, chain_sgl_flags,
  1235. chain_offset, chain_length, chain_dma);
  1236. sg_local = chain;
  1237. if (!chain_offset)
  1238. goto fill_in_last_segment;
  1239. /* fill in chain segments */
  1240. while (sges_in_segment) {
  1241. _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
  1242. sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
  1243. sg_scmd = sg_next(sg_scmd);
  1244. sg_local += ioc->sge_size_ieee;
  1245. sges_left--;
  1246. sges_in_segment--;
  1247. }
  1248. chain_req = _base_get_chain_buffer_tracker(ioc, smid);
  1249. if (!chain_req)
  1250. return -1;
  1251. chain = chain_req->chain_buffer;
  1252. chain_dma = chain_req->chain_buffer_dma;
  1253. } while (1);
  1254. fill_in_last_segment:
  1255. /* fill the last segment */
  1256. while (sges_left) {
  1257. if (sges_left == 1)
  1258. _base_add_sg_single_ieee(sg_local,
  1259. simple_sgl_flags_last, 0, sg_dma_len(sg_scmd),
  1260. sg_dma_address(sg_scmd));
  1261. else
  1262. _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
  1263. sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
  1264. sg_scmd = sg_next(sg_scmd);
  1265. sg_local += ioc->sge_size_ieee;
  1266. sges_left--;
  1267. }
  1268. return 0;
  1269. }
  1270. /**
  1271. * _base_build_sg_ieee - build generic sg for IEEE format
  1272. * @ioc: per adapter object
  1273. * @psge: virtual address for SGE
  1274. * @data_out_dma: physical address for WRITES
  1275. * @data_out_sz: data xfer size for WRITES
  1276. * @data_in_dma: physical address for READS
  1277. * @data_in_sz: data xfer size for READS
  1278. *
  1279. * Return nothing.
  1280. */
  1281. static void
  1282. _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
  1283. dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
  1284. size_t data_in_sz)
  1285. {
  1286. u8 sgl_flags;
  1287. if (!data_out_sz && !data_in_sz) {
  1288. _base_build_zero_len_sge_ieee(ioc, psge);
  1289. return;
  1290. }
  1291. if (data_out_sz && data_in_sz) {
  1292. /* WRITE sgel first */
  1293. sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
  1294. MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
  1295. _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
  1296. data_out_dma);
  1297. /* incr sgel */
  1298. psge += ioc->sge_size_ieee;
  1299. /* READ sgel last */
  1300. sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
  1301. _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
  1302. data_in_dma);
  1303. } else if (data_out_sz) /* WRITE */ {
  1304. sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
  1305. MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
  1306. MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
  1307. _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
  1308. data_out_dma);
  1309. } else if (data_in_sz) /* READ */ {
  1310. sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
  1311. MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
  1312. MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
  1313. _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
  1314. data_in_dma);
  1315. }
  1316. }
  1317. #define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
  1318. /**
  1319. * _base_config_dma_addressing - set dma addressing
  1320. * @ioc: per adapter object
  1321. * @pdev: PCI device struct
  1322. *
  1323. * Returns 0 for success, non-zero for failure.
  1324. */
  1325. static int
  1326. _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
  1327. {
  1328. struct sysinfo s;
  1329. char *desc = NULL;
  1330. if (sizeof(dma_addr_t) > 4) {
  1331. const uint64_t required_mask =
  1332. dma_get_required_mask(&pdev->dev);
  1333. if ((required_mask > DMA_BIT_MASK(32)) &&
  1334. !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
  1335. !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
  1336. ioc->base_add_sg_single = &_base_add_sg_single_64;
  1337. ioc->sge_size = sizeof(Mpi2SGESimple64_t);
  1338. desc = "64";
  1339. goto out;
  1340. }
  1341. }
  1342. if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
  1343. && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
  1344. ioc->base_add_sg_single = &_base_add_sg_single_32;
  1345. ioc->sge_size = sizeof(Mpi2SGESimple32_t);
  1346. desc = "32";
  1347. } else
  1348. return -ENODEV;
  1349. out:
  1350. si_meminfo(&s);
  1351. pr_info(MPT3SAS_FMT
  1352. "%s BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
  1353. ioc->name, desc, convert_to_kb(s.totalram));
  1354. return 0;
  1355. }
  1356. /**
  1357. * _base_check_enable_msix - checks MSIX capabable.
  1358. * @ioc: per adapter object
  1359. *
  1360. * Check to see if card is capable of MSIX, and set number
  1361. * of available msix vectors
  1362. */
  1363. static int
  1364. _base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
  1365. {
  1366. int base;
  1367. u16 message_control;
  1368. base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
  1369. if (!base) {
  1370. dfailprintk(ioc, pr_info(MPT3SAS_FMT "msix not supported\n",
  1371. ioc->name));
  1372. return -EINVAL;
  1373. }
  1374. /* get msix vector count */
  1375. pci_read_config_word(ioc->pdev, base + 2, &message_control);
  1376. ioc->msix_vector_count = (message_control & 0x3FF) + 1;
  1377. if (ioc->msix_vector_count > 8)
  1378. ioc->msix_vector_count = 8;
  1379. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  1380. "msix is supported, vector_count(%d)\n",
  1381. ioc->name, ioc->msix_vector_count));
  1382. return 0;
  1383. }
  1384. /**
  1385. * _base_free_irq - free irq
  1386. * @ioc: per adapter object
  1387. *
  1388. * Freeing respective reply_queue from the list.
  1389. */
  1390. static void
  1391. _base_free_irq(struct MPT3SAS_ADAPTER *ioc)
  1392. {
  1393. struct adapter_reply_queue *reply_q, *next;
  1394. if (list_empty(&ioc->reply_queue_list))
  1395. return;
  1396. list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
  1397. list_del(&reply_q->list);
  1398. synchronize_irq(reply_q->vector);
  1399. free_irq(reply_q->vector, reply_q);
  1400. kfree(reply_q);
  1401. }
  1402. }
  1403. /**
  1404. * _base_request_irq - request irq
  1405. * @ioc: per adapter object
  1406. * @index: msix index into vector table
  1407. * @vector: irq vector
  1408. *
  1409. * Inserting respective reply_queue into the list.
  1410. */
  1411. static int
  1412. _base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index, u32 vector)
  1413. {
  1414. struct adapter_reply_queue *reply_q;
  1415. int r;
  1416. reply_q = kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
  1417. if (!reply_q) {
  1418. pr_err(MPT3SAS_FMT "unable to allocate memory %d!\n",
  1419. ioc->name, (int)sizeof(struct adapter_reply_queue));
  1420. return -ENOMEM;
  1421. }
  1422. reply_q->ioc = ioc;
  1423. reply_q->msix_index = index;
  1424. reply_q->vector = vector;
  1425. atomic_set(&reply_q->busy, 0);
  1426. if (ioc->msix_enable)
  1427. snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
  1428. MPT3SAS_DRIVER_NAME, ioc->id, index);
  1429. else
  1430. snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
  1431. MPT3SAS_DRIVER_NAME, ioc->id);
  1432. r = request_irq(vector, _base_interrupt, IRQF_SHARED, reply_q->name,
  1433. reply_q);
  1434. if (r) {
  1435. pr_err(MPT3SAS_FMT "unable to allocate interrupt %d!\n",
  1436. reply_q->name, vector);
  1437. kfree(reply_q);
  1438. return -EBUSY;
  1439. }
  1440. INIT_LIST_HEAD(&reply_q->list);
  1441. list_add_tail(&reply_q->list, &ioc->reply_queue_list);
  1442. return 0;
  1443. }
  1444. /**
  1445. * _base_assign_reply_queues - assigning msix index for each cpu
  1446. * @ioc: per adapter object
  1447. *
  1448. * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
  1449. *
  1450. * It would nice if we could call irq_set_affinity, however it is not
  1451. * an exported symbol
  1452. */
  1453. static void
  1454. _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
  1455. {
  1456. struct adapter_reply_queue *reply_q;
  1457. int cpu_id;
  1458. int cpu_grouping, loop, grouping, grouping_mod;
  1459. int reply_queue;
  1460. if (!_base_is_controller_msix_enabled(ioc))
  1461. return;
  1462. memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
  1463. /* NUMA Hardware bug workaround - drop to less reply queues */
  1464. if (ioc->reply_queue_count > ioc->facts.MaxMSIxVectors) {
  1465. ioc->reply_queue_count = ioc->facts.MaxMSIxVectors;
  1466. reply_queue = 0;
  1467. list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
  1468. reply_q->msix_index = reply_queue;
  1469. if (++reply_queue == ioc->reply_queue_count)
  1470. reply_queue = 0;
  1471. }
  1472. }
  1473. /* when there are more cpus than available msix vectors,
  1474. * then group cpus togeather on same irq
  1475. */
  1476. if (ioc->cpu_count > ioc->msix_vector_count) {
  1477. grouping = ioc->cpu_count / ioc->msix_vector_count;
  1478. grouping_mod = ioc->cpu_count % ioc->msix_vector_count;
  1479. if (grouping < 2 || (grouping == 2 && !grouping_mod))
  1480. cpu_grouping = 2;
  1481. else if (grouping < 4 || (grouping == 4 && !grouping_mod))
  1482. cpu_grouping = 4;
  1483. else if (grouping < 8 || (grouping == 8 && !grouping_mod))
  1484. cpu_grouping = 8;
  1485. else
  1486. cpu_grouping = 16;
  1487. } else
  1488. cpu_grouping = 0;
  1489. loop = 0;
  1490. reply_q = list_entry(ioc->reply_queue_list.next,
  1491. struct adapter_reply_queue, list);
  1492. for_each_online_cpu(cpu_id) {
  1493. if (!cpu_grouping) {
  1494. ioc->cpu_msix_table[cpu_id] = reply_q->msix_index;
  1495. reply_q = list_entry(reply_q->list.next,
  1496. struct adapter_reply_queue, list);
  1497. } else {
  1498. if (loop < cpu_grouping) {
  1499. ioc->cpu_msix_table[cpu_id] =
  1500. reply_q->msix_index;
  1501. loop++;
  1502. } else {
  1503. reply_q = list_entry(reply_q->list.next,
  1504. struct adapter_reply_queue, list);
  1505. ioc->cpu_msix_table[cpu_id] =
  1506. reply_q->msix_index;
  1507. loop = 1;
  1508. }
  1509. }
  1510. }
  1511. }
  1512. /**
  1513. * _base_disable_msix - disables msix
  1514. * @ioc: per adapter object
  1515. *
  1516. */
  1517. static void
  1518. _base_disable_msix(struct MPT3SAS_ADAPTER *ioc)
  1519. {
  1520. if (!ioc->msix_enable)
  1521. return;
  1522. pci_disable_msix(ioc->pdev);
  1523. ioc->msix_enable = 0;
  1524. }
  1525. /**
  1526. * _base_enable_msix - enables msix, failback to io_apic
  1527. * @ioc: per adapter object
  1528. *
  1529. */
  1530. static int
  1531. _base_enable_msix(struct MPT3SAS_ADAPTER *ioc)
  1532. {
  1533. struct msix_entry *entries, *a;
  1534. int r;
  1535. int i;
  1536. u8 try_msix = 0;
  1537. if (msix_disable == -1 || msix_disable == 0)
  1538. try_msix = 1;
  1539. if (!try_msix)
  1540. goto try_ioapic;
  1541. if (_base_check_enable_msix(ioc) != 0)
  1542. goto try_ioapic;
  1543. ioc->reply_queue_count = min_t(int, ioc->cpu_count,
  1544. ioc->msix_vector_count);
  1545. printk(MPT3SAS_FMT "MSI-X vectors supported: %d, no of cores"
  1546. ": %d, max_msix_vectors: %d\n", ioc->name, ioc->msix_vector_count,
  1547. ioc->cpu_count, max_msix_vectors);
  1548. if (max_msix_vectors > 0) {
  1549. ioc->reply_queue_count = min_t(int, max_msix_vectors,
  1550. ioc->reply_queue_count);
  1551. ioc->msix_vector_count = ioc->reply_queue_count;
  1552. }
  1553. entries = kcalloc(ioc->reply_queue_count, sizeof(struct msix_entry),
  1554. GFP_KERNEL);
  1555. if (!entries) {
  1556. dfailprintk(ioc, pr_info(MPT3SAS_FMT
  1557. "kcalloc failed @ at %s:%d/%s() !!!\n",
  1558. ioc->name, __FILE__, __LINE__, __func__));
  1559. goto try_ioapic;
  1560. }
  1561. for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++)
  1562. a->entry = i;
  1563. r = pci_enable_msix(ioc->pdev, entries, ioc->reply_queue_count);
  1564. if (r) {
  1565. dfailprintk(ioc, pr_info(MPT3SAS_FMT
  1566. "pci_enable_msix failed (r=%d) !!!\n",
  1567. ioc->name, r));
  1568. kfree(entries);
  1569. goto try_ioapic;
  1570. }
  1571. ioc->msix_enable = 1;
  1572. for (i = 0, a = entries; i < ioc->reply_queue_count; i++, a++) {
  1573. r = _base_request_irq(ioc, i, a->vector);
  1574. if (r) {
  1575. _base_free_irq(ioc);
  1576. _base_disable_msix(ioc);
  1577. kfree(entries);
  1578. goto try_ioapic;
  1579. }
  1580. }
  1581. kfree(entries);
  1582. return 0;
  1583. /* failback to io_apic interrupt routing */
  1584. try_ioapic:
  1585. r = _base_request_irq(ioc, 0, ioc->pdev->irq);
  1586. return r;
  1587. }
  1588. /**
  1589. * mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
  1590. * @ioc: per adapter object
  1591. *
  1592. * Returns 0 for success, non-zero for failure.
  1593. */
  1594. int
  1595. mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
  1596. {
  1597. struct pci_dev *pdev = ioc->pdev;
  1598. u32 memap_sz;
  1599. u32 pio_sz;
  1600. int i, r = 0;
  1601. u64 pio_chip = 0;
  1602. u64 chip_phys = 0;
  1603. struct adapter_reply_queue *reply_q;
  1604. dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n",
  1605. ioc->name, __func__));
  1606. ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
  1607. if (pci_enable_device_mem(pdev)) {
  1608. pr_warn(MPT3SAS_FMT "pci_enable_device_mem: failed\n",
  1609. ioc->name);
  1610. ioc->bars = 0;
  1611. return -ENODEV;
  1612. }
  1613. if (pci_request_selected_regions(pdev, ioc->bars,
  1614. MPT3SAS_DRIVER_NAME)) {
  1615. pr_warn(MPT3SAS_FMT "pci_request_selected_regions: failed\n",
  1616. ioc->name);
  1617. ioc->bars = 0;
  1618. r = -ENODEV;
  1619. goto out_fail;
  1620. }
  1621. /* AER (Advanced Error Reporting) hooks */
  1622. pci_enable_pcie_error_reporting(pdev);
  1623. pci_set_master(pdev);
  1624. if (_base_config_dma_addressing(ioc, pdev) != 0) {
  1625. pr_warn(MPT3SAS_FMT "no suitable DMA mask for %s\n",
  1626. ioc->name, pci_name(pdev));
  1627. r = -ENODEV;
  1628. goto out_fail;
  1629. }
  1630. for (i = 0, memap_sz = 0, pio_sz = 0 ; i < DEVICE_COUNT_RESOURCE; i++) {
  1631. if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
  1632. if (pio_sz)
  1633. continue;
  1634. pio_chip = (u64)pci_resource_start(pdev, i);
  1635. pio_sz = pci_resource_len(pdev, i);
  1636. } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
  1637. if (memap_sz)
  1638. continue;
  1639. ioc->chip_phys = pci_resource_start(pdev, i);
  1640. chip_phys = (u64)ioc->chip_phys;
  1641. memap_sz = pci_resource_len(pdev, i);
  1642. ioc->chip = ioremap(ioc->chip_phys, memap_sz);
  1643. if (ioc->chip == NULL) {
  1644. pr_err(MPT3SAS_FMT "unable to map adapter memory!\n",
  1645. ioc->name);
  1646. r = -EINVAL;
  1647. goto out_fail;
  1648. }
  1649. }
  1650. }
  1651. _base_mask_interrupts(ioc);
  1652. r = _base_enable_msix(ioc);
  1653. if (r)
  1654. goto out_fail;
  1655. list_for_each_entry(reply_q, &ioc->reply_queue_list, list)
  1656. pr_info(MPT3SAS_FMT "%s: IRQ %d\n",
  1657. reply_q->name, ((ioc->msix_enable) ? "PCI-MSI-X enabled" :
  1658. "IO-APIC enabled"), reply_q->vector);
  1659. pr_info(MPT3SAS_FMT "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
  1660. ioc->name, (unsigned long long)chip_phys, ioc->chip, memap_sz);
  1661. pr_info(MPT3SAS_FMT "ioport(0x%016llx), size(%d)\n",
  1662. ioc->name, (unsigned long long)pio_chip, pio_sz);
  1663. /* Save PCI configuration state for recovery from PCI AER/EEH errors */
  1664. pci_save_state(pdev);
  1665. return 0;
  1666. out_fail:
  1667. if (ioc->chip_phys)
  1668. iounmap(ioc->chip);
  1669. ioc->chip_phys = 0;
  1670. pci_release_selected_regions(ioc->pdev, ioc->bars);
  1671. pci_disable_pcie_error_reporting(pdev);
  1672. pci_disable_device(pdev);
  1673. return r;
  1674. }
  1675. /**
  1676. * mpt3sas_base_get_msg_frame - obtain request mf pointer
  1677. * @ioc: per adapter object
  1678. * @smid: system request message index(smid zero is invalid)
  1679. *
  1680. * Returns virt pointer to message frame.
  1681. */
  1682. void *
  1683. mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid)
  1684. {
  1685. return (void *)(ioc->request + (smid * ioc->request_sz));
  1686. }
  1687. /**
  1688. * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr
  1689. * @ioc: per adapter object
  1690. * @smid: system request message index
  1691. *
  1692. * Returns virt pointer to sense buffer.
  1693. */
  1694. void *
  1695. mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid)
  1696. {
  1697. return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
  1698. }
  1699. /**
  1700. * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr
  1701. * @ioc: per adapter object
  1702. * @smid: system request message index
  1703. *
  1704. * Returns phys pointer to the low 32bit address of the sense buffer.
  1705. */
  1706. __le32
  1707. mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
  1708. {
  1709. return cpu_to_le32(ioc->sense_dma + ((smid - 1) *
  1710. SCSI_SENSE_BUFFERSIZE));
  1711. }
  1712. /**
  1713. * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
  1714. * @ioc: per adapter object
  1715. * @phys_addr: lower 32 physical addr of the reply
  1716. *
  1717. * Converts 32bit lower physical addr into a virt address.
  1718. */
  1719. void *
  1720. mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr)
  1721. {
  1722. if (!phys_addr)
  1723. return NULL;
  1724. return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
  1725. }
  1726. /**
  1727. * mpt3sas_base_get_smid - obtain a free smid from internal queue
  1728. * @ioc: per adapter object
  1729. * @cb_idx: callback index
  1730. *
  1731. * Returns smid (zero is invalid)
  1732. */
  1733. u16
  1734. mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
  1735. {
  1736. unsigned long flags;
  1737. struct request_tracker *request;
  1738. u16 smid;
  1739. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1740. if (list_empty(&ioc->internal_free_list)) {
  1741. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1742. pr_err(MPT3SAS_FMT "%s: smid not available\n",
  1743. ioc->name, __func__);
  1744. return 0;
  1745. }
  1746. request = list_entry(ioc->internal_free_list.next,
  1747. struct request_tracker, tracker_list);
  1748. request->cb_idx = cb_idx;
  1749. smid = request->smid;
  1750. list_del(&request->tracker_list);
  1751. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1752. return smid;
  1753. }
  1754. /**
  1755. * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
  1756. * @ioc: per adapter object
  1757. * @cb_idx: callback index
  1758. * @scmd: pointer to scsi command object
  1759. *
  1760. * Returns smid (zero is invalid)
  1761. */
  1762. u16
  1763. mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx,
  1764. struct scsi_cmnd *scmd)
  1765. {
  1766. unsigned long flags;
  1767. struct scsiio_tracker *request;
  1768. u16 smid;
  1769. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1770. if (list_empty(&ioc->free_list)) {
  1771. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1772. pr_err(MPT3SAS_FMT "%s: smid not available\n",
  1773. ioc->name, __func__);
  1774. return 0;
  1775. }
  1776. request = list_entry(ioc->free_list.next,
  1777. struct scsiio_tracker, tracker_list);
  1778. request->scmd = scmd;
  1779. request->cb_idx = cb_idx;
  1780. smid = request->smid;
  1781. list_del(&request->tracker_list);
  1782. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1783. return smid;
  1784. }
  1785. /**
  1786. * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
  1787. * @ioc: per adapter object
  1788. * @cb_idx: callback index
  1789. *
  1790. * Returns smid (zero is invalid)
  1791. */
  1792. u16
  1793. mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
  1794. {
  1795. unsigned long flags;
  1796. struct request_tracker *request;
  1797. u16 smid;
  1798. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1799. if (list_empty(&ioc->hpr_free_list)) {
  1800. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1801. return 0;
  1802. }
  1803. request = list_entry(ioc->hpr_free_list.next,
  1804. struct request_tracker, tracker_list);
  1805. request->cb_idx = cb_idx;
  1806. smid = request->smid;
  1807. list_del(&request->tracker_list);
  1808. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1809. return smid;
  1810. }
  1811. /**
  1812. * mpt3sas_base_free_smid - put smid back on free_list
  1813. * @ioc: per adapter object
  1814. * @smid: system request message index
  1815. *
  1816. * Return nothing.
  1817. */
  1818. void
  1819. mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
  1820. {
  1821. unsigned long flags;
  1822. int i;
  1823. struct chain_tracker *chain_req, *next;
  1824. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  1825. if (smid < ioc->hi_priority_smid) {
  1826. /* scsiio queue */
  1827. i = smid - 1;
  1828. if (!list_empty(&ioc->scsi_lookup[i].chain_list)) {
  1829. list_for_each_entry_safe(chain_req, next,
  1830. &ioc->scsi_lookup[i].chain_list, tracker_list) {
  1831. list_del_init(&chain_req->tracker_list);
  1832. list_add(&chain_req->tracker_list,
  1833. &ioc->free_chain_list);
  1834. }
  1835. }
  1836. ioc->scsi_lookup[i].cb_idx = 0xFF;
  1837. ioc->scsi_lookup[i].scmd = NULL;
  1838. list_add(&ioc->scsi_lookup[i].tracker_list, &ioc->free_list);
  1839. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1840. /*
  1841. * See _wait_for_commands_to_complete() call with regards
  1842. * to this code.
  1843. */
  1844. if (ioc->shost_recovery && ioc->pending_io_count) {
  1845. if (ioc->pending_io_count == 1)
  1846. wake_up(&ioc->reset_wq);
  1847. ioc->pending_io_count--;
  1848. }
  1849. return;
  1850. } else if (smid < ioc->internal_smid) {
  1851. /* hi-priority */
  1852. i = smid - ioc->hi_priority_smid;
  1853. ioc->hpr_lookup[i].cb_idx = 0xFF;
  1854. list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list);
  1855. } else if (smid <= ioc->hba_queue_depth) {
  1856. /* internal queue */
  1857. i = smid - ioc->internal_smid;
  1858. ioc->internal_lookup[i].cb_idx = 0xFF;
  1859. list_add(&ioc->internal_lookup[i].tracker_list,
  1860. &ioc->internal_free_list);
  1861. }
  1862. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  1863. }
  1864. /**
  1865. * _base_writeq - 64 bit write to MMIO
  1866. * @ioc: per adapter object
  1867. * @b: data payload
  1868. * @addr: address in MMIO space
  1869. * @writeq_lock: spin lock
  1870. *
  1871. * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
  1872. * care of 32 bit environment where its not quarenteed to send the entire word
  1873. * in one transfer.
  1874. */
  1875. #if defined(writeq) && defined(CONFIG_64BIT)
  1876. static inline void
  1877. _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
  1878. {
  1879. writeq(cpu_to_le64(b), addr);
  1880. }
  1881. #else
  1882. static inline void
  1883. _base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
  1884. {
  1885. unsigned long flags;
  1886. __u64 data_out = cpu_to_le64(b);
  1887. spin_lock_irqsave(writeq_lock, flags);
  1888. writel((u32)(data_out), addr);
  1889. writel((u32)(data_out >> 32), (addr + 4));
  1890. spin_unlock_irqrestore(writeq_lock, flags);
  1891. }
  1892. #endif
  1893. static inline u8
  1894. _base_get_msix_index(struct MPT3SAS_ADAPTER *ioc)
  1895. {
  1896. return ioc->cpu_msix_table[raw_smp_processor_id()];
  1897. }
  1898. /**
  1899. * mpt3sas_base_put_smid_scsi_io - send SCSI_IO request to firmware
  1900. * @ioc: per adapter object
  1901. * @smid: system request message index
  1902. * @handle: device handle
  1903. *
  1904. * Return nothing.
  1905. */
  1906. void
  1907. mpt3sas_base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
  1908. {
  1909. Mpi2RequestDescriptorUnion_t descriptor;
  1910. u64 *request = (u64 *)&descriptor;
  1911. descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
  1912. descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
  1913. descriptor.SCSIIO.SMID = cpu_to_le16(smid);
  1914. descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
  1915. descriptor.SCSIIO.LMID = 0;
  1916. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  1917. &ioc->scsi_lookup_lock);
  1918. }
  1919. /**
  1920. * mpt3sas_base_put_smid_fast_path - send fast path request to firmware
  1921. * @ioc: per adapter object
  1922. * @smid: system request message index
  1923. * @handle: device handle
  1924. *
  1925. * Return nothing.
  1926. */
  1927. void
  1928. mpt3sas_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
  1929. u16 handle)
  1930. {
  1931. Mpi2RequestDescriptorUnion_t descriptor;
  1932. u64 *request = (u64 *)&descriptor;
  1933. descriptor.SCSIIO.RequestFlags =
  1934. MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
  1935. descriptor.SCSIIO.MSIxIndex = _base_get_msix_index(ioc);
  1936. descriptor.SCSIIO.SMID = cpu_to_le16(smid);
  1937. descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
  1938. descriptor.SCSIIO.LMID = 0;
  1939. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  1940. &ioc->scsi_lookup_lock);
  1941. }
  1942. /**
  1943. * mpt3sas_base_put_smid_hi_priority - send Task Managment request to firmware
  1944. * @ioc: per adapter object
  1945. * @smid: system request message index
  1946. *
  1947. * Return nothing.
  1948. */
  1949. void
  1950. mpt3sas_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid)
  1951. {
  1952. Mpi2RequestDescriptorUnion_t descriptor;
  1953. u64 *request = (u64 *)&descriptor;
  1954. descriptor.HighPriority.RequestFlags =
  1955. MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
  1956. descriptor.HighPriority.MSIxIndex = 0;
  1957. descriptor.HighPriority.SMID = cpu_to_le16(smid);
  1958. descriptor.HighPriority.LMID = 0;
  1959. descriptor.HighPriority.Reserved1 = 0;
  1960. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  1961. &ioc->scsi_lookup_lock);
  1962. }
  1963. /**
  1964. * mpt3sas_base_put_smid_default - Default, primarily used for config pages
  1965. * @ioc: per adapter object
  1966. * @smid: system request message index
  1967. *
  1968. * Return nothing.
  1969. */
  1970. void
  1971. mpt3sas_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
  1972. {
  1973. Mpi2RequestDescriptorUnion_t descriptor;
  1974. u64 *request = (u64 *)&descriptor;
  1975. descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
  1976. descriptor.Default.MSIxIndex = _base_get_msix_index(ioc);
  1977. descriptor.Default.SMID = cpu_to_le16(smid);
  1978. descriptor.Default.LMID = 0;
  1979. descriptor.Default.DescriptorTypeDependent = 0;
  1980. _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
  1981. &ioc->scsi_lookup_lock);
  1982. }
  1983. /**
  1984. * _base_display_ioc_capabilities - Disply IOC's capabilities.
  1985. * @ioc: per adapter object
  1986. *
  1987. * Return nothing.
  1988. */
  1989. static void
  1990. _base_display_ioc_capabilities(struct MPT3SAS_ADAPTER *ioc)
  1991. {
  1992. int i = 0;
  1993. char desc[16];
  1994. u32 iounit_pg1_flags;
  1995. u32 bios_version;
  1996. bios_version = le32_to_cpu(ioc->bios_pg3.BiosVersion);
  1997. strncpy(desc, ioc->manu_pg0.ChipName, 16);
  1998. pr_info(MPT3SAS_FMT "%s: FWVersion(%02d.%02d.%02d.%02d), "\
  1999. "ChipRevision(0x%02x), BiosVersion(%02d.%02d.%02d.%02d)\n",
  2000. ioc->name, desc,
  2001. (ioc->facts.FWVersion.Word & 0xFF000000) >> 24,
  2002. (ioc->facts.FWVersion.Word & 0x00FF0000) >> 16,
  2003. (ioc->facts.FWVersion.Word & 0x0000FF00) >> 8,
  2004. ioc->facts.FWVersion.Word & 0x000000FF,
  2005. ioc->pdev->revision,
  2006. (bios_version & 0xFF000000) >> 24,
  2007. (bios_version & 0x00FF0000) >> 16,
  2008. (bios_version & 0x0000FF00) >> 8,
  2009. bios_version & 0x000000FF);
  2010. pr_info(MPT3SAS_FMT "Protocol=(", ioc->name);
  2011. if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR) {
  2012. pr_info("Initiator");
  2013. i++;
  2014. }
  2015. if (ioc->facts.ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET) {
  2016. pr_info("%sTarget", i ? "," : "");
  2017. i++;
  2018. }
  2019. i = 0;
  2020. pr_info("), ");
  2021. pr_info("Capabilities=(");
  2022. if (ioc->facts.IOCCapabilities &
  2023. MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) {
  2024. pr_info("Raid");
  2025. i++;
  2026. }
  2027. if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) {
  2028. pr_info("%sTLR", i ? "," : "");
  2029. i++;
  2030. }
  2031. if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_MULTICAST) {
  2032. pr_info("%sMulticast", i ? "," : "");
  2033. i++;
  2034. }
  2035. if (ioc->facts.IOCCapabilities &
  2036. MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET) {
  2037. pr_info("%sBIDI Target", i ? "," : "");
  2038. i++;
  2039. }
  2040. if (ioc->facts.IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) {
  2041. pr_info("%sEEDP", i ? "," : "");
  2042. i++;
  2043. }
  2044. if (ioc->facts.IOCCapabilities &
  2045. MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) {
  2046. pr_info("%sSnapshot Buffer", i ? "," : "");
  2047. i++;
  2048. }
  2049. if (ioc->facts.IOCCapabilities &
  2050. MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) {
  2051. pr_info("%sDiag Trace Buffer", i ? "," : "");
  2052. i++;
  2053. }
  2054. if (ioc->facts.IOCCapabilities &
  2055. MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) {
  2056. pr_info("%sDiag Extended Buffer", i ? "," : "");
  2057. i++;
  2058. }
  2059. if (ioc->facts.IOCCapabilities &
  2060. MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING) {
  2061. pr_info("%sTask Set Full", i ? "," : "");
  2062. i++;
  2063. }
  2064. iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
  2065. if (!(iounit_pg1_flags & MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE)) {
  2066. pr_info("%sNCQ", i ? "," : "");
  2067. i++;
  2068. }
  2069. pr_info(")\n");
  2070. }
  2071. /**
  2072. * mpt3sas_base_update_missing_delay - change the missing delay timers
  2073. * @ioc: per adapter object
  2074. * @device_missing_delay: amount of time till device is reported missing
  2075. * @io_missing_delay: interval IO is returned when there is a missing device
  2076. *
  2077. * Return nothing.
  2078. *
  2079. * Passed on the command line, this function will modify the device missing
  2080. * delay, as well as the io missing delay. This should be called at driver
  2081. * load time.
  2082. */
  2083. void
  2084. mpt3sas_base_update_missing_delay(struct MPT3SAS_ADAPTER *ioc,
  2085. u16 device_missing_delay, u8 io_missing_delay)
  2086. {
  2087. u16 dmd, dmd_new, dmd_orignal;
  2088. u8 io_missing_delay_original;
  2089. u16 sz;
  2090. Mpi2SasIOUnitPage1_t *sas_iounit_pg1 = NULL;
  2091. Mpi2ConfigReply_t mpi_reply;
  2092. u8 num_phys = 0;
  2093. u16 ioc_status;
  2094. mpt3sas_config_get_number_hba_phys(ioc, &num_phys);
  2095. if (!num_phys)
  2096. return;
  2097. sz = offsetof(Mpi2SasIOUnitPage1_t, PhyData) + (num_phys *
  2098. sizeof(Mpi2SasIOUnit1PhyData_t));
  2099. sas_iounit_pg1 = kzalloc(sz, GFP_KERNEL);
  2100. if (!sas_iounit_pg1) {
  2101. pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
  2102. ioc->name, __FILE__, __LINE__, __func__);
  2103. goto out;
  2104. }
  2105. if ((mpt3sas_config_get_sas_iounit_pg1(ioc, &mpi_reply,
  2106. sas_iounit_pg1, sz))) {
  2107. pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
  2108. ioc->name, __FILE__, __LINE__, __func__);
  2109. goto out;
  2110. }
  2111. ioc_status = le16_to_cpu(mpi_reply.IOCStatus) &
  2112. MPI2_IOCSTATUS_MASK;
  2113. if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
  2114. pr_err(MPT3SAS_FMT "failure at %s:%d/%s()!\n",
  2115. ioc->name, __FILE__, __LINE__, __func__);
  2116. goto out;
  2117. }
  2118. /* device missing delay */
  2119. dmd = sas_iounit_pg1->ReportDeviceMissingDelay;
  2120. if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
  2121. dmd = (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
  2122. else
  2123. dmd = dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
  2124. dmd_orignal = dmd;
  2125. if (device_missing_delay > 0x7F) {
  2126. dmd = (device_missing_delay > 0x7F0) ? 0x7F0 :
  2127. device_missing_delay;
  2128. dmd = dmd / 16;
  2129. dmd |= MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16;
  2130. } else
  2131. dmd = device_missing_delay;
  2132. sas_iounit_pg1->ReportDeviceMissingDelay = dmd;
  2133. /* io missing delay */
  2134. io_missing_delay_original = sas_iounit_pg1->IODeviceMissingDelay;
  2135. sas_iounit_pg1->IODeviceMissingDelay = io_missing_delay;
  2136. if (!mpt3sas_config_set_sas_iounit_pg1(ioc, &mpi_reply, sas_iounit_pg1,
  2137. sz)) {
  2138. if (dmd & MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16)
  2139. dmd_new = (dmd &
  2140. MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK) * 16;
  2141. else
  2142. dmd_new =
  2143. dmd & MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK;
  2144. pr_info(MPT3SAS_FMT "device_missing_delay: old(%d), new(%d)\n",
  2145. ioc->name, dmd_orignal, dmd_new);
  2146. pr_info(MPT3SAS_FMT "ioc_missing_delay: old(%d), new(%d)\n",
  2147. ioc->name, io_missing_delay_original,
  2148. io_missing_delay);
  2149. ioc->device_missing_delay = dmd_new;
  2150. ioc->io_missing_delay = io_missing_delay;
  2151. }
  2152. out:
  2153. kfree(sas_iounit_pg1);
  2154. }
  2155. /**
  2156. * _base_static_config_pages - static start of day config pages
  2157. * @ioc: per adapter object
  2158. *
  2159. * Return nothing.
  2160. */
  2161. static void
  2162. _base_static_config_pages(struct MPT3SAS_ADAPTER *ioc)
  2163. {
  2164. Mpi2ConfigReply_t mpi_reply;
  2165. u32 iounit_pg1_flags;
  2166. mpt3sas_config_get_manufacturing_pg0(ioc, &mpi_reply, &ioc->manu_pg0);
  2167. if (ioc->ir_firmware)
  2168. mpt3sas_config_get_manufacturing_pg10(ioc, &mpi_reply,
  2169. &ioc->manu_pg10);
  2170. /*
  2171. * Ensure correct T10 PI operation if vendor left EEDPTagMode
  2172. * flag unset in NVDATA.
  2173. */
  2174. mpt3sas_config_get_manufacturing_pg11(ioc, &mpi_reply, &ioc->manu_pg11);
  2175. if (ioc->manu_pg11.EEDPTagMode == 0) {
  2176. pr_err("%s: overriding NVDATA EEDPTagMode setting\n",
  2177. ioc->name);
  2178. ioc->manu_pg11.EEDPTagMode &= ~0x3;
  2179. ioc->manu_pg11.EEDPTagMode |= 0x1;
  2180. mpt3sas_config_set_manufacturing_pg11(ioc, &mpi_reply,
  2181. &ioc->manu_pg11);
  2182. }
  2183. mpt3sas_config_get_bios_pg2(ioc, &mpi_reply, &ioc->bios_pg2);
  2184. mpt3sas_config_get_bios_pg3(ioc, &mpi_reply, &ioc->bios_pg3);
  2185. mpt3sas_config_get_ioc_pg8(ioc, &mpi_reply, &ioc->ioc_pg8);
  2186. mpt3sas_config_get_iounit_pg0(ioc, &mpi_reply, &ioc->iounit_pg0);
  2187. mpt3sas_config_get_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
  2188. _base_display_ioc_capabilities(ioc);
  2189. /*
  2190. * Enable task_set_full handling in iounit_pg1 when the
  2191. * facts capabilities indicate that its supported.
  2192. */
  2193. iounit_pg1_flags = le32_to_cpu(ioc->iounit_pg1.Flags);
  2194. if ((ioc->facts.IOCCapabilities &
  2195. MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING))
  2196. iounit_pg1_flags &=
  2197. ~MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
  2198. else
  2199. iounit_pg1_flags |=
  2200. MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING;
  2201. ioc->iounit_pg1.Flags = cpu_to_le32(iounit_pg1_flags);
  2202. mpt3sas_config_set_iounit_pg1(ioc, &mpi_reply, &ioc->iounit_pg1);
  2203. }
  2204. /**
  2205. * _base_release_memory_pools - release memory
  2206. * @ioc: per adapter object
  2207. *
  2208. * Free memory allocated from _base_allocate_memory_pools.
  2209. *
  2210. * Return nothing.
  2211. */
  2212. static void
  2213. _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
  2214. {
  2215. int i;
  2216. dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2217. __func__));
  2218. if (ioc->request) {
  2219. pci_free_consistent(ioc->pdev, ioc->request_dma_sz,
  2220. ioc->request, ioc->request_dma);
  2221. dexitprintk(ioc, pr_info(MPT3SAS_FMT
  2222. "request_pool(0x%p): free\n",
  2223. ioc->name, ioc->request));
  2224. ioc->request = NULL;
  2225. }
  2226. if (ioc->sense) {
  2227. pci_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
  2228. if (ioc->sense_dma_pool)
  2229. pci_pool_destroy(ioc->sense_dma_pool);
  2230. dexitprintk(ioc, pr_info(MPT3SAS_FMT
  2231. "sense_pool(0x%p): free\n",
  2232. ioc->name, ioc->sense));
  2233. ioc->sense = NULL;
  2234. }
  2235. if (ioc->reply) {
  2236. pci_pool_free(ioc->reply_dma_pool, ioc->reply, ioc->reply_dma);
  2237. if (ioc->reply_dma_pool)
  2238. pci_pool_destroy(ioc->reply_dma_pool);
  2239. dexitprintk(ioc, pr_info(MPT3SAS_FMT
  2240. "reply_pool(0x%p): free\n",
  2241. ioc->name, ioc->reply));
  2242. ioc->reply = NULL;
  2243. }
  2244. if (ioc->reply_free) {
  2245. pci_pool_free(ioc->reply_free_dma_pool, ioc->reply_free,
  2246. ioc->reply_free_dma);
  2247. if (ioc->reply_free_dma_pool)
  2248. pci_pool_destroy(ioc->reply_free_dma_pool);
  2249. dexitprintk(ioc, pr_info(MPT3SAS_FMT
  2250. "reply_free_pool(0x%p): free\n",
  2251. ioc->name, ioc->reply_free));
  2252. ioc->reply_free = NULL;
  2253. }
  2254. if (ioc->reply_post_free) {
  2255. pci_pool_free(ioc->reply_post_free_dma_pool,
  2256. ioc->reply_post_free, ioc->reply_post_free_dma);
  2257. if (ioc->reply_post_free_dma_pool)
  2258. pci_pool_destroy(ioc->reply_post_free_dma_pool);
  2259. dexitprintk(ioc, pr_info(MPT3SAS_FMT
  2260. "reply_post_free_pool(0x%p): free\n", ioc->name,
  2261. ioc->reply_post_free));
  2262. ioc->reply_post_free = NULL;
  2263. }
  2264. if (ioc->config_page) {
  2265. dexitprintk(ioc, pr_info(MPT3SAS_FMT
  2266. "config_page(0x%p): free\n", ioc->name,
  2267. ioc->config_page));
  2268. pci_free_consistent(ioc->pdev, ioc->config_page_sz,
  2269. ioc->config_page, ioc->config_page_dma);
  2270. }
  2271. if (ioc->scsi_lookup) {
  2272. free_pages((ulong)ioc->scsi_lookup, ioc->scsi_lookup_pages);
  2273. ioc->scsi_lookup = NULL;
  2274. }
  2275. kfree(ioc->hpr_lookup);
  2276. kfree(ioc->internal_lookup);
  2277. if (ioc->chain_lookup) {
  2278. for (i = 0; i < ioc->chain_depth; i++) {
  2279. if (ioc->chain_lookup[i].chain_buffer)
  2280. pci_pool_free(ioc->chain_dma_pool,
  2281. ioc->chain_lookup[i].chain_buffer,
  2282. ioc->chain_lookup[i].chain_buffer_dma);
  2283. }
  2284. if (ioc->chain_dma_pool)
  2285. pci_pool_destroy(ioc->chain_dma_pool);
  2286. free_pages((ulong)ioc->chain_lookup, ioc->chain_pages);
  2287. ioc->chain_lookup = NULL;
  2288. }
  2289. }
  2290. /**
  2291. * _base_allocate_memory_pools - allocate start of day memory pools
  2292. * @ioc: per adapter object
  2293. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2294. *
  2295. * Returns 0 success, anything else error
  2296. */
  2297. static int
  2298. _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
  2299. {
  2300. struct mpt3sas_facts *facts;
  2301. u16 max_sge_elements;
  2302. u16 chains_needed_per_io;
  2303. u32 sz, total_sz, reply_post_free_sz;
  2304. u32 retry_sz;
  2305. u16 max_request_credit;
  2306. unsigned short sg_tablesize;
  2307. u16 sge_size;
  2308. int i;
  2309. dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2310. __func__));
  2311. retry_sz = 0;
  2312. facts = &ioc->facts;
  2313. /* command line tunables for max sgl entries */
  2314. if (max_sgl_entries != -1)
  2315. sg_tablesize = max_sgl_entries;
  2316. else
  2317. sg_tablesize = MPT3SAS_SG_DEPTH;
  2318. if (sg_tablesize < MPT3SAS_MIN_PHYS_SEGMENTS)
  2319. sg_tablesize = MPT3SAS_MIN_PHYS_SEGMENTS;
  2320. else if (sg_tablesize > MPT3SAS_MAX_PHYS_SEGMENTS)
  2321. sg_tablesize = MPT3SAS_MAX_PHYS_SEGMENTS;
  2322. ioc->shost->sg_tablesize = sg_tablesize;
  2323. ioc->hi_priority_depth = facts->HighPriorityCredit;
  2324. ioc->internal_depth = ioc->hi_priority_depth + (5);
  2325. /* command line tunables for max controller queue depth */
  2326. if (max_queue_depth != -1 && max_queue_depth != 0) {
  2327. max_request_credit = min_t(u16, max_queue_depth +
  2328. ioc->hi_priority_depth + ioc->internal_depth,
  2329. facts->RequestCredit);
  2330. if (max_request_credit > MAX_HBA_QUEUE_DEPTH)
  2331. max_request_credit = MAX_HBA_QUEUE_DEPTH;
  2332. } else
  2333. max_request_credit = min_t(u16, facts->RequestCredit,
  2334. MAX_HBA_QUEUE_DEPTH);
  2335. ioc->hba_queue_depth = max_request_credit;
  2336. /* request frame size */
  2337. ioc->request_sz = facts->IOCRequestFrameSize * 4;
  2338. /* reply frame size */
  2339. ioc->reply_sz = facts->ReplyFrameSize * 4;
  2340. /* calculate the max scatter element size */
  2341. sge_size = max_t(u16, ioc->sge_size, ioc->sge_size_ieee);
  2342. retry_allocation:
  2343. total_sz = 0;
  2344. /* calculate number of sg elements left over in the 1st frame */
  2345. max_sge_elements = ioc->request_sz - ((sizeof(Mpi2SCSIIORequest_t) -
  2346. sizeof(Mpi2SGEIOUnion_t)) + sge_size);
  2347. ioc->max_sges_in_main_message = max_sge_elements/sge_size;
  2348. /* now do the same for a chain buffer */
  2349. max_sge_elements = ioc->request_sz - sge_size;
  2350. ioc->max_sges_in_chain_message = max_sge_elements/sge_size;
  2351. /*
  2352. * MPT3SAS_SG_DEPTH = CONFIG_FUSION_MAX_SGE
  2353. */
  2354. chains_needed_per_io = ((ioc->shost->sg_tablesize -
  2355. ioc->max_sges_in_main_message)/ioc->max_sges_in_chain_message)
  2356. + 1;
  2357. if (chains_needed_per_io > facts->MaxChainDepth) {
  2358. chains_needed_per_io = facts->MaxChainDepth;
  2359. ioc->shost->sg_tablesize = min_t(u16,
  2360. ioc->max_sges_in_main_message + (ioc->max_sges_in_chain_message
  2361. * chains_needed_per_io), ioc->shost->sg_tablesize);
  2362. }
  2363. ioc->chains_needed_per_io = chains_needed_per_io;
  2364. /* reply free queue sizing - taking into account for 64 FW events */
  2365. ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
  2366. /* calculate reply descriptor post queue depth */
  2367. ioc->reply_post_queue_depth = ioc->hba_queue_depth +
  2368. ioc->reply_free_queue_depth + 1 ;
  2369. /* align the reply post queue on the next 16 count boundary */
  2370. if (ioc->reply_post_queue_depth % 16)
  2371. ioc->reply_post_queue_depth += 16 -
  2372. (ioc->reply_post_queue_depth % 16);
  2373. if (ioc->reply_post_queue_depth >
  2374. facts->MaxReplyDescriptorPostQueueDepth) {
  2375. ioc->reply_post_queue_depth =
  2376. facts->MaxReplyDescriptorPostQueueDepth -
  2377. (facts->MaxReplyDescriptorPostQueueDepth % 16);
  2378. ioc->hba_queue_depth =
  2379. ((ioc->reply_post_queue_depth - 64) / 2) - 1;
  2380. ioc->reply_free_queue_depth = ioc->hba_queue_depth + 64;
  2381. }
  2382. dinitprintk(ioc, pr_info(MPT3SAS_FMT "scatter gather: " \
  2383. "sge_in_main_msg(%d), sge_per_chain(%d), sge_per_io(%d), "
  2384. "chains_per_io(%d)\n", ioc->name, ioc->max_sges_in_main_message,
  2385. ioc->max_sges_in_chain_message, ioc->shost->sg_tablesize,
  2386. ioc->chains_needed_per_io));
  2387. ioc->scsiio_depth = ioc->hba_queue_depth -
  2388. ioc->hi_priority_depth - ioc->internal_depth;
  2389. /* set the scsi host can_queue depth
  2390. * with some internal commands that could be outstanding
  2391. */
  2392. ioc->shost->can_queue = ioc->scsiio_depth;
  2393. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  2394. "scsi host: can_queue depth (%d)\n",
  2395. ioc->name, ioc->shost->can_queue));
  2396. /* contiguous pool for request and chains, 16 byte align, one extra "
  2397. * "frame for smid=0
  2398. */
  2399. ioc->chain_depth = ioc->chains_needed_per_io * ioc->scsiio_depth;
  2400. sz = ((ioc->scsiio_depth + 1) * ioc->request_sz);
  2401. /* hi-priority queue */
  2402. sz += (ioc->hi_priority_depth * ioc->request_sz);
  2403. /* internal queue */
  2404. sz += (ioc->internal_depth * ioc->request_sz);
  2405. ioc->request_dma_sz = sz;
  2406. ioc->request = pci_alloc_consistent(ioc->pdev, sz, &ioc->request_dma);
  2407. if (!ioc->request) {
  2408. pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
  2409. "failed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
  2410. "total(%d kB)\n", ioc->name, ioc->hba_queue_depth,
  2411. ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
  2412. if (ioc->scsiio_depth < MPT3SAS_SAS_QUEUE_DEPTH)
  2413. goto out;
  2414. retry_sz += 64;
  2415. ioc->hba_queue_depth = max_request_credit - retry_sz;
  2416. goto retry_allocation;
  2417. }
  2418. if (retry_sz)
  2419. pr_err(MPT3SAS_FMT "request pool: pci_alloc_consistent " \
  2420. "succeed: hba_depth(%d), chains_per_io(%d), frame_sz(%d), "
  2421. "total(%d kb)\n", ioc->name, ioc->hba_queue_depth,
  2422. ioc->chains_needed_per_io, ioc->request_sz, sz/1024);
  2423. /* hi-priority queue */
  2424. ioc->hi_priority = ioc->request + ((ioc->scsiio_depth + 1) *
  2425. ioc->request_sz);
  2426. ioc->hi_priority_dma = ioc->request_dma + ((ioc->scsiio_depth + 1) *
  2427. ioc->request_sz);
  2428. /* internal queue */
  2429. ioc->internal = ioc->hi_priority + (ioc->hi_priority_depth *
  2430. ioc->request_sz);
  2431. ioc->internal_dma = ioc->hi_priority_dma + (ioc->hi_priority_depth *
  2432. ioc->request_sz);
  2433. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  2434. "request pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
  2435. ioc->name, ioc->request, ioc->hba_queue_depth, ioc->request_sz,
  2436. (ioc->hba_queue_depth * ioc->request_sz)/1024));
  2437. dinitprintk(ioc, pr_info(MPT3SAS_FMT "request pool: dma(0x%llx)\n",
  2438. ioc->name, (unsigned long long) ioc->request_dma));
  2439. total_sz += sz;
  2440. sz = ioc->scsiio_depth * sizeof(struct scsiio_tracker);
  2441. ioc->scsi_lookup_pages = get_order(sz);
  2442. ioc->scsi_lookup = (struct scsiio_tracker *)__get_free_pages(
  2443. GFP_KERNEL, ioc->scsi_lookup_pages);
  2444. if (!ioc->scsi_lookup) {
  2445. pr_err(MPT3SAS_FMT "scsi_lookup: get_free_pages failed, sz(%d)\n",
  2446. ioc->name, (int)sz);
  2447. goto out;
  2448. }
  2449. dinitprintk(ioc, pr_info(MPT3SAS_FMT "scsiio(0x%p): depth(%d)\n",
  2450. ioc->name, ioc->request, ioc->scsiio_depth));
  2451. ioc->chain_depth = min_t(u32, ioc->chain_depth, MAX_CHAIN_DEPTH);
  2452. sz = ioc->chain_depth * sizeof(struct chain_tracker);
  2453. ioc->chain_pages = get_order(sz);
  2454. ioc->chain_lookup = (struct chain_tracker *)__get_free_pages(
  2455. GFP_KERNEL, ioc->chain_pages);
  2456. if (!ioc->chain_lookup) {
  2457. pr_err(MPT3SAS_FMT "chain_lookup: __get_free_pages failed\n",
  2458. ioc->name);
  2459. goto out;
  2460. }
  2461. ioc->chain_dma_pool = pci_pool_create("chain pool", ioc->pdev,
  2462. ioc->request_sz, 16, 0);
  2463. if (!ioc->chain_dma_pool) {
  2464. pr_err(MPT3SAS_FMT "chain_dma_pool: pci_pool_create failed\n",
  2465. ioc->name);
  2466. goto out;
  2467. }
  2468. for (i = 0; i < ioc->chain_depth; i++) {
  2469. ioc->chain_lookup[i].chain_buffer = pci_pool_alloc(
  2470. ioc->chain_dma_pool , GFP_KERNEL,
  2471. &ioc->chain_lookup[i].chain_buffer_dma);
  2472. if (!ioc->chain_lookup[i].chain_buffer) {
  2473. ioc->chain_depth = i;
  2474. goto chain_done;
  2475. }
  2476. total_sz += ioc->request_sz;
  2477. }
  2478. chain_done:
  2479. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  2480. "chain pool depth(%d), frame_size(%d), pool_size(%d kB)\n",
  2481. ioc->name, ioc->chain_depth, ioc->request_sz,
  2482. ((ioc->chain_depth * ioc->request_sz))/1024));
  2483. /* initialize hi-priority queue smid's */
  2484. ioc->hpr_lookup = kcalloc(ioc->hi_priority_depth,
  2485. sizeof(struct request_tracker), GFP_KERNEL);
  2486. if (!ioc->hpr_lookup) {
  2487. pr_err(MPT3SAS_FMT "hpr_lookup: kcalloc failed\n",
  2488. ioc->name);
  2489. goto out;
  2490. }
  2491. ioc->hi_priority_smid = ioc->scsiio_depth + 1;
  2492. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  2493. "hi_priority(0x%p): depth(%d), start smid(%d)\n",
  2494. ioc->name, ioc->hi_priority,
  2495. ioc->hi_priority_depth, ioc->hi_priority_smid));
  2496. /* initialize internal queue smid's */
  2497. ioc->internal_lookup = kcalloc(ioc->internal_depth,
  2498. sizeof(struct request_tracker), GFP_KERNEL);
  2499. if (!ioc->internal_lookup) {
  2500. pr_err(MPT3SAS_FMT "internal_lookup: kcalloc failed\n",
  2501. ioc->name);
  2502. goto out;
  2503. }
  2504. ioc->internal_smid = ioc->hi_priority_smid + ioc->hi_priority_depth;
  2505. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  2506. "internal(0x%p): depth(%d), start smid(%d)\n",
  2507. ioc->name, ioc->internal,
  2508. ioc->internal_depth, ioc->internal_smid));
  2509. /* sense buffers, 4 byte align */
  2510. sz = ioc->scsiio_depth * SCSI_SENSE_BUFFERSIZE;
  2511. ioc->sense_dma_pool = pci_pool_create("sense pool", ioc->pdev, sz, 4,
  2512. 0);
  2513. if (!ioc->sense_dma_pool) {
  2514. pr_err(MPT3SAS_FMT "sense pool: pci_pool_create failed\n",
  2515. ioc->name);
  2516. goto out;
  2517. }
  2518. ioc->sense = pci_pool_alloc(ioc->sense_dma_pool , GFP_KERNEL,
  2519. &ioc->sense_dma);
  2520. if (!ioc->sense) {
  2521. pr_err(MPT3SAS_FMT "sense pool: pci_pool_alloc failed\n",
  2522. ioc->name);
  2523. goto out;
  2524. }
  2525. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  2526. "sense pool(0x%p): depth(%d), element_size(%d), pool_size"
  2527. "(%d kB)\n", ioc->name, ioc->sense, ioc->scsiio_depth,
  2528. SCSI_SENSE_BUFFERSIZE, sz/1024));
  2529. dinitprintk(ioc, pr_info(MPT3SAS_FMT "sense_dma(0x%llx)\n",
  2530. ioc->name, (unsigned long long)ioc->sense_dma));
  2531. total_sz += sz;
  2532. /* reply pool, 4 byte align */
  2533. sz = ioc->reply_free_queue_depth * ioc->reply_sz;
  2534. ioc->reply_dma_pool = pci_pool_create("reply pool", ioc->pdev, sz, 4,
  2535. 0);
  2536. if (!ioc->reply_dma_pool) {
  2537. pr_err(MPT3SAS_FMT "reply pool: pci_pool_create failed\n",
  2538. ioc->name);
  2539. goto out;
  2540. }
  2541. ioc->reply = pci_pool_alloc(ioc->reply_dma_pool , GFP_KERNEL,
  2542. &ioc->reply_dma);
  2543. if (!ioc->reply) {
  2544. pr_err(MPT3SAS_FMT "reply pool: pci_pool_alloc failed\n",
  2545. ioc->name);
  2546. goto out;
  2547. }
  2548. ioc->reply_dma_min_address = (u32)(ioc->reply_dma);
  2549. ioc->reply_dma_max_address = (u32)(ioc->reply_dma) + sz;
  2550. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  2551. "reply pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB)\n",
  2552. ioc->name, ioc->reply,
  2553. ioc->reply_free_queue_depth, ioc->reply_sz, sz/1024));
  2554. dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_dma(0x%llx)\n",
  2555. ioc->name, (unsigned long long)ioc->reply_dma));
  2556. total_sz += sz;
  2557. /* reply free queue, 16 byte align */
  2558. sz = ioc->reply_free_queue_depth * 4;
  2559. ioc->reply_free_dma_pool = pci_pool_create("reply_free pool",
  2560. ioc->pdev, sz, 16, 0);
  2561. if (!ioc->reply_free_dma_pool) {
  2562. pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_create failed\n",
  2563. ioc->name);
  2564. goto out;
  2565. }
  2566. ioc->reply_free = pci_pool_alloc(ioc->reply_free_dma_pool , GFP_KERNEL,
  2567. &ioc->reply_free_dma);
  2568. if (!ioc->reply_free) {
  2569. pr_err(MPT3SAS_FMT "reply_free pool: pci_pool_alloc failed\n",
  2570. ioc->name);
  2571. goto out;
  2572. }
  2573. memset(ioc->reply_free, 0, sz);
  2574. dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply_free pool(0x%p): " \
  2575. "depth(%d), element_size(%d), pool_size(%d kB)\n", ioc->name,
  2576. ioc->reply_free, ioc->reply_free_queue_depth, 4, sz/1024));
  2577. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  2578. "reply_free_dma (0x%llx)\n",
  2579. ioc->name, (unsigned long long)ioc->reply_free_dma));
  2580. total_sz += sz;
  2581. /* reply post queue, 16 byte align */
  2582. reply_post_free_sz = ioc->reply_post_queue_depth *
  2583. sizeof(Mpi2DefaultReplyDescriptor_t);
  2584. if (_base_is_controller_msix_enabled(ioc))
  2585. sz = reply_post_free_sz * ioc->reply_queue_count;
  2586. else
  2587. sz = reply_post_free_sz;
  2588. ioc->reply_post_free_dma_pool = pci_pool_create("reply_post_free pool",
  2589. ioc->pdev, sz, 16, 0);
  2590. if (!ioc->reply_post_free_dma_pool) {
  2591. pr_err(MPT3SAS_FMT
  2592. "reply_post_free pool: pci_pool_create failed\n",
  2593. ioc->name);
  2594. goto out;
  2595. }
  2596. ioc->reply_post_free = pci_pool_alloc(ioc->reply_post_free_dma_pool ,
  2597. GFP_KERNEL, &ioc->reply_post_free_dma);
  2598. if (!ioc->reply_post_free) {
  2599. pr_err(MPT3SAS_FMT
  2600. "reply_post_free pool: pci_pool_alloc failed\n",
  2601. ioc->name);
  2602. goto out;
  2603. }
  2604. memset(ioc->reply_post_free, 0, sz);
  2605. dinitprintk(ioc, pr_info(MPT3SAS_FMT "reply post free pool" \
  2606. "(0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n",
  2607. ioc->name, ioc->reply_post_free, ioc->reply_post_queue_depth, 8,
  2608. sz/1024));
  2609. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  2610. "reply_post_free_dma = (0x%llx)\n",
  2611. ioc->name, (unsigned long long)
  2612. ioc->reply_post_free_dma));
  2613. total_sz += sz;
  2614. ioc->config_page_sz = 512;
  2615. ioc->config_page = pci_alloc_consistent(ioc->pdev,
  2616. ioc->config_page_sz, &ioc->config_page_dma);
  2617. if (!ioc->config_page) {
  2618. pr_err(MPT3SAS_FMT
  2619. "config page: pci_pool_alloc failed\n",
  2620. ioc->name);
  2621. goto out;
  2622. }
  2623. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  2624. "config page(0x%p): size(%d)\n",
  2625. ioc->name, ioc->config_page, ioc->config_page_sz));
  2626. dinitprintk(ioc, pr_info(MPT3SAS_FMT "config_page_dma(0x%llx)\n",
  2627. ioc->name, (unsigned long long)ioc->config_page_dma));
  2628. total_sz += ioc->config_page_sz;
  2629. pr_info(MPT3SAS_FMT "Allocated physical memory: size(%d kB)\n",
  2630. ioc->name, total_sz/1024);
  2631. pr_info(MPT3SAS_FMT
  2632. "Current Controller Queue Depth(%d),Max Controller Queue Depth(%d)\n",
  2633. ioc->name, ioc->shost->can_queue, facts->RequestCredit);
  2634. pr_info(MPT3SAS_FMT "Scatter Gather Elements per IO(%d)\n",
  2635. ioc->name, ioc->shost->sg_tablesize);
  2636. return 0;
  2637. out:
  2638. return -ENOMEM;
  2639. }
  2640. /**
  2641. * mpt3sas_base_get_iocstate - Get the current state of a MPT adapter.
  2642. * @ioc: Pointer to MPT_ADAPTER structure
  2643. * @cooked: Request raw or cooked IOC state
  2644. *
  2645. * Returns all IOC Doorbell register bits if cooked==0, else just the
  2646. * Doorbell bits in MPI_IOC_STATE_MASK.
  2647. */
  2648. u32
  2649. mpt3sas_base_get_iocstate(struct MPT3SAS_ADAPTER *ioc, int cooked)
  2650. {
  2651. u32 s, sc;
  2652. s = readl(&ioc->chip->Doorbell);
  2653. sc = s & MPI2_IOC_STATE_MASK;
  2654. return cooked ? sc : s;
  2655. }
  2656. /**
  2657. * _base_wait_on_iocstate - waiting on a particular ioc state
  2658. * @ioc_state: controller state { READY, OPERATIONAL, or RESET }
  2659. * @timeout: timeout in second
  2660. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2661. *
  2662. * Returns 0 for success, non-zero for failure.
  2663. */
  2664. static int
  2665. _base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc, u32 ioc_state, int timeout,
  2666. int sleep_flag)
  2667. {
  2668. u32 count, cntdn;
  2669. u32 current_state;
  2670. count = 0;
  2671. cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
  2672. do {
  2673. current_state = mpt3sas_base_get_iocstate(ioc, 1);
  2674. if (current_state == ioc_state)
  2675. return 0;
  2676. if (count && current_state == MPI2_IOC_STATE_FAULT)
  2677. break;
  2678. if (sleep_flag == CAN_SLEEP)
  2679. usleep_range(1000, 1500);
  2680. else
  2681. udelay(500);
  2682. count++;
  2683. } while (--cntdn);
  2684. return current_state;
  2685. }
  2686. /**
  2687. * _base_wait_for_doorbell_int - waiting for controller interrupt(generated by
  2688. * a write to the doorbell)
  2689. * @ioc: per adapter object
  2690. * @timeout: timeout in second
  2691. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2692. *
  2693. * Returns 0 for success, non-zero for failure.
  2694. *
  2695. * Notes: MPI2_HIS_IOC2SYS_DB_STATUS - set to one when IOC writes to doorbell.
  2696. */
  2697. static int
  2698. _base_wait_for_doorbell_int(struct MPT3SAS_ADAPTER *ioc, int timeout,
  2699. int sleep_flag)
  2700. {
  2701. u32 cntdn, count;
  2702. u32 int_status;
  2703. count = 0;
  2704. cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
  2705. do {
  2706. int_status = readl(&ioc->chip->HostInterruptStatus);
  2707. if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
  2708. dhsprintk(ioc, pr_info(MPT3SAS_FMT
  2709. "%s: successful count(%d), timeout(%d)\n",
  2710. ioc->name, __func__, count, timeout));
  2711. return 0;
  2712. }
  2713. if (sleep_flag == CAN_SLEEP)
  2714. usleep_range(1000, 1500);
  2715. else
  2716. udelay(500);
  2717. count++;
  2718. } while (--cntdn);
  2719. pr_err(MPT3SAS_FMT
  2720. "%s: failed due to timeout count(%d), int_status(%x)!\n",
  2721. ioc->name, __func__, count, int_status);
  2722. return -EFAULT;
  2723. }
  2724. /**
  2725. * _base_wait_for_doorbell_ack - waiting for controller to read the doorbell.
  2726. * @ioc: per adapter object
  2727. * @timeout: timeout in second
  2728. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2729. *
  2730. * Returns 0 for success, non-zero for failure.
  2731. *
  2732. * Notes: MPI2_HIS_SYS2IOC_DB_STATUS - set to one when host writes to
  2733. * doorbell.
  2734. */
  2735. static int
  2736. _base_wait_for_doorbell_ack(struct MPT3SAS_ADAPTER *ioc, int timeout,
  2737. int sleep_flag)
  2738. {
  2739. u32 cntdn, count;
  2740. u32 int_status;
  2741. u32 doorbell;
  2742. count = 0;
  2743. cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
  2744. do {
  2745. int_status = readl(&ioc->chip->HostInterruptStatus);
  2746. if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
  2747. dhsprintk(ioc, pr_info(MPT3SAS_FMT
  2748. "%s: successful count(%d), timeout(%d)\n",
  2749. ioc->name, __func__, count, timeout));
  2750. return 0;
  2751. } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
  2752. doorbell = readl(&ioc->chip->Doorbell);
  2753. if ((doorbell & MPI2_IOC_STATE_MASK) ==
  2754. MPI2_IOC_STATE_FAULT) {
  2755. mpt3sas_base_fault_info(ioc , doorbell);
  2756. return -EFAULT;
  2757. }
  2758. } else if (int_status == 0xFFFFFFFF)
  2759. goto out;
  2760. if (sleep_flag == CAN_SLEEP)
  2761. usleep_range(1000, 1500);
  2762. else
  2763. udelay(500);
  2764. count++;
  2765. } while (--cntdn);
  2766. out:
  2767. pr_err(MPT3SAS_FMT
  2768. "%s: failed due to timeout count(%d), int_status(%x)!\n",
  2769. ioc->name, __func__, count, int_status);
  2770. return -EFAULT;
  2771. }
  2772. /**
  2773. * _base_wait_for_doorbell_not_used - waiting for doorbell to not be in use
  2774. * @ioc: per adapter object
  2775. * @timeout: timeout in second
  2776. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2777. *
  2778. * Returns 0 for success, non-zero for failure.
  2779. *
  2780. */
  2781. static int
  2782. _base_wait_for_doorbell_not_used(struct MPT3SAS_ADAPTER *ioc, int timeout,
  2783. int sleep_flag)
  2784. {
  2785. u32 cntdn, count;
  2786. u32 doorbell_reg;
  2787. count = 0;
  2788. cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
  2789. do {
  2790. doorbell_reg = readl(&ioc->chip->Doorbell);
  2791. if (!(doorbell_reg & MPI2_DOORBELL_USED)) {
  2792. dhsprintk(ioc, pr_info(MPT3SAS_FMT
  2793. "%s: successful count(%d), timeout(%d)\n",
  2794. ioc->name, __func__, count, timeout));
  2795. return 0;
  2796. }
  2797. if (sleep_flag == CAN_SLEEP)
  2798. usleep_range(1000, 1500);
  2799. else
  2800. udelay(500);
  2801. count++;
  2802. } while (--cntdn);
  2803. pr_err(MPT3SAS_FMT
  2804. "%s: failed due to timeout count(%d), doorbell_reg(%x)!\n",
  2805. ioc->name, __func__, count, doorbell_reg);
  2806. return -EFAULT;
  2807. }
  2808. /**
  2809. * _base_send_ioc_reset - send doorbell reset
  2810. * @ioc: per adapter object
  2811. * @reset_type: currently only supports: MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET
  2812. * @timeout: timeout in second
  2813. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2814. *
  2815. * Returns 0 for success, non-zero for failure.
  2816. */
  2817. static int
  2818. _base_send_ioc_reset(struct MPT3SAS_ADAPTER *ioc, u8 reset_type, int timeout,
  2819. int sleep_flag)
  2820. {
  2821. u32 ioc_state;
  2822. int r = 0;
  2823. if (reset_type != MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET) {
  2824. pr_err(MPT3SAS_FMT "%s: unknown reset_type\n",
  2825. ioc->name, __func__);
  2826. return -EFAULT;
  2827. }
  2828. if (!(ioc->facts.IOCCapabilities &
  2829. MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY))
  2830. return -EFAULT;
  2831. pr_info(MPT3SAS_FMT "sending message unit reset !!\n", ioc->name);
  2832. writel(reset_type << MPI2_DOORBELL_FUNCTION_SHIFT,
  2833. &ioc->chip->Doorbell);
  2834. if ((_base_wait_for_doorbell_ack(ioc, 15, sleep_flag))) {
  2835. r = -EFAULT;
  2836. goto out;
  2837. }
  2838. ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY,
  2839. timeout, sleep_flag);
  2840. if (ioc_state) {
  2841. pr_err(MPT3SAS_FMT
  2842. "%s: failed going to ready state (ioc_state=0x%x)\n",
  2843. ioc->name, __func__, ioc_state);
  2844. r = -EFAULT;
  2845. goto out;
  2846. }
  2847. out:
  2848. pr_info(MPT3SAS_FMT "message unit reset: %s\n",
  2849. ioc->name, ((r == 0) ? "SUCCESS" : "FAILED"));
  2850. return r;
  2851. }
  2852. /**
  2853. * _base_handshake_req_reply_wait - send request thru doorbell interface
  2854. * @ioc: per adapter object
  2855. * @request_bytes: request length
  2856. * @request: pointer having request payload
  2857. * @reply_bytes: reply length
  2858. * @reply: pointer to reply payload
  2859. * @timeout: timeout in second
  2860. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  2861. *
  2862. * Returns 0 for success, non-zero for failure.
  2863. */
  2864. static int
  2865. _base_handshake_req_reply_wait(struct MPT3SAS_ADAPTER *ioc, int request_bytes,
  2866. u32 *request, int reply_bytes, u16 *reply, int timeout, int sleep_flag)
  2867. {
  2868. MPI2DefaultReply_t *default_reply = (MPI2DefaultReply_t *)reply;
  2869. int i;
  2870. u8 failed;
  2871. u16 dummy;
  2872. __le32 *mfp;
  2873. /* make sure doorbell is not in use */
  2874. if ((readl(&ioc->chip->Doorbell) & MPI2_DOORBELL_USED)) {
  2875. pr_err(MPT3SAS_FMT
  2876. "doorbell is in use (line=%d)\n",
  2877. ioc->name, __LINE__);
  2878. return -EFAULT;
  2879. }
  2880. /* clear pending doorbell interrupts from previous state changes */
  2881. if (readl(&ioc->chip->HostInterruptStatus) &
  2882. MPI2_HIS_IOC2SYS_DB_STATUS)
  2883. writel(0, &ioc->chip->HostInterruptStatus);
  2884. /* send message to ioc */
  2885. writel(((MPI2_FUNCTION_HANDSHAKE<<MPI2_DOORBELL_FUNCTION_SHIFT) |
  2886. ((request_bytes/4)<<MPI2_DOORBELL_ADD_DWORDS_SHIFT)),
  2887. &ioc->chip->Doorbell);
  2888. if ((_base_wait_for_doorbell_int(ioc, 5, NO_SLEEP))) {
  2889. pr_err(MPT3SAS_FMT
  2890. "doorbell handshake int failed (line=%d)\n",
  2891. ioc->name, __LINE__);
  2892. return -EFAULT;
  2893. }
  2894. writel(0, &ioc->chip->HostInterruptStatus);
  2895. if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag))) {
  2896. pr_err(MPT3SAS_FMT
  2897. "doorbell handshake ack failed (line=%d)\n",
  2898. ioc->name, __LINE__);
  2899. return -EFAULT;
  2900. }
  2901. /* send message 32-bits at a time */
  2902. for (i = 0, failed = 0; i < request_bytes/4 && !failed; i++) {
  2903. writel(cpu_to_le32(request[i]), &ioc->chip->Doorbell);
  2904. if ((_base_wait_for_doorbell_ack(ioc, 5, sleep_flag)))
  2905. failed = 1;
  2906. }
  2907. if (failed) {
  2908. pr_err(MPT3SAS_FMT
  2909. "doorbell handshake sending request failed (line=%d)\n",
  2910. ioc->name, __LINE__);
  2911. return -EFAULT;
  2912. }
  2913. /* now wait for the reply */
  2914. if ((_base_wait_for_doorbell_int(ioc, timeout, sleep_flag))) {
  2915. pr_err(MPT3SAS_FMT
  2916. "doorbell handshake int failed (line=%d)\n",
  2917. ioc->name, __LINE__);
  2918. return -EFAULT;
  2919. }
  2920. /* read the first two 16-bits, it gives the total length of the reply */
  2921. reply[0] = le16_to_cpu(readl(&ioc->chip->Doorbell)
  2922. & MPI2_DOORBELL_DATA_MASK);
  2923. writel(0, &ioc->chip->HostInterruptStatus);
  2924. if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
  2925. pr_err(MPT3SAS_FMT
  2926. "doorbell handshake int failed (line=%d)\n",
  2927. ioc->name, __LINE__);
  2928. return -EFAULT;
  2929. }
  2930. reply[1] = le16_to_cpu(readl(&ioc->chip->Doorbell)
  2931. & MPI2_DOORBELL_DATA_MASK);
  2932. writel(0, &ioc->chip->HostInterruptStatus);
  2933. for (i = 2; i < default_reply->MsgLength * 2; i++) {
  2934. if ((_base_wait_for_doorbell_int(ioc, 5, sleep_flag))) {
  2935. pr_err(MPT3SAS_FMT
  2936. "doorbell handshake int failed (line=%d)\n",
  2937. ioc->name, __LINE__);
  2938. return -EFAULT;
  2939. }
  2940. if (i >= reply_bytes/2) /* overflow case */
  2941. dummy = readl(&ioc->chip->Doorbell);
  2942. else
  2943. reply[i] = le16_to_cpu(readl(&ioc->chip->Doorbell)
  2944. & MPI2_DOORBELL_DATA_MASK);
  2945. writel(0, &ioc->chip->HostInterruptStatus);
  2946. }
  2947. _base_wait_for_doorbell_int(ioc, 5, sleep_flag);
  2948. if (_base_wait_for_doorbell_not_used(ioc, 5, sleep_flag) != 0) {
  2949. dhsprintk(ioc, pr_info(MPT3SAS_FMT
  2950. "doorbell is in use (line=%d)\n", ioc->name, __LINE__));
  2951. }
  2952. writel(0, &ioc->chip->HostInterruptStatus);
  2953. if (ioc->logging_level & MPT_DEBUG_INIT) {
  2954. mfp = (__le32 *)reply;
  2955. pr_info("\toffset:data\n");
  2956. for (i = 0; i < reply_bytes/4; i++)
  2957. pr_info("\t[0x%02x]:%08x\n", i*4,
  2958. le32_to_cpu(mfp[i]));
  2959. }
  2960. return 0;
  2961. }
  2962. /**
  2963. * mpt3sas_base_sas_iounit_control - send sas iounit control to FW
  2964. * @ioc: per adapter object
  2965. * @mpi_reply: the reply payload from FW
  2966. * @mpi_request: the request payload sent to FW
  2967. *
  2968. * The SAS IO Unit Control Request message allows the host to perform low-level
  2969. * operations, such as resets on the PHYs of the IO Unit, also allows the host
  2970. * to obtain the IOC assigned device handles for a device if it has other
  2971. * identifying information about the device, in addition allows the host to
  2972. * remove IOC resources associated with the device.
  2973. *
  2974. * Returns 0 for success, non-zero for failure.
  2975. */
  2976. int
  2977. mpt3sas_base_sas_iounit_control(struct MPT3SAS_ADAPTER *ioc,
  2978. Mpi2SasIoUnitControlReply_t *mpi_reply,
  2979. Mpi2SasIoUnitControlRequest_t *mpi_request)
  2980. {
  2981. u16 smid;
  2982. u32 ioc_state;
  2983. unsigned long timeleft;
  2984. u8 issue_reset;
  2985. int rc;
  2986. void *request;
  2987. u16 wait_state_count;
  2988. dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  2989. __func__));
  2990. mutex_lock(&ioc->base_cmds.mutex);
  2991. if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
  2992. pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
  2993. ioc->name, __func__);
  2994. rc = -EAGAIN;
  2995. goto out;
  2996. }
  2997. wait_state_count = 0;
  2998. ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
  2999. while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
  3000. if (wait_state_count++ == 10) {
  3001. pr_err(MPT3SAS_FMT
  3002. "%s: failed due to ioc not operational\n",
  3003. ioc->name, __func__);
  3004. rc = -EFAULT;
  3005. goto out;
  3006. }
  3007. ssleep(1);
  3008. ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
  3009. pr_info(MPT3SAS_FMT
  3010. "%s: waiting for operational state(count=%d)\n",
  3011. ioc->name, __func__, wait_state_count);
  3012. }
  3013. smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
  3014. if (!smid) {
  3015. pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
  3016. ioc->name, __func__);
  3017. rc = -EAGAIN;
  3018. goto out;
  3019. }
  3020. rc = 0;
  3021. ioc->base_cmds.status = MPT3_CMD_PENDING;
  3022. request = mpt3sas_base_get_msg_frame(ioc, smid);
  3023. ioc->base_cmds.smid = smid;
  3024. memcpy(request, mpi_request, sizeof(Mpi2SasIoUnitControlRequest_t));
  3025. if (mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
  3026. mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET)
  3027. ioc->ioc_link_reset_in_progress = 1;
  3028. init_completion(&ioc->base_cmds.done);
  3029. mpt3sas_base_put_smid_default(ioc, smid);
  3030. timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
  3031. msecs_to_jiffies(10000));
  3032. if ((mpi_request->Operation == MPI2_SAS_OP_PHY_HARD_RESET ||
  3033. mpi_request->Operation == MPI2_SAS_OP_PHY_LINK_RESET) &&
  3034. ioc->ioc_link_reset_in_progress)
  3035. ioc->ioc_link_reset_in_progress = 0;
  3036. if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
  3037. pr_err(MPT3SAS_FMT "%s: timeout\n",
  3038. ioc->name, __func__);
  3039. _debug_dump_mf(mpi_request,
  3040. sizeof(Mpi2SasIoUnitControlRequest_t)/4);
  3041. if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
  3042. issue_reset = 1;
  3043. goto issue_host_reset;
  3044. }
  3045. if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
  3046. memcpy(mpi_reply, ioc->base_cmds.reply,
  3047. sizeof(Mpi2SasIoUnitControlReply_t));
  3048. else
  3049. memset(mpi_reply, 0, sizeof(Mpi2SasIoUnitControlReply_t));
  3050. ioc->base_cmds.status = MPT3_CMD_NOT_USED;
  3051. goto out;
  3052. issue_host_reset:
  3053. if (issue_reset)
  3054. mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
  3055. FORCE_BIG_HAMMER);
  3056. ioc->base_cmds.status = MPT3_CMD_NOT_USED;
  3057. rc = -EFAULT;
  3058. out:
  3059. mutex_unlock(&ioc->base_cmds.mutex);
  3060. return rc;
  3061. }
  3062. /**
  3063. * mpt3sas_base_scsi_enclosure_processor - sending request to sep device
  3064. * @ioc: per adapter object
  3065. * @mpi_reply: the reply payload from FW
  3066. * @mpi_request: the request payload sent to FW
  3067. *
  3068. * The SCSI Enclosure Processor request message causes the IOC to
  3069. * communicate with SES devices to control LED status signals.
  3070. *
  3071. * Returns 0 for success, non-zero for failure.
  3072. */
  3073. int
  3074. mpt3sas_base_scsi_enclosure_processor(struct MPT3SAS_ADAPTER *ioc,
  3075. Mpi2SepReply_t *mpi_reply, Mpi2SepRequest_t *mpi_request)
  3076. {
  3077. u16 smid;
  3078. u32 ioc_state;
  3079. unsigned long timeleft;
  3080. u8 issue_reset;
  3081. int rc;
  3082. void *request;
  3083. u16 wait_state_count;
  3084. dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  3085. __func__));
  3086. mutex_lock(&ioc->base_cmds.mutex);
  3087. if (ioc->base_cmds.status != MPT3_CMD_NOT_USED) {
  3088. pr_err(MPT3SAS_FMT "%s: base_cmd in use\n",
  3089. ioc->name, __func__);
  3090. rc = -EAGAIN;
  3091. goto out;
  3092. }
  3093. wait_state_count = 0;
  3094. ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
  3095. while (ioc_state != MPI2_IOC_STATE_OPERATIONAL) {
  3096. if (wait_state_count++ == 10) {
  3097. pr_err(MPT3SAS_FMT
  3098. "%s: failed due to ioc not operational\n",
  3099. ioc->name, __func__);
  3100. rc = -EFAULT;
  3101. goto out;
  3102. }
  3103. ssleep(1);
  3104. ioc_state = mpt3sas_base_get_iocstate(ioc, 1);
  3105. pr_info(MPT3SAS_FMT
  3106. "%s: waiting for operational state(count=%d)\n",
  3107. ioc->name,
  3108. __func__, wait_state_count);
  3109. }
  3110. smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
  3111. if (!smid) {
  3112. pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
  3113. ioc->name, __func__);
  3114. rc = -EAGAIN;
  3115. goto out;
  3116. }
  3117. rc = 0;
  3118. ioc->base_cmds.status = MPT3_CMD_PENDING;
  3119. request = mpt3sas_base_get_msg_frame(ioc, smid);
  3120. ioc->base_cmds.smid = smid;
  3121. memcpy(request, mpi_request, sizeof(Mpi2SepReply_t));
  3122. init_completion(&ioc->base_cmds.done);
  3123. mpt3sas_base_put_smid_default(ioc, smid);
  3124. timeleft = wait_for_completion_timeout(&ioc->base_cmds.done,
  3125. msecs_to_jiffies(10000));
  3126. if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
  3127. pr_err(MPT3SAS_FMT "%s: timeout\n",
  3128. ioc->name, __func__);
  3129. _debug_dump_mf(mpi_request,
  3130. sizeof(Mpi2SepRequest_t)/4);
  3131. if (!(ioc->base_cmds.status & MPT3_CMD_RESET))
  3132. issue_reset = 1;
  3133. goto issue_host_reset;
  3134. }
  3135. if (ioc->base_cmds.status & MPT3_CMD_REPLY_VALID)
  3136. memcpy(mpi_reply, ioc->base_cmds.reply,
  3137. sizeof(Mpi2SepReply_t));
  3138. else
  3139. memset(mpi_reply, 0, sizeof(Mpi2SepReply_t));
  3140. ioc->base_cmds.status = MPT3_CMD_NOT_USED;
  3141. goto out;
  3142. issue_host_reset:
  3143. if (issue_reset)
  3144. mpt3sas_base_hard_reset_handler(ioc, CAN_SLEEP,
  3145. FORCE_BIG_HAMMER);
  3146. ioc->base_cmds.status = MPT3_CMD_NOT_USED;
  3147. rc = -EFAULT;
  3148. out:
  3149. mutex_unlock(&ioc->base_cmds.mutex);
  3150. return rc;
  3151. }
  3152. /**
  3153. * _base_get_port_facts - obtain port facts reply and save in ioc
  3154. * @ioc: per adapter object
  3155. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3156. *
  3157. * Returns 0 for success, non-zero for failure.
  3158. */
  3159. static int
  3160. _base_get_port_facts(struct MPT3SAS_ADAPTER *ioc, int port, int sleep_flag)
  3161. {
  3162. Mpi2PortFactsRequest_t mpi_request;
  3163. Mpi2PortFactsReply_t mpi_reply;
  3164. struct mpt3sas_port_facts *pfacts;
  3165. int mpi_reply_sz, mpi_request_sz, r;
  3166. dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  3167. __func__));
  3168. mpi_reply_sz = sizeof(Mpi2PortFactsReply_t);
  3169. mpi_request_sz = sizeof(Mpi2PortFactsRequest_t);
  3170. memset(&mpi_request, 0, mpi_request_sz);
  3171. mpi_request.Function = MPI2_FUNCTION_PORT_FACTS;
  3172. mpi_request.PortNumber = port;
  3173. r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
  3174. (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
  3175. if (r != 0) {
  3176. pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
  3177. ioc->name, __func__, r);
  3178. return r;
  3179. }
  3180. pfacts = &ioc->pfacts[port];
  3181. memset(pfacts, 0, sizeof(struct mpt3sas_port_facts));
  3182. pfacts->PortNumber = mpi_reply.PortNumber;
  3183. pfacts->VP_ID = mpi_reply.VP_ID;
  3184. pfacts->VF_ID = mpi_reply.VF_ID;
  3185. pfacts->MaxPostedCmdBuffers =
  3186. le16_to_cpu(mpi_reply.MaxPostedCmdBuffers);
  3187. return 0;
  3188. }
  3189. /**
  3190. * _base_get_ioc_facts - obtain ioc facts reply and save in ioc
  3191. * @ioc: per adapter object
  3192. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3193. *
  3194. * Returns 0 for success, non-zero for failure.
  3195. */
  3196. static int
  3197. _base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
  3198. {
  3199. Mpi2IOCFactsRequest_t mpi_request;
  3200. Mpi2IOCFactsReply_t mpi_reply;
  3201. struct mpt3sas_facts *facts;
  3202. int mpi_reply_sz, mpi_request_sz, r;
  3203. dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  3204. __func__));
  3205. mpi_reply_sz = sizeof(Mpi2IOCFactsReply_t);
  3206. mpi_request_sz = sizeof(Mpi2IOCFactsRequest_t);
  3207. memset(&mpi_request, 0, mpi_request_sz);
  3208. mpi_request.Function = MPI2_FUNCTION_IOC_FACTS;
  3209. r = _base_handshake_req_reply_wait(ioc, mpi_request_sz,
  3210. (u32 *)&mpi_request, mpi_reply_sz, (u16 *)&mpi_reply, 5, CAN_SLEEP);
  3211. if (r != 0) {
  3212. pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
  3213. ioc->name, __func__, r);
  3214. return r;
  3215. }
  3216. facts = &ioc->facts;
  3217. memset(facts, 0, sizeof(struct mpt3sas_facts));
  3218. facts->MsgVersion = le16_to_cpu(mpi_reply.MsgVersion);
  3219. facts->HeaderVersion = le16_to_cpu(mpi_reply.HeaderVersion);
  3220. facts->VP_ID = mpi_reply.VP_ID;
  3221. facts->VF_ID = mpi_reply.VF_ID;
  3222. facts->IOCExceptions = le16_to_cpu(mpi_reply.IOCExceptions);
  3223. facts->MaxChainDepth = mpi_reply.MaxChainDepth;
  3224. facts->WhoInit = mpi_reply.WhoInit;
  3225. facts->NumberOfPorts = mpi_reply.NumberOfPorts;
  3226. facts->MaxMSIxVectors = mpi_reply.MaxMSIxVectors;
  3227. facts->RequestCredit = le16_to_cpu(mpi_reply.RequestCredit);
  3228. facts->MaxReplyDescriptorPostQueueDepth =
  3229. le16_to_cpu(mpi_reply.MaxReplyDescriptorPostQueueDepth);
  3230. facts->ProductID = le16_to_cpu(mpi_reply.ProductID);
  3231. facts->IOCCapabilities = le32_to_cpu(mpi_reply.IOCCapabilities);
  3232. if ((facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID))
  3233. ioc->ir_firmware = 1;
  3234. facts->FWVersion.Word = le32_to_cpu(mpi_reply.FWVersion.Word);
  3235. facts->IOCRequestFrameSize =
  3236. le16_to_cpu(mpi_reply.IOCRequestFrameSize);
  3237. facts->MaxInitiators = le16_to_cpu(mpi_reply.MaxInitiators);
  3238. facts->MaxTargets = le16_to_cpu(mpi_reply.MaxTargets);
  3239. ioc->shost->max_id = -1;
  3240. facts->MaxSasExpanders = le16_to_cpu(mpi_reply.MaxSasExpanders);
  3241. facts->MaxEnclosures = le16_to_cpu(mpi_reply.MaxEnclosures);
  3242. facts->ProtocolFlags = le16_to_cpu(mpi_reply.ProtocolFlags);
  3243. facts->HighPriorityCredit =
  3244. le16_to_cpu(mpi_reply.HighPriorityCredit);
  3245. facts->ReplyFrameSize = mpi_reply.ReplyFrameSize;
  3246. facts->MaxDevHandle = le16_to_cpu(mpi_reply.MaxDevHandle);
  3247. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  3248. "hba queue depth(%d), max chains per io(%d)\n",
  3249. ioc->name, facts->RequestCredit,
  3250. facts->MaxChainDepth));
  3251. dinitprintk(ioc, pr_info(MPT3SAS_FMT
  3252. "request frame size(%d), reply frame size(%d)\n", ioc->name,
  3253. facts->IOCRequestFrameSize * 4, facts->ReplyFrameSize * 4));
  3254. return 0;
  3255. }
  3256. /**
  3257. * _base_send_ioc_init - send ioc_init to firmware
  3258. * @ioc: per adapter object
  3259. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3260. *
  3261. * Returns 0 for success, non-zero for failure.
  3262. */
  3263. static int
  3264. _base_send_ioc_init(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
  3265. {
  3266. Mpi2IOCInitRequest_t mpi_request;
  3267. Mpi2IOCInitReply_t mpi_reply;
  3268. int r;
  3269. struct timeval current_time;
  3270. u16 ioc_status;
  3271. dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  3272. __func__));
  3273. memset(&mpi_request, 0, sizeof(Mpi2IOCInitRequest_t));
  3274. mpi_request.Function = MPI2_FUNCTION_IOC_INIT;
  3275. mpi_request.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
  3276. mpi_request.VF_ID = 0; /* TODO */
  3277. mpi_request.VP_ID = 0;
  3278. mpi_request.MsgVersion = cpu_to_le16(MPI2_VERSION);
  3279. mpi_request.HeaderVersion = cpu_to_le16(MPI2_HEADER_VERSION);
  3280. if (_base_is_controller_msix_enabled(ioc))
  3281. mpi_request.HostMSIxVectors = ioc->reply_queue_count;
  3282. mpi_request.SystemRequestFrameSize = cpu_to_le16(ioc->request_sz/4);
  3283. mpi_request.ReplyDescriptorPostQueueDepth =
  3284. cpu_to_le16(ioc->reply_post_queue_depth);
  3285. mpi_request.ReplyFreeQueueDepth =
  3286. cpu_to_le16(ioc->reply_free_queue_depth);
  3287. mpi_request.SenseBufferAddressHigh =
  3288. cpu_to_le32((u64)ioc->sense_dma >> 32);
  3289. mpi_request.SystemReplyAddressHigh =
  3290. cpu_to_le32((u64)ioc->reply_dma >> 32);
  3291. mpi_request.SystemRequestFrameBaseAddress =
  3292. cpu_to_le64((u64)ioc->request_dma);
  3293. mpi_request.ReplyFreeQueueAddress =
  3294. cpu_to_le64((u64)ioc->reply_free_dma);
  3295. mpi_request.ReplyDescriptorPostQueueAddress =
  3296. cpu_to_le64((u64)ioc->reply_post_free_dma);
  3297. /* This time stamp specifies number of milliseconds
  3298. * since epoch ~ midnight January 1, 1970.
  3299. */
  3300. do_gettimeofday(&current_time);
  3301. mpi_request.TimeStamp = cpu_to_le64((u64)current_time.tv_sec * 1000 +
  3302. (current_time.tv_usec / 1000));
  3303. if (ioc->logging_level & MPT_DEBUG_INIT) {
  3304. __le32 *mfp;
  3305. int i;
  3306. mfp = (__le32 *)&mpi_request;
  3307. pr_info("\toffset:data\n");
  3308. for (i = 0; i < sizeof(Mpi2IOCInitRequest_t)/4; i++)
  3309. pr_info("\t[0x%02x]:%08x\n", i*4,
  3310. le32_to_cpu(mfp[i]));
  3311. }
  3312. r = _base_handshake_req_reply_wait(ioc,
  3313. sizeof(Mpi2IOCInitRequest_t), (u32 *)&mpi_request,
  3314. sizeof(Mpi2IOCInitReply_t), (u16 *)&mpi_reply, 10,
  3315. sleep_flag);
  3316. if (r != 0) {
  3317. pr_err(MPT3SAS_FMT "%s: handshake failed (r=%d)\n",
  3318. ioc->name, __func__, r);
  3319. return r;
  3320. }
  3321. ioc_status = le16_to_cpu(mpi_reply.IOCStatus) & MPI2_IOCSTATUS_MASK;
  3322. if (ioc_status != MPI2_IOCSTATUS_SUCCESS ||
  3323. mpi_reply.IOCLogInfo) {
  3324. pr_err(MPT3SAS_FMT "%s: failed\n", ioc->name, __func__);
  3325. r = -EIO;
  3326. }
  3327. return 0;
  3328. }
  3329. /**
  3330. * mpt3sas_port_enable_done - command completion routine for port enable
  3331. * @ioc: per adapter object
  3332. * @smid: system request message index
  3333. * @msix_index: MSIX table index supplied by the OS
  3334. * @reply: reply message frame(lower 32bit addr)
  3335. *
  3336. * Return 1 meaning mf should be freed from _base_interrupt
  3337. * 0 means the mf is freed from this function.
  3338. */
  3339. u8
  3340. mpt3sas_port_enable_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
  3341. u32 reply)
  3342. {
  3343. MPI2DefaultReply_t *mpi_reply;
  3344. u16 ioc_status;
  3345. if (ioc->port_enable_cmds.status == MPT3_CMD_NOT_USED)
  3346. return 1;
  3347. mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
  3348. if (!mpi_reply)
  3349. return 1;
  3350. if (mpi_reply->Function != MPI2_FUNCTION_PORT_ENABLE)
  3351. return 1;
  3352. ioc->port_enable_cmds.status &= ~MPT3_CMD_PENDING;
  3353. ioc->port_enable_cmds.status |= MPT3_CMD_COMPLETE;
  3354. ioc->port_enable_cmds.status |= MPT3_CMD_REPLY_VALID;
  3355. memcpy(ioc->port_enable_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
  3356. ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
  3357. if (ioc_status != MPI2_IOCSTATUS_SUCCESS)
  3358. ioc->port_enable_failed = 1;
  3359. if (ioc->is_driver_loading) {
  3360. if (ioc_status == MPI2_IOCSTATUS_SUCCESS) {
  3361. mpt3sas_port_enable_complete(ioc);
  3362. return 1;
  3363. } else {
  3364. ioc->start_scan_failed = ioc_status;
  3365. ioc->start_scan = 0;
  3366. return 1;
  3367. }
  3368. }
  3369. complete(&ioc->port_enable_cmds.done);
  3370. return 1;
  3371. }
  3372. /**
  3373. * _base_send_port_enable - send port_enable(discovery stuff) to firmware
  3374. * @ioc: per adapter object
  3375. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3376. *
  3377. * Returns 0 for success, non-zero for failure.
  3378. */
  3379. static int
  3380. _base_send_port_enable(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
  3381. {
  3382. Mpi2PortEnableRequest_t *mpi_request;
  3383. Mpi2PortEnableReply_t *mpi_reply;
  3384. unsigned long timeleft;
  3385. int r = 0;
  3386. u16 smid;
  3387. u16 ioc_status;
  3388. pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
  3389. if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
  3390. pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
  3391. ioc->name, __func__);
  3392. return -EAGAIN;
  3393. }
  3394. smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
  3395. if (!smid) {
  3396. pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
  3397. ioc->name, __func__);
  3398. return -EAGAIN;
  3399. }
  3400. ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
  3401. mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
  3402. ioc->port_enable_cmds.smid = smid;
  3403. memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
  3404. mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
  3405. init_completion(&ioc->port_enable_cmds.done);
  3406. mpt3sas_base_put_smid_default(ioc, smid);
  3407. timeleft = wait_for_completion_timeout(&ioc->port_enable_cmds.done,
  3408. 300*HZ);
  3409. if (!(ioc->port_enable_cmds.status & MPT3_CMD_COMPLETE)) {
  3410. pr_err(MPT3SAS_FMT "%s: timeout\n",
  3411. ioc->name, __func__);
  3412. _debug_dump_mf(mpi_request,
  3413. sizeof(Mpi2PortEnableRequest_t)/4);
  3414. if (ioc->port_enable_cmds.status & MPT3_CMD_RESET)
  3415. r = -EFAULT;
  3416. else
  3417. r = -ETIME;
  3418. goto out;
  3419. }
  3420. mpi_reply = ioc->port_enable_cmds.reply;
  3421. ioc_status = le16_to_cpu(mpi_reply->IOCStatus) & MPI2_IOCSTATUS_MASK;
  3422. if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
  3423. pr_err(MPT3SAS_FMT "%s: failed with (ioc_status=0x%08x)\n",
  3424. ioc->name, __func__, ioc_status);
  3425. r = -EFAULT;
  3426. goto out;
  3427. }
  3428. out:
  3429. ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
  3430. pr_info(MPT3SAS_FMT "port enable: %s\n", ioc->name, ((r == 0) ?
  3431. "SUCCESS" : "FAILED"));
  3432. return r;
  3433. }
  3434. /**
  3435. * mpt3sas_port_enable - initiate firmware discovery (don't wait for reply)
  3436. * @ioc: per adapter object
  3437. *
  3438. * Returns 0 for success, non-zero for failure.
  3439. */
  3440. int
  3441. mpt3sas_port_enable(struct MPT3SAS_ADAPTER *ioc)
  3442. {
  3443. Mpi2PortEnableRequest_t *mpi_request;
  3444. u16 smid;
  3445. pr_info(MPT3SAS_FMT "sending port enable !!\n", ioc->name);
  3446. if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
  3447. pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
  3448. ioc->name, __func__);
  3449. return -EAGAIN;
  3450. }
  3451. smid = mpt3sas_base_get_smid(ioc, ioc->port_enable_cb_idx);
  3452. if (!smid) {
  3453. pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
  3454. ioc->name, __func__);
  3455. return -EAGAIN;
  3456. }
  3457. ioc->port_enable_cmds.status = MPT3_CMD_PENDING;
  3458. mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
  3459. ioc->port_enable_cmds.smid = smid;
  3460. memset(mpi_request, 0, sizeof(Mpi2PortEnableRequest_t));
  3461. mpi_request->Function = MPI2_FUNCTION_PORT_ENABLE;
  3462. mpt3sas_base_put_smid_default(ioc, smid);
  3463. return 0;
  3464. }
  3465. /**
  3466. * _base_determine_wait_on_discovery - desposition
  3467. * @ioc: per adapter object
  3468. *
  3469. * Decide whether to wait on discovery to complete. Used to either
  3470. * locate boot device, or report volumes ahead of physical devices.
  3471. *
  3472. * Returns 1 for wait, 0 for don't wait
  3473. */
  3474. static int
  3475. _base_determine_wait_on_discovery(struct MPT3SAS_ADAPTER *ioc)
  3476. {
  3477. /* We wait for discovery to complete if IR firmware is loaded.
  3478. * The sas topology events arrive before PD events, so we need time to
  3479. * turn on the bit in ioc->pd_handles to indicate PD
  3480. * Also, it maybe required to report Volumes ahead of physical
  3481. * devices when MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING is set.
  3482. */
  3483. if (ioc->ir_firmware)
  3484. return 1;
  3485. /* if no Bios, then we don't need to wait */
  3486. if (!ioc->bios_pg3.BiosVersion)
  3487. return 0;
  3488. /* Bios is present, then we drop down here.
  3489. *
  3490. * If there any entries in the Bios Page 2, then we wait
  3491. * for discovery to complete.
  3492. */
  3493. /* Current Boot Device */
  3494. if ((ioc->bios_pg2.CurrentBootDeviceForm &
  3495. MPI2_BIOSPAGE2_FORM_MASK) ==
  3496. MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
  3497. /* Request Boot Device */
  3498. (ioc->bios_pg2.ReqBootDeviceForm &
  3499. MPI2_BIOSPAGE2_FORM_MASK) ==
  3500. MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED &&
  3501. /* Alternate Request Boot Device */
  3502. (ioc->bios_pg2.ReqAltBootDeviceForm &
  3503. MPI2_BIOSPAGE2_FORM_MASK) ==
  3504. MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED)
  3505. return 0;
  3506. return 1;
  3507. }
  3508. /**
  3509. * _base_unmask_events - turn on notification for this event
  3510. * @ioc: per adapter object
  3511. * @event: firmware event
  3512. *
  3513. * The mask is stored in ioc->event_masks.
  3514. */
  3515. static void
  3516. _base_unmask_events(struct MPT3SAS_ADAPTER *ioc, u16 event)
  3517. {
  3518. u32 desired_event;
  3519. if (event >= 128)
  3520. return;
  3521. desired_event = (1 << (event % 32));
  3522. if (event < 32)
  3523. ioc->event_masks[0] &= ~desired_event;
  3524. else if (event < 64)
  3525. ioc->event_masks[1] &= ~desired_event;
  3526. else if (event < 96)
  3527. ioc->event_masks[2] &= ~desired_event;
  3528. else if (event < 128)
  3529. ioc->event_masks[3] &= ~desired_event;
  3530. }
  3531. /**
  3532. * _base_event_notification - send event notification
  3533. * @ioc: per adapter object
  3534. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3535. *
  3536. * Returns 0 for success, non-zero for failure.
  3537. */
  3538. static int
  3539. _base_event_notification(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
  3540. {
  3541. Mpi2EventNotificationRequest_t *mpi_request;
  3542. unsigned long timeleft;
  3543. u16 smid;
  3544. int r = 0;
  3545. int i;
  3546. dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  3547. __func__));
  3548. if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
  3549. pr_err(MPT3SAS_FMT "%s: internal command already in use\n",
  3550. ioc->name, __func__);
  3551. return -EAGAIN;
  3552. }
  3553. smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
  3554. if (!smid) {
  3555. pr_err(MPT3SAS_FMT "%s: failed obtaining a smid\n",
  3556. ioc->name, __func__);
  3557. return -EAGAIN;
  3558. }
  3559. ioc->base_cmds.status = MPT3_CMD_PENDING;
  3560. mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
  3561. ioc->base_cmds.smid = smid;
  3562. memset(mpi_request, 0, sizeof(Mpi2EventNotificationRequest_t));
  3563. mpi_request->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
  3564. mpi_request->VF_ID = 0; /* TODO */
  3565. mpi_request->VP_ID = 0;
  3566. for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
  3567. mpi_request->EventMasks[i] =
  3568. cpu_to_le32(ioc->event_masks[i]);
  3569. init_completion(&ioc->base_cmds.done);
  3570. mpt3sas_base_put_smid_default(ioc, smid);
  3571. timeleft = wait_for_completion_timeout(&ioc->base_cmds.done, 30*HZ);
  3572. if (!(ioc->base_cmds.status & MPT3_CMD_COMPLETE)) {
  3573. pr_err(MPT3SAS_FMT "%s: timeout\n",
  3574. ioc->name, __func__);
  3575. _debug_dump_mf(mpi_request,
  3576. sizeof(Mpi2EventNotificationRequest_t)/4);
  3577. if (ioc->base_cmds.status & MPT3_CMD_RESET)
  3578. r = -EFAULT;
  3579. else
  3580. r = -ETIME;
  3581. } else
  3582. dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s: complete\n",
  3583. ioc->name, __func__));
  3584. ioc->base_cmds.status = MPT3_CMD_NOT_USED;
  3585. return r;
  3586. }
  3587. /**
  3588. * mpt3sas_base_validate_event_type - validating event types
  3589. * @ioc: per adapter object
  3590. * @event: firmware event
  3591. *
  3592. * This will turn on firmware event notification when application
  3593. * ask for that event. We don't mask events that are already enabled.
  3594. */
  3595. void
  3596. mpt3sas_base_validate_event_type(struct MPT3SAS_ADAPTER *ioc, u32 *event_type)
  3597. {
  3598. int i, j;
  3599. u32 event_mask, desired_event;
  3600. u8 send_update_to_fw;
  3601. for (i = 0, send_update_to_fw = 0; i <
  3602. MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++) {
  3603. event_mask = ~event_type[i];
  3604. desired_event = 1;
  3605. for (j = 0; j < 32; j++) {
  3606. if (!(event_mask & desired_event) &&
  3607. (ioc->event_masks[i] & desired_event)) {
  3608. ioc->event_masks[i] &= ~desired_event;
  3609. send_update_to_fw = 1;
  3610. }
  3611. desired_event = (desired_event << 1);
  3612. }
  3613. }
  3614. if (!send_update_to_fw)
  3615. return;
  3616. mutex_lock(&ioc->base_cmds.mutex);
  3617. _base_event_notification(ioc, CAN_SLEEP);
  3618. mutex_unlock(&ioc->base_cmds.mutex);
  3619. }
  3620. /**
  3621. * _base_diag_reset - the "big hammer" start of day reset
  3622. * @ioc: per adapter object
  3623. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3624. *
  3625. * Returns 0 for success, non-zero for failure.
  3626. */
  3627. static int
  3628. _base_diag_reset(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
  3629. {
  3630. u32 host_diagnostic;
  3631. u32 ioc_state;
  3632. u32 count;
  3633. u32 hcb_size;
  3634. pr_info(MPT3SAS_FMT "sending diag reset !!\n", ioc->name);
  3635. drsprintk(ioc, pr_info(MPT3SAS_FMT "clear interrupts\n",
  3636. ioc->name));
  3637. count = 0;
  3638. do {
  3639. /* Write magic sequence to WriteSequence register
  3640. * Loop until in diagnostic mode
  3641. */
  3642. drsprintk(ioc, pr_info(MPT3SAS_FMT
  3643. "write magic sequence\n", ioc->name));
  3644. writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
  3645. writel(MPI2_WRSEQ_1ST_KEY_VALUE, &ioc->chip->WriteSequence);
  3646. writel(MPI2_WRSEQ_2ND_KEY_VALUE, &ioc->chip->WriteSequence);
  3647. writel(MPI2_WRSEQ_3RD_KEY_VALUE, &ioc->chip->WriteSequence);
  3648. writel(MPI2_WRSEQ_4TH_KEY_VALUE, &ioc->chip->WriteSequence);
  3649. writel(MPI2_WRSEQ_5TH_KEY_VALUE, &ioc->chip->WriteSequence);
  3650. writel(MPI2_WRSEQ_6TH_KEY_VALUE, &ioc->chip->WriteSequence);
  3651. /* wait 100 msec */
  3652. if (sleep_flag == CAN_SLEEP)
  3653. msleep(100);
  3654. else
  3655. mdelay(100);
  3656. if (count++ > 20)
  3657. goto out;
  3658. host_diagnostic = readl(&ioc->chip->HostDiagnostic);
  3659. drsprintk(ioc, pr_info(MPT3SAS_FMT
  3660. "wrote magic sequence: count(%d), host_diagnostic(0x%08x)\n",
  3661. ioc->name, count, host_diagnostic));
  3662. } while ((host_diagnostic & MPI2_DIAG_DIAG_WRITE_ENABLE) == 0);
  3663. hcb_size = readl(&ioc->chip->HCBSize);
  3664. drsprintk(ioc, pr_info(MPT3SAS_FMT "diag reset: issued\n",
  3665. ioc->name));
  3666. writel(host_diagnostic | MPI2_DIAG_RESET_ADAPTER,
  3667. &ioc->chip->HostDiagnostic);
  3668. /*This delay allows the chip PCIe hardware time to finish reset tasks*/
  3669. if (sleep_flag == CAN_SLEEP)
  3670. msleep(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
  3671. else
  3672. mdelay(MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC/1000);
  3673. /* Approximately 300 second max wait */
  3674. for (count = 0; count < (300000000 /
  3675. MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC); count++) {
  3676. host_diagnostic = readl(&ioc->chip->HostDiagnostic);
  3677. if (host_diagnostic == 0xFFFFFFFF)
  3678. goto out;
  3679. if (!(host_diagnostic & MPI2_DIAG_RESET_ADAPTER))
  3680. break;
  3681. /* Wait to pass the second read delay window */
  3682. if (sleep_flag == CAN_SLEEP)
  3683. msleep(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
  3684. / 1000);
  3685. else
  3686. mdelay(MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC
  3687. / 1000);
  3688. }
  3689. if (host_diagnostic & MPI2_DIAG_HCB_MODE) {
  3690. drsprintk(ioc, pr_info(MPT3SAS_FMT
  3691. "restart the adapter assuming the HCB Address points to good F/W\n",
  3692. ioc->name));
  3693. host_diagnostic &= ~MPI2_DIAG_BOOT_DEVICE_SELECT_MASK;
  3694. host_diagnostic |= MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW;
  3695. writel(host_diagnostic, &ioc->chip->HostDiagnostic);
  3696. drsprintk(ioc, pr_info(MPT3SAS_FMT
  3697. "re-enable the HCDW\n", ioc->name));
  3698. writel(hcb_size | MPI2_HCB_SIZE_HCB_ENABLE,
  3699. &ioc->chip->HCBSize);
  3700. }
  3701. drsprintk(ioc, pr_info(MPT3SAS_FMT "restart the adapter\n",
  3702. ioc->name));
  3703. writel(host_diagnostic & ~MPI2_DIAG_HOLD_IOC_RESET,
  3704. &ioc->chip->HostDiagnostic);
  3705. drsprintk(ioc, pr_info(MPT3SAS_FMT
  3706. "disable writes to the diagnostic register\n", ioc->name));
  3707. writel(MPI2_WRSEQ_FLUSH_KEY_VALUE, &ioc->chip->WriteSequence);
  3708. drsprintk(ioc, pr_info(MPT3SAS_FMT
  3709. "Wait for FW to go to the READY state\n", ioc->name));
  3710. ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_READY, 20,
  3711. sleep_flag);
  3712. if (ioc_state) {
  3713. pr_err(MPT3SAS_FMT
  3714. "%s: failed going to ready state (ioc_state=0x%x)\n",
  3715. ioc->name, __func__, ioc_state);
  3716. goto out;
  3717. }
  3718. pr_info(MPT3SAS_FMT "diag reset: SUCCESS\n", ioc->name);
  3719. return 0;
  3720. out:
  3721. pr_err(MPT3SAS_FMT "diag reset: FAILED\n", ioc->name);
  3722. return -EFAULT;
  3723. }
  3724. /**
  3725. * _base_make_ioc_ready - put controller in READY state
  3726. * @ioc: per adapter object
  3727. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3728. * @type: FORCE_BIG_HAMMER or SOFT_RESET
  3729. *
  3730. * Returns 0 for success, non-zero for failure.
  3731. */
  3732. static int
  3733. _base_make_ioc_ready(struct MPT3SAS_ADAPTER *ioc, int sleep_flag,
  3734. enum reset_type type)
  3735. {
  3736. u32 ioc_state;
  3737. int rc;
  3738. int count;
  3739. dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  3740. __func__));
  3741. if (ioc->pci_error_recovery)
  3742. return 0;
  3743. ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
  3744. dhsprintk(ioc, pr_info(MPT3SAS_FMT "%s: ioc_state(0x%08x)\n",
  3745. ioc->name, __func__, ioc_state));
  3746. /* if in RESET state, it should move to READY state shortly */
  3747. count = 0;
  3748. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
  3749. while ((ioc_state & MPI2_IOC_STATE_MASK) !=
  3750. MPI2_IOC_STATE_READY) {
  3751. if (count++ == 10) {
  3752. pr_err(MPT3SAS_FMT
  3753. "%s: failed going to ready state (ioc_state=0x%x)\n",
  3754. ioc->name, __func__, ioc_state);
  3755. return -EFAULT;
  3756. }
  3757. if (sleep_flag == CAN_SLEEP)
  3758. ssleep(1);
  3759. else
  3760. mdelay(1000);
  3761. ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
  3762. }
  3763. }
  3764. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_READY)
  3765. return 0;
  3766. if (ioc_state & MPI2_DOORBELL_USED) {
  3767. dhsprintk(ioc, pr_info(MPT3SAS_FMT
  3768. "unexpected doorbell active!\n",
  3769. ioc->name));
  3770. goto issue_diag_reset;
  3771. }
  3772. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
  3773. mpt3sas_base_fault_info(ioc, ioc_state &
  3774. MPI2_DOORBELL_DATA_MASK);
  3775. goto issue_diag_reset;
  3776. }
  3777. if (type == FORCE_BIG_HAMMER)
  3778. goto issue_diag_reset;
  3779. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_OPERATIONAL)
  3780. if (!(_base_send_ioc_reset(ioc,
  3781. MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET, 15, CAN_SLEEP))) {
  3782. return 0;
  3783. }
  3784. issue_diag_reset:
  3785. rc = _base_diag_reset(ioc, CAN_SLEEP);
  3786. return rc;
  3787. }
  3788. /**
  3789. * _base_make_ioc_operational - put controller in OPERATIONAL state
  3790. * @ioc: per adapter object
  3791. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  3792. *
  3793. * Returns 0 for success, non-zero for failure.
  3794. */
  3795. static int
  3796. _base_make_ioc_operational(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
  3797. {
  3798. int r, i;
  3799. unsigned long flags;
  3800. u32 reply_address;
  3801. u16 smid;
  3802. struct _tr_list *delayed_tr, *delayed_tr_next;
  3803. struct adapter_reply_queue *reply_q;
  3804. long reply_post_free;
  3805. u32 reply_post_free_sz;
  3806. dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  3807. __func__));
  3808. /* clean the delayed target reset list */
  3809. list_for_each_entry_safe(delayed_tr, delayed_tr_next,
  3810. &ioc->delayed_tr_list, list) {
  3811. list_del(&delayed_tr->list);
  3812. kfree(delayed_tr);
  3813. }
  3814. list_for_each_entry_safe(delayed_tr, delayed_tr_next,
  3815. &ioc->delayed_tr_volume_list, list) {
  3816. list_del(&delayed_tr->list);
  3817. kfree(delayed_tr);
  3818. }
  3819. /* initialize the scsi lookup free list */
  3820. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  3821. INIT_LIST_HEAD(&ioc->free_list);
  3822. smid = 1;
  3823. for (i = 0; i < ioc->scsiio_depth; i++, smid++) {
  3824. INIT_LIST_HEAD(&ioc->scsi_lookup[i].chain_list);
  3825. ioc->scsi_lookup[i].cb_idx = 0xFF;
  3826. ioc->scsi_lookup[i].smid = smid;
  3827. ioc->scsi_lookup[i].scmd = NULL;
  3828. list_add_tail(&ioc->scsi_lookup[i].tracker_list,
  3829. &ioc->free_list);
  3830. }
  3831. /* hi-priority queue */
  3832. INIT_LIST_HEAD(&ioc->hpr_free_list);
  3833. smid = ioc->hi_priority_smid;
  3834. for (i = 0; i < ioc->hi_priority_depth; i++, smid++) {
  3835. ioc->hpr_lookup[i].cb_idx = 0xFF;
  3836. ioc->hpr_lookup[i].smid = smid;
  3837. list_add_tail(&ioc->hpr_lookup[i].tracker_list,
  3838. &ioc->hpr_free_list);
  3839. }
  3840. /* internal queue */
  3841. INIT_LIST_HEAD(&ioc->internal_free_list);
  3842. smid = ioc->internal_smid;
  3843. for (i = 0; i < ioc->internal_depth; i++, smid++) {
  3844. ioc->internal_lookup[i].cb_idx = 0xFF;
  3845. ioc->internal_lookup[i].smid = smid;
  3846. list_add_tail(&ioc->internal_lookup[i].tracker_list,
  3847. &ioc->internal_free_list);
  3848. }
  3849. /* chain pool */
  3850. INIT_LIST_HEAD(&ioc->free_chain_list);
  3851. for (i = 0; i < ioc->chain_depth; i++)
  3852. list_add_tail(&ioc->chain_lookup[i].tracker_list,
  3853. &ioc->free_chain_list);
  3854. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  3855. /* initialize Reply Free Queue */
  3856. for (i = 0, reply_address = (u32)ioc->reply_dma ;
  3857. i < ioc->reply_free_queue_depth ; i++, reply_address +=
  3858. ioc->reply_sz)
  3859. ioc->reply_free[i] = cpu_to_le32(reply_address);
  3860. /* initialize reply queues */
  3861. if (ioc->is_driver_loading)
  3862. _base_assign_reply_queues(ioc);
  3863. /* initialize Reply Post Free Queue */
  3864. reply_post_free = (long)ioc->reply_post_free;
  3865. reply_post_free_sz = ioc->reply_post_queue_depth *
  3866. sizeof(Mpi2DefaultReplyDescriptor_t);
  3867. list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
  3868. reply_q->reply_post_host_index = 0;
  3869. reply_q->reply_post_free = (Mpi2ReplyDescriptorsUnion_t *)
  3870. reply_post_free;
  3871. for (i = 0; i < ioc->reply_post_queue_depth; i++)
  3872. reply_q->reply_post_free[i].Words =
  3873. cpu_to_le64(ULLONG_MAX);
  3874. if (!_base_is_controller_msix_enabled(ioc))
  3875. goto skip_init_reply_post_free_queue;
  3876. reply_post_free += reply_post_free_sz;
  3877. }
  3878. skip_init_reply_post_free_queue:
  3879. r = _base_send_ioc_init(ioc, sleep_flag);
  3880. if (r)
  3881. return r;
  3882. /* initialize reply free host index */
  3883. ioc->reply_free_host_index = ioc->reply_free_queue_depth - 1;
  3884. writel(ioc->reply_free_host_index, &ioc->chip->ReplyFreeHostIndex);
  3885. /* initialize reply post host index */
  3886. list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
  3887. writel(reply_q->msix_index << MPI2_RPHI_MSIX_INDEX_SHIFT,
  3888. &ioc->chip->ReplyPostHostIndex);
  3889. if (!_base_is_controller_msix_enabled(ioc))
  3890. goto skip_init_reply_post_host_index;
  3891. }
  3892. skip_init_reply_post_host_index:
  3893. _base_unmask_interrupts(ioc);
  3894. r = _base_event_notification(ioc, sleep_flag);
  3895. if (r)
  3896. return r;
  3897. if (sleep_flag == CAN_SLEEP)
  3898. _base_static_config_pages(ioc);
  3899. if (ioc->is_driver_loading) {
  3900. ioc->wait_for_discovery_to_complete =
  3901. _base_determine_wait_on_discovery(ioc);
  3902. return r; /* scan_start and scan_finished support */
  3903. }
  3904. r = _base_send_port_enable(ioc, sleep_flag);
  3905. if (r)
  3906. return r;
  3907. return r;
  3908. }
  3909. /**
  3910. * mpt3sas_base_free_resources - free resources controller resources
  3911. * @ioc: per adapter object
  3912. *
  3913. * Return nothing.
  3914. */
  3915. void
  3916. mpt3sas_base_free_resources(struct MPT3SAS_ADAPTER *ioc)
  3917. {
  3918. struct pci_dev *pdev = ioc->pdev;
  3919. dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  3920. __func__));
  3921. if (ioc->chip_phys && ioc->chip) {
  3922. _base_mask_interrupts(ioc);
  3923. ioc->shost_recovery = 1;
  3924. _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
  3925. ioc->shost_recovery = 0;
  3926. }
  3927. _base_free_irq(ioc);
  3928. _base_disable_msix(ioc);
  3929. if (ioc->chip_phys && ioc->chip)
  3930. iounmap(ioc->chip);
  3931. ioc->chip_phys = 0;
  3932. if (pci_is_enabled(pdev)) {
  3933. pci_release_selected_regions(ioc->pdev, ioc->bars);
  3934. pci_disable_pcie_error_reporting(pdev);
  3935. pci_disable_device(pdev);
  3936. }
  3937. return;
  3938. }
  3939. /**
  3940. * mpt3sas_base_attach - attach controller instance
  3941. * @ioc: per adapter object
  3942. *
  3943. * Returns 0 for success, non-zero for failure.
  3944. */
  3945. int
  3946. mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
  3947. {
  3948. int r, i;
  3949. int cpu_id, last_cpu_id = 0;
  3950. dinitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  3951. __func__));
  3952. /* setup cpu_msix_table */
  3953. ioc->cpu_count = num_online_cpus();
  3954. for_each_online_cpu(cpu_id)
  3955. last_cpu_id = cpu_id;
  3956. ioc->cpu_msix_table_sz = last_cpu_id + 1;
  3957. ioc->cpu_msix_table = kzalloc(ioc->cpu_msix_table_sz, GFP_KERNEL);
  3958. ioc->reply_queue_count = 1;
  3959. if (!ioc->cpu_msix_table) {
  3960. dfailprintk(ioc, pr_info(MPT3SAS_FMT
  3961. "allocation for cpu_msix_table failed!!!\n",
  3962. ioc->name));
  3963. r = -ENOMEM;
  3964. goto out_free_resources;
  3965. }
  3966. r = mpt3sas_base_map_resources(ioc);
  3967. if (r)
  3968. goto out_free_resources;
  3969. pci_set_drvdata(ioc->pdev, ioc->shost);
  3970. r = _base_get_ioc_facts(ioc, CAN_SLEEP);
  3971. if (r)
  3972. goto out_free_resources;
  3973. /*
  3974. * In SAS3.0,
  3975. * SCSI_IO, SMP_PASSTHRU, SATA_PASSTHRU, Target Assist, and
  3976. * Target Status - all require the IEEE formated scatter gather
  3977. * elements.
  3978. */
  3979. ioc->build_sg_scmd = &_base_build_sg_scmd_ieee;
  3980. ioc->build_sg = &_base_build_sg_ieee;
  3981. ioc->build_zero_len_sge = &_base_build_zero_len_sge_ieee;
  3982. ioc->mpi25 = 1;
  3983. ioc->sge_size_ieee = sizeof(Mpi2IeeeSgeSimple64_t);
  3984. /*
  3985. * These function pointers for other requests that don't
  3986. * the require IEEE scatter gather elements.
  3987. *
  3988. * For example Configuration Pages and SAS IOUNIT Control don't.
  3989. */
  3990. ioc->build_sg_mpi = &_base_build_sg;
  3991. ioc->build_zero_len_sge_mpi = &_base_build_zero_len_sge;
  3992. r = _base_make_ioc_ready(ioc, CAN_SLEEP, SOFT_RESET);
  3993. if (r)
  3994. goto out_free_resources;
  3995. ioc->pfacts = kcalloc(ioc->facts.NumberOfPorts,
  3996. sizeof(struct mpt3sas_port_facts), GFP_KERNEL);
  3997. if (!ioc->pfacts) {
  3998. r = -ENOMEM;
  3999. goto out_free_resources;
  4000. }
  4001. for (i = 0 ; i < ioc->facts.NumberOfPorts; i++) {
  4002. r = _base_get_port_facts(ioc, i, CAN_SLEEP);
  4003. if (r)
  4004. goto out_free_resources;
  4005. }
  4006. r = _base_allocate_memory_pools(ioc, CAN_SLEEP);
  4007. if (r)
  4008. goto out_free_resources;
  4009. init_waitqueue_head(&ioc->reset_wq);
  4010. /* allocate memory pd handle bitmask list */
  4011. ioc->pd_handles_sz = (ioc->facts.MaxDevHandle / 8);
  4012. if (ioc->facts.MaxDevHandle % 8)
  4013. ioc->pd_handles_sz++;
  4014. ioc->pd_handles = kzalloc(ioc->pd_handles_sz,
  4015. GFP_KERNEL);
  4016. if (!ioc->pd_handles) {
  4017. r = -ENOMEM;
  4018. goto out_free_resources;
  4019. }
  4020. ioc->blocking_handles = kzalloc(ioc->pd_handles_sz,
  4021. GFP_KERNEL);
  4022. if (!ioc->blocking_handles) {
  4023. r = -ENOMEM;
  4024. goto out_free_resources;
  4025. }
  4026. ioc->fwfault_debug = mpt3sas_fwfault_debug;
  4027. /* base internal command bits */
  4028. mutex_init(&ioc->base_cmds.mutex);
  4029. ioc->base_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  4030. ioc->base_cmds.status = MPT3_CMD_NOT_USED;
  4031. /* port_enable command bits */
  4032. ioc->port_enable_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  4033. ioc->port_enable_cmds.status = MPT3_CMD_NOT_USED;
  4034. /* transport internal command bits */
  4035. ioc->transport_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  4036. ioc->transport_cmds.status = MPT3_CMD_NOT_USED;
  4037. mutex_init(&ioc->transport_cmds.mutex);
  4038. /* scsih internal command bits */
  4039. ioc->scsih_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  4040. ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
  4041. mutex_init(&ioc->scsih_cmds.mutex);
  4042. /* task management internal command bits */
  4043. ioc->tm_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  4044. ioc->tm_cmds.status = MPT3_CMD_NOT_USED;
  4045. mutex_init(&ioc->tm_cmds.mutex);
  4046. /* config page internal command bits */
  4047. ioc->config_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  4048. ioc->config_cmds.status = MPT3_CMD_NOT_USED;
  4049. mutex_init(&ioc->config_cmds.mutex);
  4050. /* ctl module internal command bits */
  4051. ioc->ctl_cmds.reply = kzalloc(ioc->reply_sz, GFP_KERNEL);
  4052. ioc->ctl_cmds.sense = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
  4053. ioc->ctl_cmds.status = MPT3_CMD_NOT_USED;
  4054. mutex_init(&ioc->ctl_cmds.mutex);
  4055. if (!ioc->base_cmds.reply || !ioc->transport_cmds.reply ||
  4056. !ioc->scsih_cmds.reply || !ioc->tm_cmds.reply ||
  4057. !ioc->config_cmds.reply || !ioc->ctl_cmds.reply ||
  4058. !ioc->ctl_cmds.sense) {
  4059. r = -ENOMEM;
  4060. goto out_free_resources;
  4061. }
  4062. for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
  4063. ioc->event_masks[i] = -1;
  4064. /* here we enable the events we care about */
  4065. _base_unmask_events(ioc, MPI2_EVENT_SAS_DISCOVERY);
  4066. _base_unmask_events(ioc, MPI2_EVENT_SAS_BROADCAST_PRIMITIVE);
  4067. _base_unmask_events(ioc, MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
  4068. _base_unmask_events(ioc, MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE);
  4069. _base_unmask_events(ioc, MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE);
  4070. _base_unmask_events(ioc, MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST);
  4071. _base_unmask_events(ioc, MPI2_EVENT_IR_VOLUME);
  4072. _base_unmask_events(ioc, MPI2_EVENT_IR_PHYSICAL_DISK);
  4073. _base_unmask_events(ioc, MPI2_EVENT_IR_OPERATION_STATUS);
  4074. _base_unmask_events(ioc, MPI2_EVENT_LOG_ENTRY_ADDED);
  4075. r = _base_make_ioc_operational(ioc, CAN_SLEEP);
  4076. if (r)
  4077. goto out_free_resources;
  4078. return 0;
  4079. out_free_resources:
  4080. ioc->remove_host = 1;
  4081. mpt3sas_base_free_resources(ioc);
  4082. _base_release_memory_pools(ioc);
  4083. pci_set_drvdata(ioc->pdev, NULL);
  4084. kfree(ioc->cpu_msix_table);
  4085. kfree(ioc->pd_handles);
  4086. kfree(ioc->blocking_handles);
  4087. kfree(ioc->tm_cmds.reply);
  4088. kfree(ioc->transport_cmds.reply);
  4089. kfree(ioc->scsih_cmds.reply);
  4090. kfree(ioc->config_cmds.reply);
  4091. kfree(ioc->base_cmds.reply);
  4092. kfree(ioc->port_enable_cmds.reply);
  4093. kfree(ioc->ctl_cmds.reply);
  4094. kfree(ioc->ctl_cmds.sense);
  4095. kfree(ioc->pfacts);
  4096. ioc->ctl_cmds.reply = NULL;
  4097. ioc->base_cmds.reply = NULL;
  4098. ioc->tm_cmds.reply = NULL;
  4099. ioc->scsih_cmds.reply = NULL;
  4100. ioc->transport_cmds.reply = NULL;
  4101. ioc->config_cmds.reply = NULL;
  4102. ioc->pfacts = NULL;
  4103. return r;
  4104. }
  4105. /**
  4106. * mpt3sas_base_detach - remove controller instance
  4107. * @ioc: per adapter object
  4108. *
  4109. * Return nothing.
  4110. */
  4111. void
  4112. mpt3sas_base_detach(struct MPT3SAS_ADAPTER *ioc)
  4113. {
  4114. dexitprintk(ioc, pr_info(MPT3SAS_FMT "%s\n", ioc->name,
  4115. __func__));
  4116. mpt3sas_base_stop_watchdog(ioc);
  4117. mpt3sas_base_free_resources(ioc);
  4118. _base_release_memory_pools(ioc);
  4119. pci_set_drvdata(ioc->pdev, NULL);
  4120. kfree(ioc->cpu_msix_table);
  4121. kfree(ioc->pd_handles);
  4122. kfree(ioc->blocking_handles);
  4123. kfree(ioc->pfacts);
  4124. kfree(ioc->ctl_cmds.reply);
  4125. kfree(ioc->ctl_cmds.sense);
  4126. kfree(ioc->base_cmds.reply);
  4127. kfree(ioc->port_enable_cmds.reply);
  4128. kfree(ioc->tm_cmds.reply);
  4129. kfree(ioc->transport_cmds.reply);
  4130. kfree(ioc->scsih_cmds.reply);
  4131. kfree(ioc->config_cmds.reply);
  4132. }
  4133. /**
  4134. * _base_reset_handler - reset callback handler (for base)
  4135. * @ioc: per adapter object
  4136. * @reset_phase: phase
  4137. *
  4138. * The handler for doing any required cleanup or initialization.
  4139. *
  4140. * The reset phase can be MPT3_IOC_PRE_RESET, MPT3_IOC_AFTER_RESET,
  4141. * MPT3_IOC_DONE_RESET
  4142. *
  4143. * Return nothing.
  4144. */
  4145. static void
  4146. _base_reset_handler(struct MPT3SAS_ADAPTER *ioc, int reset_phase)
  4147. {
  4148. mpt3sas_scsih_reset_handler(ioc, reset_phase);
  4149. mpt3sas_ctl_reset_handler(ioc, reset_phase);
  4150. switch (reset_phase) {
  4151. case MPT3_IOC_PRE_RESET:
  4152. dtmprintk(ioc, pr_info(MPT3SAS_FMT
  4153. "%s: MPT3_IOC_PRE_RESET\n", ioc->name, __func__));
  4154. break;
  4155. case MPT3_IOC_AFTER_RESET:
  4156. dtmprintk(ioc, pr_info(MPT3SAS_FMT
  4157. "%s: MPT3_IOC_AFTER_RESET\n", ioc->name, __func__));
  4158. if (ioc->transport_cmds.status & MPT3_CMD_PENDING) {
  4159. ioc->transport_cmds.status |= MPT3_CMD_RESET;
  4160. mpt3sas_base_free_smid(ioc, ioc->transport_cmds.smid);
  4161. complete(&ioc->transport_cmds.done);
  4162. }
  4163. if (ioc->base_cmds.status & MPT3_CMD_PENDING) {
  4164. ioc->base_cmds.status |= MPT3_CMD_RESET;
  4165. mpt3sas_base_free_smid(ioc, ioc->base_cmds.smid);
  4166. complete(&ioc->base_cmds.done);
  4167. }
  4168. if (ioc->port_enable_cmds.status & MPT3_CMD_PENDING) {
  4169. ioc->port_enable_failed = 1;
  4170. ioc->port_enable_cmds.status |= MPT3_CMD_RESET;
  4171. mpt3sas_base_free_smid(ioc, ioc->port_enable_cmds.smid);
  4172. if (ioc->is_driver_loading) {
  4173. ioc->start_scan_failed =
  4174. MPI2_IOCSTATUS_INTERNAL_ERROR;
  4175. ioc->start_scan = 0;
  4176. ioc->port_enable_cmds.status =
  4177. MPT3_CMD_NOT_USED;
  4178. } else
  4179. complete(&ioc->port_enable_cmds.done);
  4180. }
  4181. if (ioc->config_cmds.status & MPT3_CMD_PENDING) {
  4182. ioc->config_cmds.status |= MPT3_CMD_RESET;
  4183. mpt3sas_base_free_smid(ioc, ioc->config_cmds.smid);
  4184. ioc->config_cmds.smid = USHRT_MAX;
  4185. complete(&ioc->config_cmds.done);
  4186. }
  4187. break;
  4188. case MPT3_IOC_DONE_RESET:
  4189. dtmprintk(ioc, pr_info(MPT3SAS_FMT
  4190. "%s: MPT3_IOC_DONE_RESET\n", ioc->name, __func__));
  4191. break;
  4192. }
  4193. }
  4194. /**
  4195. * _wait_for_commands_to_complete - reset controller
  4196. * @ioc: Pointer to MPT_ADAPTER structure
  4197. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  4198. *
  4199. * This function waiting(3s) for all pending commands to complete
  4200. * prior to putting controller in reset.
  4201. */
  4202. static void
  4203. _wait_for_commands_to_complete(struct MPT3SAS_ADAPTER *ioc, int sleep_flag)
  4204. {
  4205. u32 ioc_state;
  4206. unsigned long flags;
  4207. u16 i;
  4208. ioc->pending_io_count = 0;
  4209. if (sleep_flag != CAN_SLEEP)
  4210. return;
  4211. ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
  4212. if ((ioc_state & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL)
  4213. return;
  4214. /* pending command count */
  4215. spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
  4216. for (i = 0; i < ioc->scsiio_depth; i++)
  4217. if (ioc->scsi_lookup[i].cb_idx != 0xFF)
  4218. ioc->pending_io_count++;
  4219. spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
  4220. if (!ioc->pending_io_count)
  4221. return;
  4222. /* wait for pending commands to complete */
  4223. wait_event_timeout(ioc->reset_wq, ioc->pending_io_count == 0, 10 * HZ);
  4224. }
  4225. /**
  4226. * mpt3sas_base_hard_reset_handler - reset controller
  4227. * @ioc: Pointer to MPT_ADAPTER structure
  4228. * @sleep_flag: CAN_SLEEP or NO_SLEEP
  4229. * @type: FORCE_BIG_HAMMER or SOFT_RESET
  4230. *
  4231. * Returns 0 for success, non-zero for failure.
  4232. */
  4233. int
  4234. mpt3sas_base_hard_reset_handler(struct MPT3SAS_ADAPTER *ioc, int sleep_flag,
  4235. enum reset_type type)
  4236. {
  4237. int r;
  4238. unsigned long flags;
  4239. u32 ioc_state;
  4240. u8 is_fault = 0, is_trigger = 0;
  4241. dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: enter\n", ioc->name,
  4242. __func__));
  4243. if (ioc->pci_error_recovery) {
  4244. pr_err(MPT3SAS_FMT "%s: pci error recovery reset\n",
  4245. ioc->name, __func__);
  4246. r = 0;
  4247. goto out_unlocked;
  4248. }
  4249. if (mpt3sas_fwfault_debug)
  4250. mpt3sas_halt_firmware(ioc);
  4251. /* TODO - What we really should be doing is pulling
  4252. * out all the code associated with NO_SLEEP; its never used.
  4253. * That is legacy code from mpt fusion driver, ported over.
  4254. * I will leave this BUG_ON here for now till its been resolved.
  4255. */
  4256. BUG_ON(sleep_flag == NO_SLEEP);
  4257. /* wait for an active reset in progress to complete */
  4258. if (!mutex_trylock(&ioc->reset_in_progress_mutex)) {
  4259. do {
  4260. ssleep(1);
  4261. } while (ioc->shost_recovery == 1);
  4262. dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
  4263. __func__));
  4264. return ioc->ioc_reset_in_progress_status;
  4265. }
  4266. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  4267. ioc->shost_recovery = 1;
  4268. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  4269. if ((ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
  4270. MPT3_DIAG_BUFFER_IS_REGISTERED) &&
  4271. (!(ioc->diag_buffer_status[MPI2_DIAG_BUF_TYPE_TRACE] &
  4272. MPT3_DIAG_BUFFER_IS_RELEASED))) {
  4273. is_trigger = 1;
  4274. ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
  4275. if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT)
  4276. is_fault = 1;
  4277. }
  4278. _base_reset_handler(ioc, MPT3_IOC_PRE_RESET);
  4279. _wait_for_commands_to_complete(ioc, sleep_flag);
  4280. _base_mask_interrupts(ioc);
  4281. r = _base_make_ioc_ready(ioc, sleep_flag, type);
  4282. if (r)
  4283. goto out;
  4284. _base_reset_handler(ioc, MPT3_IOC_AFTER_RESET);
  4285. /* If this hard reset is called while port enable is active, then
  4286. * there is no reason to call make_ioc_operational
  4287. */
  4288. if (ioc->is_driver_loading && ioc->port_enable_failed) {
  4289. ioc->remove_host = 1;
  4290. r = -EFAULT;
  4291. goto out;
  4292. }
  4293. r = _base_get_ioc_facts(ioc, CAN_SLEEP);
  4294. if (r)
  4295. goto out;
  4296. r = _base_make_ioc_operational(ioc, sleep_flag);
  4297. if (!r)
  4298. _base_reset_handler(ioc, MPT3_IOC_DONE_RESET);
  4299. out:
  4300. dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: %s\n",
  4301. ioc->name, __func__, ((r == 0) ? "SUCCESS" : "FAILED")));
  4302. spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
  4303. ioc->ioc_reset_in_progress_status = r;
  4304. ioc->shost_recovery = 0;
  4305. spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
  4306. ioc->ioc_reset_count++;
  4307. mutex_unlock(&ioc->reset_in_progress_mutex);
  4308. out_unlocked:
  4309. if ((r == 0) && is_trigger) {
  4310. if (is_fault)
  4311. mpt3sas_trigger_master(ioc, MASTER_TRIGGER_FW_FAULT);
  4312. else
  4313. mpt3sas_trigger_master(ioc,
  4314. MASTER_TRIGGER_ADAPTER_RESET);
  4315. }
  4316. dtmprintk(ioc, pr_info(MPT3SAS_FMT "%s: exit\n", ioc->name,
  4317. __func__));
  4318. return r;
  4319. }