csio_hw_chip.h 6.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175
  1. /*
  2. * This file is part of the Chelsio FCoE driver for Linux.
  3. *
  4. * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #ifndef __CSIO_HW_CHIP_H__
  34. #define __CSIO_HW_CHIP_H__
  35. #include "csio_defs.h"
  36. /* FCoE device IDs for T4 */
  37. #define CSIO_DEVID_T440DBG_FCOE 0x4600
  38. #define CSIO_DEVID_T420CR_FCOE 0x4601
  39. #define CSIO_DEVID_T422CR_FCOE 0x4602
  40. #define CSIO_DEVID_T440CR_FCOE 0x4603
  41. #define CSIO_DEVID_T420BCH_FCOE 0x4604
  42. #define CSIO_DEVID_T440BCH_FCOE 0x4605
  43. #define CSIO_DEVID_T440CH_FCOE 0x4606
  44. #define CSIO_DEVID_T420SO_FCOE 0x4607
  45. #define CSIO_DEVID_T420CX_FCOE 0x4608
  46. #define CSIO_DEVID_T420BT_FCOE 0x4609
  47. #define CSIO_DEVID_T404BT_FCOE 0x460A
  48. #define CSIO_DEVID_B420_FCOE 0x460B
  49. #define CSIO_DEVID_B404_FCOE 0x460C
  50. #define CSIO_DEVID_T480CR_FCOE 0x460D
  51. #define CSIO_DEVID_T440LPCR_FCOE 0x460E
  52. #define CSIO_DEVID_AMSTERDAM_T4_FCOE 0x460F
  53. #define CSIO_DEVID_HUAWEI_T480_FCOE 0x4680
  54. #define CSIO_DEVID_HUAWEI_T440_FCOE 0x4681
  55. #define CSIO_DEVID_HUAWEI_STG310_FCOE 0x4682
  56. #define CSIO_DEVID_ACROMAG_XMC_XAUI 0x4683
  57. #define CSIO_DEVID_ACROMAG_XMC_SFP_FCOE 0x4684
  58. #define CSIO_DEVID_QUANTA_MEZZ_SFP_FCOE 0x4685
  59. #define CSIO_DEVID_HUAWEI_10GT_FCOE 0x4686
  60. #define CSIO_DEVID_HUAWEI_T440_TOE_FCOE 0x4687
  61. /* FCoE device IDs for T5 */
  62. #define CSIO_DEVID_T580DBG_FCOE 0x5600
  63. #define CSIO_DEVID_T520CR_FCOE 0x5601
  64. #define CSIO_DEVID_T522CR_FCOE 0x5602
  65. #define CSIO_DEVID_T540CR_FCOE 0x5603
  66. #define CSIO_DEVID_T520BCH_FCOE 0x5604
  67. #define CSIO_DEVID_T540BCH_FCOE 0x5605
  68. #define CSIO_DEVID_T540CH_FCOE 0x5606
  69. #define CSIO_DEVID_T520SO_FCOE 0x5607
  70. #define CSIO_DEVID_T520CX_FCOE 0x5608
  71. #define CSIO_DEVID_T520BT_FCOE 0x5609
  72. #define CSIO_DEVID_T504BT_FCOE 0x560A
  73. #define CSIO_DEVID_B520_FCOE 0x560B
  74. #define CSIO_DEVID_B504_FCOE 0x560C
  75. #define CSIO_DEVID_T580CR2_FCOE 0x560D
  76. #define CSIO_DEVID_T540LPCR_FCOE 0x560E
  77. #define CSIO_DEVID_AMSTERDAM_T5_FCOE 0x560F
  78. #define CSIO_DEVID_T580LPCR_FCOE 0x5610
  79. #define CSIO_DEVID_T520LLCR_FCOE 0x5611
  80. #define CSIO_DEVID_T560CR_FCOE 0x5612
  81. #define CSIO_DEVID_T580CR_FCOE 0x5613
  82. /* Define MACRO values */
  83. #define CSIO_HW_T4 0x4000
  84. #define CSIO_T4_FCOE_ASIC 0x4600
  85. #define CSIO_HW_T5 0x5000
  86. #define CSIO_T5_FCOE_ASIC 0x5600
  87. #define CSIO_HW_CHIP_MASK 0xF000
  88. #define T4_REGMAP_SIZE (160 * 1024)
  89. #define T5_REGMAP_SIZE (332 * 1024)
  90. #define FW_FNAME_T4 "cxgb4/t4fw.bin"
  91. #define FW_FNAME_T5 "cxgb4/t5fw.bin"
  92. #define FW_CFG_NAME_T4 "cxgb4/t4-config.txt"
  93. #define FW_CFG_NAME_T5 "cxgb4/t5-config.txt"
  94. /* Define static functions */
  95. static inline int csio_is_t4(uint16_t chip)
  96. {
  97. return (chip == CSIO_HW_T4);
  98. }
  99. static inline int csio_is_t5(uint16_t chip)
  100. {
  101. return (chip == CSIO_HW_T5);
  102. }
  103. /* Define MACRO DEFINITIONS */
  104. #define CSIO_DEVICE(devid, idx) \
  105. { PCI_VENDOR_ID_CHELSIO, (devid), PCI_ANY_ID, PCI_ANY_ID, 0, 0, (idx) }
  106. #define CSIO_HW_PIDX(hw, index) \
  107. (csio_is_t4(hw->chip_id) ? (PIDX(index)) : \
  108. (PIDX_T5(index) | DBTYPE(1U)))
  109. #define CSIO_HW_LP_INT_THRESH(hw, val) \
  110. (csio_is_t4(hw->chip_id) ? (LP_INT_THRESH(val)) : \
  111. (V_LP_INT_THRESH_T5(val)))
  112. #define CSIO_HW_M_LP_INT_THRESH(hw) \
  113. (csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_MASK) : (M_LP_INT_THRESH_T5))
  114. #define CSIO_MAC_INT_CAUSE_REG(hw, port) \
  115. (csio_is_t4(hw->chip_id) ? (PORT_REG(port, XGMAC_PORT_INT_CAUSE)) : \
  116. (T5_PORT_REG(port, MAC_PORT_INT_CAUSE)))
  117. #define FW_VERSION_MAJOR(hw) (csio_is_t4(hw->chip_id) ? 1 : 0)
  118. #define FW_VERSION_MINOR(hw) (csio_is_t4(hw->chip_id) ? 2 : 0)
  119. #define FW_VERSION_MICRO(hw) (csio_is_t4(hw->chip_id) ? 8 : 0)
  120. #define CSIO_FW_FNAME(hw) \
  121. (csio_is_t4(hw->chip_id) ? FW_FNAME_T4 : FW_FNAME_T5)
  122. #define CSIO_CF_FNAME(hw) \
  123. (csio_is_t4(hw->chip_id) ? FW_CFG_NAME_T4 : FW_CFG_NAME_T5)
  124. /* Declare ENUMS */
  125. enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
  126. enum {
  127. MEMWIN_APERTURE = 2048,
  128. MEMWIN_BASE = 0x1b800,
  129. MEMWIN_CSIOSTOR = 6, /* PCI-e Memory Window access */
  130. };
  131. /* Slow path handlers */
  132. struct intr_info {
  133. unsigned int mask; /* bits to check in interrupt status */
  134. const char *msg; /* message to print or NULL */
  135. short stat_idx; /* stat counter to increment or -1 */
  136. unsigned short fatal; /* whether the condition reported is fatal */
  137. };
  138. /* T4/T5 Chip specific ops */
  139. struct csio_hw;
  140. struct csio_hw_chip_ops {
  141. int (*chip_set_mem_win)(struct csio_hw *, uint32_t);
  142. void (*chip_pcie_intr_handler)(struct csio_hw *);
  143. uint32_t (*chip_flash_cfg_addr)(struct csio_hw *);
  144. int (*chip_mc_read)(struct csio_hw *, int, uint32_t,
  145. __be32 *, uint64_t *);
  146. int (*chip_edc_read)(struct csio_hw *, int, uint32_t,
  147. __be32 *, uint64_t *);
  148. int (*chip_memory_rw)(struct csio_hw *, u32, int, u32,
  149. u32, uint32_t *, int);
  150. void (*chip_dfs_create_ext_mem)(struct csio_hw *);
  151. };
  152. extern struct csio_hw_chip_ops t4_ops;
  153. extern struct csio_hw_chip_ops t5_ops;
  154. #endif /* #ifndef __CSIO_HW_CHIP_H__ */