phy-exynos-mipi-video.c 4.6 KB

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  1. /*
  2. * Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
  3. *
  4. * Copyright (C) 2013 Samsung Electronics Co., Ltd.
  5. * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/io.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/of_address.h>
  16. #include <linux/phy/phy.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/spinlock.h>
  19. /* MIPI_PHYn_CONTROL register offset: n = 0..1 */
  20. #define EXYNOS_MIPI_PHY_CONTROL(n) ((n) * 4)
  21. #define EXYNOS_MIPI_PHY_ENABLE (1 << 0)
  22. #define EXYNOS_MIPI_PHY_SRESETN (1 << 1)
  23. #define EXYNOS_MIPI_PHY_MRESETN (1 << 2)
  24. #define EXYNOS_MIPI_PHY_RESET_MASK (3 << 1)
  25. enum exynos_mipi_phy_id {
  26. EXYNOS_MIPI_PHY_ID_CSIS0,
  27. EXYNOS_MIPI_PHY_ID_DSIM0,
  28. EXYNOS_MIPI_PHY_ID_CSIS1,
  29. EXYNOS_MIPI_PHY_ID_DSIM1,
  30. EXYNOS_MIPI_PHYS_NUM
  31. };
  32. #define is_mipi_dsim_phy_id(id) \
  33. ((id) == EXYNOS_MIPI_PHY_ID_DSIM0 || (id) == EXYNOS_MIPI_PHY_ID_DSIM1)
  34. struct exynos_mipi_video_phy {
  35. spinlock_t slock;
  36. struct video_phy_desc {
  37. struct phy *phy;
  38. unsigned int index;
  39. } phys[EXYNOS_MIPI_PHYS_NUM];
  40. void __iomem *regs;
  41. };
  42. static int __set_phy_state(struct exynos_mipi_video_phy *state,
  43. enum exynos_mipi_phy_id id, unsigned int on)
  44. {
  45. void __iomem *addr;
  46. u32 reg, reset;
  47. addr = state->regs + EXYNOS_MIPI_PHY_CONTROL(id / 2);
  48. if (is_mipi_dsim_phy_id(id))
  49. reset = EXYNOS_MIPI_PHY_MRESETN;
  50. else
  51. reset = EXYNOS_MIPI_PHY_SRESETN;
  52. spin_lock(&state->slock);
  53. reg = readl(addr);
  54. if (on)
  55. reg |= reset;
  56. else
  57. reg &= ~reset;
  58. writel(reg, addr);
  59. /* Clear ENABLE bit only if MRESETN, SRESETN bits are not set. */
  60. if (on)
  61. reg |= EXYNOS_MIPI_PHY_ENABLE;
  62. else if (!(reg & EXYNOS_MIPI_PHY_RESET_MASK))
  63. reg &= ~EXYNOS_MIPI_PHY_ENABLE;
  64. writel(reg, addr);
  65. spin_unlock(&state->slock);
  66. return 0;
  67. }
  68. #define to_mipi_video_phy(desc) \
  69. container_of((desc), struct exynos_mipi_video_phy, phys[(desc)->index]);
  70. static int exynos_mipi_video_phy_power_on(struct phy *phy)
  71. {
  72. struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
  73. struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
  74. return __set_phy_state(state, phy_desc->index, 1);
  75. }
  76. static int exynos_mipi_video_phy_power_off(struct phy *phy)
  77. {
  78. struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
  79. struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
  80. return __set_phy_state(state, phy_desc->index, 0);
  81. }
  82. static struct phy *exynos_mipi_video_phy_xlate(struct device *dev,
  83. struct of_phandle_args *args)
  84. {
  85. struct exynos_mipi_video_phy *state = dev_get_drvdata(dev);
  86. if (WARN_ON(args->args[0] > EXYNOS_MIPI_PHYS_NUM))
  87. return ERR_PTR(-ENODEV);
  88. return state->phys[args->args[0]].phy;
  89. }
  90. static struct phy_ops exynos_mipi_video_phy_ops = {
  91. .power_on = exynos_mipi_video_phy_power_on,
  92. .power_off = exynos_mipi_video_phy_power_off,
  93. .owner = THIS_MODULE,
  94. };
  95. static int exynos_mipi_video_phy_probe(struct platform_device *pdev)
  96. {
  97. struct exynos_mipi_video_phy *state;
  98. struct device *dev = &pdev->dev;
  99. struct resource *res;
  100. struct phy_provider *phy_provider;
  101. unsigned int i;
  102. state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
  103. if (!state)
  104. return -ENOMEM;
  105. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  106. state->regs = devm_ioremap_resource(dev, res);
  107. if (IS_ERR(state->regs))
  108. return PTR_ERR(state->regs);
  109. dev_set_drvdata(dev, state);
  110. spin_lock_init(&state->slock);
  111. phy_provider = devm_of_phy_provider_register(dev,
  112. exynos_mipi_video_phy_xlate);
  113. if (IS_ERR(phy_provider))
  114. return PTR_ERR(phy_provider);
  115. for (i = 0; i < EXYNOS_MIPI_PHYS_NUM; i++) {
  116. struct phy *phy = devm_phy_create(dev,
  117. &exynos_mipi_video_phy_ops, NULL);
  118. if (IS_ERR(phy)) {
  119. dev_err(dev, "failed to create PHY %d\n", i);
  120. return PTR_ERR(phy);
  121. }
  122. state->phys[i].phy = phy;
  123. state->phys[i].index = i;
  124. phy_set_drvdata(phy, &state->phys[i]);
  125. }
  126. return 0;
  127. }
  128. static const struct of_device_id exynos_mipi_video_phy_of_match[] = {
  129. { .compatible = "samsung,s5pv210-mipi-video-phy" },
  130. { },
  131. };
  132. MODULE_DEVICE_TABLE(of, exynos_mipi_video_phy_of_match);
  133. static struct platform_driver exynos_mipi_video_phy_driver = {
  134. .probe = exynos_mipi_video_phy_probe,
  135. .driver = {
  136. .of_match_table = exynos_mipi_video_phy_of_match,
  137. .name = "exynos-mipi-video-phy",
  138. .owner = THIS_MODULE,
  139. }
  140. };
  141. module_platform_driver(exynos_mipi_video_phy_driver);
  142. MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC MIPI CSI-2/DSI PHY driver");
  143. MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
  144. MODULE_LICENSE("GPL v2");