st_rc.c 11 KB

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  1. /*
  2. * Copyright (C) 2013 STMicroelectronics Limited
  3. * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/clk.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/platform_device.h>
  16. #include <media/rc-core.h>
  17. #include <linux/pinctrl/consumer.h>
  18. struct st_rc_device {
  19. struct device *dev;
  20. int irq;
  21. int irq_wake;
  22. struct clk *sys_clock;
  23. void *base; /* Register base address */
  24. void *rx_base;/* RX Register base address */
  25. struct rc_dev *rdev;
  26. bool overclocking;
  27. int sample_mult;
  28. int sample_div;
  29. bool rxuhfmode;
  30. };
  31. /* Registers */
  32. #define IRB_SAMPLE_RATE_COMM 0x64 /* sample freq divisor*/
  33. #define IRB_CLOCK_SEL 0x70 /* clock select */
  34. #define IRB_CLOCK_SEL_STATUS 0x74 /* clock status */
  35. /* IRB IR/UHF receiver registers */
  36. #define IRB_RX_ON 0x40 /* pulse time capture */
  37. #define IRB_RX_SYS 0X44 /* sym period capture */
  38. #define IRB_RX_INT_EN 0x48 /* IRQ enable (R/W) */
  39. #define IRB_RX_INT_STATUS 0x4c /* IRQ status (R/W) */
  40. #define IRB_RX_EN 0x50 /* Receive enable */
  41. #define IRB_MAX_SYM_PERIOD 0x54 /* max sym value */
  42. #define IRB_RX_INT_CLEAR 0x58 /* overrun status */
  43. #define IRB_RX_STATUS 0x6c /* receive status */
  44. #define IRB_RX_NOISE_SUPPR 0x5c /* noise suppression */
  45. #define IRB_RX_POLARITY_INV 0x68 /* polarity inverter */
  46. /**
  47. * IRQ set: Enable full FIFO 1 -> bit 3;
  48. * Enable overrun IRQ 1 -> bit 2;
  49. * Enable last symbol IRQ 1 -> bit 1:
  50. * Enable RX interrupt 1 -> bit 0;
  51. */
  52. #define IRB_RX_INTS 0x0f
  53. #define IRB_RX_OVERRUN_INT 0x04
  54. /* maximum symbol period (microsecs),timeout to detect end of symbol train */
  55. #define MAX_SYMB_TIME 0x5000
  56. #define IRB_SAMPLE_FREQ 10000000
  57. #define IRB_FIFO_NOT_EMPTY 0xff00
  58. #define IRB_OVERFLOW 0x4
  59. #define IRB_TIMEOUT 0xffff
  60. #define IR_ST_NAME "st-rc"
  61. static void st_rc_send_lirc_timeout(struct rc_dev *rdev)
  62. {
  63. DEFINE_IR_RAW_EVENT(ev);
  64. ev.timeout = true;
  65. ir_raw_event_store(rdev, &ev);
  66. }
  67. /**
  68. * RX graphical example to better understand the difference between ST IR block
  69. * output and standard definition used by LIRC (and most of the world!)
  70. *
  71. * mark mark
  72. * |-IRB_RX_ON-| |-IRB_RX_ON-|
  73. * ___ ___ ___ ___ ___ ___ _
  74. * | | | | | | | | | | | | |
  75. * | | | | | | space 0 | | | | | | space 1 |
  76. * _____| |__| |__| |____________________________| |__| |__| |_____________|
  77. *
  78. * |--------------- IRB_RX_SYS -------------|------ IRB_RX_SYS -------|
  79. *
  80. * |------------- encoding bit 0 -----------|---- encoding bit 1 -----|
  81. *
  82. * ST hardware returns mark (IRB_RX_ON) and total symbol time (IRB_RX_SYS), so
  83. * convert to standard mark/space we have to calculate space=(IRB_RX_SYS-mark)
  84. * The mark time represents the amount of time the carrier (usually 36-40kHz)
  85. * is detected.The above examples shows Pulse Width Modulation encoding where
  86. * bit 0 is represented by space>mark.
  87. */
  88. static irqreturn_t st_rc_rx_interrupt(int irq, void *data)
  89. {
  90. unsigned int symbol, mark = 0;
  91. struct st_rc_device *dev = data;
  92. int last_symbol = 0;
  93. u32 status;
  94. DEFINE_IR_RAW_EVENT(ev);
  95. if (dev->irq_wake)
  96. pm_wakeup_event(dev->dev, 0);
  97. status = readl(dev->rx_base + IRB_RX_STATUS);
  98. while (status & (IRB_FIFO_NOT_EMPTY | IRB_OVERFLOW)) {
  99. u32 int_status = readl(dev->rx_base + IRB_RX_INT_STATUS);
  100. if (unlikely(int_status & IRB_RX_OVERRUN_INT)) {
  101. /* discard the entire collection in case of errors! */
  102. ir_raw_event_reset(dev->rdev);
  103. dev_info(dev->dev, "IR RX overrun\n");
  104. writel(IRB_RX_OVERRUN_INT,
  105. dev->rx_base + IRB_RX_INT_CLEAR);
  106. continue;
  107. }
  108. symbol = readl(dev->rx_base + IRB_RX_SYS);
  109. mark = readl(dev->rx_base + IRB_RX_ON);
  110. if (symbol == IRB_TIMEOUT)
  111. last_symbol = 1;
  112. /* Ignore any noise */
  113. if ((mark > 2) && (symbol > 1)) {
  114. symbol -= mark;
  115. if (dev->overclocking) { /* adjustments to timings */
  116. symbol *= dev->sample_mult;
  117. symbol /= dev->sample_div;
  118. mark *= dev->sample_mult;
  119. mark /= dev->sample_div;
  120. }
  121. ev.duration = US_TO_NS(mark);
  122. ev.pulse = true;
  123. ir_raw_event_store(dev->rdev, &ev);
  124. if (!last_symbol) {
  125. ev.duration = US_TO_NS(symbol);
  126. ev.pulse = false;
  127. ir_raw_event_store(dev->rdev, &ev);
  128. } else {
  129. st_rc_send_lirc_timeout(dev->rdev);
  130. }
  131. }
  132. last_symbol = 0;
  133. status = readl(dev->rx_base + IRB_RX_STATUS);
  134. }
  135. writel(IRB_RX_INTS, dev->rx_base + IRB_RX_INT_CLEAR);
  136. /* Empty software fifo */
  137. ir_raw_event_handle(dev->rdev);
  138. return IRQ_HANDLED;
  139. }
  140. static void st_rc_hardware_init(struct st_rc_device *dev)
  141. {
  142. int baseclock, freqdiff;
  143. unsigned int rx_max_symbol_per = MAX_SYMB_TIME;
  144. unsigned int rx_sampling_freq_div;
  145. clk_prepare_enable(dev->sys_clock);
  146. baseclock = clk_get_rate(dev->sys_clock);
  147. /* IRB input pins are inverted internally from high to low. */
  148. writel(1, dev->rx_base + IRB_RX_POLARITY_INV);
  149. rx_sampling_freq_div = baseclock / IRB_SAMPLE_FREQ;
  150. writel(rx_sampling_freq_div, dev->base + IRB_SAMPLE_RATE_COMM);
  151. freqdiff = baseclock - (rx_sampling_freq_div * IRB_SAMPLE_FREQ);
  152. if (freqdiff) { /* over clocking, workout the adjustment factors */
  153. dev->overclocking = true;
  154. dev->sample_mult = 1000;
  155. dev->sample_div = baseclock / (10000 * rx_sampling_freq_div);
  156. rx_max_symbol_per = (rx_max_symbol_per * 1000)/dev->sample_div;
  157. }
  158. writel(rx_max_symbol_per, dev->rx_base + IRB_MAX_SYM_PERIOD);
  159. }
  160. static int st_rc_remove(struct platform_device *pdev)
  161. {
  162. struct st_rc_device *rc_dev = platform_get_drvdata(pdev);
  163. clk_disable_unprepare(rc_dev->sys_clock);
  164. rc_unregister_device(rc_dev->rdev);
  165. return 0;
  166. }
  167. static int st_rc_open(struct rc_dev *rdev)
  168. {
  169. struct st_rc_device *dev = rdev->priv;
  170. unsigned long flags;
  171. local_irq_save(flags);
  172. /* enable interrupts and receiver */
  173. writel(IRB_RX_INTS, dev->rx_base + IRB_RX_INT_EN);
  174. writel(0x01, dev->rx_base + IRB_RX_EN);
  175. local_irq_restore(flags);
  176. return 0;
  177. }
  178. static void st_rc_close(struct rc_dev *rdev)
  179. {
  180. struct st_rc_device *dev = rdev->priv;
  181. /* disable interrupts and receiver */
  182. writel(0x00, dev->rx_base + IRB_RX_EN);
  183. writel(0x00, dev->rx_base + IRB_RX_INT_EN);
  184. }
  185. static int st_rc_probe(struct platform_device *pdev)
  186. {
  187. int ret = -EINVAL;
  188. struct rc_dev *rdev;
  189. struct device *dev = &pdev->dev;
  190. struct resource *res;
  191. struct st_rc_device *rc_dev;
  192. struct device_node *np = pdev->dev.of_node;
  193. const char *rx_mode;
  194. rc_dev = devm_kzalloc(dev, sizeof(struct st_rc_device), GFP_KERNEL);
  195. if (!rc_dev)
  196. return -ENOMEM;
  197. rdev = rc_allocate_device();
  198. if (!rdev)
  199. return -ENOMEM;
  200. if (np && !of_property_read_string(np, "rx-mode", &rx_mode)) {
  201. if (!strcmp(rx_mode, "uhf")) {
  202. rc_dev->rxuhfmode = true;
  203. } else if (!strcmp(rx_mode, "infrared")) {
  204. rc_dev->rxuhfmode = false;
  205. } else {
  206. dev_err(dev, "Unsupported rx mode [%s]\n", rx_mode);
  207. goto err;
  208. }
  209. } else {
  210. goto err;
  211. }
  212. rc_dev->sys_clock = devm_clk_get(dev, NULL);
  213. if (IS_ERR(rc_dev->sys_clock)) {
  214. dev_err(dev, "System clock not found\n");
  215. ret = PTR_ERR(rc_dev->sys_clock);
  216. goto err;
  217. }
  218. rc_dev->irq = platform_get_irq(pdev, 0);
  219. if (rc_dev->irq < 0) {
  220. ret = rc_dev->irq;
  221. goto err;
  222. }
  223. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  224. rc_dev->base = devm_ioremap_resource(dev, res);
  225. if (IS_ERR(rc_dev->base)) {
  226. ret = PTR_ERR(rc_dev->base);
  227. goto err;
  228. }
  229. if (rc_dev->rxuhfmode)
  230. rc_dev->rx_base = rc_dev->base + 0x40;
  231. else
  232. rc_dev->rx_base = rc_dev->base;
  233. rc_dev->dev = dev;
  234. platform_set_drvdata(pdev, rc_dev);
  235. st_rc_hardware_init(rc_dev);
  236. rdev->driver_type = RC_DRIVER_IR_RAW;
  237. rdev->allowed_protos = RC_BIT_ALL;
  238. /* rx sampling rate is 10Mhz */
  239. rdev->rx_resolution = 100;
  240. rdev->timeout = US_TO_NS(MAX_SYMB_TIME);
  241. rdev->priv = rc_dev;
  242. rdev->open = st_rc_open;
  243. rdev->close = st_rc_close;
  244. rdev->driver_name = IR_ST_NAME;
  245. rdev->map_name = RC_MAP_LIRC;
  246. rdev->input_name = "ST Remote Control Receiver";
  247. /* enable wake via this device */
  248. device_set_wakeup_capable(dev, true);
  249. device_set_wakeup_enable(dev, true);
  250. ret = rc_register_device(rdev);
  251. if (ret < 0)
  252. goto clkerr;
  253. rc_dev->rdev = rdev;
  254. if (devm_request_irq(dev, rc_dev->irq, st_rc_rx_interrupt,
  255. IRQF_NO_SUSPEND, IR_ST_NAME, rc_dev) < 0) {
  256. dev_err(dev, "IRQ %d register failed\n", rc_dev->irq);
  257. ret = -EINVAL;
  258. goto rcerr;
  259. }
  260. /**
  261. * for LIRC_MODE_MODE2 or LIRC_MODE_PULSE or LIRC_MODE_RAW
  262. * lircd expects a long space first before a signal train to sync.
  263. */
  264. st_rc_send_lirc_timeout(rdev);
  265. dev_info(dev, "setup in %s mode\n", rc_dev->rxuhfmode ? "UHF" : "IR");
  266. return ret;
  267. rcerr:
  268. rc_unregister_device(rdev);
  269. rdev = NULL;
  270. clkerr:
  271. clk_disable_unprepare(rc_dev->sys_clock);
  272. err:
  273. rc_free_device(rdev);
  274. dev_err(dev, "Unable to register device (%d)\n", ret);
  275. return ret;
  276. }
  277. #ifdef CONFIG_PM
  278. static int st_rc_suspend(struct device *dev)
  279. {
  280. struct st_rc_device *rc_dev = dev_get_drvdata(dev);
  281. if (device_may_wakeup(dev)) {
  282. if (!enable_irq_wake(rc_dev->irq))
  283. rc_dev->irq_wake = 1;
  284. else
  285. return -EINVAL;
  286. } else {
  287. pinctrl_pm_select_sleep_state(dev);
  288. writel(0x00, rc_dev->rx_base + IRB_RX_EN);
  289. writel(0x00, rc_dev->rx_base + IRB_RX_INT_EN);
  290. clk_disable_unprepare(rc_dev->sys_clock);
  291. }
  292. return 0;
  293. }
  294. static int st_rc_resume(struct device *dev)
  295. {
  296. struct st_rc_device *rc_dev = dev_get_drvdata(dev);
  297. struct rc_dev *rdev = rc_dev->rdev;
  298. if (rc_dev->irq_wake) {
  299. disable_irq_wake(rc_dev->irq);
  300. rc_dev->irq_wake = 0;
  301. } else {
  302. pinctrl_pm_select_default_state(dev);
  303. st_rc_hardware_init(rc_dev);
  304. if (rdev->users) {
  305. writel(IRB_RX_INTS, rc_dev->rx_base + IRB_RX_INT_EN);
  306. writel(0x01, rc_dev->rx_base + IRB_RX_EN);
  307. }
  308. }
  309. return 0;
  310. }
  311. static SIMPLE_DEV_PM_OPS(st_rc_pm_ops, st_rc_suspend, st_rc_resume);
  312. #endif
  313. #ifdef CONFIG_OF
  314. static struct of_device_id st_rc_match[] = {
  315. { .compatible = "st,comms-irb", },
  316. {},
  317. };
  318. MODULE_DEVICE_TABLE(of, st_rc_match);
  319. #endif
  320. static struct platform_driver st_rc_driver = {
  321. .driver = {
  322. .name = IR_ST_NAME,
  323. .owner = THIS_MODULE,
  324. .of_match_table = of_match_ptr(st_rc_match),
  325. #ifdef CONFIG_PM
  326. .pm = &st_rc_pm_ops,
  327. #endif
  328. },
  329. .probe = st_rc_probe,
  330. .remove = st_rc_remove,
  331. };
  332. module_platform_driver(st_rc_driver);
  333. MODULE_DESCRIPTION("RC Transceiver driver for STMicroelectronics platforms");
  334. MODULE_AUTHOR("STMicroelectronics (R&D) Ltd");
  335. MODULE_LICENSE("GPL");