ohci.c 106 KB

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  1. /*
  2. * Driver for OHCI 1394 controllers
  3. *
  4. * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software Foundation,
  18. * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19. */
  20. #include <linux/bitops.h>
  21. #include <linux/bug.h>
  22. #include <linux/compiler.h>
  23. #include <linux/delay.h>
  24. #include <linux/device.h>
  25. #include <linux/dma-mapping.h>
  26. #include <linux/firewire.h>
  27. #include <linux/firewire-constants.h>
  28. #include <linux/init.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/io.h>
  31. #include <linux/kernel.h>
  32. #include <linux/list.h>
  33. #include <linux/mm.h>
  34. #include <linux/module.h>
  35. #include <linux/moduleparam.h>
  36. #include <linux/mutex.h>
  37. #include <linux/pci.h>
  38. #include <linux/pci_ids.h>
  39. #include <linux/slab.h>
  40. #include <linux/spinlock.h>
  41. #include <linux/string.h>
  42. #include <linux/time.h>
  43. #include <linux/vmalloc.h>
  44. #include <linux/workqueue.h>
  45. #include <asm/byteorder.h>
  46. #include <asm/page.h>
  47. #ifdef CONFIG_PPC_PMAC
  48. #include <asm/pmac_feature.h>
  49. #endif
  50. #include "core.h"
  51. #include "ohci.h"
  52. #define ohci_info(ohci, f, args...) dev_info(ohci->card.device, f, ##args)
  53. #define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args)
  54. #define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args)
  55. #define DESCRIPTOR_OUTPUT_MORE 0
  56. #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
  57. #define DESCRIPTOR_INPUT_MORE (2 << 12)
  58. #define DESCRIPTOR_INPUT_LAST (3 << 12)
  59. #define DESCRIPTOR_STATUS (1 << 11)
  60. #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
  61. #define DESCRIPTOR_PING (1 << 7)
  62. #define DESCRIPTOR_YY (1 << 6)
  63. #define DESCRIPTOR_NO_IRQ (0 << 4)
  64. #define DESCRIPTOR_IRQ_ERROR (1 << 4)
  65. #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
  66. #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
  67. #define DESCRIPTOR_WAIT (3 << 0)
  68. #define DESCRIPTOR_CMD (0xf << 12)
  69. struct descriptor {
  70. __le16 req_count;
  71. __le16 control;
  72. __le32 data_address;
  73. __le32 branch_address;
  74. __le16 res_count;
  75. __le16 transfer_status;
  76. } __attribute__((aligned(16)));
  77. #define CONTROL_SET(regs) (regs)
  78. #define CONTROL_CLEAR(regs) ((regs) + 4)
  79. #define COMMAND_PTR(regs) ((regs) + 12)
  80. #define CONTEXT_MATCH(regs) ((regs) + 16)
  81. #define AR_BUFFER_SIZE (32*1024)
  82. #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
  83. /* we need at least two pages for proper list management */
  84. #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
  85. #define MAX_ASYNC_PAYLOAD 4096
  86. #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
  87. #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
  88. struct ar_context {
  89. struct fw_ohci *ohci;
  90. struct page *pages[AR_BUFFERS];
  91. void *buffer;
  92. struct descriptor *descriptors;
  93. dma_addr_t descriptors_bus;
  94. void *pointer;
  95. unsigned int last_buffer_index;
  96. u32 regs;
  97. struct tasklet_struct tasklet;
  98. };
  99. struct context;
  100. typedef int (*descriptor_callback_t)(struct context *ctx,
  101. struct descriptor *d,
  102. struct descriptor *last);
  103. /*
  104. * A buffer that contains a block of DMA-able coherent memory used for
  105. * storing a portion of a DMA descriptor program.
  106. */
  107. struct descriptor_buffer {
  108. struct list_head list;
  109. dma_addr_t buffer_bus;
  110. size_t buffer_size;
  111. size_t used;
  112. struct descriptor buffer[0];
  113. };
  114. struct context {
  115. struct fw_ohci *ohci;
  116. u32 regs;
  117. int total_allocation;
  118. u32 current_bus;
  119. bool running;
  120. bool flushing;
  121. /*
  122. * List of page-sized buffers for storing DMA descriptors.
  123. * Head of list contains buffers in use and tail of list contains
  124. * free buffers.
  125. */
  126. struct list_head buffer_list;
  127. /*
  128. * Pointer to a buffer inside buffer_list that contains the tail
  129. * end of the current DMA program.
  130. */
  131. struct descriptor_buffer *buffer_tail;
  132. /*
  133. * The descriptor containing the branch address of the first
  134. * descriptor that has not yet been filled by the device.
  135. */
  136. struct descriptor *last;
  137. /*
  138. * The last descriptor block in the DMA program. It contains the branch
  139. * address that must be updated upon appending a new descriptor.
  140. */
  141. struct descriptor *prev;
  142. int prev_z;
  143. descriptor_callback_t callback;
  144. struct tasklet_struct tasklet;
  145. };
  146. #define IT_HEADER_SY(v) ((v) << 0)
  147. #define IT_HEADER_TCODE(v) ((v) << 4)
  148. #define IT_HEADER_CHANNEL(v) ((v) << 8)
  149. #define IT_HEADER_TAG(v) ((v) << 14)
  150. #define IT_HEADER_SPEED(v) ((v) << 16)
  151. #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
  152. struct iso_context {
  153. struct fw_iso_context base;
  154. struct context context;
  155. void *header;
  156. size_t header_length;
  157. unsigned long flushing_completions;
  158. u32 mc_buffer_bus;
  159. u16 mc_completed;
  160. u16 last_timestamp;
  161. u8 sync;
  162. u8 tags;
  163. };
  164. #define CONFIG_ROM_SIZE 1024
  165. struct fw_ohci {
  166. struct fw_card card;
  167. __iomem char *registers;
  168. int node_id;
  169. int generation;
  170. int request_generation; /* for timestamping incoming requests */
  171. unsigned quirks;
  172. unsigned int pri_req_max;
  173. u32 bus_time;
  174. bool bus_time_running;
  175. bool is_root;
  176. bool csr_state_setclear_abdicate;
  177. int n_ir;
  178. int n_it;
  179. /*
  180. * Spinlock for accessing fw_ohci data. Never call out of
  181. * this driver with this lock held.
  182. */
  183. spinlock_t lock;
  184. struct mutex phy_reg_mutex;
  185. void *misc_buffer;
  186. dma_addr_t misc_buffer_bus;
  187. struct ar_context ar_request_ctx;
  188. struct ar_context ar_response_ctx;
  189. struct context at_request_ctx;
  190. struct context at_response_ctx;
  191. u32 it_context_support;
  192. u32 it_context_mask; /* unoccupied IT contexts */
  193. struct iso_context *it_context_list;
  194. u64 ir_context_channels; /* unoccupied channels */
  195. u32 ir_context_support;
  196. u32 ir_context_mask; /* unoccupied IR contexts */
  197. struct iso_context *ir_context_list;
  198. u64 mc_channels; /* channels in use by the multichannel IR context */
  199. bool mc_allocated;
  200. __be32 *config_rom;
  201. dma_addr_t config_rom_bus;
  202. __be32 *next_config_rom;
  203. dma_addr_t next_config_rom_bus;
  204. __be32 next_header;
  205. __le32 *self_id;
  206. dma_addr_t self_id_bus;
  207. struct work_struct bus_reset_work;
  208. u32 self_id_buffer[512];
  209. };
  210. static struct workqueue_struct *selfid_workqueue;
  211. static inline struct fw_ohci *fw_ohci(struct fw_card *card)
  212. {
  213. return container_of(card, struct fw_ohci, card);
  214. }
  215. #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
  216. #define IR_CONTEXT_BUFFER_FILL 0x80000000
  217. #define IR_CONTEXT_ISOCH_HEADER 0x40000000
  218. #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
  219. #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
  220. #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
  221. #define CONTEXT_RUN 0x8000
  222. #define CONTEXT_WAKE 0x1000
  223. #define CONTEXT_DEAD 0x0800
  224. #define CONTEXT_ACTIVE 0x0400
  225. #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
  226. #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
  227. #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
  228. #define OHCI1394_REGISTER_SIZE 0x800
  229. #define OHCI1394_PCI_HCI_Control 0x40
  230. #define SELF_ID_BUF_SIZE 0x800
  231. #define OHCI_TCODE_PHY_PACKET 0x0e
  232. #define OHCI_VERSION_1_1 0x010010
  233. static char ohci_driver_name[] = KBUILD_MODNAME;
  234. #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd
  235. #define PCI_DEVICE_ID_AGERE_FW643 0x5901
  236. #define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001
  237. #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
  238. #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
  239. #define PCI_DEVICE_ID_TI_TSB12LV26 0x8020
  240. #define PCI_DEVICE_ID_TI_TSB82AA2 0x8025
  241. #define PCI_DEVICE_ID_VIA_VT630X 0x3044
  242. #define PCI_REV_ID_VIA_VT6306 0x46
  243. #define QUIRK_CYCLE_TIMER 0x1
  244. #define QUIRK_RESET_PACKET 0x2
  245. #define QUIRK_BE_HEADERS 0x4
  246. #define QUIRK_NO_1394A 0x8
  247. #define QUIRK_NO_MSI 0x10
  248. #define QUIRK_TI_SLLZ059 0x20
  249. #define QUIRK_IR_WAKE 0x40
  250. #define QUIRK_PHY_LCTRL_TIMEOUT 0x80
  251. /* In case of multiple matches in ohci_quirks[], only the first one is used. */
  252. static const struct {
  253. unsigned short vendor, device, revision, flags;
  254. } ohci_quirks[] = {
  255. {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
  256. QUIRK_CYCLE_TIMER},
  257. {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
  258. QUIRK_BE_HEADERS},
  259. {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
  260. QUIRK_PHY_LCTRL_TIMEOUT | QUIRK_NO_MSI},
  261. {PCI_VENDOR_ID_ATT, PCI_ANY_ID, PCI_ANY_ID,
  262. QUIRK_PHY_LCTRL_TIMEOUT},
  263. {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
  264. QUIRK_RESET_PACKET},
  265. {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
  266. QUIRK_NO_MSI},
  267. {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
  268. QUIRK_CYCLE_TIMER},
  269. {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
  270. QUIRK_NO_MSI},
  271. {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
  272. QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
  273. {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
  274. QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
  275. {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
  276. QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
  277. {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
  278. QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
  279. {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
  280. QUIRK_RESET_PACKET},
  281. {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306,
  282. QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE},
  283. {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
  284. QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
  285. };
  286. /* This overrides anything that was found in ohci_quirks[]. */
  287. static int param_quirks;
  288. module_param_named(quirks, param_quirks, int, 0644);
  289. MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
  290. ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
  291. ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
  292. ", AR/selfID endianness = " __stringify(QUIRK_BE_HEADERS)
  293. ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
  294. ", disable MSI = " __stringify(QUIRK_NO_MSI)
  295. ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059)
  296. ", IR wake unreliable = " __stringify(QUIRK_IR_WAKE)
  297. ", phy LCtrl timeout = " __stringify(QUIRK_PHY_LCTRL_TIMEOUT)
  298. ")");
  299. #define OHCI_PARAM_DEBUG_AT_AR 1
  300. #define OHCI_PARAM_DEBUG_SELFIDS 2
  301. #define OHCI_PARAM_DEBUG_IRQS 4
  302. #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
  303. static int param_debug;
  304. module_param_named(debug, param_debug, int, 0644);
  305. MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
  306. ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
  307. ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
  308. ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
  309. ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
  310. ", or a combination, or all = -1)");
  311. static void log_irqs(struct fw_ohci *ohci, u32 evt)
  312. {
  313. if (likely(!(param_debug &
  314. (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
  315. return;
  316. if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
  317. !(evt & OHCI1394_busReset))
  318. return;
  319. ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
  320. evt & OHCI1394_selfIDComplete ? " selfID" : "",
  321. evt & OHCI1394_RQPkt ? " AR_req" : "",
  322. evt & OHCI1394_RSPkt ? " AR_resp" : "",
  323. evt & OHCI1394_reqTxComplete ? " AT_req" : "",
  324. evt & OHCI1394_respTxComplete ? " AT_resp" : "",
  325. evt & OHCI1394_isochRx ? " IR" : "",
  326. evt & OHCI1394_isochTx ? " IT" : "",
  327. evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
  328. evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
  329. evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
  330. evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
  331. evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
  332. evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "",
  333. evt & OHCI1394_busReset ? " busReset" : "",
  334. evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
  335. OHCI1394_RSPkt | OHCI1394_reqTxComplete |
  336. OHCI1394_respTxComplete | OHCI1394_isochRx |
  337. OHCI1394_isochTx | OHCI1394_postedWriteErr |
  338. OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
  339. OHCI1394_cycleInconsistent |
  340. OHCI1394_regAccessFail | OHCI1394_busReset)
  341. ? " ?" : "");
  342. }
  343. static const char *speed[] = {
  344. [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
  345. };
  346. static const char *power[] = {
  347. [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
  348. [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
  349. };
  350. static const char port[] = { '.', '-', 'p', 'c', };
  351. static char _p(u32 *s, int shift)
  352. {
  353. return port[*s >> shift & 3];
  354. }
  355. static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
  356. {
  357. u32 *s;
  358. if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
  359. return;
  360. ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n",
  361. self_id_count, generation, ohci->node_id);
  362. for (s = ohci->self_id_buffer; self_id_count--; ++s)
  363. if ((*s & 1 << 23) == 0)
  364. ohci_notice(ohci,
  365. "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n",
  366. *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
  367. speed[*s >> 14 & 3], *s >> 16 & 63,
  368. power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
  369. *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
  370. else
  371. ohci_notice(ohci,
  372. "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
  373. *s, *s >> 24 & 63,
  374. _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
  375. _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
  376. }
  377. static const char *evts[] = {
  378. [0x00] = "evt_no_status", [0x01] = "-reserved-",
  379. [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
  380. [0x04] = "evt_underrun", [0x05] = "evt_overrun",
  381. [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
  382. [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
  383. [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
  384. [0x0c] = "-reserved-", [0x0d] = "-reserved-",
  385. [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
  386. [0x10] = "-reserved-", [0x11] = "ack_complete",
  387. [0x12] = "ack_pending ", [0x13] = "-reserved-",
  388. [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
  389. [0x16] = "ack_busy_B", [0x17] = "-reserved-",
  390. [0x18] = "-reserved-", [0x19] = "-reserved-",
  391. [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
  392. [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
  393. [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
  394. [0x20] = "pending/cancelled",
  395. };
  396. static const char *tcodes[] = {
  397. [0x0] = "QW req", [0x1] = "BW req",
  398. [0x2] = "W resp", [0x3] = "-reserved-",
  399. [0x4] = "QR req", [0x5] = "BR req",
  400. [0x6] = "QR resp", [0x7] = "BR resp",
  401. [0x8] = "cycle start", [0x9] = "Lk req",
  402. [0xa] = "async stream packet", [0xb] = "Lk resp",
  403. [0xc] = "-reserved-", [0xd] = "-reserved-",
  404. [0xe] = "link internal", [0xf] = "-reserved-",
  405. };
  406. static void log_ar_at_event(struct fw_ohci *ohci,
  407. char dir, int speed, u32 *header, int evt)
  408. {
  409. int tcode = header[0] >> 4 & 0xf;
  410. char specific[12];
  411. if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
  412. return;
  413. if (unlikely(evt >= ARRAY_SIZE(evts)))
  414. evt = 0x1f;
  415. if (evt == OHCI1394_evt_bus_reset) {
  416. ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n",
  417. dir, (header[2] >> 16) & 0xff);
  418. return;
  419. }
  420. switch (tcode) {
  421. case 0x0: case 0x6: case 0x8:
  422. snprintf(specific, sizeof(specific), " = %08x",
  423. be32_to_cpu((__force __be32)header[3]));
  424. break;
  425. case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
  426. snprintf(specific, sizeof(specific), " %x,%x",
  427. header[3] >> 16, header[3] & 0xffff);
  428. break;
  429. default:
  430. specific[0] = '\0';
  431. }
  432. switch (tcode) {
  433. case 0xa:
  434. ohci_notice(ohci, "A%c %s, %s\n",
  435. dir, evts[evt], tcodes[tcode]);
  436. break;
  437. case 0xe:
  438. ohci_notice(ohci, "A%c %s, PHY %08x %08x\n",
  439. dir, evts[evt], header[1], header[2]);
  440. break;
  441. case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
  442. ohci_notice(ohci,
  443. "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %04x%08x%s\n",
  444. dir, speed, header[0] >> 10 & 0x3f,
  445. header[1] >> 16, header[0] >> 16, evts[evt],
  446. tcodes[tcode], header[1] & 0xffff, header[2], specific);
  447. break;
  448. default:
  449. ohci_notice(ohci,
  450. "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n",
  451. dir, speed, header[0] >> 10 & 0x3f,
  452. header[1] >> 16, header[0] >> 16, evts[evt],
  453. tcodes[tcode], specific);
  454. }
  455. }
  456. static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
  457. {
  458. writel(data, ohci->registers + offset);
  459. }
  460. static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
  461. {
  462. return readl(ohci->registers + offset);
  463. }
  464. static inline void flush_writes(const struct fw_ohci *ohci)
  465. {
  466. /* Do a dummy read to flush writes. */
  467. reg_read(ohci, OHCI1394_Version);
  468. }
  469. /*
  470. * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and
  471. * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
  472. * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
  473. * directly. Exceptions are intrinsically serialized contexts like pci_probe.
  474. */
  475. static int read_phy_reg(struct fw_ohci *ohci, int addr)
  476. {
  477. u32 val;
  478. int i;
  479. reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
  480. for (i = 0; i < 3 + 100; i++) {
  481. val = reg_read(ohci, OHCI1394_PhyControl);
  482. if (!~val)
  483. return -ENODEV; /* Card was ejected. */
  484. if (val & OHCI1394_PhyControl_ReadDone)
  485. return OHCI1394_PhyControl_ReadData(val);
  486. /*
  487. * Try a few times without waiting. Sleeping is necessary
  488. * only when the link/PHY interface is busy.
  489. */
  490. if (i >= 3)
  491. msleep(1);
  492. }
  493. ohci_err(ohci, "failed to read phy reg %d\n", addr);
  494. dump_stack();
  495. return -EBUSY;
  496. }
  497. static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
  498. {
  499. int i;
  500. reg_write(ohci, OHCI1394_PhyControl,
  501. OHCI1394_PhyControl_Write(addr, val));
  502. for (i = 0; i < 3 + 100; i++) {
  503. val = reg_read(ohci, OHCI1394_PhyControl);
  504. if (!~val)
  505. return -ENODEV; /* Card was ejected. */
  506. if (!(val & OHCI1394_PhyControl_WritePending))
  507. return 0;
  508. if (i >= 3)
  509. msleep(1);
  510. }
  511. ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val);
  512. dump_stack();
  513. return -EBUSY;
  514. }
  515. static int update_phy_reg(struct fw_ohci *ohci, int addr,
  516. int clear_bits, int set_bits)
  517. {
  518. int ret = read_phy_reg(ohci, addr);
  519. if (ret < 0)
  520. return ret;
  521. /*
  522. * The interrupt status bits are cleared by writing a one bit.
  523. * Avoid clearing them unless explicitly requested in set_bits.
  524. */
  525. if (addr == 5)
  526. clear_bits |= PHY_INT_STATUS_BITS;
  527. return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
  528. }
  529. static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
  530. {
  531. int ret;
  532. ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
  533. if (ret < 0)
  534. return ret;
  535. return read_phy_reg(ohci, addr);
  536. }
  537. static int ohci_read_phy_reg(struct fw_card *card, int addr)
  538. {
  539. struct fw_ohci *ohci = fw_ohci(card);
  540. int ret;
  541. mutex_lock(&ohci->phy_reg_mutex);
  542. ret = read_phy_reg(ohci, addr);
  543. mutex_unlock(&ohci->phy_reg_mutex);
  544. return ret;
  545. }
  546. static int ohci_update_phy_reg(struct fw_card *card, int addr,
  547. int clear_bits, int set_bits)
  548. {
  549. struct fw_ohci *ohci = fw_ohci(card);
  550. int ret;
  551. mutex_lock(&ohci->phy_reg_mutex);
  552. ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
  553. mutex_unlock(&ohci->phy_reg_mutex);
  554. return ret;
  555. }
  556. static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
  557. {
  558. return page_private(ctx->pages[i]);
  559. }
  560. static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
  561. {
  562. struct descriptor *d;
  563. d = &ctx->descriptors[index];
  564. d->branch_address &= cpu_to_le32(~0xf);
  565. d->res_count = cpu_to_le16(PAGE_SIZE);
  566. d->transfer_status = 0;
  567. wmb(); /* finish init of new descriptors before branch_address update */
  568. d = &ctx->descriptors[ctx->last_buffer_index];
  569. d->branch_address |= cpu_to_le32(1);
  570. ctx->last_buffer_index = index;
  571. reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
  572. }
  573. static void ar_context_release(struct ar_context *ctx)
  574. {
  575. unsigned int i;
  576. if (ctx->buffer)
  577. vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
  578. for (i = 0; i < AR_BUFFERS; i++)
  579. if (ctx->pages[i]) {
  580. dma_unmap_page(ctx->ohci->card.device,
  581. ar_buffer_bus(ctx, i),
  582. PAGE_SIZE, DMA_FROM_DEVICE);
  583. __free_page(ctx->pages[i]);
  584. }
  585. }
  586. static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
  587. {
  588. struct fw_ohci *ohci = ctx->ohci;
  589. if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
  590. reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
  591. flush_writes(ohci);
  592. ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg);
  593. }
  594. /* FIXME: restart? */
  595. }
  596. static inline unsigned int ar_next_buffer_index(unsigned int index)
  597. {
  598. return (index + 1) % AR_BUFFERS;
  599. }
  600. static inline unsigned int ar_prev_buffer_index(unsigned int index)
  601. {
  602. return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
  603. }
  604. static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
  605. {
  606. return ar_next_buffer_index(ctx->last_buffer_index);
  607. }
  608. /*
  609. * We search for the buffer that contains the last AR packet DMA data written
  610. * by the controller.
  611. */
  612. static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
  613. unsigned int *buffer_offset)
  614. {
  615. unsigned int i, next_i, last = ctx->last_buffer_index;
  616. __le16 res_count, next_res_count;
  617. i = ar_first_buffer_index(ctx);
  618. res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
  619. /* A buffer that is not yet completely filled must be the last one. */
  620. while (i != last && res_count == 0) {
  621. /* Peek at the next descriptor. */
  622. next_i = ar_next_buffer_index(i);
  623. rmb(); /* read descriptors in order */
  624. next_res_count = ACCESS_ONCE(
  625. ctx->descriptors[next_i].res_count);
  626. /*
  627. * If the next descriptor is still empty, we must stop at this
  628. * descriptor.
  629. */
  630. if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
  631. /*
  632. * The exception is when the DMA data for one packet is
  633. * split over three buffers; in this case, the middle
  634. * buffer's descriptor might be never updated by the
  635. * controller and look still empty, and we have to peek
  636. * at the third one.
  637. */
  638. if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
  639. next_i = ar_next_buffer_index(next_i);
  640. rmb();
  641. next_res_count = ACCESS_ONCE(
  642. ctx->descriptors[next_i].res_count);
  643. if (next_res_count != cpu_to_le16(PAGE_SIZE))
  644. goto next_buffer_is_active;
  645. }
  646. break;
  647. }
  648. next_buffer_is_active:
  649. i = next_i;
  650. res_count = next_res_count;
  651. }
  652. rmb(); /* read res_count before the DMA data */
  653. *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
  654. if (*buffer_offset > PAGE_SIZE) {
  655. *buffer_offset = 0;
  656. ar_context_abort(ctx, "corrupted descriptor");
  657. }
  658. return i;
  659. }
  660. static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
  661. unsigned int end_buffer_index,
  662. unsigned int end_buffer_offset)
  663. {
  664. unsigned int i;
  665. i = ar_first_buffer_index(ctx);
  666. while (i != end_buffer_index) {
  667. dma_sync_single_for_cpu(ctx->ohci->card.device,
  668. ar_buffer_bus(ctx, i),
  669. PAGE_SIZE, DMA_FROM_DEVICE);
  670. i = ar_next_buffer_index(i);
  671. }
  672. if (end_buffer_offset > 0)
  673. dma_sync_single_for_cpu(ctx->ohci->card.device,
  674. ar_buffer_bus(ctx, i),
  675. end_buffer_offset, DMA_FROM_DEVICE);
  676. }
  677. #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
  678. #define cond_le32_to_cpu(v) \
  679. (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
  680. #else
  681. #define cond_le32_to_cpu(v) le32_to_cpu(v)
  682. #endif
  683. static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
  684. {
  685. struct fw_ohci *ohci = ctx->ohci;
  686. struct fw_packet p;
  687. u32 status, length, tcode;
  688. int evt;
  689. p.header[0] = cond_le32_to_cpu(buffer[0]);
  690. p.header[1] = cond_le32_to_cpu(buffer[1]);
  691. p.header[2] = cond_le32_to_cpu(buffer[2]);
  692. tcode = (p.header[0] >> 4) & 0x0f;
  693. switch (tcode) {
  694. case TCODE_WRITE_QUADLET_REQUEST:
  695. case TCODE_READ_QUADLET_RESPONSE:
  696. p.header[3] = (__force __u32) buffer[3];
  697. p.header_length = 16;
  698. p.payload_length = 0;
  699. break;
  700. case TCODE_READ_BLOCK_REQUEST :
  701. p.header[3] = cond_le32_to_cpu(buffer[3]);
  702. p.header_length = 16;
  703. p.payload_length = 0;
  704. break;
  705. case TCODE_WRITE_BLOCK_REQUEST:
  706. case TCODE_READ_BLOCK_RESPONSE:
  707. case TCODE_LOCK_REQUEST:
  708. case TCODE_LOCK_RESPONSE:
  709. p.header[3] = cond_le32_to_cpu(buffer[3]);
  710. p.header_length = 16;
  711. p.payload_length = p.header[3] >> 16;
  712. if (p.payload_length > MAX_ASYNC_PAYLOAD) {
  713. ar_context_abort(ctx, "invalid packet length");
  714. return NULL;
  715. }
  716. break;
  717. case TCODE_WRITE_RESPONSE:
  718. case TCODE_READ_QUADLET_REQUEST:
  719. case OHCI_TCODE_PHY_PACKET:
  720. p.header_length = 12;
  721. p.payload_length = 0;
  722. break;
  723. default:
  724. ar_context_abort(ctx, "invalid tcode");
  725. return NULL;
  726. }
  727. p.payload = (void *) buffer + p.header_length;
  728. /* FIXME: What to do about evt_* errors? */
  729. length = (p.header_length + p.payload_length + 3) / 4;
  730. status = cond_le32_to_cpu(buffer[length]);
  731. evt = (status >> 16) & 0x1f;
  732. p.ack = evt - 16;
  733. p.speed = (status >> 21) & 0x7;
  734. p.timestamp = status & 0xffff;
  735. p.generation = ohci->request_generation;
  736. log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
  737. /*
  738. * Several controllers, notably from NEC and VIA, forget to
  739. * write ack_complete status at PHY packet reception.
  740. */
  741. if (evt == OHCI1394_evt_no_status &&
  742. (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
  743. p.ack = ACK_COMPLETE;
  744. /*
  745. * The OHCI bus reset handler synthesizes a PHY packet with
  746. * the new generation number when a bus reset happens (see
  747. * section 8.4.2.3). This helps us determine when a request
  748. * was received and make sure we send the response in the same
  749. * generation. We only need this for requests; for responses
  750. * we use the unique tlabel for finding the matching
  751. * request.
  752. *
  753. * Alas some chips sometimes emit bus reset packets with a
  754. * wrong generation. We set the correct generation for these
  755. * at a slightly incorrect time (in bus_reset_work).
  756. */
  757. if (evt == OHCI1394_evt_bus_reset) {
  758. if (!(ohci->quirks & QUIRK_RESET_PACKET))
  759. ohci->request_generation = (p.header[2] >> 16) & 0xff;
  760. } else if (ctx == &ohci->ar_request_ctx) {
  761. fw_core_handle_request(&ohci->card, &p);
  762. } else {
  763. fw_core_handle_response(&ohci->card, &p);
  764. }
  765. return buffer + length + 1;
  766. }
  767. static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
  768. {
  769. void *next;
  770. while (p < end) {
  771. next = handle_ar_packet(ctx, p);
  772. if (!next)
  773. return p;
  774. p = next;
  775. }
  776. return p;
  777. }
  778. static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
  779. {
  780. unsigned int i;
  781. i = ar_first_buffer_index(ctx);
  782. while (i != end_buffer) {
  783. dma_sync_single_for_device(ctx->ohci->card.device,
  784. ar_buffer_bus(ctx, i),
  785. PAGE_SIZE, DMA_FROM_DEVICE);
  786. ar_context_link_page(ctx, i);
  787. i = ar_next_buffer_index(i);
  788. }
  789. }
  790. static void ar_context_tasklet(unsigned long data)
  791. {
  792. struct ar_context *ctx = (struct ar_context *)data;
  793. unsigned int end_buffer_index, end_buffer_offset;
  794. void *p, *end;
  795. p = ctx->pointer;
  796. if (!p)
  797. return;
  798. end_buffer_index = ar_search_last_active_buffer(ctx,
  799. &end_buffer_offset);
  800. ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
  801. end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
  802. if (end_buffer_index < ar_first_buffer_index(ctx)) {
  803. /*
  804. * The filled part of the overall buffer wraps around; handle
  805. * all packets up to the buffer end here. If the last packet
  806. * wraps around, its tail will be visible after the buffer end
  807. * because the buffer start pages are mapped there again.
  808. */
  809. void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
  810. p = handle_ar_packets(ctx, p, buffer_end);
  811. if (p < buffer_end)
  812. goto error;
  813. /* adjust p to point back into the actual buffer */
  814. p -= AR_BUFFERS * PAGE_SIZE;
  815. }
  816. p = handle_ar_packets(ctx, p, end);
  817. if (p != end) {
  818. if (p > end)
  819. ar_context_abort(ctx, "inconsistent descriptor");
  820. goto error;
  821. }
  822. ctx->pointer = p;
  823. ar_recycle_buffers(ctx, end_buffer_index);
  824. return;
  825. error:
  826. ctx->pointer = NULL;
  827. }
  828. static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
  829. unsigned int descriptors_offset, u32 regs)
  830. {
  831. unsigned int i;
  832. dma_addr_t dma_addr;
  833. struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
  834. struct descriptor *d;
  835. ctx->regs = regs;
  836. ctx->ohci = ohci;
  837. tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
  838. for (i = 0; i < AR_BUFFERS; i++) {
  839. ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
  840. if (!ctx->pages[i])
  841. goto out_of_memory;
  842. dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
  843. 0, PAGE_SIZE, DMA_FROM_DEVICE);
  844. if (dma_mapping_error(ohci->card.device, dma_addr)) {
  845. __free_page(ctx->pages[i]);
  846. ctx->pages[i] = NULL;
  847. goto out_of_memory;
  848. }
  849. set_page_private(ctx->pages[i], dma_addr);
  850. }
  851. for (i = 0; i < AR_BUFFERS; i++)
  852. pages[i] = ctx->pages[i];
  853. for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
  854. pages[AR_BUFFERS + i] = ctx->pages[i];
  855. ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
  856. -1, PAGE_KERNEL);
  857. if (!ctx->buffer)
  858. goto out_of_memory;
  859. ctx->descriptors = ohci->misc_buffer + descriptors_offset;
  860. ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
  861. for (i = 0; i < AR_BUFFERS; i++) {
  862. d = &ctx->descriptors[i];
  863. d->req_count = cpu_to_le16(PAGE_SIZE);
  864. d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
  865. DESCRIPTOR_STATUS |
  866. DESCRIPTOR_BRANCH_ALWAYS);
  867. d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
  868. d->branch_address = cpu_to_le32(ctx->descriptors_bus +
  869. ar_next_buffer_index(i) * sizeof(struct descriptor));
  870. }
  871. return 0;
  872. out_of_memory:
  873. ar_context_release(ctx);
  874. return -ENOMEM;
  875. }
  876. static void ar_context_run(struct ar_context *ctx)
  877. {
  878. unsigned int i;
  879. for (i = 0; i < AR_BUFFERS; i++)
  880. ar_context_link_page(ctx, i);
  881. ctx->pointer = ctx->buffer;
  882. reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
  883. reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
  884. }
  885. static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
  886. {
  887. __le16 branch;
  888. branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
  889. /* figure out which descriptor the branch address goes in */
  890. if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
  891. return d;
  892. else
  893. return d + z - 1;
  894. }
  895. static void context_tasklet(unsigned long data)
  896. {
  897. struct context *ctx = (struct context *) data;
  898. struct descriptor *d, *last;
  899. u32 address;
  900. int z;
  901. struct descriptor_buffer *desc;
  902. desc = list_entry(ctx->buffer_list.next,
  903. struct descriptor_buffer, list);
  904. last = ctx->last;
  905. while (last->branch_address != 0) {
  906. struct descriptor_buffer *old_desc = desc;
  907. address = le32_to_cpu(last->branch_address);
  908. z = address & 0xf;
  909. address &= ~0xf;
  910. ctx->current_bus = address;
  911. /* If the branch address points to a buffer outside of the
  912. * current buffer, advance to the next buffer. */
  913. if (address < desc->buffer_bus ||
  914. address >= desc->buffer_bus + desc->used)
  915. desc = list_entry(desc->list.next,
  916. struct descriptor_buffer, list);
  917. d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
  918. last = find_branch_descriptor(d, z);
  919. if (!ctx->callback(ctx, d, last))
  920. break;
  921. if (old_desc != desc) {
  922. /* If we've advanced to the next buffer, move the
  923. * previous buffer to the free list. */
  924. unsigned long flags;
  925. old_desc->used = 0;
  926. spin_lock_irqsave(&ctx->ohci->lock, flags);
  927. list_move_tail(&old_desc->list, &ctx->buffer_list);
  928. spin_unlock_irqrestore(&ctx->ohci->lock, flags);
  929. }
  930. ctx->last = last;
  931. }
  932. }
  933. /*
  934. * Allocate a new buffer and add it to the list of free buffers for this
  935. * context. Must be called with ohci->lock held.
  936. */
  937. static int context_add_buffer(struct context *ctx)
  938. {
  939. struct descriptor_buffer *desc;
  940. dma_addr_t uninitialized_var(bus_addr);
  941. int offset;
  942. /*
  943. * 16MB of descriptors should be far more than enough for any DMA
  944. * program. This will catch run-away userspace or DoS attacks.
  945. */
  946. if (ctx->total_allocation >= 16*1024*1024)
  947. return -ENOMEM;
  948. desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
  949. &bus_addr, GFP_ATOMIC);
  950. if (!desc)
  951. return -ENOMEM;
  952. offset = (void *)&desc->buffer - (void *)desc;
  953. desc->buffer_size = PAGE_SIZE - offset;
  954. desc->buffer_bus = bus_addr + offset;
  955. desc->used = 0;
  956. list_add_tail(&desc->list, &ctx->buffer_list);
  957. ctx->total_allocation += PAGE_SIZE;
  958. return 0;
  959. }
  960. static int context_init(struct context *ctx, struct fw_ohci *ohci,
  961. u32 regs, descriptor_callback_t callback)
  962. {
  963. ctx->ohci = ohci;
  964. ctx->regs = regs;
  965. ctx->total_allocation = 0;
  966. INIT_LIST_HEAD(&ctx->buffer_list);
  967. if (context_add_buffer(ctx) < 0)
  968. return -ENOMEM;
  969. ctx->buffer_tail = list_entry(ctx->buffer_list.next,
  970. struct descriptor_buffer, list);
  971. tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
  972. ctx->callback = callback;
  973. /*
  974. * We put a dummy descriptor in the buffer that has a NULL
  975. * branch address and looks like it's been sent. That way we
  976. * have a descriptor to append DMA programs to.
  977. */
  978. memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
  979. ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
  980. ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
  981. ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
  982. ctx->last = ctx->buffer_tail->buffer;
  983. ctx->prev = ctx->buffer_tail->buffer;
  984. ctx->prev_z = 1;
  985. return 0;
  986. }
  987. static void context_release(struct context *ctx)
  988. {
  989. struct fw_card *card = &ctx->ohci->card;
  990. struct descriptor_buffer *desc, *tmp;
  991. list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
  992. dma_free_coherent(card->device, PAGE_SIZE, desc,
  993. desc->buffer_bus -
  994. ((void *)&desc->buffer - (void *)desc));
  995. }
  996. /* Must be called with ohci->lock held */
  997. static struct descriptor *context_get_descriptors(struct context *ctx,
  998. int z, dma_addr_t *d_bus)
  999. {
  1000. struct descriptor *d = NULL;
  1001. struct descriptor_buffer *desc = ctx->buffer_tail;
  1002. if (z * sizeof(*d) > desc->buffer_size)
  1003. return NULL;
  1004. if (z * sizeof(*d) > desc->buffer_size - desc->used) {
  1005. /* No room for the descriptor in this buffer, so advance to the
  1006. * next one. */
  1007. if (desc->list.next == &ctx->buffer_list) {
  1008. /* If there is no free buffer next in the list,
  1009. * allocate one. */
  1010. if (context_add_buffer(ctx) < 0)
  1011. return NULL;
  1012. }
  1013. desc = list_entry(desc->list.next,
  1014. struct descriptor_buffer, list);
  1015. ctx->buffer_tail = desc;
  1016. }
  1017. d = desc->buffer + desc->used / sizeof(*d);
  1018. memset(d, 0, z * sizeof(*d));
  1019. *d_bus = desc->buffer_bus + desc->used;
  1020. return d;
  1021. }
  1022. static void context_run(struct context *ctx, u32 extra)
  1023. {
  1024. struct fw_ohci *ohci = ctx->ohci;
  1025. reg_write(ohci, COMMAND_PTR(ctx->regs),
  1026. le32_to_cpu(ctx->last->branch_address));
  1027. reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
  1028. reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
  1029. ctx->running = true;
  1030. flush_writes(ohci);
  1031. }
  1032. static void context_append(struct context *ctx,
  1033. struct descriptor *d, int z, int extra)
  1034. {
  1035. dma_addr_t d_bus;
  1036. struct descriptor_buffer *desc = ctx->buffer_tail;
  1037. struct descriptor *d_branch;
  1038. d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
  1039. desc->used += (z + extra) * sizeof(*d);
  1040. wmb(); /* finish init of new descriptors before branch_address update */
  1041. d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z);
  1042. d_branch->branch_address = cpu_to_le32(d_bus | z);
  1043. /*
  1044. * VT6306 incorrectly checks only the single descriptor at the
  1045. * CommandPtr when the wake bit is written, so if it's a
  1046. * multi-descriptor block starting with an INPUT_MORE, put a copy of
  1047. * the branch address in the first descriptor.
  1048. *
  1049. * Not doing this for transmit contexts since not sure how it interacts
  1050. * with skip addresses.
  1051. */
  1052. if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) &&
  1053. d_branch != ctx->prev &&
  1054. (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) ==
  1055. cpu_to_le16(DESCRIPTOR_INPUT_MORE)) {
  1056. ctx->prev->branch_address = cpu_to_le32(d_bus | z);
  1057. }
  1058. ctx->prev = d;
  1059. ctx->prev_z = z;
  1060. }
  1061. static void context_stop(struct context *ctx)
  1062. {
  1063. struct fw_ohci *ohci = ctx->ohci;
  1064. u32 reg;
  1065. int i;
  1066. reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
  1067. ctx->running = false;
  1068. for (i = 0; i < 1000; i++) {
  1069. reg = reg_read(ohci, CONTROL_SET(ctx->regs));
  1070. if ((reg & CONTEXT_ACTIVE) == 0)
  1071. return;
  1072. if (i)
  1073. udelay(10);
  1074. }
  1075. ohci_err(ohci, "DMA context still active (0x%08x)\n", reg);
  1076. }
  1077. struct driver_data {
  1078. u8 inline_data[8];
  1079. struct fw_packet *packet;
  1080. };
  1081. /*
  1082. * This function apppends a packet to the DMA queue for transmission.
  1083. * Must always be called with the ochi->lock held to ensure proper
  1084. * generation handling and locking around packet queue manipulation.
  1085. */
  1086. static int at_context_queue_packet(struct context *ctx,
  1087. struct fw_packet *packet)
  1088. {
  1089. struct fw_ohci *ohci = ctx->ohci;
  1090. dma_addr_t d_bus, uninitialized_var(payload_bus);
  1091. struct driver_data *driver_data;
  1092. struct descriptor *d, *last;
  1093. __le32 *header;
  1094. int z, tcode;
  1095. d = context_get_descriptors(ctx, 4, &d_bus);
  1096. if (d == NULL) {
  1097. packet->ack = RCODE_SEND_ERROR;
  1098. return -1;
  1099. }
  1100. d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
  1101. d[0].res_count = cpu_to_le16(packet->timestamp);
  1102. /*
  1103. * The DMA format for asynchronous link packets is different
  1104. * from the IEEE1394 layout, so shift the fields around
  1105. * accordingly.
  1106. */
  1107. tcode = (packet->header[0] >> 4) & 0x0f;
  1108. header = (__le32 *) &d[1];
  1109. switch (tcode) {
  1110. case TCODE_WRITE_QUADLET_REQUEST:
  1111. case TCODE_WRITE_BLOCK_REQUEST:
  1112. case TCODE_WRITE_RESPONSE:
  1113. case TCODE_READ_QUADLET_REQUEST:
  1114. case TCODE_READ_BLOCK_REQUEST:
  1115. case TCODE_READ_QUADLET_RESPONSE:
  1116. case TCODE_READ_BLOCK_RESPONSE:
  1117. case TCODE_LOCK_REQUEST:
  1118. case TCODE_LOCK_RESPONSE:
  1119. header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
  1120. (packet->speed << 16));
  1121. header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
  1122. (packet->header[0] & 0xffff0000));
  1123. header[2] = cpu_to_le32(packet->header[2]);
  1124. if (TCODE_IS_BLOCK_PACKET(tcode))
  1125. header[3] = cpu_to_le32(packet->header[3]);
  1126. else
  1127. header[3] = (__force __le32) packet->header[3];
  1128. d[0].req_count = cpu_to_le16(packet->header_length);
  1129. break;
  1130. case TCODE_LINK_INTERNAL:
  1131. header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
  1132. (packet->speed << 16));
  1133. header[1] = cpu_to_le32(packet->header[1]);
  1134. header[2] = cpu_to_le32(packet->header[2]);
  1135. d[0].req_count = cpu_to_le16(12);
  1136. if (is_ping_packet(&packet->header[1]))
  1137. d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
  1138. break;
  1139. case TCODE_STREAM_DATA:
  1140. header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
  1141. (packet->speed << 16));
  1142. header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
  1143. d[0].req_count = cpu_to_le16(8);
  1144. break;
  1145. default:
  1146. /* BUG(); */
  1147. packet->ack = RCODE_SEND_ERROR;
  1148. return -1;
  1149. }
  1150. BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
  1151. driver_data = (struct driver_data *) &d[3];
  1152. driver_data->packet = packet;
  1153. packet->driver_data = driver_data;
  1154. if (packet->payload_length > 0) {
  1155. if (packet->payload_length > sizeof(driver_data->inline_data)) {
  1156. payload_bus = dma_map_single(ohci->card.device,
  1157. packet->payload,
  1158. packet->payload_length,
  1159. DMA_TO_DEVICE);
  1160. if (dma_mapping_error(ohci->card.device, payload_bus)) {
  1161. packet->ack = RCODE_SEND_ERROR;
  1162. return -1;
  1163. }
  1164. packet->payload_bus = payload_bus;
  1165. packet->payload_mapped = true;
  1166. } else {
  1167. memcpy(driver_data->inline_data, packet->payload,
  1168. packet->payload_length);
  1169. payload_bus = d_bus + 3 * sizeof(*d);
  1170. }
  1171. d[2].req_count = cpu_to_le16(packet->payload_length);
  1172. d[2].data_address = cpu_to_le32(payload_bus);
  1173. last = &d[2];
  1174. z = 3;
  1175. } else {
  1176. last = &d[0];
  1177. z = 2;
  1178. }
  1179. last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
  1180. DESCRIPTOR_IRQ_ALWAYS |
  1181. DESCRIPTOR_BRANCH_ALWAYS);
  1182. /* FIXME: Document how the locking works. */
  1183. if (ohci->generation != packet->generation) {
  1184. if (packet->payload_mapped)
  1185. dma_unmap_single(ohci->card.device, payload_bus,
  1186. packet->payload_length, DMA_TO_DEVICE);
  1187. packet->ack = RCODE_GENERATION;
  1188. return -1;
  1189. }
  1190. context_append(ctx, d, z, 4 - z);
  1191. if (ctx->running)
  1192. reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
  1193. else
  1194. context_run(ctx, 0);
  1195. return 0;
  1196. }
  1197. static void at_context_flush(struct context *ctx)
  1198. {
  1199. tasklet_disable(&ctx->tasklet);
  1200. ctx->flushing = true;
  1201. context_tasklet((unsigned long)ctx);
  1202. ctx->flushing = false;
  1203. tasklet_enable(&ctx->tasklet);
  1204. }
  1205. static int handle_at_packet(struct context *context,
  1206. struct descriptor *d,
  1207. struct descriptor *last)
  1208. {
  1209. struct driver_data *driver_data;
  1210. struct fw_packet *packet;
  1211. struct fw_ohci *ohci = context->ohci;
  1212. int evt;
  1213. if (last->transfer_status == 0 && !context->flushing)
  1214. /* This descriptor isn't done yet, stop iteration. */
  1215. return 0;
  1216. driver_data = (struct driver_data *) &d[3];
  1217. packet = driver_data->packet;
  1218. if (packet == NULL)
  1219. /* This packet was cancelled, just continue. */
  1220. return 1;
  1221. if (packet->payload_mapped)
  1222. dma_unmap_single(ohci->card.device, packet->payload_bus,
  1223. packet->payload_length, DMA_TO_DEVICE);
  1224. evt = le16_to_cpu(last->transfer_status) & 0x1f;
  1225. packet->timestamp = le16_to_cpu(last->res_count);
  1226. log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
  1227. switch (evt) {
  1228. case OHCI1394_evt_timeout:
  1229. /* Async response transmit timed out. */
  1230. packet->ack = RCODE_CANCELLED;
  1231. break;
  1232. case OHCI1394_evt_flushed:
  1233. /*
  1234. * The packet was flushed should give same error as
  1235. * when we try to use a stale generation count.
  1236. */
  1237. packet->ack = RCODE_GENERATION;
  1238. break;
  1239. case OHCI1394_evt_missing_ack:
  1240. if (context->flushing)
  1241. packet->ack = RCODE_GENERATION;
  1242. else {
  1243. /*
  1244. * Using a valid (current) generation count, but the
  1245. * node is not on the bus or not sending acks.
  1246. */
  1247. packet->ack = RCODE_NO_ACK;
  1248. }
  1249. break;
  1250. case ACK_COMPLETE + 0x10:
  1251. case ACK_PENDING + 0x10:
  1252. case ACK_BUSY_X + 0x10:
  1253. case ACK_BUSY_A + 0x10:
  1254. case ACK_BUSY_B + 0x10:
  1255. case ACK_DATA_ERROR + 0x10:
  1256. case ACK_TYPE_ERROR + 0x10:
  1257. packet->ack = evt - 0x10;
  1258. break;
  1259. case OHCI1394_evt_no_status:
  1260. if (context->flushing) {
  1261. packet->ack = RCODE_GENERATION;
  1262. break;
  1263. }
  1264. /* fall through */
  1265. default:
  1266. packet->ack = RCODE_SEND_ERROR;
  1267. break;
  1268. }
  1269. packet->callback(packet, &ohci->card, packet->ack);
  1270. return 1;
  1271. }
  1272. #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
  1273. #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
  1274. #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
  1275. #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
  1276. #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
  1277. static void handle_local_rom(struct fw_ohci *ohci,
  1278. struct fw_packet *packet, u32 csr)
  1279. {
  1280. struct fw_packet response;
  1281. int tcode, length, i;
  1282. tcode = HEADER_GET_TCODE(packet->header[0]);
  1283. if (TCODE_IS_BLOCK_PACKET(tcode))
  1284. length = HEADER_GET_DATA_LENGTH(packet->header[3]);
  1285. else
  1286. length = 4;
  1287. i = csr - CSR_CONFIG_ROM;
  1288. if (i + length > CONFIG_ROM_SIZE) {
  1289. fw_fill_response(&response, packet->header,
  1290. RCODE_ADDRESS_ERROR, NULL, 0);
  1291. } else if (!TCODE_IS_READ_REQUEST(tcode)) {
  1292. fw_fill_response(&response, packet->header,
  1293. RCODE_TYPE_ERROR, NULL, 0);
  1294. } else {
  1295. fw_fill_response(&response, packet->header, RCODE_COMPLETE,
  1296. (void *) ohci->config_rom + i, length);
  1297. }
  1298. fw_core_handle_response(&ohci->card, &response);
  1299. }
  1300. static void handle_local_lock(struct fw_ohci *ohci,
  1301. struct fw_packet *packet, u32 csr)
  1302. {
  1303. struct fw_packet response;
  1304. int tcode, length, ext_tcode, sel, try;
  1305. __be32 *payload, lock_old;
  1306. u32 lock_arg, lock_data;
  1307. tcode = HEADER_GET_TCODE(packet->header[0]);
  1308. length = HEADER_GET_DATA_LENGTH(packet->header[3]);
  1309. payload = packet->payload;
  1310. ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
  1311. if (tcode == TCODE_LOCK_REQUEST &&
  1312. ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
  1313. lock_arg = be32_to_cpu(payload[0]);
  1314. lock_data = be32_to_cpu(payload[1]);
  1315. } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
  1316. lock_arg = 0;
  1317. lock_data = 0;
  1318. } else {
  1319. fw_fill_response(&response, packet->header,
  1320. RCODE_TYPE_ERROR, NULL, 0);
  1321. goto out;
  1322. }
  1323. sel = (csr - CSR_BUS_MANAGER_ID) / 4;
  1324. reg_write(ohci, OHCI1394_CSRData, lock_data);
  1325. reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
  1326. reg_write(ohci, OHCI1394_CSRControl, sel);
  1327. for (try = 0; try < 20; try++)
  1328. if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
  1329. lock_old = cpu_to_be32(reg_read(ohci,
  1330. OHCI1394_CSRData));
  1331. fw_fill_response(&response, packet->header,
  1332. RCODE_COMPLETE,
  1333. &lock_old, sizeof(lock_old));
  1334. goto out;
  1335. }
  1336. ohci_err(ohci, "swap not done (CSR lock timeout)\n");
  1337. fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
  1338. out:
  1339. fw_core_handle_response(&ohci->card, &response);
  1340. }
  1341. static void handle_local_request(struct context *ctx, struct fw_packet *packet)
  1342. {
  1343. u64 offset, csr;
  1344. if (ctx == &ctx->ohci->at_request_ctx) {
  1345. packet->ack = ACK_PENDING;
  1346. packet->callback(packet, &ctx->ohci->card, packet->ack);
  1347. }
  1348. offset =
  1349. ((unsigned long long)
  1350. HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
  1351. packet->header[2];
  1352. csr = offset - CSR_REGISTER_BASE;
  1353. /* Handle config rom reads. */
  1354. if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
  1355. handle_local_rom(ctx->ohci, packet, csr);
  1356. else switch (csr) {
  1357. case CSR_BUS_MANAGER_ID:
  1358. case CSR_BANDWIDTH_AVAILABLE:
  1359. case CSR_CHANNELS_AVAILABLE_HI:
  1360. case CSR_CHANNELS_AVAILABLE_LO:
  1361. handle_local_lock(ctx->ohci, packet, csr);
  1362. break;
  1363. default:
  1364. if (ctx == &ctx->ohci->at_request_ctx)
  1365. fw_core_handle_request(&ctx->ohci->card, packet);
  1366. else
  1367. fw_core_handle_response(&ctx->ohci->card, packet);
  1368. break;
  1369. }
  1370. if (ctx == &ctx->ohci->at_response_ctx) {
  1371. packet->ack = ACK_COMPLETE;
  1372. packet->callback(packet, &ctx->ohci->card, packet->ack);
  1373. }
  1374. }
  1375. static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
  1376. {
  1377. unsigned long flags;
  1378. int ret;
  1379. spin_lock_irqsave(&ctx->ohci->lock, flags);
  1380. if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
  1381. ctx->ohci->generation == packet->generation) {
  1382. spin_unlock_irqrestore(&ctx->ohci->lock, flags);
  1383. handle_local_request(ctx, packet);
  1384. return;
  1385. }
  1386. ret = at_context_queue_packet(ctx, packet);
  1387. spin_unlock_irqrestore(&ctx->ohci->lock, flags);
  1388. if (ret < 0)
  1389. packet->callback(packet, &ctx->ohci->card, packet->ack);
  1390. }
  1391. static void detect_dead_context(struct fw_ohci *ohci,
  1392. const char *name, unsigned int regs)
  1393. {
  1394. u32 ctl;
  1395. ctl = reg_read(ohci, CONTROL_SET(regs));
  1396. if (ctl & CONTEXT_DEAD)
  1397. ohci_err(ohci, "DMA context %s has stopped, error code: %s\n",
  1398. name, evts[ctl & 0x1f]);
  1399. }
  1400. static void handle_dead_contexts(struct fw_ohci *ohci)
  1401. {
  1402. unsigned int i;
  1403. char name[8];
  1404. detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
  1405. detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
  1406. detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
  1407. detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
  1408. for (i = 0; i < 32; ++i) {
  1409. if (!(ohci->it_context_support & (1 << i)))
  1410. continue;
  1411. sprintf(name, "IT%u", i);
  1412. detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
  1413. }
  1414. for (i = 0; i < 32; ++i) {
  1415. if (!(ohci->ir_context_support & (1 << i)))
  1416. continue;
  1417. sprintf(name, "IR%u", i);
  1418. detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
  1419. }
  1420. /* TODO: maybe try to flush and restart the dead contexts */
  1421. }
  1422. static u32 cycle_timer_ticks(u32 cycle_timer)
  1423. {
  1424. u32 ticks;
  1425. ticks = cycle_timer & 0xfff;
  1426. ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
  1427. ticks += (3072 * 8000) * (cycle_timer >> 25);
  1428. return ticks;
  1429. }
  1430. /*
  1431. * Some controllers exhibit one or more of the following bugs when updating the
  1432. * iso cycle timer register:
  1433. * - When the lowest six bits are wrapping around to zero, a read that happens
  1434. * at the same time will return garbage in the lowest ten bits.
  1435. * - When the cycleOffset field wraps around to zero, the cycleCount field is
  1436. * not incremented for about 60 ns.
  1437. * - Occasionally, the entire register reads zero.
  1438. *
  1439. * To catch these, we read the register three times and ensure that the
  1440. * difference between each two consecutive reads is approximately the same, i.e.
  1441. * less than twice the other. Furthermore, any negative difference indicates an
  1442. * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
  1443. * execute, so we have enough precision to compute the ratio of the differences.)
  1444. */
  1445. static u32 get_cycle_time(struct fw_ohci *ohci)
  1446. {
  1447. u32 c0, c1, c2;
  1448. u32 t0, t1, t2;
  1449. s32 diff01, diff12;
  1450. int i;
  1451. c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
  1452. if (ohci->quirks & QUIRK_CYCLE_TIMER) {
  1453. i = 0;
  1454. c1 = c2;
  1455. c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
  1456. do {
  1457. c0 = c1;
  1458. c1 = c2;
  1459. c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
  1460. t0 = cycle_timer_ticks(c0);
  1461. t1 = cycle_timer_ticks(c1);
  1462. t2 = cycle_timer_ticks(c2);
  1463. diff01 = t1 - t0;
  1464. diff12 = t2 - t1;
  1465. } while ((diff01 <= 0 || diff12 <= 0 ||
  1466. diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
  1467. && i++ < 20);
  1468. }
  1469. return c2;
  1470. }
  1471. /*
  1472. * This function has to be called at least every 64 seconds. The bus_time
  1473. * field stores not only the upper 25 bits of the BUS_TIME register but also
  1474. * the most significant bit of the cycle timer in bit 6 so that we can detect
  1475. * changes in this bit.
  1476. */
  1477. static u32 update_bus_time(struct fw_ohci *ohci)
  1478. {
  1479. u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
  1480. if (unlikely(!ohci->bus_time_running)) {
  1481. reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds);
  1482. ohci->bus_time = (lower_32_bits(get_seconds()) & ~0x7f) |
  1483. (cycle_time_seconds & 0x40);
  1484. ohci->bus_time_running = true;
  1485. }
  1486. if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
  1487. ohci->bus_time += 0x40;
  1488. return ohci->bus_time | cycle_time_seconds;
  1489. }
  1490. static int get_status_for_port(struct fw_ohci *ohci, int port_index)
  1491. {
  1492. int reg;
  1493. mutex_lock(&ohci->phy_reg_mutex);
  1494. reg = write_phy_reg(ohci, 7, port_index);
  1495. if (reg >= 0)
  1496. reg = read_phy_reg(ohci, 8);
  1497. mutex_unlock(&ohci->phy_reg_mutex);
  1498. if (reg < 0)
  1499. return reg;
  1500. switch (reg & 0x0f) {
  1501. case 0x06:
  1502. return 2; /* is child node (connected to parent node) */
  1503. case 0x0e:
  1504. return 3; /* is parent node (connected to child node) */
  1505. }
  1506. return 1; /* not connected */
  1507. }
  1508. static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
  1509. int self_id_count)
  1510. {
  1511. int i;
  1512. u32 entry;
  1513. for (i = 0; i < self_id_count; i++) {
  1514. entry = ohci->self_id_buffer[i];
  1515. if ((self_id & 0xff000000) == (entry & 0xff000000))
  1516. return -1;
  1517. if ((self_id & 0xff000000) < (entry & 0xff000000))
  1518. return i;
  1519. }
  1520. return i;
  1521. }
  1522. static int initiated_reset(struct fw_ohci *ohci)
  1523. {
  1524. int reg;
  1525. int ret = 0;
  1526. mutex_lock(&ohci->phy_reg_mutex);
  1527. reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */
  1528. if (reg >= 0) {
  1529. reg = read_phy_reg(ohci, 8);
  1530. reg |= 0x40;
  1531. reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */
  1532. if (reg >= 0) {
  1533. reg = read_phy_reg(ohci, 12); /* read register 12 */
  1534. if (reg >= 0) {
  1535. if ((reg & 0x08) == 0x08) {
  1536. /* bit 3 indicates "initiated reset" */
  1537. ret = 0x2;
  1538. }
  1539. }
  1540. }
  1541. }
  1542. mutex_unlock(&ohci->phy_reg_mutex);
  1543. return ret;
  1544. }
  1545. /*
  1546. * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
  1547. * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
  1548. * Construct the selfID from phy register contents.
  1549. */
  1550. static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
  1551. {
  1552. int reg, i, pos, status;
  1553. /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
  1554. u32 self_id = 0x8040c800;
  1555. reg = reg_read(ohci, OHCI1394_NodeID);
  1556. if (!(reg & OHCI1394_NodeID_idValid)) {
  1557. ohci_notice(ohci,
  1558. "node ID not valid, new bus reset in progress\n");
  1559. return -EBUSY;
  1560. }
  1561. self_id |= ((reg & 0x3f) << 24); /* phy ID */
  1562. reg = ohci_read_phy_reg(&ohci->card, 4);
  1563. if (reg < 0)
  1564. return reg;
  1565. self_id |= ((reg & 0x07) << 8); /* power class */
  1566. reg = ohci_read_phy_reg(&ohci->card, 1);
  1567. if (reg < 0)
  1568. return reg;
  1569. self_id |= ((reg & 0x3f) << 16); /* gap count */
  1570. for (i = 0; i < 3; i++) {
  1571. status = get_status_for_port(ohci, i);
  1572. if (status < 0)
  1573. return status;
  1574. self_id |= ((status & 0x3) << (6 - (i * 2)));
  1575. }
  1576. self_id |= initiated_reset(ohci);
  1577. pos = get_self_id_pos(ohci, self_id, self_id_count);
  1578. if (pos >= 0) {
  1579. memmove(&(ohci->self_id_buffer[pos+1]),
  1580. &(ohci->self_id_buffer[pos]),
  1581. (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
  1582. ohci->self_id_buffer[pos] = self_id;
  1583. self_id_count++;
  1584. }
  1585. return self_id_count;
  1586. }
  1587. static void bus_reset_work(struct work_struct *work)
  1588. {
  1589. struct fw_ohci *ohci =
  1590. container_of(work, struct fw_ohci, bus_reset_work);
  1591. int self_id_count, generation, new_generation, i, j;
  1592. u32 reg;
  1593. void *free_rom = NULL;
  1594. dma_addr_t free_rom_bus = 0;
  1595. bool is_new_root;
  1596. reg = reg_read(ohci, OHCI1394_NodeID);
  1597. if (!(reg & OHCI1394_NodeID_idValid)) {
  1598. ohci_notice(ohci,
  1599. "node ID not valid, new bus reset in progress\n");
  1600. return;
  1601. }
  1602. if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
  1603. ohci_notice(ohci, "malconfigured bus\n");
  1604. return;
  1605. }
  1606. ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
  1607. OHCI1394_NodeID_nodeNumber);
  1608. is_new_root = (reg & OHCI1394_NodeID_root) != 0;
  1609. if (!(ohci->is_root && is_new_root))
  1610. reg_write(ohci, OHCI1394_LinkControlSet,
  1611. OHCI1394_LinkControl_cycleMaster);
  1612. ohci->is_root = is_new_root;
  1613. reg = reg_read(ohci, OHCI1394_SelfIDCount);
  1614. if (reg & OHCI1394_SelfIDCount_selfIDError) {
  1615. ohci_notice(ohci, "self ID receive error\n");
  1616. return;
  1617. }
  1618. /*
  1619. * The count in the SelfIDCount register is the number of
  1620. * bytes in the self ID receive buffer. Since we also receive
  1621. * the inverted quadlets and a header quadlet, we shift one
  1622. * bit extra to get the actual number of self IDs.
  1623. */
  1624. self_id_count = (reg >> 3) & 0xff;
  1625. if (self_id_count > 252) {
  1626. ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg);
  1627. return;
  1628. }
  1629. generation = (cond_le32_to_cpu(ohci->self_id[0]) >> 16) & 0xff;
  1630. rmb();
  1631. for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
  1632. u32 id = cond_le32_to_cpu(ohci->self_id[i]);
  1633. u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1]);
  1634. if (id != ~id2) {
  1635. /*
  1636. * If the invalid data looks like a cycle start packet,
  1637. * it's likely to be the result of the cycle master
  1638. * having a wrong gap count. In this case, the self IDs
  1639. * so far are valid and should be processed so that the
  1640. * bus manager can then correct the gap count.
  1641. */
  1642. if (id == 0xffff008f) {
  1643. ohci_notice(ohci, "ignoring spurious self IDs\n");
  1644. self_id_count = j;
  1645. break;
  1646. }
  1647. ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n",
  1648. j, self_id_count, id, id2);
  1649. return;
  1650. }
  1651. ohci->self_id_buffer[j] = id;
  1652. }
  1653. if (ohci->quirks & QUIRK_TI_SLLZ059) {
  1654. self_id_count = find_and_insert_self_id(ohci, self_id_count);
  1655. if (self_id_count < 0) {
  1656. ohci_notice(ohci,
  1657. "could not construct local self ID\n");
  1658. return;
  1659. }
  1660. }
  1661. if (self_id_count == 0) {
  1662. ohci_notice(ohci, "no self IDs\n");
  1663. return;
  1664. }
  1665. rmb();
  1666. /*
  1667. * Check the consistency of the self IDs we just read. The
  1668. * problem we face is that a new bus reset can start while we
  1669. * read out the self IDs from the DMA buffer. If this happens,
  1670. * the DMA buffer will be overwritten with new self IDs and we
  1671. * will read out inconsistent data. The OHCI specification
  1672. * (section 11.2) recommends a technique similar to
  1673. * linux/seqlock.h, where we remember the generation of the
  1674. * self IDs in the buffer before reading them out and compare
  1675. * it to the current generation after reading them out. If
  1676. * the two generations match we know we have a consistent set
  1677. * of self IDs.
  1678. */
  1679. new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
  1680. if (new_generation != generation) {
  1681. ohci_notice(ohci, "new bus reset, discarding self ids\n");
  1682. return;
  1683. }
  1684. /* FIXME: Document how the locking works. */
  1685. spin_lock_irq(&ohci->lock);
  1686. ohci->generation = -1; /* prevent AT packet queueing */
  1687. context_stop(&ohci->at_request_ctx);
  1688. context_stop(&ohci->at_response_ctx);
  1689. spin_unlock_irq(&ohci->lock);
  1690. /*
  1691. * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
  1692. * packets in the AT queues and software needs to drain them.
  1693. * Some OHCI 1.1 controllers (JMicron) apparently require this too.
  1694. */
  1695. at_context_flush(&ohci->at_request_ctx);
  1696. at_context_flush(&ohci->at_response_ctx);
  1697. spin_lock_irq(&ohci->lock);
  1698. ohci->generation = generation;
  1699. reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
  1700. if (ohci->quirks & QUIRK_RESET_PACKET)
  1701. ohci->request_generation = generation;
  1702. /*
  1703. * This next bit is unrelated to the AT context stuff but we
  1704. * have to do it under the spinlock also. If a new config rom
  1705. * was set up before this reset, the old one is now no longer
  1706. * in use and we can free it. Update the config rom pointers
  1707. * to point to the current config rom and clear the
  1708. * next_config_rom pointer so a new update can take place.
  1709. */
  1710. if (ohci->next_config_rom != NULL) {
  1711. if (ohci->next_config_rom != ohci->config_rom) {
  1712. free_rom = ohci->config_rom;
  1713. free_rom_bus = ohci->config_rom_bus;
  1714. }
  1715. ohci->config_rom = ohci->next_config_rom;
  1716. ohci->config_rom_bus = ohci->next_config_rom_bus;
  1717. ohci->next_config_rom = NULL;
  1718. /*
  1719. * Restore config_rom image and manually update
  1720. * config_rom registers. Writing the header quadlet
  1721. * will indicate that the config rom is ready, so we
  1722. * do that last.
  1723. */
  1724. reg_write(ohci, OHCI1394_BusOptions,
  1725. be32_to_cpu(ohci->config_rom[2]));
  1726. ohci->config_rom[0] = ohci->next_header;
  1727. reg_write(ohci, OHCI1394_ConfigROMhdr,
  1728. be32_to_cpu(ohci->next_header));
  1729. }
  1730. #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
  1731. reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
  1732. reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
  1733. #endif
  1734. spin_unlock_irq(&ohci->lock);
  1735. if (free_rom)
  1736. dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
  1737. free_rom, free_rom_bus);
  1738. log_selfids(ohci, generation, self_id_count);
  1739. fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
  1740. self_id_count, ohci->self_id_buffer,
  1741. ohci->csr_state_setclear_abdicate);
  1742. ohci->csr_state_setclear_abdicate = false;
  1743. }
  1744. static irqreturn_t irq_handler(int irq, void *data)
  1745. {
  1746. struct fw_ohci *ohci = data;
  1747. u32 event, iso_event;
  1748. int i;
  1749. event = reg_read(ohci, OHCI1394_IntEventClear);
  1750. if (!event || !~event)
  1751. return IRQ_NONE;
  1752. /*
  1753. * busReset and postedWriteErr must not be cleared yet
  1754. * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
  1755. */
  1756. reg_write(ohci, OHCI1394_IntEventClear,
  1757. event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
  1758. log_irqs(ohci, event);
  1759. if (event & OHCI1394_selfIDComplete)
  1760. queue_work(selfid_workqueue, &ohci->bus_reset_work);
  1761. if (event & OHCI1394_RQPkt)
  1762. tasklet_schedule(&ohci->ar_request_ctx.tasklet);
  1763. if (event & OHCI1394_RSPkt)
  1764. tasklet_schedule(&ohci->ar_response_ctx.tasklet);
  1765. if (event & OHCI1394_reqTxComplete)
  1766. tasklet_schedule(&ohci->at_request_ctx.tasklet);
  1767. if (event & OHCI1394_respTxComplete)
  1768. tasklet_schedule(&ohci->at_response_ctx.tasklet);
  1769. if (event & OHCI1394_isochRx) {
  1770. iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
  1771. reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
  1772. while (iso_event) {
  1773. i = ffs(iso_event) - 1;
  1774. tasklet_schedule(
  1775. &ohci->ir_context_list[i].context.tasklet);
  1776. iso_event &= ~(1 << i);
  1777. }
  1778. }
  1779. if (event & OHCI1394_isochTx) {
  1780. iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
  1781. reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
  1782. while (iso_event) {
  1783. i = ffs(iso_event) - 1;
  1784. tasklet_schedule(
  1785. &ohci->it_context_list[i].context.tasklet);
  1786. iso_event &= ~(1 << i);
  1787. }
  1788. }
  1789. if (unlikely(event & OHCI1394_regAccessFail))
  1790. ohci_err(ohci, "register access failure\n");
  1791. if (unlikely(event & OHCI1394_postedWriteErr)) {
  1792. reg_read(ohci, OHCI1394_PostedWriteAddressHi);
  1793. reg_read(ohci, OHCI1394_PostedWriteAddressLo);
  1794. reg_write(ohci, OHCI1394_IntEventClear,
  1795. OHCI1394_postedWriteErr);
  1796. if (printk_ratelimit())
  1797. ohci_err(ohci, "PCI posted write error\n");
  1798. }
  1799. if (unlikely(event & OHCI1394_cycleTooLong)) {
  1800. if (printk_ratelimit())
  1801. ohci_notice(ohci, "isochronous cycle too long\n");
  1802. reg_write(ohci, OHCI1394_LinkControlSet,
  1803. OHCI1394_LinkControl_cycleMaster);
  1804. }
  1805. if (unlikely(event & OHCI1394_cycleInconsistent)) {
  1806. /*
  1807. * We need to clear this event bit in order to make
  1808. * cycleMatch isochronous I/O work. In theory we should
  1809. * stop active cycleMatch iso contexts now and restart
  1810. * them at least two cycles later. (FIXME?)
  1811. */
  1812. if (printk_ratelimit())
  1813. ohci_notice(ohci, "isochronous cycle inconsistent\n");
  1814. }
  1815. if (unlikely(event & OHCI1394_unrecoverableError))
  1816. handle_dead_contexts(ohci);
  1817. if (event & OHCI1394_cycle64Seconds) {
  1818. spin_lock(&ohci->lock);
  1819. update_bus_time(ohci);
  1820. spin_unlock(&ohci->lock);
  1821. } else
  1822. flush_writes(ohci);
  1823. return IRQ_HANDLED;
  1824. }
  1825. static int software_reset(struct fw_ohci *ohci)
  1826. {
  1827. u32 val;
  1828. int i;
  1829. reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
  1830. for (i = 0; i < 500; i++) {
  1831. val = reg_read(ohci, OHCI1394_HCControlSet);
  1832. if (!~val)
  1833. return -ENODEV; /* Card was ejected. */
  1834. if (!(val & OHCI1394_HCControl_softReset))
  1835. return 0;
  1836. msleep(1);
  1837. }
  1838. return -EBUSY;
  1839. }
  1840. static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
  1841. {
  1842. size_t size = length * 4;
  1843. memcpy(dest, src, size);
  1844. if (size < CONFIG_ROM_SIZE)
  1845. memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
  1846. }
  1847. static int configure_1394a_enhancements(struct fw_ohci *ohci)
  1848. {
  1849. bool enable_1394a;
  1850. int ret, clear, set, offset;
  1851. /* Check if the driver should configure link and PHY. */
  1852. if (!(reg_read(ohci, OHCI1394_HCControlSet) &
  1853. OHCI1394_HCControl_programPhyEnable))
  1854. return 0;
  1855. /* Paranoia: check whether the PHY supports 1394a, too. */
  1856. enable_1394a = false;
  1857. ret = read_phy_reg(ohci, 2);
  1858. if (ret < 0)
  1859. return ret;
  1860. if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
  1861. ret = read_paged_phy_reg(ohci, 1, 8);
  1862. if (ret < 0)
  1863. return ret;
  1864. if (ret >= 1)
  1865. enable_1394a = true;
  1866. }
  1867. if (ohci->quirks & QUIRK_NO_1394A)
  1868. enable_1394a = false;
  1869. /* Configure PHY and link consistently. */
  1870. if (enable_1394a) {
  1871. clear = 0;
  1872. set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
  1873. } else {
  1874. clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
  1875. set = 0;
  1876. }
  1877. ret = update_phy_reg(ohci, 5, clear, set);
  1878. if (ret < 0)
  1879. return ret;
  1880. if (enable_1394a)
  1881. offset = OHCI1394_HCControlSet;
  1882. else
  1883. offset = OHCI1394_HCControlClear;
  1884. reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
  1885. /* Clean up: configuration has been taken care of. */
  1886. reg_write(ohci, OHCI1394_HCControlClear,
  1887. OHCI1394_HCControl_programPhyEnable);
  1888. return 0;
  1889. }
  1890. static int probe_tsb41ba3d(struct fw_ohci *ohci)
  1891. {
  1892. /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
  1893. static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
  1894. int reg, i;
  1895. reg = read_phy_reg(ohci, 2);
  1896. if (reg < 0)
  1897. return reg;
  1898. if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
  1899. return 0;
  1900. for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
  1901. reg = read_paged_phy_reg(ohci, 1, i + 10);
  1902. if (reg < 0)
  1903. return reg;
  1904. if (reg != id[i])
  1905. return 0;
  1906. }
  1907. return 1;
  1908. }
  1909. static int ohci_enable(struct fw_card *card,
  1910. const __be32 *config_rom, size_t length)
  1911. {
  1912. struct fw_ohci *ohci = fw_ohci(card);
  1913. u32 lps, version, irqs;
  1914. int i, ret;
  1915. if (software_reset(ohci)) {
  1916. ohci_err(ohci, "failed to reset ohci card\n");
  1917. return -EBUSY;
  1918. }
  1919. /*
  1920. * Now enable LPS, which we need in order to start accessing
  1921. * most of the registers. In fact, on some cards (ALI M5251),
  1922. * accessing registers in the SClk domain without LPS enabled
  1923. * will lock up the machine. Wait 50msec to make sure we have
  1924. * full link enabled. However, with some cards (well, at least
  1925. * a JMicron PCIe card), we have to try again sometimes.
  1926. *
  1927. * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but
  1928. * cannot actually use the phy at that time. These need tens of
  1929. * millisecods pause between LPS write and first phy access too.
  1930. *
  1931. * But do not wait for 50msec on Agere/LSI cards. Their phy
  1932. * arbitration state machine may time out during such a long wait.
  1933. */
  1934. reg_write(ohci, OHCI1394_HCControlSet,
  1935. OHCI1394_HCControl_LPS |
  1936. OHCI1394_HCControl_postedWriteEnable);
  1937. flush_writes(ohci);
  1938. if (!(ohci->quirks & QUIRK_PHY_LCTRL_TIMEOUT))
  1939. msleep(50);
  1940. for (lps = 0, i = 0; !lps && i < 150; i++) {
  1941. msleep(1);
  1942. lps = reg_read(ohci, OHCI1394_HCControlSet) &
  1943. OHCI1394_HCControl_LPS;
  1944. }
  1945. if (!lps) {
  1946. ohci_err(ohci, "failed to set Link Power Status\n");
  1947. return -EIO;
  1948. }
  1949. if (ohci->quirks & QUIRK_TI_SLLZ059) {
  1950. ret = probe_tsb41ba3d(ohci);
  1951. if (ret < 0)
  1952. return ret;
  1953. if (ret)
  1954. ohci_notice(ohci, "local TSB41BA3D phy\n");
  1955. else
  1956. ohci->quirks &= ~QUIRK_TI_SLLZ059;
  1957. }
  1958. reg_write(ohci, OHCI1394_HCControlClear,
  1959. OHCI1394_HCControl_noByteSwapData);
  1960. reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
  1961. reg_write(ohci, OHCI1394_LinkControlSet,
  1962. OHCI1394_LinkControl_cycleTimerEnable |
  1963. OHCI1394_LinkControl_cycleMaster);
  1964. reg_write(ohci, OHCI1394_ATRetries,
  1965. OHCI1394_MAX_AT_REQ_RETRIES |
  1966. (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
  1967. (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
  1968. (200 << 16));
  1969. ohci->bus_time_running = false;
  1970. for (i = 0; i < 32; i++)
  1971. if (ohci->ir_context_support & (1 << i))
  1972. reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i),
  1973. IR_CONTEXT_MULTI_CHANNEL_MODE);
  1974. version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
  1975. if (version >= OHCI_VERSION_1_1) {
  1976. reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
  1977. 0xfffffffe);
  1978. card->broadcast_channel_auto_allocated = true;
  1979. }
  1980. /* Get implemented bits of the priority arbitration request counter. */
  1981. reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
  1982. ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
  1983. reg_write(ohci, OHCI1394_FairnessControl, 0);
  1984. card->priority_budget_implemented = ohci->pri_req_max != 0;
  1985. reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
  1986. reg_write(ohci, OHCI1394_IntEventClear, ~0);
  1987. reg_write(ohci, OHCI1394_IntMaskClear, ~0);
  1988. ret = configure_1394a_enhancements(ohci);
  1989. if (ret < 0)
  1990. return ret;
  1991. /* Activate link_on bit and contender bit in our self ID packets.*/
  1992. ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
  1993. if (ret < 0)
  1994. return ret;
  1995. /*
  1996. * When the link is not yet enabled, the atomic config rom
  1997. * update mechanism described below in ohci_set_config_rom()
  1998. * is not active. We have to update ConfigRomHeader and
  1999. * BusOptions manually, and the write to ConfigROMmap takes
  2000. * effect immediately. We tie this to the enabling of the
  2001. * link, so we have a valid config rom before enabling - the
  2002. * OHCI requires that ConfigROMhdr and BusOptions have valid
  2003. * values before enabling.
  2004. *
  2005. * However, when the ConfigROMmap is written, some controllers
  2006. * always read back quadlets 0 and 2 from the config rom to
  2007. * the ConfigRomHeader and BusOptions registers on bus reset.
  2008. * They shouldn't do that in this initial case where the link
  2009. * isn't enabled. This means we have to use the same
  2010. * workaround here, setting the bus header to 0 and then write
  2011. * the right values in the bus reset tasklet.
  2012. */
  2013. if (config_rom) {
  2014. ohci->next_config_rom =
  2015. dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
  2016. &ohci->next_config_rom_bus,
  2017. GFP_KERNEL);
  2018. if (ohci->next_config_rom == NULL)
  2019. return -ENOMEM;
  2020. copy_config_rom(ohci->next_config_rom, config_rom, length);
  2021. } else {
  2022. /*
  2023. * In the suspend case, config_rom is NULL, which
  2024. * means that we just reuse the old config rom.
  2025. */
  2026. ohci->next_config_rom = ohci->config_rom;
  2027. ohci->next_config_rom_bus = ohci->config_rom_bus;
  2028. }
  2029. ohci->next_header = ohci->next_config_rom[0];
  2030. ohci->next_config_rom[0] = 0;
  2031. reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
  2032. reg_write(ohci, OHCI1394_BusOptions,
  2033. be32_to_cpu(ohci->next_config_rom[2]));
  2034. reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
  2035. reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
  2036. irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
  2037. OHCI1394_RQPkt | OHCI1394_RSPkt |
  2038. OHCI1394_isochTx | OHCI1394_isochRx |
  2039. OHCI1394_postedWriteErr |
  2040. OHCI1394_selfIDComplete |
  2041. OHCI1394_regAccessFail |
  2042. OHCI1394_cycleInconsistent |
  2043. OHCI1394_unrecoverableError |
  2044. OHCI1394_cycleTooLong |
  2045. OHCI1394_masterIntEnable;
  2046. if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
  2047. irqs |= OHCI1394_busReset;
  2048. reg_write(ohci, OHCI1394_IntMaskSet, irqs);
  2049. reg_write(ohci, OHCI1394_HCControlSet,
  2050. OHCI1394_HCControl_linkEnable |
  2051. OHCI1394_HCControl_BIBimageValid);
  2052. reg_write(ohci, OHCI1394_LinkControlSet,
  2053. OHCI1394_LinkControl_rcvSelfID |
  2054. OHCI1394_LinkControl_rcvPhyPkt);
  2055. ar_context_run(&ohci->ar_request_ctx);
  2056. ar_context_run(&ohci->ar_response_ctx);
  2057. flush_writes(ohci);
  2058. /* We are ready to go, reset bus to finish initialization. */
  2059. fw_schedule_bus_reset(&ohci->card, false, true);
  2060. return 0;
  2061. }
  2062. static int ohci_set_config_rom(struct fw_card *card,
  2063. const __be32 *config_rom, size_t length)
  2064. {
  2065. struct fw_ohci *ohci;
  2066. __be32 *next_config_rom;
  2067. dma_addr_t uninitialized_var(next_config_rom_bus);
  2068. ohci = fw_ohci(card);
  2069. /*
  2070. * When the OHCI controller is enabled, the config rom update
  2071. * mechanism is a bit tricky, but easy enough to use. See
  2072. * section 5.5.6 in the OHCI specification.
  2073. *
  2074. * The OHCI controller caches the new config rom address in a
  2075. * shadow register (ConfigROMmapNext) and needs a bus reset
  2076. * for the changes to take place. When the bus reset is
  2077. * detected, the controller loads the new values for the
  2078. * ConfigRomHeader and BusOptions registers from the specified
  2079. * config rom and loads ConfigROMmap from the ConfigROMmapNext
  2080. * shadow register. All automatically and atomically.
  2081. *
  2082. * Now, there's a twist to this story. The automatic load of
  2083. * ConfigRomHeader and BusOptions doesn't honor the
  2084. * noByteSwapData bit, so with a be32 config rom, the
  2085. * controller will load be32 values in to these registers
  2086. * during the atomic update, even on litte endian
  2087. * architectures. The workaround we use is to put a 0 in the
  2088. * header quadlet; 0 is endian agnostic and means that the
  2089. * config rom isn't ready yet. In the bus reset tasklet we
  2090. * then set up the real values for the two registers.
  2091. *
  2092. * We use ohci->lock to avoid racing with the code that sets
  2093. * ohci->next_config_rom to NULL (see bus_reset_work).
  2094. */
  2095. next_config_rom =
  2096. dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
  2097. &next_config_rom_bus, GFP_KERNEL);
  2098. if (next_config_rom == NULL)
  2099. return -ENOMEM;
  2100. spin_lock_irq(&ohci->lock);
  2101. /*
  2102. * If there is not an already pending config_rom update,
  2103. * push our new allocation into the ohci->next_config_rom
  2104. * and then mark the local variable as null so that we
  2105. * won't deallocate the new buffer.
  2106. *
  2107. * OTOH, if there is a pending config_rom update, just
  2108. * use that buffer with the new config_rom data, and
  2109. * let this routine free the unused DMA allocation.
  2110. */
  2111. if (ohci->next_config_rom == NULL) {
  2112. ohci->next_config_rom = next_config_rom;
  2113. ohci->next_config_rom_bus = next_config_rom_bus;
  2114. next_config_rom = NULL;
  2115. }
  2116. copy_config_rom(ohci->next_config_rom, config_rom, length);
  2117. ohci->next_header = config_rom[0];
  2118. ohci->next_config_rom[0] = 0;
  2119. reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
  2120. spin_unlock_irq(&ohci->lock);
  2121. /* If we didn't use the DMA allocation, delete it. */
  2122. if (next_config_rom != NULL)
  2123. dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
  2124. next_config_rom, next_config_rom_bus);
  2125. /*
  2126. * Now initiate a bus reset to have the changes take
  2127. * effect. We clean up the old config rom memory and DMA
  2128. * mappings in the bus reset tasklet, since the OHCI
  2129. * controller could need to access it before the bus reset
  2130. * takes effect.
  2131. */
  2132. fw_schedule_bus_reset(&ohci->card, true, true);
  2133. return 0;
  2134. }
  2135. static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
  2136. {
  2137. struct fw_ohci *ohci = fw_ohci(card);
  2138. at_context_transmit(&ohci->at_request_ctx, packet);
  2139. }
  2140. static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
  2141. {
  2142. struct fw_ohci *ohci = fw_ohci(card);
  2143. at_context_transmit(&ohci->at_response_ctx, packet);
  2144. }
  2145. static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
  2146. {
  2147. struct fw_ohci *ohci = fw_ohci(card);
  2148. struct context *ctx = &ohci->at_request_ctx;
  2149. struct driver_data *driver_data = packet->driver_data;
  2150. int ret = -ENOENT;
  2151. tasklet_disable(&ctx->tasklet);
  2152. if (packet->ack != 0)
  2153. goto out;
  2154. if (packet->payload_mapped)
  2155. dma_unmap_single(ohci->card.device, packet->payload_bus,
  2156. packet->payload_length, DMA_TO_DEVICE);
  2157. log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
  2158. driver_data->packet = NULL;
  2159. packet->ack = RCODE_CANCELLED;
  2160. packet->callback(packet, &ohci->card, packet->ack);
  2161. ret = 0;
  2162. out:
  2163. tasklet_enable(&ctx->tasklet);
  2164. return ret;
  2165. }
  2166. static int ohci_enable_phys_dma(struct fw_card *card,
  2167. int node_id, int generation)
  2168. {
  2169. #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
  2170. return 0;
  2171. #else
  2172. struct fw_ohci *ohci = fw_ohci(card);
  2173. unsigned long flags;
  2174. int n, ret = 0;
  2175. /*
  2176. * FIXME: Make sure this bitmask is cleared when we clear the busReset
  2177. * interrupt bit. Clear physReqResourceAllBuses on bus reset.
  2178. */
  2179. spin_lock_irqsave(&ohci->lock, flags);
  2180. if (ohci->generation != generation) {
  2181. ret = -ESTALE;
  2182. goto out;
  2183. }
  2184. /*
  2185. * Note, if the node ID contains a non-local bus ID, physical DMA is
  2186. * enabled for _all_ nodes on remote buses.
  2187. */
  2188. n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
  2189. if (n < 32)
  2190. reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
  2191. else
  2192. reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
  2193. flush_writes(ohci);
  2194. out:
  2195. spin_unlock_irqrestore(&ohci->lock, flags);
  2196. return ret;
  2197. #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
  2198. }
  2199. static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
  2200. {
  2201. struct fw_ohci *ohci = fw_ohci(card);
  2202. unsigned long flags;
  2203. u32 value;
  2204. switch (csr_offset) {
  2205. case CSR_STATE_CLEAR:
  2206. case CSR_STATE_SET:
  2207. if (ohci->is_root &&
  2208. (reg_read(ohci, OHCI1394_LinkControlSet) &
  2209. OHCI1394_LinkControl_cycleMaster))
  2210. value = CSR_STATE_BIT_CMSTR;
  2211. else
  2212. value = 0;
  2213. if (ohci->csr_state_setclear_abdicate)
  2214. value |= CSR_STATE_BIT_ABDICATE;
  2215. return value;
  2216. case CSR_NODE_IDS:
  2217. return reg_read(ohci, OHCI1394_NodeID) << 16;
  2218. case CSR_CYCLE_TIME:
  2219. return get_cycle_time(ohci);
  2220. case CSR_BUS_TIME:
  2221. /*
  2222. * We might be called just after the cycle timer has wrapped
  2223. * around but just before the cycle64Seconds handler, so we
  2224. * better check here, too, if the bus time needs to be updated.
  2225. */
  2226. spin_lock_irqsave(&ohci->lock, flags);
  2227. value = update_bus_time(ohci);
  2228. spin_unlock_irqrestore(&ohci->lock, flags);
  2229. return value;
  2230. case CSR_BUSY_TIMEOUT:
  2231. value = reg_read(ohci, OHCI1394_ATRetries);
  2232. return (value >> 4) & 0x0ffff00f;
  2233. case CSR_PRIORITY_BUDGET:
  2234. return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
  2235. (ohci->pri_req_max << 8);
  2236. default:
  2237. WARN_ON(1);
  2238. return 0;
  2239. }
  2240. }
  2241. static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
  2242. {
  2243. struct fw_ohci *ohci = fw_ohci(card);
  2244. unsigned long flags;
  2245. switch (csr_offset) {
  2246. case CSR_STATE_CLEAR:
  2247. if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
  2248. reg_write(ohci, OHCI1394_LinkControlClear,
  2249. OHCI1394_LinkControl_cycleMaster);
  2250. flush_writes(ohci);
  2251. }
  2252. if (value & CSR_STATE_BIT_ABDICATE)
  2253. ohci->csr_state_setclear_abdicate = false;
  2254. break;
  2255. case CSR_STATE_SET:
  2256. if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
  2257. reg_write(ohci, OHCI1394_LinkControlSet,
  2258. OHCI1394_LinkControl_cycleMaster);
  2259. flush_writes(ohci);
  2260. }
  2261. if (value & CSR_STATE_BIT_ABDICATE)
  2262. ohci->csr_state_setclear_abdicate = true;
  2263. break;
  2264. case CSR_NODE_IDS:
  2265. reg_write(ohci, OHCI1394_NodeID, value >> 16);
  2266. flush_writes(ohci);
  2267. break;
  2268. case CSR_CYCLE_TIME:
  2269. reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
  2270. reg_write(ohci, OHCI1394_IntEventSet,
  2271. OHCI1394_cycleInconsistent);
  2272. flush_writes(ohci);
  2273. break;
  2274. case CSR_BUS_TIME:
  2275. spin_lock_irqsave(&ohci->lock, flags);
  2276. ohci->bus_time = (update_bus_time(ohci) & 0x40) |
  2277. (value & ~0x7f);
  2278. spin_unlock_irqrestore(&ohci->lock, flags);
  2279. break;
  2280. case CSR_BUSY_TIMEOUT:
  2281. value = (value & 0xf) | ((value & 0xf) << 4) |
  2282. ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
  2283. reg_write(ohci, OHCI1394_ATRetries, value);
  2284. flush_writes(ohci);
  2285. break;
  2286. case CSR_PRIORITY_BUDGET:
  2287. reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
  2288. flush_writes(ohci);
  2289. break;
  2290. default:
  2291. WARN_ON(1);
  2292. break;
  2293. }
  2294. }
  2295. static void flush_iso_completions(struct iso_context *ctx)
  2296. {
  2297. ctx->base.callback.sc(&ctx->base, ctx->last_timestamp,
  2298. ctx->header_length, ctx->header,
  2299. ctx->base.callback_data);
  2300. ctx->header_length = 0;
  2301. }
  2302. static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr)
  2303. {
  2304. u32 *ctx_hdr;
  2305. if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) {
  2306. if (ctx->base.drop_overflow_headers)
  2307. return;
  2308. flush_iso_completions(ctx);
  2309. }
  2310. ctx_hdr = ctx->header + ctx->header_length;
  2311. ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]);
  2312. /*
  2313. * The two iso header quadlets are byteswapped to little
  2314. * endian by the controller, but we want to present them
  2315. * as big endian for consistency with the bus endianness.
  2316. */
  2317. if (ctx->base.header_size > 0)
  2318. ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */
  2319. if (ctx->base.header_size > 4)
  2320. ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */
  2321. if (ctx->base.header_size > 8)
  2322. memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8);
  2323. ctx->header_length += ctx->base.header_size;
  2324. }
  2325. static int handle_ir_packet_per_buffer(struct context *context,
  2326. struct descriptor *d,
  2327. struct descriptor *last)
  2328. {
  2329. struct iso_context *ctx =
  2330. container_of(context, struct iso_context, context);
  2331. struct descriptor *pd;
  2332. u32 buffer_dma;
  2333. for (pd = d; pd <= last; pd++)
  2334. if (pd->transfer_status)
  2335. break;
  2336. if (pd > last)
  2337. /* Descriptor(s) not done yet, stop iteration */
  2338. return 0;
  2339. while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
  2340. d++;
  2341. buffer_dma = le32_to_cpu(d->data_address);
  2342. dma_sync_single_range_for_cpu(context->ohci->card.device,
  2343. buffer_dma & PAGE_MASK,
  2344. buffer_dma & ~PAGE_MASK,
  2345. le16_to_cpu(d->req_count),
  2346. DMA_FROM_DEVICE);
  2347. }
  2348. copy_iso_headers(ctx, (u32 *) (last + 1));
  2349. if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
  2350. flush_iso_completions(ctx);
  2351. return 1;
  2352. }
  2353. /* d == last because each descriptor block is only a single descriptor. */
  2354. static int handle_ir_buffer_fill(struct context *context,
  2355. struct descriptor *d,
  2356. struct descriptor *last)
  2357. {
  2358. struct iso_context *ctx =
  2359. container_of(context, struct iso_context, context);
  2360. unsigned int req_count, res_count, completed;
  2361. u32 buffer_dma;
  2362. req_count = le16_to_cpu(last->req_count);
  2363. res_count = le16_to_cpu(ACCESS_ONCE(last->res_count));
  2364. completed = req_count - res_count;
  2365. buffer_dma = le32_to_cpu(last->data_address);
  2366. if (completed > 0) {
  2367. ctx->mc_buffer_bus = buffer_dma;
  2368. ctx->mc_completed = completed;
  2369. }
  2370. if (res_count != 0)
  2371. /* Descriptor(s) not done yet, stop iteration */
  2372. return 0;
  2373. dma_sync_single_range_for_cpu(context->ohci->card.device,
  2374. buffer_dma & PAGE_MASK,
  2375. buffer_dma & ~PAGE_MASK,
  2376. completed, DMA_FROM_DEVICE);
  2377. if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) {
  2378. ctx->base.callback.mc(&ctx->base,
  2379. buffer_dma + completed,
  2380. ctx->base.callback_data);
  2381. ctx->mc_completed = 0;
  2382. }
  2383. return 1;
  2384. }
  2385. static void flush_ir_buffer_fill(struct iso_context *ctx)
  2386. {
  2387. dma_sync_single_range_for_cpu(ctx->context.ohci->card.device,
  2388. ctx->mc_buffer_bus & PAGE_MASK,
  2389. ctx->mc_buffer_bus & ~PAGE_MASK,
  2390. ctx->mc_completed, DMA_FROM_DEVICE);
  2391. ctx->base.callback.mc(&ctx->base,
  2392. ctx->mc_buffer_bus + ctx->mc_completed,
  2393. ctx->base.callback_data);
  2394. ctx->mc_completed = 0;
  2395. }
  2396. static inline void sync_it_packet_for_cpu(struct context *context,
  2397. struct descriptor *pd)
  2398. {
  2399. __le16 control;
  2400. u32 buffer_dma;
  2401. /* only packets beginning with OUTPUT_MORE* have data buffers */
  2402. if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
  2403. return;
  2404. /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
  2405. pd += 2;
  2406. /*
  2407. * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
  2408. * data buffer is in the context program's coherent page and must not
  2409. * be synced.
  2410. */
  2411. if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
  2412. (context->current_bus & PAGE_MASK)) {
  2413. if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
  2414. return;
  2415. pd++;
  2416. }
  2417. do {
  2418. buffer_dma = le32_to_cpu(pd->data_address);
  2419. dma_sync_single_range_for_cpu(context->ohci->card.device,
  2420. buffer_dma & PAGE_MASK,
  2421. buffer_dma & ~PAGE_MASK,
  2422. le16_to_cpu(pd->req_count),
  2423. DMA_TO_DEVICE);
  2424. control = pd->control;
  2425. pd++;
  2426. } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
  2427. }
  2428. static int handle_it_packet(struct context *context,
  2429. struct descriptor *d,
  2430. struct descriptor *last)
  2431. {
  2432. struct iso_context *ctx =
  2433. container_of(context, struct iso_context, context);
  2434. struct descriptor *pd;
  2435. __be32 *ctx_hdr;
  2436. for (pd = d; pd <= last; pd++)
  2437. if (pd->transfer_status)
  2438. break;
  2439. if (pd > last)
  2440. /* Descriptor(s) not done yet, stop iteration */
  2441. return 0;
  2442. sync_it_packet_for_cpu(context, d);
  2443. if (ctx->header_length + 4 > PAGE_SIZE) {
  2444. if (ctx->base.drop_overflow_headers)
  2445. return 1;
  2446. flush_iso_completions(ctx);
  2447. }
  2448. ctx_hdr = ctx->header + ctx->header_length;
  2449. ctx->last_timestamp = le16_to_cpu(last->res_count);
  2450. /* Present this value as big-endian to match the receive code */
  2451. *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) |
  2452. le16_to_cpu(pd->res_count));
  2453. ctx->header_length += 4;
  2454. if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
  2455. flush_iso_completions(ctx);
  2456. return 1;
  2457. }
  2458. static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
  2459. {
  2460. u32 hi = channels >> 32, lo = channels;
  2461. reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
  2462. reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
  2463. reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
  2464. reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
  2465. mmiowb();
  2466. ohci->mc_channels = channels;
  2467. }
  2468. static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
  2469. int type, int channel, size_t header_size)
  2470. {
  2471. struct fw_ohci *ohci = fw_ohci(card);
  2472. struct iso_context *uninitialized_var(ctx);
  2473. descriptor_callback_t uninitialized_var(callback);
  2474. u64 *uninitialized_var(channels);
  2475. u32 *uninitialized_var(mask), uninitialized_var(regs);
  2476. int index, ret = -EBUSY;
  2477. spin_lock_irq(&ohci->lock);
  2478. switch (type) {
  2479. case FW_ISO_CONTEXT_TRANSMIT:
  2480. mask = &ohci->it_context_mask;
  2481. callback = handle_it_packet;
  2482. index = ffs(*mask) - 1;
  2483. if (index >= 0) {
  2484. *mask &= ~(1 << index);
  2485. regs = OHCI1394_IsoXmitContextBase(index);
  2486. ctx = &ohci->it_context_list[index];
  2487. }
  2488. break;
  2489. case FW_ISO_CONTEXT_RECEIVE:
  2490. channels = &ohci->ir_context_channels;
  2491. mask = &ohci->ir_context_mask;
  2492. callback = handle_ir_packet_per_buffer;
  2493. index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
  2494. if (index >= 0) {
  2495. *channels &= ~(1ULL << channel);
  2496. *mask &= ~(1 << index);
  2497. regs = OHCI1394_IsoRcvContextBase(index);
  2498. ctx = &ohci->ir_context_list[index];
  2499. }
  2500. break;
  2501. case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
  2502. mask = &ohci->ir_context_mask;
  2503. callback = handle_ir_buffer_fill;
  2504. index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
  2505. if (index >= 0) {
  2506. ohci->mc_allocated = true;
  2507. *mask &= ~(1 << index);
  2508. regs = OHCI1394_IsoRcvContextBase(index);
  2509. ctx = &ohci->ir_context_list[index];
  2510. }
  2511. break;
  2512. default:
  2513. index = -1;
  2514. ret = -ENOSYS;
  2515. }
  2516. spin_unlock_irq(&ohci->lock);
  2517. if (index < 0)
  2518. return ERR_PTR(ret);
  2519. memset(ctx, 0, sizeof(*ctx));
  2520. ctx->header_length = 0;
  2521. ctx->header = (void *) __get_free_page(GFP_KERNEL);
  2522. if (ctx->header == NULL) {
  2523. ret = -ENOMEM;
  2524. goto out;
  2525. }
  2526. ret = context_init(&ctx->context, ohci, regs, callback);
  2527. if (ret < 0)
  2528. goto out_with_header;
  2529. if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
  2530. set_multichannel_mask(ohci, 0);
  2531. ctx->mc_completed = 0;
  2532. }
  2533. return &ctx->base;
  2534. out_with_header:
  2535. free_page((unsigned long)ctx->header);
  2536. out:
  2537. spin_lock_irq(&ohci->lock);
  2538. switch (type) {
  2539. case FW_ISO_CONTEXT_RECEIVE:
  2540. *channels |= 1ULL << channel;
  2541. break;
  2542. case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
  2543. ohci->mc_allocated = false;
  2544. break;
  2545. }
  2546. *mask |= 1 << index;
  2547. spin_unlock_irq(&ohci->lock);
  2548. return ERR_PTR(ret);
  2549. }
  2550. static int ohci_start_iso(struct fw_iso_context *base,
  2551. s32 cycle, u32 sync, u32 tags)
  2552. {
  2553. struct iso_context *ctx = container_of(base, struct iso_context, base);
  2554. struct fw_ohci *ohci = ctx->context.ohci;
  2555. u32 control = IR_CONTEXT_ISOCH_HEADER, match;
  2556. int index;
  2557. /* the controller cannot start without any queued packets */
  2558. if (ctx->context.last->branch_address == 0)
  2559. return -ENODATA;
  2560. switch (ctx->base.type) {
  2561. case FW_ISO_CONTEXT_TRANSMIT:
  2562. index = ctx - ohci->it_context_list;
  2563. match = 0;
  2564. if (cycle >= 0)
  2565. match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
  2566. (cycle & 0x7fff) << 16;
  2567. reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
  2568. reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
  2569. context_run(&ctx->context, match);
  2570. break;
  2571. case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
  2572. control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
  2573. /* fall through */
  2574. case FW_ISO_CONTEXT_RECEIVE:
  2575. index = ctx - ohci->ir_context_list;
  2576. match = (tags << 28) | (sync << 8) | ctx->base.channel;
  2577. if (cycle >= 0) {
  2578. match |= (cycle & 0x07fff) << 12;
  2579. control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
  2580. }
  2581. reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
  2582. reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
  2583. reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
  2584. context_run(&ctx->context, control);
  2585. ctx->sync = sync;
  2586. ctx->tags = tags;
  2587. break;
  2588. }
  2589. return 0;
  2590. }
  2591. static int ohci_stop_iso(struct fw_iso_context *base)
  2592. {
  2593. struct fw_ohci *ohci = fw_ohci(base->card);
  2594. struct iso_context *ctx = container_of(base, struct iso_context, base);
  2595. int index;
  2596. switch (ctx->base.type) {
  2597. case FW_ISO_CONTEXT_TRANSMIT:
  2598. index = ctx - ohci->it_context_list;
  2599. reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
  2600. break;
  2601. case FW_ISO_CONTEXT_RECEIVE:
  2602. case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
  2603. index = ctx - ohci->ir_context_list;
  2604. reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
  2605. break;
  2606. }
  2607. flush_writes(ohci);
  2608. context_stop(&ctx->context);
  2609. tasklet_kill(&ctx->context.tasklet);
  2610. return 0;
  2611. }
  2612. static void ohci_free_iso_context(struct fw_iso_context *base)
  2613. {
  2614. struct fw_ohci *ohci = fw_ohci(base->card);
  2615. struct iso_context *ctx = container_of(base, struct iso_context, base);
  2616. unsigned long flags;
  2617. int index;
  2618. ohci_stop_iso(base);
  2619. context_release(&ctx->context);
  2620. free_page((unsigned long)ctx->header);
  2621. spin_lock_irqsave(&ohci->lock, flags);
  2622. switch (base->type) {
  2623. case FW_ISO_CONTEXT_TRANSMIT:
  2624. index = ctx - ohci->it_context_list;
  2625. ohci->it_context_mask |= 1 << index;
  2626. break;
  2627. case FW_ISO_CONTEXT_RECEIVE:
  2628. index = ctx - ohci->ir_context_list;
  2629. ohci->ir_context_mask |= 1 << index;
  2630. ohci->ir_context_channels |= 1ULL << base->channel;
  2631. break;
  2632. case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
  2633. index = ctx - ohci->ir_context_list;
  2634. ohci->ir_context_mask |= 1 << index;
  2635. ohci->ir_context_channels |= ohci->mc_channels;
  2636. ohci->mc_channels = 0;
  2637. ohci->mc_allocated = false;
  2638. break;
  2639. }
  2640. spin_unlock_irqrestore(&ohci->lock, flags);
  2641. }
  2642. static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
  2643. {
  2644. struct fw_ohci *ohci = fw_ohci(base->card);
  2645. unsigned long flags;
  2646. int ret;
  2647. switch (base->type) {
  2648. case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
  2649. spin_lock_irqsave(&ohci->lock, flags);
  2650. /* Don't allow multichannel to grab other contexts' channels. */
  2651. if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
  2652. *channels = ohci->ir_context_channels;
  2653. ret = -EBUSY;
  2654. } else {
  2655. set_multichannel_mask(ohci, *channels);
  2656. ret = 0;
  2657. }
  2658. spin_unlock_irqrestore(&ohci->lock, flags);
  2659. break;
  2660. default:
  2661. ret = -EINVAL;
  2662. }
  2663. return ret;
  2664. }
  2665. #ifdef CONFIG_PM
  2666. static void ohci_resume_iso_dma(struct fw_ohci *ohci)
  2667. {
  2668. int i;
  2669. struct iso_context *ctx;
  2670. for (i = 0 ; i < ohci->n_ir ; i++) {
  2671. ctx = &ohci->ir_context_list[i];
  2672. if (ctx->context.running)
  2673. ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
  2674. }
  2675. for (i = 0 ; i < ohci->n_it ; i++) {
  2676. ctx = &ohci->it_context_list[i];
  2677. if (ctx->context.running)
  2678. ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
  2679. }
  2680. }
  2681. #endif
  2682. static int queue_iso_transmit(struct iso_context *ctx,
  2683. struct fw_iso_packet *packet,
  2684. struct fw_iso_buffer *buffer,
  2685. unsigned long payload)
  2686. {
  2687. struct descriptor *d, *last, *pd;
  2688. struct fw_iso_packet *p;
  2689. __le32 *header;
  2690. dma_addr_t d_bus, page_bus;
  2691. u32 z, header_z, payload_z, irq;
  2692. u32 payload_index, payload_end_index, next_page_index;
  2693. int page, end_page, i, length, offset;
  2694. p = packet;
  2695. payload_index = payload;
  2696. if (p->skip)
  2697. z = 1;
  2698. else
  2699. z = 2;
  2700. if (p->header_length > 0)
  2701. z++;
  2702. /* Determine the first page the payload isn't contained in. */
  2703. end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
  2704. if (p->payload_length > 0)
  2705. payload_z = end_page - (payload_index >> PAGE_SHIFT);
  2706. else
  2707. payload_z = 0;
  2708. z += payload_z;
  2709. /* Get header size in number of descriptors. */
  2710. header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
  2711. d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
  2712. if (d == NULL)
  2713. return -ENOMEM;
  2714. if (!p->skip) {
  2715. d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
  2716. d[0].req_count = cpu_to_le16(8);
  2717. /*
  2718. * Link the skip address to this descriptor itself. This causes
  2719. * a context to skip a cycle whenever lost cycles or FIFO
  2720. * overruns occur, without dropping the data. The application
  2721. * should then decide whether this is an error condition or not.
  2722. * FIXME: Make the context's cycle-lost behaviour configurable?
  2723. */
  2724. d[0].branch_address = cpu_to_le32(d_bus | z);
  2725. header = (__le32 *) &d[1];
  2726. header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
  2727. IT_HEADER_TAG(p->tag) |
  2728. IT_HEADER_TCODE(TCODE_STREAM_DATA) |
  2729. IT_HEADER_CHANNEL(ctx->base.channel) |
  2730. IT_HEADER_SPEED(ctx->base.speed));
  2731. header[1] =
  2732. cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
  2733. p->payload_length));
  2734. }
  2735. if (p->header_length > 0) {
  2736. d[2].req_count = cpu_to_le16(p->header_length);
  2737. d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
  2738. memcpy(&d[z], p->header, p->header_length);
  2739. }
  2740. pd = d + z - payload_z;
  2741. payload_end_index = payload_index + p->payload_length;
  2742. for (i = 0; i < payload_z; i++) {
  2743. page = payload_index >> PAGE_SHIFT;
  2744. offset = payload_index & ~PAGE_MASK;
  2745. next_page_index = (page + 1) << PAGE_SHIFT;
  2746. length =
  2747. min(next_page_index, payload_end_index) - payload_index;
  2748. pd[i].req_count = cpu_to_le16(length);
  2749. page_bus = page_private(buffer->pages[page]);
  2750. pd[i].data_address = cpu_to_le32(page_bus + offset);
  2751. dma_sync_single_range_for_device(ctx->context.ohci->card.device,
  2752. page_bus, offset, length,
  2753. DMA_TO_DEVICE);
  2754. payload_index += length;
  2755. }
  2756. if (p->interrupt)
  2757. irq = DESCRIPTOR_IRQ_ALWAYS;
  2758. else
  2759. irq = DESCRIPTOR_NO_IRQ;
  2760. last = z == 2 ? d : d + z - 1;
  2761. last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
  2762. DESCRIPTOR_STATUS |
  2763. DESCRIPTOR_BRANCH_ALWAYS |
  2764. irq);
  2765. context_append(&ctx->context, d, z, header_z);
  2766. return 0;
  2767. }
  2768. static int queue_iso_packet_per_buffer(struct iso_context *ctx,
  2769. struct fw_iso_packet *packet,
  2770. struct fw_iso_buffer *buffer,
  2771. unsigned long payload)
  2772. {
  2773. struct device *device = ctx->context.ohci->card.device;
  2774. struct descriptor *d, *pd;
  2775. dma_addr_t d_bus, page_bus;
  2776. u32 z, header_z, rest;
  2777. int i, j, length;
  2778. int page, offset, packet_count, header_size, payload_per_buffer;
  2779. /*
  2780. * The OHCI controller puts the isochronous header and trailer in the
  2781. * buffer, so we need at least 8 bytes.
  2782. */
  2783. packet_count = packet->header_length / ctx->base.header_size;
  2784. header_size = max(ctx->base.header_size, (size_t)8);
  2785. /* Get header size in number of descriptors. */
  2786. header_z = DIV_ROUND_UP(header_size, sizeof(*d));
  2787. page = payload >> PAGE_SHIFT;
  2788. offset = payload & ~PAGE_MASK;
  2789. payload_per_buffer = packet->payload_length / packet_count;
  2790. for (i = 0; i < packet_count; i++) {
  2791. /* d points to the header descriptor */
  2792. z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
  2793. d = context_get_descriptors(&ctx->context,
  2794. z + header_z, &d_bus);
  2795. if (d == NULL)
  2796. return -ENOMEM;
  2797. d->control = cpu_to_le16(DESCRIPTOR_STATUS |
  2798. DESCRIPTOR_INPUT_MORE);
  2799. if (packet->skip && i == 0)
  2800. d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
  2801. d->req_count = cpu_to_le16(header_size);
  2802. d->res_count = d->req_count;
  2803. d->transfer_status = 0;
  2804. d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
  2805. rest = payload_per_buffer;
  2806. pd = d;
  2807. for (j = 1; j < z; j++) {
  2808. pd++;
  2809. pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
  2810. DESCRIPTOR_INPUT_MORE);
  2811. if (offset + rest < PAGE_SIZE)
  2812. length = rest;
  2813. else
  2814. length = PAGE_SIZE - offset;
  2815. pd->req_count = cpu_to_le16(length);
  2816. pd->res_count = pd->req_count;
  2817. pd->transfer_status = 0;
  2818. page_bus = page_private(buffer->pages[page]);
  2819. pd->data_address = cpu_to_le32(page_bus + offset);
  2820. dma_sync_single_range_for_device(device, page_bus,
  2821. offset, length,
  2822. DMA_FROM_DEVICE);
  2823. offset = (offset + length) & ~PAGE_MASK;
  2824. rest -= length;
  2825. if (offset == 0)
  2826. page++;
  2827. }
  2828. pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
  2829. DESCRIPTOR_INPUT_LAST |
  2830. DESCRIPTOR_BRANCH_ALWAYS);
  2831. if (packet->interrupt && i == packet_count - 1)
  2832. pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
  2833. context_append(&ctx->context, d, z, header_z);
  2834. }
  2835. return 0;
  2836. }
  2837. static int queue_iso_buffer_fill(struct iso_context *ctx,
  2838. struct fw_iso_packet *packet,
  2839. struct fw_iso_buffer *buffer,
  2840. unsigned long payload)
  2841. {
  2842. struct descriptor *d;
  2843. dma_addr_t d_bus, page_bus;
  2844. int page, offset, rest, z, i, length;
  2845. page = payload >> PAGE_SHIFT;
  2846. offset = payload & ~PAGE_MASK;
  2847. rest = packet->payload_length;
  2848. /* We need one descriptor for each page in the buffer. */
  2849. z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
  2850. if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
  2851. return -EFAULT;
  2852. for (i = 0; i < z; i++) {
  2853. d = context_get_descriptors(&ctx->context, 1, &d_bus);
  2854. if (d == NULL)
  2855. return -ENOMEM;
  2856. d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
  2857. DESCRIPTOR_BRANCH_ALWAYS);
  2858. if (packet->skip && i == 0)
  2859. d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
  2860. if (packet->interrupt && i == z - 1)
  2861. d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
  2862. if (offset + rest < PAGE_SIZE)
  2863. length = rest;
  2864. else
  2865. length = PAGE_SIZE - offset;
  2866. d->req_count = cpu_to_le16(length);
  2867. d->res_count = d->req_count;
  2868. d->transfer_status = 0;
  2869. page_bus = page_private(buffer->pages[page]);
  2870. d->data_address = cpu_to_le32(page_bus + offset);
  2871. dma_sync_single_range_for_device(ctx->context.ohci->card.device,
  2872. page_bus, offset, length,
  2873. DMA_FROM_DEVICE);
  2874. rest -= length;
  2875. offset = 0;
  2876. page++;
  2877. context_append(&ctx->context, d, 1, 0);
  2878. }
  2879. return 0;
  2880. }
  2881. static int ohci_queue_iso(struct fw_iso_context *base,
  2882. struct fw_iso_packet *packet,
  2883. struct fw_iso_buffer *buffer,
  2884. unsigned long payload)
  2885. {
  2886. struct iso_context *ctx = container_of(base, struct iso_context, base);
  2887. unsigned long flags;
  2888. int ret = -ENOSYS;
  2889. spin_lock_irqsave(&ctx->context.ohci->lock, flags);
  2890. switch (base->type) {
  2891. case FW_ISO_CONTEXT_TRANSMIT:
  2892. ret = queue_iso_transmit(ctx, packet, buffer, payload);
  2893. break;
  2894. case FW_ISO_CONTEXT_RECEIVE:
  2895. ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
  2896. break;
  2897. case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
  2898. ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
  2899. break;
  2900. }
  2901. spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
  2902. return ret;
  2903. }
  2904. static void ohci_flush_queue_iso(struct fw_iso_context *base)
  2905. {
  2906. struct context *ctx =
  2907. &container_of(base, struct iso_context, base)->context;
  2908. reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
  2909. }
  2910. static int ohci_flush_iso_completions(struct fw_iso_context *base)
  2911. {
  2912. struct iso_context *ctx = container_of(base, struct iso_context, base);
  2913. int ret = 0;
  2914. tasklet_disable(&ctx->context.tasklet);
  2915. if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) {
  2916. context_tasklet((unsigned long)&ctx->context);
  2917. switch (base->type) {
  2918. case FW_ISO_CONTEXT_TRANSMIT:
  2919. case FW_ISO_CONTEXT_RECEIVE:
  2920. if (ctx->header_length != 0)
  2921. flush_iso_completions(ctx);
  2922. break;
  2923. case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
  2924. if (ctx->mc_completed != 0)
  2925. flush_ir_buffer_fill(ctx);
  2926. break;
  2927. default:
  2928. ret = -ENOSYS;
  2929. }
  2930. clear_bit_unlock(0, &ctx->flushing_completions);
  2931. smp_mb__after_clear_bit();
  2932. }
  2933. tasklet_enable(&ctx->context.tasklet);
  2934. return ret;
  2935. }
  2936. static const struct fw_card_driver ohci_driver = {
  2937. .enable = ohci_enable,
  2938. .read_phy_reg = ohci_read_phy_reg,
  2939. .update_phy_reg = ohci_update_phy_reg,
  2940. .set_config_rom = ohci_set_config_rom,
  2941. .send_request = ohci_send_request,
  2942. .send_response = ohci_send_response,
  2943. .cancel_packet = ohci_cancel_packet,
  2944. .enable_phys_dma = ohci_enable_phys_dma,
  2945. .read_csr = ohci_read_csr,
  2946. .write_csr = ohci_write_csr,
  2947. .allocate_iso_context = ohci_allocate_iso_context,
  2948. .free_iso_context = ohci_free_iso_context,
  2949. .set_iso_channels = ohci_set_iso_channels,
  2950. .queue_iso = ohci_queue_iso,
  2951. .flush_queue_iso = ohci_flush_queue_iso,
  2952. .flush_iso_completions = ohci_flush_iso_completions,
  2953. .start_iso = ohci_start_iso,
  2954. .stop_iso = ohci_stop_iso,
  2955. };
  2956. #ifdef CONFIG_PPC_PMAC
  2957. static void pmac_ohci_on(struct pci_dev *dev)
  2958. {
  2959. if (machine_is(powermac)) {
  2960. struct device_node *ofn = pci_device_to_OF_node(dev);
  2961. if (ofn) {
  2962. pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
  2963. pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
  2964. }
  2965. }
  2966. }
  2967. static void pmac_ohci_off(struct pci_dev *dev)
  2968. {
  2969. if (machine_is(powermac)) {
  2970. struct device_node *ofn = pci_device_to_OF_node(dev);
  2971. if (ofn) {
  2972. pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
  2973. pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
  2974. }
  2975. }
  2976. }
  2977. #else
  2978. static inline void pmac_ohci_on(struct pci_dev *dev) {}
  2979. static inline void pmac_ohci_off(struct pci_dev *dev) {}
  2980. #endif /* CONFIG_PPC_PMAC */
  2981. static int pci_probe(struct pci_dev *dev,
  2982. const struct pci_device_id *ent)
  2983. {
  2984. struct fw_ohci *ohci;
  2985. u32 bus_options, max_receive, link_speed, version;
  2986. u64 guid;
  2987. int i, err;
  2988. size_t size;
  2989. if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
  2990. dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
  2991. return -ENOSYS;
  2992. }
  2993. ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
  2994. if (ohci == NULL) {
  2995. err = -ENOMEM;
  2996. goto fail;
  2997. }
  2998. fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
  2999. pmac_ohci_on(dev);
  3000. err = pci_enable_device(dev);
  3001. if (err) {
  3002. dev_err(&dev->dev, "failed to enable OHCI hardware\n");
  3003. goto fail_free;
  3004. }
  3005. pci_set_master(dev);
  3006. pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
  3007. pci_set_drvdata(dev, ohci);
  3008. spin_lock_init(&ohci->lock);
  3009. mutex_init(&ohci->phy_reg_mutex);
  3010. INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
  3011. if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) ||
  3012. pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) {
  3013. ohci_err(ohci, "invalid MMIO resource\n");
  3014. err = -ENXIO;
  3015. goto fail_disable;
  3016. }
  3017. err = pci_request_region(dev, 0, ohci_driver_name);
  3018. if (err) {
  3019. ohci_err(ohci, "MMIO resource unavailable\n");
  3020. goto fail_disable;
  3021. }
  3022. ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
  3023. if (ohci->registers == NULL) {
  3024. ohci_err(ohci, "failed to remap registers\n");
  3025. err = -ENXIO;
  3026. goto fail_iomem;
  3027. }
  3028. for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
  3029. if ((ohci_quirks[i].vendor == dev->vendor) &&
  3030. (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
  3031. ohci_quirks[i].device == dev->device) &&
  3032. (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
  3033. ohci_quirks[i].revision >= dev->revision)) {
  3034. ohci->quirks = ohci_quirks[i].flags;
  3035. break;
  3036. }
  3037. if (param_quirks)
  3038. ohci->quirks = param_quirks;
  3039. /*
  3040. * Because dma_alloc_coherent() allocates at least one page,
  3041. * we save space by using a common buffer for the AR request/
  3042. * response descriptors and the self IDs buffer.
  3043. */
  3044. BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
  3045. BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
  3046. ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
  3047. PAGE_SIZE,
  3048. &ohci->misc_buffer_bus,
  3049. GFP_KERNEL);
  3050. if (!ohci->misc_buffer) {
  3051. err = -ENOMEM;
  3052. goto fail_iounmap;
  3053. }
  3054. err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
  3055. OHCI1394_AsReqRcvContextControlSet);
  3056. if (err < 0)
  3057. goto fail_misc_buf;
  3058. err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
  3059. OHCI1394_AsRspRcvContextControlSet);
  3060. if (err < 0)
  3061. goto fail_arreq_ctx;
  3062. err = context_init(&ohci->at_request_ctx, ohci,
  3063. OHCI1394_AsReqTrContextControlSet, handle_at_packet);
  3064. if (err < 0)
  3065. goto fail_arrsp_ctx;
  3066. err = context_init(&ohci->at_response_ctx, ohci,
  3067. OHCI1394_AsRspTrContextControlSet, handle_at_packet);
  3068. if (err < 0)
  3069. goto fail_atreq_ctx;
  3070. reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
  3071. ohci->ir_context_channels = ~0ULL;
  3072. ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
  3073. reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
  3074. ohci->ir_context_mask = ohci->ir_context_support;
  3075. ohci->n_ir = hweight32(ohci->ir_context_mask);
  3076. size = sizeof(struct iso_context) * ohci->n_ir;
  3077. ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
  3078. reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
  3079. ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
  3080. reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
  3081. ohci->it_context_mask = ohci->it_context_support;
  3082. ohci->n_it = hweight32(ohci->it_context_mask);
  3083. size = sizeof(struct iso_context) * ohci->n_it;
  3084. ohci->it_context_list = kzalloc(size, GFP_KERNEL);
  3085. if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
  3086. err = -ENOMEM;
  3087. goto fail_contexts;
  3088. }
  3089. ohci->self_id = ohci->misc_buffer + PAGE_SIZE/2;
  3090. ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
  3091. bus_options = reg_read(ohci, OHCI1394_BusOptions);
  3092. max_receive = (bus_options >> 12) & 0xf;
  3093. link_speed = bus_options & 0x7;
  3094. guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
  3095. reg_read(ohci, OHCI1394_GUIDLo);
  3096. if (!(ohci->quirks & QUIRK_NO_MSI))
  3097. pci_enable_msi(dev);
  3098. if (request_irq(dev->irq, irq_handler,
  3099. pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
  3100. ohci_driver_name, ohci)) {
  3101. ohci_err(ohci, "failed to allocate interrupt %d\n", dev->irq);
  3102. err = -EIO;
  3103. goto fail_msi;
  3104. }
  3105. err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
  3106. if (err)
  3107. goto fail_irq;
  3108. version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
  3109. ohci_notice(ohci,
  3110. "added OHCI v%x.%x device as card %d, "
  3111. "%d IR + %d IT contexts, quirks 0x%x\n",
  3112. version >> 16, version & 0xff, ohci->card.index,
  3113. ohci->n_ir, ohci->n_it, ohci->quirks);
  3114. return 0;
  3115. fail_irq:
  3116. free_irq(dev->irq, ohci);
  3117. fail_msi:
  3118. pci_disable_msi(dev);
  3119. fail_contexts:
  3120. kfree(ohci->ir_context_list);
  3121. kfree(ohci->it_context_list);
  3122. context_release(&ohci->at_response_ctx);
  3123. fail_atreq_ctx:
  3124. context_release(&ohci->at_request_ctx);
  3125. fail_arrsp_ctx:
  3126. ar_context_release(&ohci->ar_response_ctx);
  3127. fail_arreq_ctx:
  3128. ar_context_release(&ohci->ar_request_ctx);
  3129. fail_misc_buf:
  3130. dma_free_coherent(ohci->card.device, PAGE_SIZE,
  3131. ohci->misc_buffer, ohci->misc_buffer_bus);
  3132. fail_iounmap:
  3133. pci_iounmap(dev, ohci->registers);
  3134. fail_iomem:
  3135. pci_release_region(dev, 0);
  3136. fail_disable:
  3137. pci_disable_device(dev);
  3138. fail_free:
  3139. kfree(ohci);
  3140. pmac_ohci_off(dev);
  3141. fail:
  3142. return err;
  3143. }
  3144. static void pci_remove(struct pci_dev *dev)
  3145. {
  3146. struct fw_ohci *ohci = pci_get_drvdata(dev);
  3147. /*
  3148. * If the removal is happening from the suspend state, LPS won't be
  3149. * enabled and host registers (eg., IntMaskClear) won't be accessible.
  3150. */
  3151. if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) {
  3152. reg_write(ohci, OHCI1394_IntMaskClear, ~0);
  3153. flush_writes(ohci);
  3154. }
  3155. cancel_work_sync(&ohci->bus_reset_work);
  3156. fw_core_remove_card(&ohci->card);
  3157. /*
  3158. * FIXME: Fail all pending packets here, now that the upper
  3159. * layers can't queue any more.
  3160. */
  3161. software_reset(ohci);
  3162. free_irq(dev->irq, ohci);
  3163. if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
  3164. dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
  3165. ohci->next_config_rom, ohci->next_config_rom_bus);
  3166. if (ohci->config_rom)
  3167. dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
  3168. ohci->config_rom, ohci->config_rom_bus);
  3169. ar_context_release(&ohci->ar_request_ctx);
  3170. ar_context_release(&ohci->ar_response_ctx);
  3171. dma_free_coherent(ohci->card.device, PAGE_SIZE,
  3172. ohci->misc_buffer, ohci->misc_buffer_bus);
  3173. context_release(&ohci->at_request_ctx);
  3174. context_release(&ohci->at_response_ctx);
  3175. kfree(ohci->it_context_list);
  3176. kfree(ohci->ir_context_list);
  3177. pci_disable_msi(dev);
  3178. pci_iounmap(dev, ohci->registers);
  3179. pci_release_region(dev, 0);
  3180. pci_disable_device(dev);
  3181. kfree(ohci);
  3182. pmac_ohci_off(dev);
  3183. dev_notice(&dev->dev, "removed fw-ohci device\n");
  3184. }
  3185. #ifdef CONFIG_PM
  3186. static int pci_suspend(struct pci_dev *dev, pm_message_t state)
  3187. {
  3188. struct fw_ohci *ohci = pci_get_drvdata(dev);
  3189. int err;
  3190. software_reset(ohci);
  3191. err = pci_save_state(dev);
  3192. if (err) {
  3193. ohci_err(ohci, "pci_save_state failed\n");
  3194. return err;
  3195. }
  3196. err = pci_set_power_state(dev, pci_choose_state(dev, state));
  3197. if (err)
  3198. ohci_err(ohci, "pci_set_power_state failed with %d\n", err);
  3199. pmac_ohci_off(dev);
  3200. return 0;
  3201. }
  3202. static int pci_resume(struct pci_dev *dev)
  3203. {
  3204. struct fw_ohci *ohci = pci_get_drvdata(dev);
  3205. int err;
  3206. pmac_ohci_on(dev);
  3207. pci_set_power_state(dev, PCI_D0);
  3208. pci_restore_state(dev);
  3209. err = pci_enable_device(dev);
  3210. if (err) {
  3211. ohci_err(ohci, "pci_enable_device failed\n");
  3212. return err;
  3213. }
  3214. /* Some systems don't setup GUID register on resume from ram */
  3215. if (!reg_read(ohci, OHCI1394_GUIDLo) &&
  3216. !reg_read(ohci, OHCI1394_GUIDHi)) {
  3217. reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
  3218. reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
  3219. }
  3220. err = ohci_enable(&ohci->card, NULL, 0);
  3221. if (err)
  3222. return err;
  3223. ohci_resume_iso_dma(ohci);
  3224. return 0;
  3225. }
  3226. #endif
  3227. static const struct pci_device_id pci_table[] = {
  3228. { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
  3229. { }
  3230. };
  3231. MODULE_DEVICE_TABLE(pci, pci_table);
  3232. static struct pci_driver fw_ohci_pci_driver = {
  3233. .name = ohci_driver_name,
  3234. .id_table = pci_table,
  3235. .probe = pci_probe,
  3236. .remove = pci_remove,
  3237. #ifdef CONFIG_PM
  3238. .resume = pci_resume,
  3239. .suspend = pci_suspend,
  3240. #endif
  3241. };
  3242. static int __init fw_ohci_init(void)
  3243. {
  3244. selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0);
  3245. if (!selfid_workqueue)
  3246. return -ENOMEM;
  3247. return pci_register_driver(&fw_ohci_pci_driver);
  3248. }
  3249. static void __exit fw_ohci_cleanup(void)
  3250. {
  3251. pci_unregister_driver(&fw_ohci_pci_driver);
  3252. destroy_workqueue(selfid_workqueue);
  3253. }
  3254. module_init(fw_ohci_init);
  3255. module_exit(fw_ohci_cleanup);
  3256. MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
  3257. MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
  3258. MODULE_LICENSE("GPL");
  3259. /* Provide a module alias so root-on-sbp2 initrds don't break. */
  3260. MODULE_ALIAS("ohci1394");