libahci.c 63 KB

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  1. /*
  2. * libahci.c - Common AHCI SATA low-level routines
  3. *
  4. * Maintained by: Tejun Heo <tj@kernel.org>
  5. * Please ALWAYS copy linux-ide@vger.kernel.org
  6. * on emails.
  7. *
  8. * Copyright 2004-2005 Red Hat, Inc.
  9. *
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2, or (at your option)
  14. * any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; see the file COPYING. If not, write to
  23. * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  24. *
  25. *
  26. * libata documentation is available via 'make {ps|pdf}docs',
  27. * as Documentation/DocBook/libata.*
  28. *
  29. * AHCI hardware documentation:
  30. * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
  31. * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
  32. *
  33. */
  34. #include <linux/kernel.h>
  35. #include <linux/gfp.h>
  36. #include <linux/module.h>
  37. #include <linux/init.h>
  38. #include <linux/blkdev.h>
  39. #include <linux/delay.h>
  40. #include <linux/interrupt.h>
  41. #include <linux/dma-mapping.h>
  42. #include <linux/device.h>
  43. #include <scsi/scsi_host.h>
  44. #include <scsi/scsi_cmnd.h>
  45. #include <linux/libata.h>
  46. #include "ahci.h"
  47. #include "libata.h"
  48. static int ahci_skip_host_reset;
  49. int ahci_ignore_sss;
  50. EXPORT_SYMBOL_GPL(ahci_ignore_sss);
  51. module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
  52. MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
  53. module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
  54. MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
  55. static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
  56. unsigned hints);
  57. static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
  58. static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
  59. size_t size);
  60. static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
  61. ssize_t size);
  62. static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
  63. static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
  64. static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
  65. static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
  66. static int ahci_port_start(struct ata_port *ap);
  67. static void ahci_port_stop(struct ata_port *ap);
  68. static void ahci_qc_prep(struct ata_queued_cmd *qc);
  69. static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
  70. static void ahci_freeze(struct ata_port *ap);
  71. static void ahci_thaw(struct ata_port *ap);
  72. static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
  73. static void ahci_enable_fbs(struct ata_port *ap);
  74. static void ahci_disable_fbs(struct ata_port *ap);
  75. static void ahci_pmp_attach(struct ata_port *ap);
  76. static void ahci_pmp_detach(struct ata_port *ap);
  77. static int ahci_softreset(struct ata_link *link, unsigned int *class,
  78. unsigned long deadline);
  79. static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
  80. unsigned long deadline);
  81. static int ahci_hardreset(struct ata_link *link, unsigned int *class,
  82. unsigned long deadline);
  83. static void ahci_postreset(struct ata_link *link, unsigned int *class);
  84. static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
  85. static void ahci_dev_config(struct ata_device *dev);
  86. #ifdef CONFIG_PM
  87. static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
  88. #endif
  89. static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
  90. static ssize_t ahci_activity_store(struct ata_device *dev,
  91. enum sw_activity val);
  92. static void ahci_init_sw_activity(struct ata_link *link);
  93. static ssize_t ahci_show_host_caps(struct device *dev,
  94. struct device_attribute *attr, char *buf);
  95. static ssize_t ahci_show_host_cap2(struct device *dev,
  96. struct device_attribute *attr, char *buf);
  97. static ssize_t ahci_show_host_version(struct device *dev,
  98. struct device_attribute *attr, char *buf);
  99. static ssize_t ahci_show_port_cmd(struct device *dev,
  100. struct device_attribute *attr, char *buf);
  101. static ssize_t ahci_read_em_buffer(struct device *dev,
  102. struct device_attribute *attr, char *buf);
  103. static ssize_t ahci_store_em_buffer(struct device *dev,
  104. struct device_attribute *attr,
  105. const char *buf, size_t size);
  106. static ssize_t ahci_show_em_supported(struct device *dev,
  107. struct device_attribute *attr, char *buf);
  108. static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
  109. static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
  110. static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
  111. static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
  112. static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
  113. ahci_read_em_buffer, ahci_store_em_buffer);
  114. static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
  115. struct device_attribute *ahci_shost_attrs[] = {
  116. &dev_attr_link_power_management_policy,
  117. &dev_attr_em_message_type,
  118. &dev_attr_em_message,
  119. &dev_attr_ahci_host_caps,
  120. &dev_attr_ahci_host_cap2,
  121. &dev_attr_ahci_host_version,
  122. &dev_attr_ahci_port_cmd,
  123. &dev_attr_em_buffer,
  124. &dev_attr_em_message_supported,
  125. NULL
  126. };
  127. EXPORT_SYMBOL_GPL(ahci_shost_attrs);
  128. struct device_attribute *ahci_sdev_attrs[] = {
  129. &dev_attr_sw_activity,
  130. &dev_attr_unload_heads,
  131. NULL
  132. };
  133. EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
  134. struct ata_port_operations ahci_ops = {
  135. .inherits = &sata_pmp_port_ops,
  136. .qc_defer = ahci_pmp_qc_defer,
  137. .qc_prep = ahci_qc_prep,
  138. .qc_issue = ahci_qc_issue,
  139. .qc_fill_rtf = ahci_qc_fill_rtf,
  140. .freeze = ahci_freeze,
  141. .thaw = ahci_thaw,
  142. .softreset = ahci_softreset,
  143. .hardreset = ahci_hardreset,
  144. .postreset = ahci_postreset,
  145. .pmp_softreset = ahci_softreset,
  146. .error_handler = ahci_error_handler,
  147. .post_internal_cmd = ahci_post_internal_cmd,
  148. .dev_config = ahci_dev_config,
  149. .scr_read = ahci_scr_read,
  150. .scr_write = ahci_scr_write,
  151. .pmp_attach = ahci_pmp_attach,
  152. .pmp_detach = ahci_pmp_detach,
  153. .set_lpm = ahci_set_lpm,
  154. .em_show = ahci_led_show,
  155. .em_store = ahci_led_store,
  156. .sw_activity_show = ahci_activity_show,
  157. .sw_activity_store = ahci_activity_store,
  158. .transmit_led_message = ahci_transmit_led_message,
  159. #ifdef CONFIG_PM
  160. .port_suspend = ahci_port_suspend,
  161. .port_resume = ahci_port_resume,
  162. #endif
  163. .port_start = ahci_port_start,
  164. .port_stop = ahci_port_stop,
  165. };
  166. EXPORT_SYMBOL_GPL(ahci_ops);
  167. struct ata_port_operations ahci_pmp_retry_srst_ops = {
  168. .inherits = &ahci_ops,
  169. .softreset = ahci_pmp_retry_softreset,
  170. };
  171. EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
  172. static bool ahci_em_messages __read_mostly = true;
  173. EXPORT_SYMBOL_GPL(ahci_em_messages);
  174. module_param(ahci_em_messages, bool, 0444);
  175. /* add other LED protocol types when they become supported */
  176. MODULE_PARM_DESC(ahci_em_messages,
  177. "AHCI Enclosure Management Message control (0 = off, 1 = on)");
  178. /* device sleep idle timeout in ms */
  179. static int devslp_idle_timeout __read_mostly = 1000;
  180. module_param(devslp_idle_timeout, int, 0644);
  181. MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
  182. static void ahci_enable_ahci(void __iomem *mmio)
  183. {
  184. int i;
  185. u32 tmp;
  186. /* turn on AHCI_EN */
  187. tmp = readl(mmio + HOST_CTL);
  188. if (tmp & HOST_AHCI_EN)
  189. return;
  190. /* Some controllers need AHCI_EN to be written multiple times.
  191. * Try a few times before giving up.
  192. */
  193. for (i = 0; i < 5; i++) {
  194. tmp |= HOST_AHCI_EN;
  195. writel(tmp, mmio + HOST_CTL);
  196. tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
  197. if (tmp & HOST_AHCI_EN)
  198. return;
  199. msleep(10);
  200. }
  201. WARN_ON(1);
  202. }
  203. static ssize_t ahci_show_host_caps(struct device *dev,
  204. struct device_attribute *attr, char *buf)
  205. {
  206. struct Scsi_Host *shost = class_to_shost(dev);
  207. struct ata_port *ap = ata_shost_to_port(shost);
  208. struct ahci_host_priv *hpriv = ap->host->private_data;
  209. return sprintf(buf, "%x\n", hpriv->cap);
  210. }
  211. static ssize_t ahci_show_host_cap2(struct device *dev,
  212. struct device_attribute *attr, char *buf)
  213. {
  214. struct Scsi_Host *shost = class_to_shost(dev);
  215. struct ata_port *ap = ata_shost_to_port(shost);
  216. struct ahci_host_priv *hpriv = ap->host->private_data;
  217. return sprintf(buf, "%x\n", hpriv->cap2);
  218. }
  219. static ssize_t ahci_show_host_version(struct device *dev,
  220. struct device_attribute *attr, char *buf)
  221. {
  222. struct Scsi_Host *shost = class_to_shost(dev);
  223. struct ata_port *ap = ata_shost_to_port(shost);
  224. struct ahci_host_priv *hpriv = ap->host->private_data;
  225. void __iomem *mmio = hpriv->mmio;
  226. return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
  227. }
  228. static ssize_t ahci_show_port_cmd(struct device *dev,
  229. struct device_attribute *attr, char *buf)
  230. {
  231. struct Scsi_Host *shost = class_to_shost(dev);
  232. struct ata_port *ap = ata_shost_to_port(shost);
  233. void __iomem *port_mmio = ahci_port_base(ap);
  234. return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
  235. }
  236. static ssize_t ahci_read_em_buffer(struct device *dev,
  237. struct device_attribute *attr, char *buf)
  238. {
  239. struct Scsi_Host *shost = class_to_shost(dev);
  240. struct ata_port *ap = ata_shost_to_port(shost);
  241. struct ahci_host_priv *hpriv = ap->host->private_data;
  242. void __iomem *mmio = hpriv->mmio;
  243. void __iomem *em_mmio = mmio + hpriv->em_loc;
  244. u32 em_ctl, msg;
  245. unsigned long flags;
  246. size_t count;
  247. int i;
  248. spin_lock_irqsave(ap->lock, flags);
  249. em_ctl = readl(mmio + HOST_EM_CTL);
  250. if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
  251. !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
  252. spin_unlock_irqrestore(ap->lock, flags);
  253. return -EINVAL;
  254. }
  255. if (!(em_ctl & EM_CTL_MR)) {
  256. spin_unlock_irqrestore(ap->lock, flags);
  257. return -EAGAIN;
  258. }
  259. if (!(em_ctl & EM_CTL_SMB))
  260. em_mmio += hpriv->em_buf_sz;
  261. count = hpriv->em_buf_sz;
  262. /* the count should not be larger than PAGE_SIZE */
  263. if (count > PAGE_SIZE) {
  264. if (printk_ratelimit())
  265. ata_port_warn(ap,
  266. "EM read buffer size too large: "
  267. "buffer size %u, page size %lu\n",
  268. hpriv->em_buf_sz, PAGE_SIZE);
  269. count = PAGE_SIZE;
  270. }
  271. for (i = 0; i < count; i += 4) {
  272. msg = readl(em_mmio + i);
  273. buf[i] = msg & 0xff;
  274. buf[i + 1] = (msg >> 8) & 0xff;
  275. buf[i + 2] = (msg >> 16) & 0xff;
  276. buf[i + 3] = (msg >> 24) & 0xff;
  277. }
  278. spin_unlock_irqrestore(ap->lock, flags);
  279. return i;
  280. }
  281. static ssize_t ahci_store_em_buffer(struct device *dev,
  282. struct device_attribute *attr,
  283. const char *buf, size_t size)
  284. {
  285. struct Scsi_Host *shost = class_to_shost(dev);
  286. struct ata_port *ap = ata_shost_to_port(shost);
  287. struct ahci_host_priv *hpriv = ap->host->private_data;
  288. void __iomem *mmio = hpriv->mmio;
  289. void __iomem *em_mmio = mmio + hpriv->em_loc;
  290. const unsigned char *msg_buf = buf;
  291. u32 em_ctl, msg;
  292. unsigned long flags;
  293. int i;
  294. /* check size validity */
  295. if (!(ap->flags & ATA_FLAG_EM) ||
  296. !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
  297. size % 4 || size > hpriv->em_buf_sz)
  298. return -EINVAL;
  299. spin_lock_irqsave(ap->lock, flags);
  300. em_ctl = readl(mmio + HOST_EM_CTL);
  301. if (em_ctl & EM_CTL_TM) {
  302. spin_unlock_irqrestore(ap->lock, flags);
  303. return -EBUSY;
  304. }
  305. for (i = 0; i < size; i += 4) {
  306. msg = msg_buf[i] | msg_buf[i + 1] << 8 |
  307. msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
  308. writel(msg, em_mmio + i);
  309. }
  310. writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
  311. spin_unlock_irqrestore(ap->lock, flags);
  312. return size;
  313. }
  314. static ssize_t ahci_show_em_supported(struct device *dev,
  315. struct device_attribute *attr, char *buf)
  316. {
  317. struct Scsi_Host *shost = class_to_shost(dev);
  318. struct ata_port *ap = ata_shost_to_port(shost);
  319. struct ahci_host_priv *hpriv = ap->host->private_data;
  320. void __iomem *mmio = hpriv->mmio;
  321. u32 em_ctl;
  322. em_ctl = readl(mmio + HOST_EM_CTL);
  323. return sprintf(buf, "%s%s%s%s\n",
  324. em_ctl & EM_CTL_LED ? "led " : "",
  325. em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
  326. em_ctl & EM_CTL_SES ? "ses-2 " : "",
  327. em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
  328. }
  329. /**
  330. * ahci_save_initial_config - Save and fixup initial config values
  331. * @dev: target AHCI device
  332. * @hpriv: host private area to store config values
  333. * @force_port_map: force port map to a specified value
  334. * @mask_port_map: mask out particular bits from port map
  335. *
  336. * Some registers containing configuration info might be setup by
  337. * BIOS and might be cleared on reset. This function saves the
  338. * initial values of those registers into @hpriv such that they
  339. * can be restored after controller reset.
  340. *
  341. * If inconsistent, config values are fixed up by this function.
  342. *
  343. * LOCKING:
  344. * None.
  345. */
  346. void ahci_save_initial_config(struct device *dev,
  347. struct ahci_host_priv *hpriv,
  348. unsigned int force_port_map,
  349. unsigned int mask_port_map)
  350. {
  351. void __iomem *mmio = hpriv->mmio;
  352. u32 cap, cap2, vers, port_map;
  353. int i;
  354. /* make sure AHCI mode is enabled before accessing CAP */
  355. ahci_enable_ahci(mmio);
  356. /* Values prefixed with saved_ are written back to host after
  357. * reset. Values without are used for driver operation.
  358. */
  359. hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
  360. hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
  361. /* CAP2 register is only defined for AHCI 1.2 and later */
  362. vers = readl(mmio + HOST_VERSION);
  363. if ((vers >> 16) > 1 ||
  364. ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
  365. hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
  366. else
  367. hpriv->saved_cap2 = cap2 = 0;
  368. /* some chips have errata preventing 64bit use */
  369. if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
  370. dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
  371. cap &= ~HOST_CAP_64;
  372. }
  373. if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
  374. dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
  375. cap &= ~HOST_CAP_NCQ;
  376. }
  377. if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
  378. dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
  379. cap |= HOST_CAP_NCQ;
  380. }
  381. if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
  382. dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
  383. cap &= ~HOST_CAP_PMP;
  384. }
  385. if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
  386. dev_info(dev,
  387. "controller can't do SNTF, turning off CAP_SNTF\n");
  388. cap &= ~HOST_CAP_SNTF;
  389. }
  390. if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
  391. dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
  392. cap |= HOST_CAP_FBS;
  393. }
  394. if (force_port_map && port_map != force_port_map) {
  395. dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
  396. port_map, force_port_map);
  397. port_map = force_port_map;
  398. }
  399. if (mask_port_map) {
  400. dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
  401. port_map,
  402. port_map & mask_port_map);
  403. port_map &= mask_port_map;
  404. }
  405. /* cross check port_map and cap.n_ports */
  406. if (port_map) {
  407. int map_ports = 0;
  408. for (i = 0; i < AHCI_MAX_PORTS; i++)
  409. if (port_map & (1 << i))
  410. map_ports++;
  411. /* If PI has more ports than n_ports, whine, clear
  412. * port_map and let it be generated from n_ports.
  413. */
  414. if (map_ports > ahci_nr_ports(cap)) {
  415. dev_warn(dev,
  416. "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
  417. port_map, ahci_nr_ports(cap));
  418. port_map = 0;
  419. }
  420. }
  421. /* fabricate port_map from cap.nr_ports */
  422. if (!port_map) {
  423. port_map = (1 << ahci_nr_ports(cap)) - 1;
  424. dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
  425. /* write the fixed up value to the PI register */
  426. hpriv->saved_port_map = port_map;
  427. }
  428. /* record values to use during operation */
  429. hpriv->cap = cap;
  430. hpriv->cap2 = cap2;
  431. hpriv->port_map = port_map;
  432. }
  433. EXPORT_SYMBOL_GPL(ahci_save_initial_config);
  434. /**
  435. * ahci_restore_initial_config - Restore initial config
  436. * @host: target ATA host
  437. *
  438. * Restore initial config stored by ahci_save_initial_config().
  439. *
  440. * LOCKING:
  441. * None.
  442. */
  443. static void ahci_restore_initial_config(struct ata_host *host)
  444. {
  445. struct ahci_host_priv *hpriv = host->private_data;
  446. void __iomem *mmio = hpriv->mmio;
  447. writel(hpriv->saved_cap, mmio + HOST_CAP);
  448. if (hpriv->saved_cap2)
  449. writel(hpriv->saved_cap2, mmio + HOST_CAP2);
  450. writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
  451. (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
  452. }
  453. static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
  454. {
  455. static const int offset[] = {
  456. [SCR_STATUS] = PORT_SCR_STAT,
  457. [SCR_CONTROL] = PORT_SCR_CTL,
  458. [SCR_ERROR] = PORT_SCR_ERR,
  459. [SCR_ACTIVE] = PORT_SCR_ACT,
  460. [SCR_NOTIFICATION] = PORT_SCR_NTF,
  461. };
  462. struct ahci_host_priv *hpriv = ap->host->private_data;
  463. if (sc_reg < ARRAY_SIZE(offset) &&
  464. (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
  465. return offset[sc_reg];
  466. return 0;
  467. }
  468. static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
  469. {
  470. void __iomem *port_mmio = ahci_port_base(link->ap);
  471. int offset = ahci_scr_offset(link->ap, sc_reg);
  472. if (offset) {
  473. *val = readl(port_mmio + offset);
  474. return 0;
  475. }
  476. return -EINVAL;
  477. }
  478. static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
  479. {
  480. void __iomem *port_mmio = ahci_port_base(link->ap);
  481. int offset = ahci_scr_offset(link->ap, sc_reg);
  482. if (offset) {
  483. writel(val, port_mmio + offset);
  484. return 0;
  485. }
  486. return -EINVAL;
  487. }
  488. void ahci_start_engine(struct ata_port *ap)
  489. {
  490. void __iomem *port_mmio = ahci_port_base(ap);
  491. u32 tmp;
  492. /* start DMA */
  493. tmp = readl(port_mmio + PORT_CMD);
  494. tmp |= PORT_CMD_START;
  495. writel(tmp, port_mmio + PORT_CMD);
  496. readl(port_mmio + PORT_CMD); /* flush */
  497. }
  498. EXPORT_SYMBOL_GPL(ahci_start_engine);
  499. int ahci_stop_engine(struct ata_port *ap)
  500. {
  501. void __iomem *port_mmio = ahci_port_base(ap);
  502. u32 tmp;
  503. tmp = readl(port_mmio + PORT_CMD);
  504. /* check if the HBA is idle */
  505. if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
  506. return 0;
  507. /* setting HBA to idle */
  508. tmp &= ~PORT_CMD_START;
  509. writel(tmp, port_mmio + PORT_CMD);
  510. /* wait for engine to stop. This could be as long as 500 msec */
  511. tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
  512. PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
  513. if (tmp & PORT_CMD_LIST_ON)
  514. return -EIO;
  515. return 0;
  516. }
  517. EXPORT_SYMBOL_GPL(ahci_stop_engine);
  518. static void ahci_start_fis_rx(struct ata_port *ap)
  519. {
  520. void __iomem *port_mmio = ahci_port_base(ap);
  521. struct ahci_host_priv *hpriv = ap->host->private_data;
  522. struct ahci_port_priv *pp = ap->private_data;
  523. u32 tmp;
  524. /* set FIS registers */
  525. if (hpriv->cap & HOST_CAP_64)
  526. writel((pp->cmd_slot_dma >> 16) >> 16,
  527. port_mmio + PORT_LST_ADDR_HI);
  528. writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
  529. if (hpriv->cap & HOST_CAP_64)
  530. writel((pp->rx_fis_dma >> 16) >> 16,
  531. port_mmio + PORT_FIS_ADDR_HI);
  532. writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
  533. /* enable FIS reception */
  534. tmp = readl(port_mmio + PORT_CMD);
  535. tmp |= PORT_CMD_FIS_RX;
  536. writel(tmp, port_mmio + PORT_CMD);
  537. /* flush */
  538. readl(port_mmio + PORT_CMD);
  539. }
  540. static int ahci_stop_fis_rx(struct ata_port *ap)
  541. {
  542. void __iomem *port_mmio = ahci_port_base(ap);
  543. u32 tmp;
  544. /* disable FIS reception */
  545. tmp = readl(port_mmio + PORT_CMD);
  546. tmp &= ~PORT_CMD_FIS_RX;
  547. writel(tmp, port_mmio + PORT_CMD);
  548. /* wait for completion, spec says 500ms, give it 1000 */
  549. tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
  550. PORT_CMD_FIS_ON, 10, 1000);
  551. if (tmp & PORT_CMD_FIS_ON)
  552. return -EBUSY;
  553. return 0;
  554. }
  555. static void ahci_power_up(struct ata_port *ap)
  556. {
  557. struct ahci_host_priv *hpriv = ap->host->private_data;
  558. void __iomem *port_mmio = ahci_port_base(ap);
  559. u32 cmd;
  560. cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
  561. /* spin up device */
  562. if (hpriv->cap & HOST_CAP_SSS) {
  563. cmd |= PORT_CMD_SPIN_UP;
  564. writel(cmd, port_mmio + PORT_CMD);
  565. }
  566. /* wake up link */
  567. writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
  568. }
  569. static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
  570. unsigned int hints)
  571. {
  572. struct ata_port *ap = link->ap;
  573. struct ahci_host_priv *hpriv = ap->host->private_data;
  574. struct ahci_port_priv *pp = ap->private_data;
  575. void __iomem *port_mmio = ahci_port_base(ap);
  576. if (policy != ATA_LPM_MAX_POWER) {
  577. /*
  578. * Disable interrupts on Phy Ready. This keeps us from
  579. * getting woken up due to spurious phy ready
  580. * interrupts.
  581. */
  582. pp->intr_mask &= ~PORT_IRQ_PHYRDY;
  583. writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
  584. sata_link_scr_lpm(link, policy, false);
  585. }
  586. if (hpriv->cap & HOST_CAP_ALPM) {
  587. u32 cmd = readl(port_mmio + PORT_CMD);
  588. if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
  589. cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
  590. cmd |= PORT_CMD_ICC_ACTIVE;
  591. writel(cmd, port_mmio + PORT_CMD);
  592. readl(port_mmio + PORT_CMD);
  593. /* wait 10ms to be sure we've come out of LPM state */
  594. ata_msleep(ap, 10);
  595. } else {
  596. cmd |= PORT_CMD_ALPE;
  597. if (policy == ATA_LPM_MIN_POWER)
  598. cmd |= PORT_CMD_ASP;
  599. /* write out new cmd value */
  600. writel(cmd, port_mmio + PORT_CMD);
  601. }
  602. }
  603. /* set aggressive device sleep */
  604. if ((hpriv->cap2 & HOST_CAP2_SDS) &&
  605. (hpriv->cap2 & HOST_CAP2_SADM) &&
  606. (link->device->flags & ATA_DFLAG_DEVSLP)) {
  607. if (policy == ATA_LPM_MIN_POWER)
  608. ahci_set_aggressive_devslp(ap, true);
  609. else
  610. ahci_set_aggressive_devslp(ap, false);
  611. }
  612. if (policy == ATA_LPM_MAX_POWER) {
  613. sata_link_scr_lpm(link, policy, false);
  614. /* turn PHYRDY IRQ back on */
  615. pp->intr_mask |= PORT_IRQ_PHYRDY;
  616. writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
  617. }
  618. return 0;
  619. }
  620. #ifdef CONFIG_PM
  621. static void ahci_power_down(struct ata_port *ap)
  622. {
  623. struct ahci_host_priv *hpriv = ap->host->private_data;
  624. void __iomem *port_mmio = ahci_port_base(ap);
  625. u32 cmd, scontrol;
  626. if (!(hpriv->cap & HOST_CAP_SSS))
  627. return;
  628. /* put device into listen mode, first set PxSCTL.DET to 0 */
  629. scontrol = readl(port_mmio + PORT_SCR_CTL);
  630. scontrol &= ~0xf;
  631. writel(scontrol, port_mmio + PORT_SCR_CTL);
  632. /* then set PxCMD.SUD to 0 */
  633. cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
  634. cmd &= ~PORT_CMD_SPIN_UP;
  635. writel(cmd, port_mmio + PORT_CMD);
  636. }
  637. #endif
  638. static void ahci_start_port(struct ata_port *ap)
  639. {
  640. struct ahci_host_priv *hpriv = ap->host->private_data;
  641. struct ahci_port_priv *pp = ap->private_data;
  642. struct ata_link *link;
  643. struct ahci_em_priv *emp;
  644. ssize_t rc;
  645. int i;
  646. /* enable FIS reception */
  647. ahci_start_fis_rx(ap);
  648. /* enable DMA */
  649. if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
  650. ahci_start_engine(ap);
  651. /* turn on LEDs */
  652. if (ap->flags & ATA_FLAG_EM) {
  653. ata_for_each_link(link, ap, EDGE) {
  654. emp = &pp->em_priv[link->pmp];
  655. /* EM Transmit bit maybe busy during init */
  656. for (i = 0; i < EM_MAX_RETRY; i++) {
  657. rc = ap->ops->transmit_led_message(ap,
  658. emp->led_state,
  659. 4);
  660. /*
  661. * If busy, give a breather but do not
  662. * release EH ownership by using msleep()
  663. * instead of ata_msleep(). EM Transmit
  664. * bit is busy for the whole host and
  665. * releasing ownership will cause other
  666. * ports to fail the same way.
  667. */
  668. if (rc == -EBUSY)
  669. msleep(1);
  670. else
  671. break;
  672. }
  673. }
  674. }
  675. if (ap->flags & ATA_FLAG_SW_ACTIVITY)
  676. ata_for_each_link(link, ap, EDGE)
  677. ahci_init_sw_activity(link);
  678. }
  679. static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
  680. {
  681. int rc;
  682. /* disable DMA */
  683. rc = ahci_stop_engine(ap);
  684. if (rc) {
  685. *emsg = "failed to stop engine";
  686. return rc;
  687. }
  688. /* disable FIS reception */
  689. rc = ahci_stop_fis_rx(ap);
  690. if (rc) {
  691. *emsg = "failed stop FIS RX";
  692. return rc;
  693. }
  694. return 0;
  695. }
  696. int ahci_reset_controller(struct ata_host *host)
  697. {
  698. struct ahci_host_priv *hpriv = host->private_data;
  699. void __iomem *mmio = hpriv->mmio;
  700. u32 tmp;
  701. /* we must be in AHCI mode, before using anything
  702. * AHCI-specific, such as HOST_RESET.
  703. */
  704. ahci_enable_ahci(mmio);
  705. /* global controller reset */
  706. if (!ahci_skip_host_reset) {
  707. tmp = readl(mmio + HOST_CTL);
  708. if ((tmp & HOST_RESET) == 0) {
  709. writel(tmp | HOST_RESET, mmio + HOST_CTL);
  710. readl(mmio + HOST_CTL); /* flush */
  711. }
  712. /*
  713. * to perform host reset, OS should set HOST_RESET
  714. * and poll until this bit is read to be "0".
  715. * reset must complete within 1 second, or
  716. * the hardware should be considered fried.
  717. */
  718. tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
  719. HOST_RESET, 10, 1000);
  720. if (tmp & HOST_RESET) {
  721. dev_err(host->dev, "controller reset failed (0x%x)\n",
  722. tmp);
  723. return -EIO;
  724. }
  725. /* turn on AHCI mode */
  726. ahci_enable_ahci(mmio);
  727. /* Some registers might be cleared on reset. Restore
  728. * initial values.
  729. */
  730. ahci_restore_initial_config(host);
  731. } else
  732. dev_info(host->dev, "skipping global host reset\n");
  733. return 0;
  734. }
  735. EXPORT_SYMBOL_GPL(ahci_reset_controller);
  736. static void ahci_sw_activity(struct ata_link *link)
  737. {
  738. struct ata_port *ap = link->ap;
  739. struct ahci_port_priv *pp = ap->private_data;
  740. struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
  741. if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
  742. return;
  743. emp->activity++;
  744. if (!timer_pending(&emp->timer))
  745. mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
  746. }
  747. static void ahci_sw_activity_blink(unsigned long arg)
  748. {
  749. struct ata_link *link = (struct ata_link *)arg;
  750. struct ata_port *ap = link->ap;
  751. struct ahci_port_priv *pp = ap->private_data;
  752. struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
  753. unsigned long led_message = emp->led_state;
  754. u32 activity_led_state;
  755. unsigned long flags;
  756. led_message &= EM_MSG_LED_VALUE;
  757. led_message |= ap->port_no | (link->pmp << 8);
  758. /* check to see if we've had activity. If so,
  759. * toggle state of LED and reset timer. If not,
  760. * turn LED to desired idle state.
  761. */
  762. spin_lock_irqsave(ap->lock, flags);
  763. if (emp->saved_activity != emp->activity) {
  764. emp->saved_activity = emp->activity;
  765. /* get the current LED state */
  766. activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
  767. if (activity_led_state)
  768. activity_led_state = 0;
  769. else
  770. activity_led_state = 1;
  771. /* clear old state */
  772. led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
  773. /* toggle state */
  774. led_message |= (activity_led_state << 16);
  775. mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
  776. } else {
  777. /* switch to idle */
  778. led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
  779. if (emp->blink_policy == BLINK_OFF)
  780. led_message |= (1 << 16);
  781. }
  782. spin_unlock_irqrestore(ap->lock, flags);
  783. ap->ops->transmit_led_message(ap, led_message, 4);
  784. }
  785. static void ahci_init_sw_activity(struct ata_link *link)
  786. {
  787. struct ata_port *ap = link->ap;
  788. struct ahci_port_priv *pp = ap->private_data;
  789. struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
  790. /* init activity stats, setup timer */
  791. emp->saved_activity = emp->activity = 0;
  792. setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
  793. /* check our blink policy and set flag for link if it's enabled */
  794. if (emp->blink_policy)
  795. link->flags |= ATA_LFLAG_SW_ACTIVITY;
  796. }
  797. int ahci_reset_em(struct ata_host *host)
  798. {
  799. struct ahci_host_priv *hpriv = host->private_data;
  800. void __iomem *mmio = hpriv->mmio;
  801. u32 em_ctl;
  802. em_ctl = readl(mmio + HOST_EM_CTL);
  803. if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
  804. return -EINVAL;
  805. writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
  806. return 0;
  807. }
  808. EXPORT_SYMBOL_GPL(ahci_reset_em);
  809. static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
  810. ssize_t size)
  811. {
  812. struct ahci_host_priv *hpriv = ap->host->private_data;
  813. struct ahci_port_priv *pp = ap->private_data;
  814. void __iomem *mmio = hpriv->mmio;
  815. u32 em_ctl;
  816. u32 message[] = {0, 0};
  817. unsigned long flags;
  818. int pmp;
  819. struct ahci_em_priv *emp;
  820. /* get the slot number from the message */
  821. pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
  822. if (pmp < EM_MAX_SLOTS)
  823. emp = &pp->em_priv[pmp];
  824. else
  825. return -EINVAL;
  826. spin_lock_irqsave(ap->lock, flags);
  827. /*
  828. * if we are still busy transmitting a previous message,
  829. * do not allow
  830. */
  831. em_ctl = readl(mmio + HOST_EM_CTL);
  832. if (em_ctl & EM_CTL_TM) {
  833. spin_unlock_irqrestore(ap->lock, flags);
  834. return -EBUSY;
  835. }
  836. if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
  837. /*
  838. * create message header - this is all zero except for
  839. * the message size, which is 4 bytes.
  840. */
  841. message[0] |= (4 << 8);
  842. /* ignore 0:4 of byte zero, fill in port info yourself */
  843. message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
  844. /* write message to EM_LOC */
  845. writel(message[0], mmio + hpriv->em_loc);
  846. writel(message[1], mmio + hpriv->em_loc+4);
  847. /*
  848. * tell hardware to transmit the message
  849. */
  850. writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
  851. }
  852. /* save off new led state for port/slot */
  853. emp->led_state = state;
  854. spin_unlock_irqrestore(ap->lock, flags);
  855. return size;
  856. }
  857. static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
  858. {
  859. struct ahci_port_priv *pp = ap->private_data;
  860. struct ata_link *link;
  861. struct ahci_em_priv *emp;
  862. int rc = 0;
  863. ata_for_each_link(link, ap, EDGE) {
  864. emp = &pp->em_priv[link->pmp];
  865. rc += sprintf(buf, "%lx\n", emp->led_state);
  866. }
  867. return rc;
  868. }
  869. static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
  870. size_t size)
  871. {
  872. int state;
  873. int pmp;
  874. struct ahci_port_priv *pp = ap->private_data;
  875. struct ahci_em_priv *emp;
  876. state = simple_strtoul(buf, NULL, 0);
  877. /* get the slot number from the message */
  878. pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
  879. if (pmp < EM_MAX_SLOTS)
  880. emp = &pp->em_priv[pmp];
  881. else
  882. return -EINVAL;
  883. /* mask off the activity bits if we are in sw_activity
  884. * mode, user should turn off sw_activity before setting
  885. * activity led through em_message
  886. */
  887. if (emp->blink_policy)
  888. state &= ~EM_MSG_LED_VALUE_ACTIVITY;
  889. return ap->ops->transmit_led_message(ap, state, size);
  890. }
  891. static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
  892. {
  893. struct ata_link *link = dev->link;
  894. struct ata_port *ap = link->ap;
  895. struct ahci_port_priv *pp = ap->private_data;
  896. struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
  897. u32 port_led_state = emp->led_state;
  898. /* save the desired Activity LED behavior */
  899. if (val == OFF) {
  900. /* clear LFLAG */
  901. link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
  902. /* set the LED to OFF */
  903. port_led_state &= EM_MSG_LED_VALUE_OFF;
  904. port_led_state |= (ap->port_no | (link->pmp << 8));
  905. ap->ops->transmit_led_message(ap, port_led_state, 4);
  906. } else {
  907. link->flags |= ATA_LFLAG_SW_ACTIVITY;
  908. if (val == BLINK_OFF) {
  909. /* set LED to ON for idle */
  910. port_led_state &= EM_MSG_LED_VALUE_OFF;
  911. port_led_state |= (ap->port_no | (link->pmp << 8));
  912. port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
  913. ap->ops->transmit_led_message(ap, port_led_state, 4);
  914. }
  915. }
  916. emp->blink_policy = val;
  917. return 0;
  918. }
  919. static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
  920. {
  921. struct ata_link *link = dev->link;
  922. struct ata_port *ap = link->ap;
  923. struct ahci_port_priv *pp = ap->private_data;
  924. struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
  925. /* display the saved value of activity behavior for this
  926. * disk.
  927. */
  928. return sprintf(buf, "%d\n", emp->blink_policy);
  929. }
  930. static void ahci_port_init(struct device *dev, struct ata_port *ap,
  931. int port_no, void __iomem *mmio,
  932. void __iomem *port_mmio)
  933. {
  934. const char *emsg = NULL;
  935. int rc;
  936. u32 tmp;
  937. /* make sure port is not active */
  938. rc = ahci_deinit_port(ap, &emsg);
  939. if (rc)
  940. dev_warn(dev, "%s (%d)\n", emsg, rc);
  941. /* clear SError */
  942. tmp = readl(port_mmio + PORT_SCR_ERR);
  943. VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
  944. writel(tmp, port_mmio + PORT_SCR_ERR);
  945. /* clear port IRQ */
  946. tmp = readl(port_mmio + PORT_IRQ_STAT);
  947. VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
  948. if (tmp)
  949. writel(tmp, port_mmio + PORT_IRQ_STAT);
  950. writel(1 << port_no, mmio + HOST_IRQ_STAT);
  951. }
  952. void ahci_init_controller(struct ata_host *host)
  953. {
  954. struct ahci_host_priv *hpriv = host->private_data;
  955. void __iomem *mmio = hpriv->mmio;
  956. int i;
  957. void __iomem *port_mmio;
  958. u32 tmp;
  959. for (i = 0; i < host->n_ports; i++) {
  960. struct ata_port *ap = host->ports[i];
  961. port_mmio = ahci_port_base(ap);
  962. if (ata_port_is_dummy(ap))
  963. continue;
  964. ahci_port_init(host->dev, ap, i, mmio, port_mmio);
  965. }
  966. tmp = readl(mmio + HOST_CTL);
  967. VPRINTK("HOST_CTL 0x%x\n", tmp);
  968. writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
  969. tmp = readl(mmio + HOST_CTL);
  970. VPRINTK("HOST_CTL 0x%x\n", tmp);
  971. }
  972. EXPORT_SYMBOL_GPL(ahci_init_controller);
  973. static void ahci_dev_config(struct ata_device *dev)
  974. {
  975. struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
  976. if (hpriv->flags & AHCI_HFLAG_SECT255) {
  977. dev->max_sectors = 255;
  978. ata_dev_info(dev,
  979. "SB600 AHCI: limiting to 255 sectors per cmd\n");
  980. }
  981. }
  982. unsigned int ahci_dev_classify(struct ata_port *ap)
  983. {
  984. void __iomem *port_mmio = ahci_port_base(ap);
  985. struct ata_taskfile tf;
  986. u32 tmp;
  987. tmp = readl(port_mmio + PORT_SIG);
  988. tf.lbah = (tmp >> 24) & 0xff;
  989. tf.lbam = (tmp >> 16) & 0xff;
  990. tf.lbal = (tmp >> 8) & 0xff;
  991. tf.nsect = (tmp) & 0xff;
  992. return ata_dev_classify(&tf);
  993. }
  994. EXPORT_SYMBOL_GPL(ahci_dev_classify);
  995. void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
  996. u32 opts)
  997. {
  998. dma_addr_t cmd_tbl_dma;
  999. cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
  1000. pp->cmd_slot[tag].opts = cpu_to_le32(opts);
  1001. pp->cmd_slot[tag].status = 0;
  1002. pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
  1003. pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
  1004. }
  1005. EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
  1006. int ahci_kick_engine(struct ata_port *ap)
  1007. {
  1008. void __iomem *port_mmio = ahci_port_base(ap);
  1009. struct ahci_host_priv *hpriv = ap->host->private_data;
  1010. u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
  1011. u32 tmp;
  1012. int busy, rc;
  1013. /* stop engine */
  1014. rc = ahci_stop_engine(ap);
  1015. if (rc)
  1016. goto out_restart;
  1017. /* need to do CLO?
  1018. * always do CLO if PMP is attached (AHCI-1.3 9.2)
  1019. */
  1020. busy = status & (ATA_BUSY | ATA_DRQ);
  1021. if (!busy && !sata_pmp_attached(ap)) {
  1022. rc = 0;
  1023. goto out_restart;
  1024. }
  1025. if (!(hpriv->cap & HOST_CAP_CLO)) {
  1026. rc = -EOPNOTSUPP;
  1027. goto out_restart;
  1028. }
  1029. /* perform CLO */
  1030. tmp = readl(port_mmio + PORT_CMD);
  1031. tmp |= PORT_CMD_CLO;
  1032. writel(tmp, port_mmio + PORT_CMD);
  1033. rc = 0;
  1034. tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
  1035. PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
  1036. if (tmp & PORT_CMD_CLO)
  1037. rc = -EIO;
  1038. /* restart engine */
  1039. out_restart:
  1040. ahci_start_engine(ap);
  1041. return rc;
  1042. }
  1043. EXPORT_SYMBOL_GPL(ahci_kick_engine);
  1044. static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
  1045. struct ata_taskfile *tf, int is_cmd, u16 flags,
  1046. unsigned long timeout_msec)
  1047. {
  1048. const u32 cmd_fis_len = 5; /* five dwords */
  1049. struct ahci_port_priv *pp = ap->private_data;
  1050. void __iomem *port_mmio = ahci_port_base(ap);
  1051. u8 *fis = pp->cmd_tbl;
  1052. u32 tmp;
  1053. /* prep the command */
  1054. ata_tf_to_fis(tf, pmp, is_cmd, fis);
  1055. ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
  1056. /* issue & wait */
  1057. writel(1, port_mmio + PORT_CMD_ISSUE);
  1058. if (timeout_msec) {
  1059. tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
  1060. 0x1, 0x1, 1, timeout_msec);
  1061. if (tmp & 0x1) {
  1062. ahci_kick_engine(ap);
  1063. return -EBUSY;
  1064. }
  1065. } else
  1066. readl(port_mmio + PORT_CMD_ISSUE); /* flush */
  1067. return 0;
  1068. }
  1069. int ahci_do_softreset(struct ata_link *link, unsigned int *class,
  1070. int pmp, unsigned long deadline,
  1071. int (*check_ready)(struct ata_link *link))
  1072. {
  1073. struct ata_port *ap = link->ap;
  1074. struct ahci_host_priv *hpriv = ap->host->private_data;
  1075. struct ahci_port_priv *pp = ap->private_data;
  1076. const char *reason = NULL;
  1077. unsigned long now, msecs;
  1078. struct ata_taskfile tf;
  1079. bool fbs_disabled = false;
  1080. int rc;
  1081. DPRINTK("ENTER\n");
  1082. /* prepare for SRST (AHCI-1.1 10.4.1) */
  1083. rc = ahci_kick_engine(ap);
  1084. if (rc && rc != -EOPNOTSUPP)
  1085. ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
  1086. /*
  1087. * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
  1088. * clear PxFBS.EN to '0' prior to issuing software reset to devices
  1089. * that is attached to port multiplier.
  1090. */
  1091. if (!ata_is_host_link(link) && pp->fbs_enabled) {
  1092. ahci_disable_fbs(ap);
  1093. fbs_disabled = true;
  1094. }
  1095. ata_tf_init(link->device, &tf);
  1096. /* issue the first D2H Register FIS */
  1097. msecs = 0;
  1098. now = jiffies;
  1099. if (time_after(deadline, now))
  1100. msecs = jiffies_to_msecs(deadline - now);
  1101. tf.ctl |= ATA_SRST;
  1102. if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
  1103. AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
  1104. rc = -EIO;
  1105. reason = "1st FIS failed";
  1106. goto fail;
  1107. }
  1108. /* spec says at least 5us, but be generous and sleep for 1ms */
  1109. ata_msleep(ap, 1);
  1110. /* issue the second D2H Register FIS */
  1111. tf.ctl &= ~ATA_SRST;
  1112. ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
  1113. /* wait for link to become ready */
  1114. rc = ata_wait_after_reset(link, deadline, check_ready);
  1115. if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
  1116. /*
  1117. * Workaround for cases where link online status can't
  1118. * be trusted. Treat device readiness timeout as link
  1119. * offline.
  1120. */
  1121. ata_link_info(link, "device not ready, treating as offline\n");
  1122. *class = ATA_DEV_NONE;
  1123. } else if (rc) {
  1124. /* link occupied, -ENODEV too is an error */
  1125. reason = "device not ready";
  1126. goto fail;
  1127. } else
  1128. *class = ahci_dev_classify(ap);
  1129. /* re-enable FBS if disabled before */
  1130. if (fbs_disabled)
  1131. ahci_enable_fbs(ap);
  1132. DPRINTK("EXIT, class=%u\n", *class);
  1133. return 0;
  1134. fail:
  1135. ata_link_err(link, "softreset failed (%s)\n", reason);
  1136. return rc;
  1137. }
  1138. int ahci_check_ready(struct ata_link *link)
  1139. {
  1140. void __iomem *port_mmio = ahci_port_base(link->ap);
  1141. u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
  1142. return ata_check_ready(status);
  1143. }
  1144. EXPORT_SYMBOL_GPL(ahci_check_ready);
  1145. static int ahci_softreset(struct ata_link *link, unsigned int *class,
  1146. unsigned long deadline)
  1147. {
  1148. int pmp = sata_srst_pmp(link);
  1149. DPRINTK("ENTER\n");
  1150. return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
  1151. }
  1152. EXPORT_SYMBOL_GPL(ahci_do_softreset);
  1153. static int ahci_bad_pmp_check_ready(struct ata_link *link)
  1154. {
  1155. void __iomem *port_mmio = ahci_port_base(link->ap);
  1156. u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
  1157. u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
  1158. /*
  1159. * There is no need to check TFDATA if BAD PMP is found due to HW bug,
  1160. * which can save timeout delay.
  1161. */
  1162. if (irq_status & PORT_IRQ_BAD_PMP)
  1163. return -EIO;
  1164. return ata_check_ready(status);
  1165. }
  1166. int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
  1167. unsigned long deadline)
  1168. {
  1169. struct ata_port *ap = link->ap;
  1170. void __iomem *port_mmio = ahci_port_base(ap);
  1171. int pmp = sata_srst_pmp(link);
  1172. int rc;
  1173. u32 irq_sts;
  1174. DPRINTK("ENTER\n");
  1175. rc = ahci_do_softreset(link, class, pmp, deadline,
  1176. ahci_bad_pmp_check_ready);
  1177. /*
  1178. * Soft reset fails with IPMS set when PMP is enabled but
  1179. * SATA HDD/ODD is connected to SATA port, do soft reset
  1180. * again to port 0.
  1181. */
  1182. if (rc == -EIO) {
  1183. irq_sts = readl(port_mmio + PORT_IRQ_STAT);
  1184. if (irq_sts & PORT_IRQ_BAD_PMP) {
  1185. ata_link_warn(link,
  1186. "applying PMP SRST workaround "
  1187. "and retrying\n");
  1188. rc = ahci_do_softreset(link, class, 0, deadline,
  1189. ahci_check_ready);
  1190. }
  1191. }
  1192. return rc;
  1193. }
  1194. static int ahci_hardreset(struct ata_link *link, unsigned int *class,
  1195. unsigned long deadline)
  1196. {
  1197. const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
  1198. struct ata_port *ap = link->ap;
  1199. struct ahci_port_priv *pp = ap->private_data;
  1200. u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
  1201. struct ata_taskfile tf;
  1202. bool online;
  1203. int rc;
  1204. DPRINTK("ENTER\n");
  1205. ahci_stop_engine(ap);
  1206. /* clear D2H reception area to properly wait for D2H FIS */
  1207. ata_tf_init(link->device, &tf);
  1208. tf.command = ATA_BUSY;
  1209. ata_tf_to_fis(&tf, 0, 0, d2h_fis);
  1210. rc = sata_link_hardreset(link, timing, deadline, &online,
  1211. ahci_check_ready);
  1212. ahci_start_engine(ap);
  1213. if (online)
  1214. *class = ahci_dev_classify(ap);
  1215. DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
  1216. return rc;
  1217. }
  1218. static void ahci_postreset(struct ata_link *link, unsigned int *class)
  1219. {
  1220. struct ata_port *ap = link->ap;
  1221. void __iomem *port_mmio = ahci_port_base(ap);
  1222. u32 new_tmp, tmp;
  1223. ata_std_postreset(link, class);
  1224. /* Make sure port's ATAPI bit is set appropriately */
  1225. new_tmp = tmp = readl(port_mmio + PORT_CMD);
  1226. if (*class == ATA_DEV_ATAPI)
  1227. new_tmp |= PORT_CMD_ATAPI;
  1228. else
  1229. new_tmp &= ~PORT_CMD_ATAPI;
  1230. if (new_tmp != tmp) {
  1231. writel(new_tmp, port_mmio + PORT_CMD);
  1232. readl(port_mmio + PORT_CMD); /* flush */
  1233. }
  1234. }
  1235. static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
  1236. {
  1237. struct scatterlist *sg;
  1238. struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
  1239. unsigned int si;
  1240. VPRINTK("ENTER\n");
  1241. /*
  1242. * Next, the S/G list.
  1243. */
  1244. for_each_sg(qc->sg, sg, qc->n_elem, si) {
  1245. dma_addr_t addr = sg_dma_address(sg);
  1246. u32 sg_len = sg_dma_len(sg);
  1247. ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
  1248. ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
  1249. ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
  1250. }
  1251. return si;
  1252. }
  1253. static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
  1254. {
  1255. struct ata_port *ap = qc->ap;
  1256. struct ahci_port_priv *pp = ap->private_data;
  1257. if (!sata_pmp_attached(ap) || pp->fbs_enabled)
  1258. return ata_std_qc_defer(qc);
  1259. else
  1260. return sata_pmp_qc_defer_cmd_switch(qc);
  1261. }
  1262. static void ahci_qc_prep(struct ata_queued_cmd *qc)
  1263. {
  1264. struct ata_port *ap = qc->ap;
  1265. struct ahci_port_priv *pp = ap->private_data;
  1266. int is_atapi = ata_is_atapi(qc->tf.protocol);
  1267. void *cmd_tbl;
  1268. u32 opts;
  1269. const u32 cmd_fis_len = 5; /* five dwords */
  1270. unsigned int n_elem;
  1271. /*
  1272. * Fill in command table information. First, the header,
  1273. * a SATA Register - Host to Device command FIS.
  1274. */
  1275. cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
  1276. ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
  1277. if (is_atapi) {
  1278. memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
  1279. memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
  1280. }
  1281. n_elem = 0;
  1282. if (qc->flags & ATA_QCFLAG_DMAMAP)
  1283. n_elem = ahci_fill_sg(qc, cmd_tbl);
  1284. /*
  1285. * Fill in command slot information.
  1286. */
  1287. opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
  1288. if (qc->tf.flags & ATA_TFLAG_WRITE)
  1289. opts |= AHCI_CMD_WRITE;
  1290. if (is_atapi)
  1291. opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
  1292. ahci_fill_cmd_slot(pp, qc->tag, opts);
  1293. }
  1294. static void ahci_fbs_dec_intr(struct ata_port *ap)
  1295. {
  1296. struct ahci_port_priv *pp = ap->private_data;
  1297. void __iomem *port_mmio = ahci_port_base(ap);
  1298. u32 fbs = readl(port_mmio + PORT_FBS);
  1299. int retries = 3;
  1300. DPRINTK("ENTER\n");
  1301. BUG_ON(!pp->fbs_enabled);
  1302. /* time to wait for DEC is not specified by AHCI spec,
  1303. * add a retry loop for safety.
  1304. */
  1305. writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
  1306. fbs = readl(port_mmio + PORT_FBS);
  1307. while ((fbs & PORT_FBS_DEC) && retries--) {
  1308. udelay(1);
  1309. fbs = readl(port_mmio + PORT_FBS);
  1310. }
  1311. if (fbs & PORT_FBS_DEC)
  1312. dev_err(ap->host->dev, "failed to clear device error\n");
  1313. }
  1314. static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
  1315. {
  1316. struct ahci_host_priv *hpriv = ap->host->private_data;
  1317. struct ahci_port_priv *pp = ap->private_data;
  1318. struct ata_eh_info *host_ehi = &ap->link.eh_info;
  1319. struct ata_link *link = NULL;
  1320. struct ata_queued_cmd *active_qc;
  1321. struct ata_eh_info *active_ehi;
  1322. bool fbs_need_dec = false;
  1323. u32 serror;
  1324. /* determine active link with error */
  1325. if (pp->fbs_enabled) {
  1326. void __iomem *port_mmio = ahci_port_base(ap);
  1327. u32 fbs = readl(port_mmio + PORT_FBS);
  1328. int pmp = fbs >> PORT_FBS_DWE_OFFSET;
  1329. if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
  1330. link = &ap->pmp_link[pmp];
  1331. fbs_need_dec = true;
  1332. }
  1333. } else
  1334. ata_for_each_link(link, ap, EDGE)
  1335. if (ata_link_active(link))
  1336. break;
  1337. if (!link)
  1338. link = &ap->link;
  1339. active_qc = ata_qc_from_tag(ap, link->active_tag);
  1340. active_ehi = &link->eh_info;
  1341. /* record irq stat */
  1342. ata_ehi_clear_desc(host_ehi);
  1343. ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
  1344. /* AHCI needs SError cleared; otherwise, it might lock up */
  1345. ahci_scr_read(&ap->link, SCR_ERROR, &serror);
  1346. ahci_scr_write(&ap->link, SCR_ERROR, serror);
  1347. host_ehi->serror |= serror;
  1348. /* some controllers set IRQ_IF_ERR on device errors, ignore it */
  1349. if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
  1350. irq_stat &= ~PORT_IRQ_IF_ERR;
  1351. if (irq_stat & PORT_IRQ_TF_ERR) {
  1352. /* If qc is active, charge it; otherwise, the active
  1353. * link. There's no active qc on NCQ errors. It will
  1354. * be determined by EH by reading log page 10h.
  1355. */
  1356. if (active_qc)
  1357. active_qc->err_mask |= AC_ERR_DEV;
  1358. else
  1359. active_ehi->err_mask |= AC_ERR_DEV;
  1360. if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
  1361. host_ehi->serror &= ~SERR_INTERNAL;
  1362. }
  1363. if (irq_stat & PORT_IRQ_UNK_FIS) {
  1364. u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
  1365. active_ehi->err_mask |= AC_ERR_HSM;
  1366. active_ehi->action |= ATA_EH_RESET;
  1367. ata_ehi_push_desc(active_ehi,
  1368. "unknown FIS %08x %08x %08x %08x" ,
  1369. unk[0], unk[1], unk[2], unk[3]);
  1370. }
  1371. if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
  1372. active_ehi->err_mask |= AC_ERR_HSM;
  1373. active_ehi->action |= ATA_EH_RESET;
  1374. ata_ehi_push_desc(active_ehi, "incorrect PMP");
  1375. }
  1376. if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
  1377. host_ehi->err_mask |= AC_ERR_HOST_BUS;
  1378. host_ehi->action |= ATA_EH_RESET;
  1379. ata_ehi_push_desc(host_ehi, "host bus error");
  1380. }
  1381. if (irq_stat & PORT_IRQ_IF_ERR) {
  1382. if (fbs_need_dec)
  1383. active_ehi->err_mask |= AC_ERR_DEV;
  1384. else {
  1385. host_ehi->err_mask |= AC_ERR_ATA_BUS;
  1386. host_ehi->action |= ATA_EH_RESET;
  1387. }
  1388. ata_ehi_push_desc(host_ehi, "interface fatal error");
  1389. }
  1390. if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
  1391. ata_ehi_hotplugged(host_ehi);
  1392. ata_ehi_push_desc(host_ehi, "%s",
  1393. irq_stat & PORT_IRQ_CONNECT ?
  1394. "connection status changed" : "PHY RDY changed");
  1395. }
  1396. /* okay, let's hand over to EH */
  1397. if (irq_stat & PORT_IRQ_FREEZE)
  1398. ata_port_freeze(ap);
  1399. else if (fbs_need_dec) {
  1400. ata_link_abort(link);
  1401. ahci_fbs_dec_intr(ap);
  1402. } else
  1403. ata_port_abort(ap);
  1404. }
  1405. static void ahci_handle_port_interrupt(struct ata_port *ap,
  1406. void __iomem *port_mmio, u32 status)
  1407. {
  1408. struct ata_eh_info *ehi = &ap->link.eh_info;
  1409. struct ahci_port_priv *pp = ap->private_data;
  1410. struct ahci_host_priv *hpriv = ap->host->private_data;
  1411. int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
  1412. u32 qc_active = 0;
  1413. int rc;
  1414. /* ignore BAD_PMP while resetting */
  1415. if (unlikely(resetting))
  1416. status &= ~PORT_IRQ_BAD_PMP;
  1417. /* if LPM is enabled, PHYRDY doesn't mean anything */
  1418. if (ap->link.lpm_policy > ATA_LPM_MAX_POWER) {
  1419. status &= ~PORT_IRQ_PHYRDY;
  1420. ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
  1421. }
  1422. if (unlikely(status & PORT_IRQ_ERROR)) {
  1423. ahci_error_intr(ap, status);
  1424. return;
  1425. }
  1426. if (status & PORT_IRQ_SDB_FIS) {
  1427. /* If SNotification is available, leave notification
  1428. * handling to sata_async_notification(). If not,
  1429. * emulate it by snooping SDB FIS RX area.
  1430. *
  1431. * Snooping FIS RX area is probably cheaper than
  1432. * poking SNotification but some constrollers which
  1433. * implement SNotification, ICH9 for example, don't
  1434. * store AN SDB FIS into receive area.
  1435. */
  1436. if (hpriv->cap & HOST_CAP_SNTF)
  1437. sata_async_notification(ap);
  1438. else {
  1439. /* If the 'N' bit in word 0 of the FIS is set,
  1440. * we just received asynchronous notification.
  1441. * Tell libata about it.
  1442. *
  1443. * Lack of SNotification should not appear in
  1444. * ahci 1.2, so the workaround is unnecessary
  1445. * when FBS is enabled.
  1446. */
  1447. if (pp->fbs_enabled)
  1448. WARN_ON_ONCE(1);
  1449. else {
  1450. const __le32 *f = pp->rx_fis + RX_FIS_SDB;
  1451. u32 f0 = le32_to_cpu(f[0]);
  1452. if (f0 & (1 << 15))
  1453. sata_async_notification(ap);
  1454. }
  1455. }
  1456. }
  1457. /* pp->active_link is not reliable once FBS is enabled, both
  1458. * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
  1459. * NCQ and non-NCQ commands may be in flight at the same time.
  1460. */
  1461. if (pp->fbs_enabled) {
  1462. if (ap->qc_active) {
  1463. qc_active = readl(port_mmio + PORT_SCR_ACT);
  1464. qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
  1465. }
  1466. } else {
  1467. /* pp->active_link is valid iff any command is in flight */
  1468. if (ap->qc_active && pp->active_link->sactive)
  1469. qc_active = readl(port_mmio + PORT_SCR_ACT);
  1470. else
  1471. qc_active = readl(port_mmio + PORT_CMD_ISSUE);
  1472. }
  1473. rc = ata_qc_complete_multiple(ap, qc_active);
  1474. /* while resetting, invalid completions are expected */
  1475. if (unlikely(rc < 0 && !resetting)) {
  1476. ehi->err_mask |= AC_ERR_HSM;
  1477. ehi->action |= ATA_EH_RESET;
  1478. ata_port_freeze(ap);
  1479. }
  1480. }
  1481. void ahci_port_intr(struct ata_port *ap)
  1482. {
  1483. void __iomem *port_mmio = ahci_port_base(ap);
  1484. u32 status;
  1485. status = readl(port_mmio + PORT_IRQ_STAT);
  1486. writel(status, port_mmio + PORT_IRQ_STAT);
  1487. ahci_handle_port_interrupt(ap, port_mmio, status);
  1488. }
  1489. irqreturn_t ahci_thread_fn(int irq, void *dev_instance)
  1490. {
  1491. struct ata_port *ap = dev_instance;
  1492. struct ahci_port_priv *pp = ap->private_data;
  1493. void __iomem *port_mmio = ahci_port_base(ap);
  1494. unsigned long flags;
  1495. u32 status;
  1496. spin_lock_irqsave(&ap->host->lock, flags);
  1497. status = pp->intr_status;
  1498. if (status)
  1499. pp->intr_status = 0;
  1500. spin_unlock_irqrestore(&ap->host->lock, flags);
  1501. spin_lock_bh(ap->lock);
  1502. ahci_handle_port_interrupt(ap, port_mmio, status);
  1503. spin_unlock_bh(ap->lock);
  1504. return IRQ_HANDLED;
  1505. }
  1506. EXPORT_SYMBOL_GPL(ahci_thread_fn);
  1507. void ahci_hw_port_interrupt(struct ata_port *ap)
  1508. {
  1509. void __iomem *port_mmio = ahci_port_base(ap);
  1510. struct ahci_port_priv *pp = ap->private_data;
  1511. u32 status;
  1512. status = readl(port_mmio + PORT_IRQ_STAT);
  1513. writel(status, port_mmio + PORT_IRQ_STAT);
  1514. pp->intr_status |= status;
  1515. }
  1516. irqreturn_t ahci_hw_interrupt(int irq, void *dev_instance)
  1517. {
  1518. struct ata_port *ap_this = dev_instance;
  1519. struct ahci_port_priv *pp = ap_this->private_data;
  1520. struct ata_host *host = ap_this->host;
  1521. struct ahci_host_priv *hpriv = host->private_data;
  1522. void __iomem *mmio = hpriv->mmio;
  1523. unsigned int i;
  1524. u32 irq_stat, irq_masked;
  1525. VPRINTK("ENTER\n");
  1526. spin_lock(&host->lock);
  1527. irq_stat = readl(mmio + HOST_IRQ_STAT);
  1528. if (!irq_stat) {
  1529. u32 status = pp->intr_status;
  1530. spin_unlock(&host->lock);
  1531. VPRINTK("EXIT\n");
  1532. return status ? IRQ_WAKE_THREAD : IRQ_NONE;
  1533. }
  1534. irq_masked = irq_stat & hpriv->port_map;
  1535. for (i = 0; i < host->n_ports; i++) {
  1536. struct ata_port *ap;
  1537. if (!(irq_masked & (1 << i)))
  1538. continue;
  1539. ap = host->ports[i];
  1540. if (ap) {
  1541. ahci_hw_port_interrupt(ap);
  1542. VPRINTK("port %u\n", i);
  1543. } else {
  1544. VPRINTK("port %u (no irq)\n", i);
  1545. if (ata_ratelimit())
  1546. dev_warn(host->dev,
  1547. "interrupt on disabled port %u\n", i);
  1548. }
  1549. }
  1550. writel(irq_stat, mmio + HOST_IRQ_STAT);
  1551. spin_unlock(&host->lock);
  1552. VPRINTK("EXIT\n");
  1553. return IRQ_WAKE_THREAD;
  1554. }
  1555. EXPORT_SYMBOL_GPL(ahci_hw_interrupt);
  1556. irqreturn_t ahci_interrupt(int irq, void *dev_instance)
  1557. {
  1558. struct ata_host *host = dev_instance;
  1559. struct ahci_host_priv *hpriv;
  1560. unsigned int i, handled = 0;
  1561. void __iomem *mmio;
  1562. u32 irq_stat, irq_masked;
  1563. VPRINTK("ENTER\n");
  1564. hpriv = host->private_data;
  1565. mmio = hpriv->mmio;
  1566. /* sigh. 0xffffffff is a valid return from h/w */
  1567. irq_stat = readl(mmio + HOST_IRQ_STAT);
  1568. if (!irq_stat)
  1569. return IRQ_NONE;
  1570. irq_masked = irq_stat & hpriv->port_map;
  1571. spin_lock(&host->lock);
  1572. for (i = 0; i < host->n_ports; i++) {
  1573. struct ata_port *ap;
  1574. if (!(irq_masked & (1 << i)))
  1575. continue;
  1576. ap = host->ports[i];
  1577. if (ap) {
  1578. ahci_port_intr(ap);
  1579. VPRINTK("port %u\n", i);
  1580. } else {
  1581. VPRINTK("port %u (no irq)\n", i);
  1582. if (ata_ratelimit())
  1583. dev_warn(host->dev,
  1584. "interrupt on disabled port %u\n", i);
  1585. }
  1586. handled = 1;
  1587. }
  1588. /* HOST_IRQ_STAT behaves as level triggered latch meaning that
  1589. * it should be cleared after all the port events are cleared;
  1590. * otherwise, it will raise a spurious interrupt after each
  1591. * valid one. Please read section 10.6.2 of ahci 1.1 for more
  1592. * information.
  1593. *
  1594. * Also, use the unmasked value to clear interrupt as spurious
  1595. * pending event on a dummy port might cause screaming IRQ.
  1596. */
  1597. writel(irq_stat, mmio + HOST_IRQ_STAT);
  1598. spin_unlock(&host->lock);
  1599. VPRINTK("EXIT\n");
  1600. return IRQ_RETVAL(handled);
  1601. }
  1602. EXPORT_SYMBOL_GPL(ahci_interrupt);
  1603. static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
  1604. {
  1605. struct ata_port *ap = qc->ap;
  1606. void __iomem *port_mmio = ahci_port_base(ap);
  1607. struct ahci_port_priv *pp = ap->private_data;
  1608. /* Keep track of the currently active link. It will be used
  1609. * in completion path to determine whether NCQ phase is in
  1610. * progress.
  1611. */
  1612. pp->active_link = qc->dev->link;
  1613. if (qc->tf.protocol == ATA_PROT_NCQ)
  1614. writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
  1615. if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
  1616. u32 fbs = readl(port_mmio + PORT_FBS);
  1617. fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
  1618. fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
  1619. writel(fbs, port_mmio + PORT_FBS);
  1620. pp->fbs_last_dev = qc->dev->link->pmp;
  1621. }
  1622. writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
  1623. ahci_sw_activity(qc->dev->link);
  1624. return 0;
  1625. }
  1626. static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
  1627. {
  1628. struct ahci_port_priv *pp = qc->ap->private_data;
  1629. u8 *rx_fis = pp->rx_fis;
  1630. if (pp->fbs_enabled)
  1631. rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
  1632. /*
  1633. * After a successful execution of an ATA PIO data-in command,
  1634. * the device doesn't send D2H Reg FIS to update the TF and
  1635. * the host should take TF and E_Status from the preceding PIO
  1636. * Setup FIS.
  1637. */
  1638. if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
  1639. !(qc->flags & ATA_QCFLAG_FAILED)) {
  1640. ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
  1641. qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
  1642. } else
  1643. ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
  1644. return true;
  1645. }
  1646. static void ahci_freeze(struct ata_port *ap)
  1647. {
  1648. void __iomem *port_mmio = ahci_port_base(ap);
  1649. /* turn IRQ off */
  1650. writel(0, port_mmio + PORT_IRQ_MASK);
  1651. }
  1652. static void ahci_thaw(struct ata_port *ap)
  1653. {
  1654. struct ahci_host_priv *hpriv = ap->host->private_data;
  1655. void __iomem *mmio = hpriv->mmio;
  1656. void __iomem *port_mmio = ahci_port_base(ap);
  1657. u32 tmp;
  1658. struct ahci_port_priv *pp = ap->private_data;
  1659. /* clear IRQ */
  1660. tmp = readl(port_mmio + PORT_IRQ_STAT);
  1661. writel(tmp, port_mmio + PORT_IRQ_STAT);
  1662. writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
  1663. /* turn IRQ back on */
  1664. writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
  1665. }
  1666. void ahci_error_handler(struct ata_port *ap)
  1667. {
  1668. if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
  1669. /* restart engine */
  1670. ahci_stop_engine(ap);
  1671. ahci_start_engine(ap);
  1672. }
  1673. sata_pmp_error_handler(ap);
  1674. if (!ata_dev_enabled(ap->link.device))
  1675. ahci_stop_engine(ap);
  1676. }
  1677. EXPORT_SYMBOL_GPL(ahci_error_handler);
  1678. static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
  1679. {
  1680. struct ata_port *ap = qc->ap;
  1681. /* make DMA engine forget about the failed command */
  1682. if (qc->flags & ATA_QCFLAG_FAILED)
  1683. ahci_kick_engine(ap);
  1684. }
  1685. static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
  1686. {
  1687. void __iomem *port_mmio = ahci_port_base(ap);
  1688. struct ata_device *dev = ap->link.device;
  1689. u32 devslp, dm, dito, mdat, deto;
  1690. int rc;
  1691. unsigned int err_mask;
  1692. devslp = readl(port_mmio + PORT_DEVSLP);
  1693. if (!(devslp & PORT_DEVSLP_DSP)) {
  1694. dev_err(ap->host->dev, "port does not support device sleep\n");
  1695. return;
  1696. }
  1697. /* disable device sleep */
  1698. if (!sleep) {
  1699. if (devslp & PORT_DEVSLP_ADSE) {
  1700. writel(devslp & ~PORT_DEVSLP_ADSE,
  1701. port_mmio + PORT_DEVSLP);
  1702. err_mask = ata_dev_set_feature(dev,
  1703. SETFEATURES_SATA_DISABLE,
  1704. SATA_DEVSLP);
  1705. if (err_mask && err_mask != AC_ERR_DEV)
  1706. ata_dev_warn(dev, "failed to disable DEVSLP\n");
  1707. }
  1708. return;
  1709. }
  1710. /* device sleep was already enabled */
  1711. if (devslp & PORT_DEVSLP_ADSE)
  1712. return;
  1713. /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
  1714. rc = ahci_stop_engine(ap);
  1715. if (rc)
  1716. return;
  1717. dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
  1718. dito = devslp_idle_timeout / (dm + 1);
  1719. if (dito > 0x3ff)
  1720. dito = 0x3ff;
  1721. /* Use the nominal value 10 ms if the read MDAT is zero,
  1722. * the nominal value of DETO is 20 ms.
  1723. */
  1724. if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
  1725. ATA_LOG_DEVSLP_VALID_MASK) {
  1726. mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
  1727. ATA_LOG_DEVSLP_MDAT_MASK;
  1728. if (!mdat)
  1729. mdat = 10;
  1730. deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
  1731. if (!deto)
  1732. deto = 20;
  1733. } else {
  1734. mdat = 10;
  1735. deto = 20;
  1736. }
  1737. devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
  1738. (mdat << PORT_DEVSLP_MDAT_OFFSET) |
  1739. (deto << PORT_DEVSLP_DETO_OFFSET) |
  1740. PORT_DEVSLP_ADSE);
  1741. writel(devslp, port_mmio + PORT_DEVSLP);
  1742. ahci_start_engine(ap);
  1743. /* enable device sleep feature for the drive */
  1744. err_mask = ata_dev_set_feature(dev,
  1745. SETFEATURES_SATA_ENABLE,
  1746. SATA_DEVSLP);
  1747. if (err_mask && err_mask != AC_ERR_DEV)
  1748. ata_dev_warn(dev, "failed to enable DEVSLP\n");
  1749. }
  1750. static void ahci_enable_fbs(struct ata_port *ap)
  1751. {
  1752. struct ahci_port_priv *pp = ap->private_data;
  1753. void __iomem *port_mmio = ahci_port_base(ap);
  1754. u32 fbs;
  1755. int rc;
  1756. if (!pp->fbs_supported)
  1757. return;
  1758. fbs = readl(port_mmio + PORT_FBS);
  1759. if (fbs & PORT_FBS_EN) {
  1760. pp->fbs_enabled = true;
  1761. pp->fbs_last_dev = -1; /* initialization */
  1762. return;
  1763. }
  1764. rc = ahci_stop_engine(ap);
  1765. if (rc)
  1766. return;
  1767. writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
  1768. fbs = readl(port_mmio + PORT_FBS);
  1769. if (fbs & PORT_FBS_EN) {
  1770. dev_info(ap->host->dev, "FBS is enabled\n");
  1771. pp->fbs_enabled = true;
  1772. pp->fbs_last_dev = -1; /* initialization */
  1773. } else
  1774. dev_err(ap->host->dev, "Failed to enable FBS\n");
  1775. ahci_start_engine(ap);
  1776. }
  1777. static void ahci_disable_fbs(struct ata_port *ap)
  1778. {
  1779. struct ahci_port_priv *pp = ap->private_data;
  1780. void __iomem *port_mmio = ahci_port_base(ap);
  1781. u32 fbs;
  1782. int rc;
  1783. if (!pp->fbs_supported)
  1784. return;
  1785. fbs = readl(port_mmio + PORT_FBS);
  1786. if ((fbs & PORT_FBS_EN) == 0) {
  1787. pp->fbs_enabled = false;
  1788. return;
  1789. }
  1790. rc = ahci_stop_engine(ap);
  1791. if (rc)
  1792. return;
  1793. writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
  1794. fbs = readl(port_mmio + PORT_FBS);
  1795. if (fbs & PORT_FBS_EN)
  1796. dev_err(ap->host->dev, "Failed to disable FBS\n");
  1797. else {
  1798. dev_info(ap->host->dev, "FBS is disabled\n");
  1799. pp->fbs_enabled = false;
  1800. }
  1801. ahci_start_engine(ap);
  1802. }
  1803. static void ahci_pmp_attach(struct ata_port *ap)
  1804. {
  1805. void __iomem *port_mmio = ahci_port_base(ap);
  1806. struct ahci_port_priv *pp = ap->private_data;
  1807. u32 cmd;
  1808. cmd = readl(port_mmio + PORT_CMD);
  1809. cmd |= PORT_CMD_PMP;
  1810. writel(cmd, port_mmio + PORT_CMD);
  1811. ahci_enable_fbs(ap);
  1812. pp->intr_mask |= PORT_IRQ_BAD_PMP;
  1813. /*
  1814. * We must not change the port interrupt mask register if the
  1815. * port is marked frozen, the value in pp->intr_mask will be
  1816. * restored later when the port is thawed.
  1817. *
  1818. * Note that during initialization, the port is marked as
  1819. * frozen since the irq handler is not yet registered.
  1820. */
  1821. if (!(ap->pflags & ATA_PFLAG_FROZEN))
  1822. writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
  1823. }
  1824. static void ahci_pmp_detach(struct ata_port *ap)
  1825. {
  1826. void __iomem *port_mmio = ahci_port_base(ap);
  1827. struct ahci_port_priv *pp = ap->private_data;
  1828. u32 cmd;
  1829. ahci_disable_fbs(ap);
  1830. cmd = readl(port_mmio + PORT_CMD);
  1831. cmd &= ~PORT_CMD_PMP;
  1832. writel(cmd, port_mmio + PORT_CMD);
  1833. pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
  1834. /* see comment above in ahci_pmp_attach() */
  1835. if (!(ap->pflags & ATA_PFLAG_FROZEN))
  1836. writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
  1837. }
  1838. int ahci_port_resume(struct ata_port *ap)
  1839. {
  1840. ahci_power_up(ap);
  1841. ahci_start_port(ap);
  1842. if (sata_pmp_attached(ap))
  1843. ahci_pmp_attach(ap);
  1844. else
  1845. ahci_pmp_detach(ap);
  1846. return 0;
  1847. }
  1848. EXPORT_SYMBOL_GPL(ahci_port_resume);
  1849. #ifdef CONFIG_PM
  1850. static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
  1851. {
  1852. const char *emsg = NULL;
  1853. int rc;
  1854. rc = ahci_deinit_port(ap, &emsg);
  1855. if (rc == 0)
  1856. ahci_power_down(ap);
  1857. else {
  1858. ata_port_err(ap, "%s (%d)\n", emsg, rc);
  1859. ata_port_freeze(ap);
  1860. }
  1861. return rc;
  1862. }
  1863. #endif
  1864. static int ahci_port_start(struct ata_port *ap)
  1865. {
  1866. struct ahci_host_priv *hpriv = ap->host->private_data;
  1867. struct device *dev = ap->host->dev;
  1868. struct ahci_port_priv *pp;
  1869. void *mem;
  1870. dma_addr_t mem_dma;
  1871. size_t dma_sz, rx_fis_sz;
  1872. pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
  1873. if (!pp)
  1874. return -ENOMEM;
  1875. if (ap->host->n_ports > 1) {
  1876. pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
  1877. if (!pp->irq_desc) {
  1878. devm_kfree(dev, pp);
  1879. return -ENOMEM;
  1880. }
  1881. snprintf(pp->irq_desc, 8,
  1882. "%s%d", dev_driver_string(dev), ap->port_no);
  1883. }
  1884. /* check FBS capability */
  1885. if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
  1886. void __iomem *port_mmio = ahci_port_base(ap);
  1887. u32 cmd = readl(port_mmio + PORT_CMD);
  1888. if (cmd & PORT_CMD_FBSCP)
  1889. pp->fbs_supported = true;
  1890. else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
  1891. dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
  1892. ap->port_no);
  1893. pp->fbs_supported = true;
  1894. } else
  1895. dev_warn(dev, "port %d is not capable of FBS\n",
  1896. ap->port_no);
  1897. }
  1898. if (pp->fbs_supported) {
  1899. dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
  1900. rx_fis_sz = AHCI_RX_FIS_SZ * 16;
  1901. } else {
  1902. dma_sz = AHCI_PORT_PRIV_DMA_SZ;
  1903. rx_fis_sz = AHCI_RX_FIS_SZ;
  1904. }
  1905. mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
  1906. if (!mem)
  1907. return -ENOMEM;
  1908. memset(mem, 0, dma_sz);
  1909. /*
  1910. * First item in chunk of DMA memory: 32-slot command table,
  1911. * 32 bytes each in size
  1912. */
  1913. pp->cmd_slot = mem;
  1914. pp->cmd_slot_dma = mem_dma;
  1915. mem += AHCI_CMD_SLOT_SZ;
  1916. mem_dma += AHCI_CMD_SLOT_SZ;
  1917. /*
  1918. * Second item: Received-FIS area
  1919. */
  1920. pp->rx_fis = mem;
  1921. pp->rx_fis_dma = mem_dma;
  1922. mem += rx_fis_sz;
  1923. mem_dma += rx_fis_sz;
  1924. /*
  1925. * Third item: data area for storing a single command
  1926. * and its scatter-gather table
  1927. */
  1928. pp->cmd_tbl = mem;
  1929. pp->cmd_tbl_dma = mem_dma;
  1930. /*
  1931. * Save off initial list of interrupts to be enabled.
  1932. * This could be changed later
  1933. */
  1934. pp->intr_mask = DEF_PORT_IRQ;
  1935. /*
  1936. * Switch to per-port locking in case each port has its own MSI vector.
  1937. */
  1938. if ((hpriv->flags & AHCI_HFLAG_MULTI_MSI)) {
  1939. spin_lock_init(&pp->lock);
  1940. ap->lock = &pp->lock;
  1941. }
  1942. ap->private_data = pp;
  1943. /* engage engines, captain */
  1944. return ahci_port_resume(ap);
  1945. }
  1946. static void ahci_port_stop(struct ata_port *ap)
  1947. {
  1948. const char *emsg = NULL;
  1949. int rc;
  1950. /* de-initialize port */
  1951. rc = ahci_deinit_port(ap, &emsg);
  1952. if (rc)
  1953. ata_port_warn(ap, "%s (%d)\n", emsg, rc);
  1954. }
  1955. void ahci_print_info(struct ata_host *host, const char *scc_s)
  1956. {
  1957. struct ahci_host_priv *hpriv = host->private_data;
  1958. void __iomem *mmio = hpriv->mmio;
  1959. u32 vers, cap, cap2, impl, speed;
  1960. const char *speed_s;
  1961. vers = readl(mmio + HOST_VERSION);
  1962. cap = hpriv->cap;
  1963. cap2 = hpriv->cap2;
  1964. impl = hpriv->port_map;
  1965. speed = (cap >> 20) & 0xf;
  1966. if (speed == 1)
  1967. speed_s = "1.5";
  1968. else if (speed == 2)
  1969. speed_s = "3";
  1970. else if (speed == 3)
  1971. speed_s = "6";
  1972. else
  1973. speed_s = "?";
  1974. dev_info(host->dev,
  1975. "AHCI %02x%02x.%02x%02x "
  1976. "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
  1977. ,
  1978. (vers >> 24) & 0xff,
  1979. (vers >> 16) & 0xff,
  1980. (vers >> 8) & 0xff,
  1981. vers & 0xff,
  1982. ((cap >> 8) & 0x1f) + 1,
  1983. (cap & 0x1f) + 1,
  1984. speed_s,
  1985. impl,
  1986. scc_s);
  1987. dev_info(host->dev,
  1988. "flags: "
  1989. "%s%s%s%s%s%s%s"
  1990. "%s%s%s%s%s%s%s"
  1991. "%s%s%s%s%s%s%s"
  1992. "%s%s\n"
  1993. ,
  1994. cap & HOST_CAP_64 ? "64bit " : "",
  1995. cap & HOST_CAP_NCQ ? "ncq " : "",
  1996. cap & HOST_CAP_SNTF ? "sntf " : "",
  1997. cap & HOST_CAP_MPS ? "ilck " : "",
  1998. cap & HOST_CAP_SSS ? "stag " : "",
  1999. cap & HOST_CAP_ALPM ? "pm " : "",
  2000. cap & HOST_CAP_LED ? "led " : "",
  2001. cap & HOST_CAP_CLO ? "clo " : "",
  2002. cap & HOST_CAP_ONLY ? "only " : "",
  2003. cap & HOST_CAP_PMP ? "pmp " : "",
  2004. cap & HOST_CAP_FBS ? "fbs " : "",
  2005. cap & HOST_CAP_PIO_MULTI ? "pio " : "",
  2006. cap & HOST_CAP_SSC ? "slum " : "",
  2007. cap & HOST_CAP_PART ? "part " : "",
  2008. cap & HOST_CAP_CCC ? "ccc " : "",
  2009. cap & HOST_CAP_EMS ? "ems " : "",
  2010. cap & HOST_CAP_SXS ? "sxs " : "",
  2011. cap2 & HOST_CAP2_DESO ? "deso " : "",
  2012. cap2 & HOST_CAP2_SADM ? "sadm " : "",
  2013. cap2 & HOST_CAP2_SDS ? "sds " : "",
  2014. cap2 & HOST_CAP2_APST ? "apst " : "",
  2015. cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
  2016. cap2 & HOST_CAP2_BOH ? "boh " : ""
  2017. );
  2018. }
  2019. EXPORT_SYMBOL_GPL(ahci_print_info);
  2020. void ahci_set_em_messages(struct ahci_host_priv *hpriv,
  2021. struct ata_port_info *pi)
  2022. {
  2023. u8 messages;
  2024. void __iomem *mmio = hpriv->mmio;
  2025. u32 em_loc = readl(mmio + HOST_EM_LOC);
  2026. u32 em_ctl = readl(mmio + HOST_EM_CTL);
  2027. if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
  2028. return;
  2029. messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
  2030. if (messages) {
  2031. /* store em_loc */
  2032. hpriv->em_loc = ((em_loc >> 16) * 4);
  2033. hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
  2034. hpriv->em_msg_type = messages;
  2035. pi->flags |= ATA_FLAG_EM;
  2036. if (!(em_ctl & EM_CTL_ALHD))
  2037. pi->flags |= ATA_FLAG_SW_ACTIVITY;
  2038. }
  2039. }
  2040. EXPORT_SYMBOL_GPL(ahci_set_em_messages);
  2041. MODULE_AUTHOR("Jeff Garzik");
  2042. MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
  2043. MODULE_LICENSE("GPL");