b4860emu.dts 5.4 KB

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  1. /*
  2. * B4860 emulator Device Tree Source
  3. *
  4. * Copyright 2013 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * This software is provided by Freescale Semiconductor "as is" and any
  24. * express or implied warranties, including, but not limited to, the implied
  25. * warranties of merchantability and fitness for a particular purpose are
  26. * disclaimed. In no event shall Freescale Semiconductor be liable for any
  27. * direct, indirect, incidental, special, exemplary, or consequential damages
  28. * (including, but not limited to, procurement of substitute goods or services;
  29. * loss of use, data, or profits; or business interruption) however caused and
  30. * on any theory of liability, whether in contract, strict liability, or tort
  31. * (including negligence or otherwise) arising in any way out of the use of
  32. * this software, even if advised of the possibility of such damage.
  33. */
  34. /dts-v1/;
  35. /include/ "fsl/e6500_power_isa.dtsi"
  36. / {
  37. compatible = "fsl,B4860";
  38. #address-cells = <2>;
  39. #size-cells = <2>;
  40. interrupt-parent = <&mpic>;
  41. aliases {
  42. ccsr = &soc;
  43. serial0 = &serial0;
  44. serial1 = &serial1;
  45. serial2 = &serial2;
  46. serial3 = &serial3;
  47. dma0 = &dma0;
  48. dma1 = &dma1;
  49. };
  50. cpus {
  51. #address-cells = <1>;
  52. #size-cells = <0>;
  53. cpu0: PowerPC,e6500@0 {
  54. device_type = "cpu";
  55. reg = <0 1>;
  56. next-level-cache = <&L2>;
  57. };
  58. cpu1: PowerPC,e6500@2 {
  59. device_type = "cpu";
  60. reg = <2 3>;
  61. next-level-cache = <&L2>;
  62. };
  63. cpu2: PowerPC,e6500@4 {
  64. device_type = "cpu";
  65. reg = <4 5>;
  66. next-level-cache = <&L2>;
  67. };
  68. cpu3: PowerPC,e6500@6 {
  69. device_type = "cpu";
  70. reg = <6 7>;
  71. next-level-cache = <&L2>;
  72. };
  73. };
  74. };
  75. / {
  76. model = "fsl,B4860QDS";
  77. compatible = "fsl,B4860EMU", "fsl,B4860QDS";
  78. #address-cells = <2>;
  79. #size-cells = <2>;
  80. interrupt-parent = <&mpic>;
  81. ifc: localbus@ffe124000 {
  82. reg = <0xf 0xfe124000 0 0x2000>;
  83. ranges = <0 0 0xf 0xe8000000 0x08000000
  84. 2 0 0xf 0xff800000 0x00010000
  85. 3 0 0xf 0xffdf0000 0x00008000>;
  86. nor@0,0 {
  87. #address-cells = <1>;
  88. #size-cells = <1>;
  89. compatible = "cfi-flash";
  90. reg = <0x0 0x0 0x8000000>;
  91. bank-width = <2>;
  92. device-width = <1>;
  93. };
  94. };
  95. memory {
  96. device_type = "memory";
  97. };
  98. soc: soc@ffe000000 {
  99. ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  100. reg = <0xf 0xfe000000 0 0x00001000>;
  101. };
  102. };
  103. &ifc {
  104. #address-cells = <2>;
  105. #size-cells = <1>;
  106. compatible = "fsl,ifc", "simple-bus";
  107. interrupts = <25 2 0 0>;
  108. };
  109. &soc {
  110. #address-cells = <1>;
  111. #size-cells = <1>;
  112. device_type = "soc";
  113. compatible = "simple-bus";
  114. soc-sram-error {
  115. compatible = "fsl,soc-sram-error";
  116. interrupts = <16 2 1 2>;
  117. };
  118. corenet-law@0 {
  119. compatible = "fsl,corenet-law";
  120. reg = <0x0 0x1000>;
  121. fsl,num-laws = <32>;
  122. };
  123. ddr1: memory-controller@8000 {
  124. compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
  125. reg = <0x8000 0x1000>;
  126. interrupts = <16 2 1 8>;
  127. };
  128. ddr2: memory-controller@9000 {
  129. compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
  130. reg = <0x9000 0x1000>;
  131. interrupts = <16 2 1 9>;
  132. };
  133. cpc: l3-cache-controller@10000 {
  134. compatible = "fsl,b4-l3-cache-controller", "cache";
  135. reg = <0x10000 0x1000
  136. 0x11000 0x1000>;
  137. interrupts = <16 2 1 4>;
  138. };
  139. corenet-cf@18000 {
  140. compatible = "fsl,b4-corenet-cf";
  141. reg = <0x18000 0x1000>;
  142. interrupts = <16 2 1 0>;
  143. fsl,ccf-num-csdids = <32>;
  144. fsl,ccf-num-snoopids = <32>;
  145. };
  146. iommu@20000 {
  147. compatible = "fsl,pamu-v1.0", "fsl,pamu";
  148. reg = <0x20000 0x4000>;
  149. #address-cells = <1>;
  150. #size-cells = <1>;
  151. interrupts = <
  152. 24 2 0 0
  153. 16 2 1 1>;
  154. pamu0: pamu@0 {
  155. reg = <0 0x1000>;
  156. fsl,primary-cache-geometry = <8 1>;
  157. fsl,secondary-cache-geometry = <32 2>;
  158. };
  159. };
  160. /include/ "fsl/qoriq-mpic.dtsi"
  161. guts: global-utilities@e0000 {
  162. compatible = "fsl,b4-device-config";
  163. reg = <0xe0000 0xe00>;
  164. fsl,has-rstcr;
  165. fsl,liodn-bits = <12>;
  166. };
  167. clockgen: global-utilities@e1000 {
  168. compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
  169. reg = <0xe1000 0x1000>;
  170. };
  171. /include/ "fsl/qoriq-dma-0.dtsi"
  172. dma@100300 {
  173. fsl,iommu-parent = <&pamu0>;
  174. fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
  175. };
  176. /include/ "fsl/qoriq-dma-1.dtsi"
  177. dma@101300 {
  178. fsl,iommu-parent = <&pamu0>;
  179. fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
  180. };
  181. /include/ "fsl/qoriq-i2c-0.dtsi"
  182. /include/ "fsl/qoriq-i2c-1.dtsi"
  183. /include/ "fsl/qoriq-duart-0.dtsi"
  184. /include/ "fsl/qoriq-duart-1.dtsi"
  185. L2: l2-cache-controller@c20000 {
  186. compatible = "fsl,b4-l2-cache-controller";
  187. reg = <0xc20000 0x1000>;
  188. next-level-cache = <&cpc>;
  189. };
  190. };