cpu.c 4.6 KB

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  1. /*
  2. * Copyright (C) ST-Ericsson SA 2010
  3. *
  4. * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
  5. * Author: Lee Jones <lee.jones@linaro.org> for ST-Ericsson
  6. * License terms: GNU General Public License (GPL) version 2
  7. */
  8. #include <linux/platform_device.h>
  9. #include <linux/io.h>
  10. #include <linux/mfd/dbx500-prcmu.h>
  11. #include <linux/clksrc-dbx500-prcmu.h>
  12. #include <linux/sys_soc.h>
  13. #include <linux/err.h>
  14. #include <linux/slab.h>
  15. #include <linux/stat.h>
  16. #include <linux/of.h>
  17. #include <linux/of_irq.h>
  18. #include <linux/irq.h>
  19. #include <linux/irqchip.h>
  20. #include <linux/irqchip/arm-gic.h>
  21. #include <linux/platform_data/clk-ux500.h>
  22. #include <linux/platform_data/arm-ux500-pm.h>
  23. #include <asm/mach/map.h>
  24. #include "setup.h"
  25. #include "devices.h"
  26. #include "board-mop500.h"
  27. #include "db8500-regs.h"
  28. #include "id.h"
  29. void ux500_restart(enum reboot_mode mode, const char *cmd)
  30. {
  31. local_irq_disable();
  32. local_fiq_disable();
  33. prcmu_system_reset(0);
  34. }
  35. /*
  36. * FIXME: Should we set up the GPIO domain here?
  37. *
  38. * The problem is that we cannot put the interrupt resources into the platform
  39. * device until the irqdomain has been added. Right now, we set the GIC interrupt
  40. * domain from init_irq(), then load the gpio driver from
  41. * core_initcall(nmk_gpio_init) and add the platform devices from
  42. * arch_initcall(customize_machine).
  43. *
  44. * This feels fragile because it depends on the gpio device getting probed
  45. * _before_ any device uses the gpio interrupts.
  46. */
  47. void __init ux500_init_irq(void)
  48. {
  49. void __iomem *dist_base;
  50. void __iomem *cpu_base;
  51. gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
  52. if (cpu_is_u8500_family() || cpu_is_ux540_family()) {
  53. dist_base = __io_address(U8500_GIC_DIST_BASE);
  54. cpu_base = __io_address(U8500_GIC_CPU_BASE);
  55. } else
  56. ux500_unknown_soc();
  57. #ifdef CONFIG_OF
  58. if (of_have_populated_dt())
  59. irqchip_init();
  60. else
  61. #endif
  62. gic_init(0, 29, dist_base, cpu_base);
  63. /*
  64. * Init clocks here so that they are available for system timer
  65. * initialization.
  66. */
  67. if (cpu_is_u8500_family()) {
  68. prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
  69. ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
  70. if (of_have_populated_dt())
  71. u8500_of_clk_init(U8500_CLKRST1_BASE,
  72. U8500_CLKRST2_BASE,
  73. U8500_CLKRST3_BASE,
  74. U8500_CLKRST5_BASE,
  75. U8500_CLKRST6_BASE);
  76. else
  77. u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
  78. U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
  79. U8500_CLKRST6_BASE);
  80. } else if (cpu_is_u9540()) {
  81. prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
  82. ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
  83. u9540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
  84. U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
  85. U8500_CLKRST6_BASE);
  86. } else if (cpu_is_u8540()) {
  87. prcmu_early_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
  88. ux500_pm_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
  89. u8540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
  90. U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
  91. U8500_CLKRST6_BASE);
  92. }
  93. }
  94. static const char * __init ux500_get_machine(void)
  95. {
  96. return kasprintf(GFP_KERNEL, "DB%4x", dbx500_partnumber());
  97. }
  98. static const char * __init ux500_get_family(void)
  99. {
  100. return kasprintf(GFP_KERNEL, "ux500");
  101. }
  102. static const char * __init ux500_get_revision(void)
  103. {
  104. unsigned int rev = dbx500_revision();
  105. if (rev == 0x01)
  106. return kasprintf(GFP_KERNEL, "%s", "ED");
  107. else if (rev >= 0xA0)
  108. return kasprintf(GFP_KERNEL, "%d.%d",
  109. (rev >> 4) - 0xA + 1, rev & 0xf);
  110. return kasprintf(GFP_KERNEL, "%s", "Unknown");
  111. }
  112. static ssize_t ux500_get_process(struct device *dev,
  113. struct device_attribute *attr,
  114. char *buf)
  115. {
  116. if (dbx500_id.process == 0x00)
  117. return sprintf(buf, "Standard\n");
  118. return sprintf(buf, "%02xnm\n", dbx500_id.process);
  119. }
  120. static void __init soc_info_populate(struct soc_device_attribute *soc_dev_attr,
  121. const char *soc_id)
  122. {
  123. soc_dev_attr->soc_id = soc_id;
  124. soc_dev_attr->machine = ux500_get_machine();
  125. soc_dev_attr->family = ux500_get_family();
  126. soc_dev_attr->revision = ux500_get_revision();
  127. }
  128. struct device_attribute ux500_soc_attr =
  129. __ATTR(process, S_IRUGO, ux500_get_process, NULL);
  130. struct device * __init ux500_soc_device_init(const char *soc_id)
  131. {
  132. struct device *parent;
  133. struct soc_device *soc_dev;
  134. struct soc_device_attribute *soc_dev_attr;
  135. soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
  136. if (!soc_dev_attr)
  137. return ERR_PTR(-ENOMEM);
  138. soc_info_populate(soc_dev_attr, soc_id);
  139. soc_dev = soc_device_register(soc_dev_attr);
  140. if (IS_ERR(soc_dev)) {
  141. kfree(soc_dev_attr);
  142. return NULL;
  143. }
  144. parent = soc_device_to_device(soc_dev);
  145. device_create_file(parent, &ux500_soc_attr);
  146. return parent;
  147. }