platsmp-apmu.c 4.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195
  1. /*
  2. * SMP support for SoCs with APMU
  3. *
  4. * Copyright (C) 2013 Magnus Damm
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/init.h>
  12. #include <linux/io.h>
  13. #include <linux/ioport.h>
  14. #include <linux/of_address.h>
  15. #include <linux/smp.h>
  16. #include <asm/cacheflush.h>
  17. #include <asm/cp15.h>
  18. #include <asm/smp_plat.h>
  19. #include <mach/common.h>
  20. static struct {
  21. void __iomem *iomem;
  22. int bit;
  23. } apmu_cpus[CONFIG_NR_CPUS];
  24. #define WUPCR_OFFS 0x10
  25. #define PSTR_OFFS 0x40
  26. #define CPUNCR_OFFS(n) (0x100 + (0x10 * (n)))
  27. static int apmu_power_on(void __iomem *p, int bit)
  28. {
  29. /* request power on */
  30. writel_relaxed(BIT(bit), p + WUPCR_OFFS);
  31. /* wait for APMU to finish */
  32. while (readl_relaxed(p + WUPCR_OFFS) != 0)
  33. ;
  34. return 0;
  35. }
  36. static int apmu_power_off(void __iomem *p, int bit)
  37. {
  38. /* request Core Standby for next WFI */
  39. writel_relaxed(3, p + CPUNCR_OFFS(bit));
  40. return 0;
  41. }
  42. static int apmu_power_off_poll(void __iomem *p, int bit)
  43. {
  44. int k;
  45. for (k = 0; k < 1000; k++) {
  46. if (((readl_relaxed(p + PSTR_OFFS) >> (bit * 4)) & 0x03) == 3)
  47. return 1;
  48. mdelay(1);
  49. }
  50. return 0;
  51. }
  52. static int apmu_wrap(int cpu, int (*fn)(void __iomem *p, int cpu))
  53. {
  54. void __iomem *p = apmu_cpus[cpu].iomem;
  55. return p ? fn(p, apmu_cpus[cpu].bit) : -EINVAL;
  56. }
  57. static void apmu_init_cpu(struct resource *res, int cpu, int bit)
  58. {
  59. if (apmu_cpus[cpu].iomem)
  60. return;
  61. apmu_cpus[cpu].iomem = ioremap_nocache(res->start, resource_size(res));
  62. apmu_cpus[cpu].bit = bit;
  63. pr_debug("apmu ioremap %d %d 0x%08x 0x%08x\n", cpu, bit,
  64. res->start, resource_size(res));
  65. }
  66. static struct {
  67. struct resource iomem;
  68. int cpus[4];
  69. } apmu_config[] = {
  70. {
  71. .iomem = DEFINE_RES_MEM(0xe6152000, 0x88),
  72. .cpus = { 0, 1, 2, 3 },
  73. },
  74. {
  75. .iomem = DEFINE_RES_MEM(0xe6151000, 0x88),
  76. .cpus = { 0x100, 0x101, 0x102, 0x103 },
  77. }
  78. };
  79. static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit))
  80. {
  81. u32 id;
  82. int k;
  83. int bit, index;
  84. bool is_allowed;
  85. for (k = 0; k < ARRAY_SIZE(apmu_config); k++) {
  86. /* only enable the cluster that includes the boot CPU */
  87. is_allowed = false;
  88. for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) {
  89. id = apmu_config[k].cpus[bit];
  90. if (id >= 0) {
  91. if (id == cpu_logical_map(0))
  92. is_allowed = true;
  93. }
  94. }
  95. if (!is_allowed)
  96. continue;
  97. for (bit = 0; bit < ARRAY_SIZE(apmu_config[k].cpus); bit++) {
  98. id = apmu_config[k].cpus[bit];
  99. if (id >= 0) {
  100. index = get_logical_index(id);
  101. if (index >= 0)
  102. fn(&apmu_config[k].iomem, index, bit);
  103. }
  104. }
  105. }
  106. }
  107. void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus)
  108. {
  109. /* install boot code shared by all CPUs */
  110. shmobile_boot_fn = virt_to_phys(shmobile_smp_boot);
  111. shmobile_boot_arg = MPIDR_HWID_BITMASK;
  112. /* perform per-cpu setup */
  113. apmu_parse_cfg(apmu_init_cpu);
  114. }
  115. int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
  116. {
  117. /* For this particular CPU register boot vector */
  118. shmobile_smp_hook(cpu, virt_to_phys(shmobile_invalidate_start), 0);
  119. return apmu_wrap(cpu, apmu_power_on);
  120. }
  121. #ifdef CONFIG_HOTPLUG_CPU
  122. /* nicked from arch/arm/mach-exynos/hotplug.c */
  123. static inline void cpu_enter_lowpower_a15(void)
  124. {
  125. unsigned int v;
  126. asm volatile(
  127. " mrc p15, 0, %0, c1, c0, 0\n"
  128. " bic %0, %0, %1\n"
  129. " mcr p15, 0, %0, c1, c0, 0\n"
  130. : "=&r" (v)
  131. : "Ir" (CR_C)
  132. : "cc");
  133. flush_cache_louis();
  134. asm volatile(
  135. /*
  136. * Turn off coherency
  137. */
  138. " mrc p15, 0, %0, c1, c0, 1\n"
  139. " bic %0, %0, %1\n"
  140. " mcr p15, 0, %0, c1, c0, 1\n"
  141. : "=&r" (v)
  142. : "Ir" (0x40)
  143. : "cc");
  144. isb();
  145. dsb();
  146. }
  147. void shmobile_smp_apmu_cpu_die(unsigned int cpu)
  148. {
  149. /* For this particular CPU deregister boot vector */
  150. shmobile_smp_hook(cpu, 0, 0);
  151. /* Select next sleep mode using the APMU */
  152. apmu_wrap(cpu, apmu_power_off);
  153. /* Do ARM specific CPU shutdown */
  154. cpu_enter_lowpower_a15();
  155. /* jump to shared mach-shmobile sleep / reset code */
  156. shmobile_smp_sleep();
  157. }
  158. int shmobile_smp_apmu_cpu_kill(unsigned int cpu)
  159. {
  160. return apmu_wrap(cpu, apmu_power_off_poll);
  161. }
  162. #endif