devices-da8xx.c 25 KB

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  1. /*
  2. * DA8XX/OMAP L1XX platform device data
  3. *
  4. * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
  5. * Derived from code that was:
  6. * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #include <linux/init.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/dma-contiguous.h>
  16. #include <linux/serial_8250.h>
  17. #include <linux/ahci_platform.h>
  18. #include <linux/clk.h>
  19. #include <linux/reboot.h>
  20. #include <mach/cputype.h>
  21. #include <mach/common.h>
  22. #include <mach/time.h>
  23. #include <mach/da8xx.h>
  24. #include <mach/cpuidle.h>
  25. #include <mach/sram.h>
  26. #include "clock.h"
  27. #include "asp.h"
  28. #define DA8XX_TPCC_BASE 0x01c00000
  29. #define DA8XX_TPTC0_BASE 0x01c08000
  30. #define DA8XX_TPTC1_BASE 0x01c08400
  31. #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
  32. #define DA8XX_I2C0_BASE 0x01c22000
  33. #define DA8XX_RTC_BASE 0x01c23000
  34. #define DA8XX_PRUSS_MEM_BASE 0x01c30000
  35. #define DA8XX_MMCSD0_BASE 0x01c40000
  36. #define DA8XX_SPI0_BASE 0x01c41000
  37. #define DA830_SPI1_BASE 0x01e12000
  38. #define DA8XX_LCD_CNTRL_BASE 0x01e13000
  39. #define DA850_SATA_BASE 0x01e18000
  40. #define DA850_MMCSD1_BASE 0x01e1b000
  41. #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
  42. #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
  43. #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
  44. #define DA8XX_EMAC_MDIO_BASE 0x01e24000
  45. #define DA8XX_I2C1_BASE 0x01e28000
  46. #define DA850_TPCC1_BASE 0x01e30000
  47. #define DA850_TPTC2_BASE 0x01e38000
  48. #define DA850_SPI1_BASE 0x01f0e000
  49. #define DA8XX_DDR2_CTL_BASE 0xb0000000
  50. #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
  51. #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
  52. #define DA8XX_EMAC_RAM_OFFSET 0x0000
  53. #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
  54. #define DA8XX_DMA_SPI0_RX EDMA_CTLR_CHAN(0, 14)
  55. #define DA8XX_DMA_SPI0_TX EDMA_CTLR_CHAN(0, 15)
  56. #define DA8XX_DMA_MMCSD0_RX EDMA_CTLR_CHAN(0, 16)
  57. #define DA8XX_DMA_MMCSD0_TX EDMA_CTLR_CHAN(0, 17)
  58. #define DA8XX_DMA_SPI1_RX EDMA_CTLR_CHAN(0, 18)
  59. #define DA8XX_DMA_SPI1_TX EDMA_CTLR_CHAN(0, 19)
  60. #define DA850_DMA_MMCSD1_RX EDMA_CTLR_CHAN(1, 28)
  61. #define DA850_DMA_MMCSD1_TX EDMA_CTLR_CHAN(1, 29)
  62. void __iomem *da8xx_syscfg0_base;
  63. void __iomem *da8xx_syscfg1_base;
  64. static struct plat_serial8250_port da8xx_serial0_pdata[] = {
  65. {
  66. .mapbase = DA8XX_UART0_BASE,
  67. .irq = IRQ_DA8XX_UARTINT0,
  68. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  69. UPF_IOREMAP,
  70. .iotype = UPIO_MEM,
  71. .regshift = 2,
  72. },
  73. {
  74. .flags = 0,
  75. }
  76. };
  77. static struct plat_serial8250_port da8xx_serial1_pdata[] = {
  78. {
  79. .mapbase = DA8XX_UART1_BASE,
  80. .irq = IRQ_DA8XX_UARTINT1,
  81. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  82. UPF_IOREMAP,
  83. .iotype = UPIO_MEM,
  84. .regshift = 2,
  85. },
  86. {
  87. .flags = 0,
  88. }
  89. };
  90. static struct plat_serial8250_port da8xx_serial2_pdata[] = {
  91. {
  92. .mapbase = DA8XX_UART2_BASE,
  93. .irq = IRQ_DA8XX_UARTINT2,
  94. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
  95. UPF_IOREMAP,
  96. .iotype = UPIO_MEM,
  97. .regshift = 2,
  98. },
  99. {
  100. .flags = 0,
  101. }
  102. };
  103. struct platform_device da8xx_serial_device[] = {
  104. {
  105. .name = "serial8250",
  106. .id = PLAT8250_DEV_PLATFORM,
  107. .dev = {
  108. .platform_data = da8xx_serial0_pdata,
  109. }
  110. },
  111. {
  112. .name = "serial8250",
  113. .id = PLAT8250_DEV_PLATFORM1,
  114. .dev = {
  115. .platform_data = da8xx_serial1_pdata,
  116. }
  117. },
  118. {
  119. .name = "serial8250",
  120. .id = PLAT8250_DEV_PLATFORM2,
  121. .dev = {
  122. .platform_data = da8xx_serial2_pdata,
  123. }
  124. },
  125. {
  126. }
  127. };
  128. static s8 da8xx_queue_tc_mapping[][2] = {
  129. /* {event queue no, TC no} */
  130. {0, 0},
  131. {1, 1},
  132. {-1, -1}
  133. };
  134. static s8 da8xx_queue_priority_mapping[][2] = {
  135. /* {event queue no, Priority} */
  136. {0, 3},
  137. {1, 7},
  138. {-1, -1}
  139. };
  140. static s8 da850_queue_tc_mapping[][2] = {
  141. /* {event queue no, TC no} */
  142. {0, 0},
  143. {-1, -1}
  144. };
  145. static s8 da850_queue_priority_mapping[][2] = {
  146. /* {event queue no, Priority} */
  147. {0, 3},
  148. {-1, -1}
  149. };
  150. static struct edma_soc_info da830_edma_cc0_info = {
  151. .n_channel = 32,
  152. .n_region = 4,
  153. .n_slot = 128,
  154. .n_tc = 2,
  155. .n_cc = 1,
  156. .queue_tc_mapping = da8xx_queue_tc_mapping,
  157. .queue_priority_mapping = da8xx_queue_priority_mapping,
  158. .default_queue = EVENTQ_1,
  159. };
  160. static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
  161. &da830_edma_cc0_info,
  162. };
  163. static struct edma_soc_info da850_edma_cc_info[] = {
  164. {
  165. .n_channel = 32,
  166. .n_region = 4,
  167. .n_slot = 128,
  168. .n_tc = 2,
  169. .n_cc = 1,
  170. .queue_tc_mapping = da8xx_queue_tc_mapping,
  171. .queue_priority_mapping = da8xx_queue_priority_mapping,
  172. .default_queue = EVENTQ_1,
  173. },
  174. {
  175. .n_channel = 32,
  176. .n_region = 4,
  177. .n_slot = 128,
  178. .n_tc = 1,
  179. .n_cc = 1,
  180. .queue_tc_mapping = da850_queue_tc_mapping,
  181. .queue_priority_mapping = da850_queue_priority_mapping,
  182. .default_queue = EVENTQ_0,
  183. },
  184. };
  185. static struct edma_soc_info *da850_edma_info[EDMA_MAX_CC] = {
  186. &da850_edma_cc_info[0],
  187. &da850_edma_cc_info[1],
  188. };
  189. static struct resource da830_edma_resources[] = {
  190. {
  191. .name = "edma_cc0",
  192. .start = DA8XX_TPCC_BASE,
  193. .end = DA8XX_TPCC_BASE + SZ_32K - 1,
  194. .flags = IORESOURCE_MEM,
  195. },
  196. {
  197. .name = "edma_tc0",
  198. .start = DA8XX_TPTC0_BASE,
  199. .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
  200. .flags = IORESOURCE_MEM,
  201. },
  202. {
  203. .name = "edma_tc1",
  204. .start = DA8XX_TPTC1_BASE,
  205. .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
  206. .flags = IORESOURCE_MEM,
  207. },
  208. {
  209. .name = "edma0",
  210. .start = IRQ_DA8XX_CCINT0,
  211. .flags = IORESOURCE_IRQ,
  212. },
  213. {
  214. .name = "edma0_err",
  215. .start = IRQ_DA8XX_CCERRINT,
  216. .flags = IORESOURCE_IRQ,
  217. },
  218. };
  219. static struct resource da850_edma_resources[] = {
  220. {
  221. .name = "edma_cc0",
  222. .start = DA8XX_TPCC_BASE,
  223. .end = DA8XX_TPCC_BASE + SZ_32K - 1,
  224. .flags = IORESOURCE_MEM,
  225. },
  226. {
  227. .name = "edma_tc0",
  228. .start = DA8XX_TPTC0_BASE,
  229. .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
  230. .flags = IORESOURCE_MEM,
  231. },
  232. {
  233. .name = "edma_tc1",
  234. .start = DA8XX_TPTC1_BASE,
  235. .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
  236. .flags = IORESOURCE_MEM,
  237. },
  238. {
  239. .name = "edma_cc1",
  240. .start = DA850_TPCC1_BASE,
  241. .end = DA850_TPCC1_BASE + SZ_32K - 1,
  242. .flags = IORESOURCE_MEM,
  243. },
  244. {
  245. .name = "edma_tc2",
  246. .start = DA850_TPTC2_BASE,
  247. .end = DA850_TPTC2_BASE + SZ_1K - 1,
  248. .flags = IORESOURCE_MEM,
  249. },
  250. {
  251. .name = "edma0",
  252. .start = IRQ_DA8XX_CCINT0,
  253. .flags = IORESOURCE_IRQ,
  254. },
  255. {
  256. .name = "edma0_err",
  257. .start = IRQ_DA8XX_CCERRINT,
  258. .flags = IORESOURCE_IRQ,
  259. },
  260. {
  261. .name = "edma1",
  262. .start = IRQ_DA850_CCINT1,
  263. .flags = IORESOURCE_IRQ,
  264. },
  265. {
  266. .name = "edma1_err",
  267. .start = IRQ_DA850_CCERRINT1,
  268. .flags = IORESOURCE_IRQ,
  269. },
  270. };
  271. static struct platform_device da830_edma_device = {
  272. .name = "edma",
  273. .id = -1,
  274. .dev = {
  275. .platform_data = da830_edma_info,
  276. },
  277. .num_resources = ARRAY_SIZE(da830_edma_resources),
  278. .resource = da830_edma_resources,
  279. };
  280. static struct platform_device da850_edma_device = {
  281. .name = "edma",
  282. .id = -1,
  283. .dev = {
  284. .platform_data = da850_edma_info,
  285. },
  286. .num_resources = ARRAY_SIZE(da850_edma_resources),
  287. .resource = da850_edma_resources,
  288. };
  289. int __init da830_register_edma(struct edma_rsv_info *rsv)
  290. {
  291. da830_edma_cc0_info.rsv = rsv;
  292. return platform_device_register(&da830_edma_device);
  293. }
  294. int __init da850_register_edma(struct edma_rsv_info *rsv[2])
  295. {
  296. if (rsv) {
  297. da850_edma_cc_info[0].rsv = rsv[0];
  298. da850_edma_cc_info[1].rsv = rsv[1];
  299. }
  300. return platform_device_register(&da850_edma_device);
  301. }
  302. static struct resource da8xx_i2c_resources0[] = {
  303. {
  304. .start = DA8XX_I2C0_BASE,
  305. .end = DA8XX_I2C0_BASE + SZ_4K - 1,
  306. .flags = IORESOURCE_MEM,
  307. },
  308. {
  309. .start = IRQ_DA8XX_I2CINT0,
  310. .end = IRQ_DA8XX_I2CINT0,
  311. .flags = IORESOURCE_IRQ,
  312. },
  313. };
  314. static struct platform_device da8xx_i2c_device0 = {
  315. .name = "i2c_davinci",
  316. .id = 1,
  317. .num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
  318. .resource = da8xx_i2c_resources0,
  319. };
  320. static struct resource da8xx_i2c_resources1[] = {
  321. {
  322. .start = DA8XX_I2C1_BASE,
  323. .end = DA8XX_I2C1_BASE + SZ_4K - 1,
  324. .flags = IORESOURCE_MEM,
  325. },
  326. {
  327. .start = IRQ_DA8XX_I2CINT1,
  328. .end = IRQ_DA8XX_I2CINT1,
  329. .flags = IORESOURCE_IRQ,
  330. },
  331. };
  332. static struct platform_device da8xx_i2c_device1 = {
  333. .name = "i2c_davinci",
  334. .id = 2,
  335. .num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
  336. .resource = da8xx_i2c_resources1,
  337. };
  338. int __init da8xx_register_i2c(int instance,
  339. struct davinci_i2c_platform_data *pdata)
  340. {
  341. struct platform_device *pdev;
  342. if (instance == 0)
  343. pdev = &da8xx_i2c_device0;
  344. else if (instance == 1)
  345. pdev = &da8xx_i2c_device1;
  346. else
  347. return -EINVAL;
  348. pdev->dev.platform_data = pdata;
  349. return platform_device_register(pdev);
  350. }
  351. static struct resource da8xx_watchdog_resources[] = {
  352. {
  353. .start = DA8XX_WDOG_BASE,
  354. .end = DA8XX_WDOG_BASE + SZ_4K - 1,
  355. .flags = IORESOURCE_MEM,
  356. },
  357. };
  358. static struct platform_device da8xx_wdt_device = {
  359. .name = "watchdog",
  360. .id = -1,
  361. .num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
  362. .resource = da8xx_watchdog_resources,
  363. };
  364. void da8xx_restart(enum reboot_mode mode, const char *cmd)
  365. {
  366. struct device *dev;
  367. dev = bus_find_device_by_name(&platform_bus_type, NULL, "watchdog");
  368. if (!dev) {
  369. pr_err("%s: failed to find watchdog device\n", __func__);
  370. return;
  371. }
  372. davinci_watchdog_reset(to_platform_device(dev));
  373. }
  374. int __init da8xx_register_watchdog(void)
  375. {
  376. return platform_device_register(&da8xx_wdt_device);
  377. }
  378. static struct resource da8xx_emac_resources[] = {
  379. {
  380. .start = DA8XX_EMAC_CPPI_PORT_BASE,
  381. .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
  382. .flags = IORESOURCE_MEM,
  383. },
  384. {
  385. .start = IRQ_DA8XX_C0_RX_THRESH_PULSE,
  386. .end = IRQ_DA8XX_C0_RX_THRESH_PULSE,
  387. .flags = IORESOURCE_IRQ,
  388. },
  389. {
  390. .start = IRQ_DA8XX_C0_RX_PULSE,
  391. .end = IRQ_DA8XX_C0_RX_PULSE,
  392. .flags = IORESOURCE_IRQ,
  393. },
  394. {
  395. .start = IRQ_DA8XX_C0_TX_PULSE,
  396. .end = IRQ_DA8XX_C0_TX_PULSE,
  397. .flags = IORESOURCE_IRQ,
  398. },
  399. {
  400. .start = IRQ_DA8XX_C0_MISC_PULSE,
  401. .end = IRQ_DA8XX_C0_MISC_PULSE,
  402. .flags = IORESOURCE_IRQ,
  403. },
  404. };
  405. struct emac_platform_data da8xx_emac_pdata = {
  406. .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
  407. .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
  408. .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
  409. .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
  410. .version = EMAC_VERSION_2,
  411. };
  412. static struct platform_device da8xx_emac_device = {
  413. .name = "davinci_emac",
  414. .id = 1,
  415. .dev = {
  416. .platform_data = &da8xx_emac_pdata,
  417. },
  418. .num_resources = ARRAY_SIZE(da8xx_emac_resources),
  419. .resource = da8xx_emac_resources,
  420. };
  421. static struct resource da8xx_mdio_resources[] = {
  422. {
  423. .start = DA8XX_EMAC_MDIO_BASE,
  424. .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
  425. .flags = IORESOURCE_MEM,
  426. },
  427. };
  428. static struct platform_device da8xx_mdio_device = {
  429. .name = "davinci_mdio",
  430. .id = 0,
  431. .num_resources = ARRAY_SIZE(da8xx_mdio_resources),
  432. .resource = da8xx_mdio_resources,
  433. };
  434. int __init da8xx_register_emac(void)
  435. {
  436. int ret;
  437. ret = platform_device_register(&da8xx_mdio_device);
  438. if (ret < 0)
  439. return ret;
  440. return platform_device_register(&da8xx_emac_device);
  441. }
  442. static struct resource da830_mcasp1_resources[] = {
  443. {
  444. .name = "mcasp1",
  445. .start = DAVINCI_DA830_MCASP1_REG_BASE,
  446. .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
  447. .flags = IORESOURCE_MEM,
  448. },
  449. /* TX event */
  450. {
  451. .start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
  452. .end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
  453. .flags = IORESOURCE_DMA,
  454. },
  455. /* RX event */
  456. {
  457. .start = DAVINCI_DA830_DMA_MCASP1_AREVT,
  458. .end = DAVINCI_DA830_DMA_MCASP1_AREVT,
  459. .flags = IORESOURCE_DMA,
  460. },
  461. };
  462. static struct platform_device da830_mcasp1_device = {
  463. .name = "davinci-mcasp",
  464. .id = 1,
  465. .num_resources = ARRAY_SIZE(da830_mcasp1_resources),
  466. .resource = da830_mcasp1_resources,
  467. };
  468. static struct resource da850_mcasp_resources[] = {
  469. {
  470. .name = "mcasp",
  471. .start = DAVINCI_DA8XX_MCASP0_REG_BASE,
  472. .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
  473. .flags = IORESOURCE_MEM,
  474. },
  475. /* TX event */
  476. {
  477. .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
  478. .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
  479. .flags = IORESOURCE_DMA,
  480. },
  481. /* RX event */
  482. {
  483. .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
  484. .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
  485. .flags = IORESOURCE_DMA,
  486. },
  487. };
  488. static struct platform_device da850_mcasp_device = {
  489. .name = "davinci-mcasp",
  490. .id = 0,
  491. .num_resources = ARRAY_SIZE(da850_mcasp_resources),
  492. .resource = da850_mcasp_resources,
  493. };
  494. void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
  495. {
  496. /* DA830/OMAP-L137 has 3 instances of McASP */
  497. if (cpu_is_davinci_da830() && id == 1) {
  498. da830_mcasp1_device.dev.platform_data = pdata;
  499. platform_device_register(&da830_mcasp1_device);
  500. } else if (cpu_is_davinci_da850()) {
  501. da850_mcasp_device.dev.platform_data = pdata;
  502. platform_device_register(&da850_mcasp_device);
  503. }
  504. }
  505. static struct resource da8xx_pruss_resources[] = {
  506. {
  507. .start = DA8XX_PRUSS_MEM_BASE,
  508. .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
  509. .flags = IORESOURCE_MEM,
  510. },
  511. {
  512. .start = IRQ_DA8XX_EVTOUT0,
  513. .end = IRQ_DA8XX_EVTOUT0,
  514. .flags = IORESOURCE_IRQ,
  515. },
  516. {
  517. .start = IRQ_DA8XX_EVTOUT1,
  518. .end = IRQ_DA8XX_EVTOUT1,
  519. .flags = IORESOURCE_IRQ,
  520. },
  521. {
  522. .start = IRQ_DA8XX_EVTOUT2,
  523. .end = IRQ_DA8XX_EVTOUT2,
  524. .flags = IORESOURCE_IRQ,
  525. },
  526. {
  527. .start = IRQ_DA8XX_EVTOUT3,
  528. .end = IRQ_DA8XX_EVTOUT3,
  529. .flags = IORESOURCE_IRQ,
  530. },
  531. {
  532. .start = IRQ_DA8XX_EVTOUT4,
  533. .end = IRQ_DA8XX_EVTOUT4,
  534. .flags = IORESOURCE_IRQ,
  535. },
  536. {
  537. .start = IRQ_DA8XX_EVTOUT5,
  538. .end = IRQ_DA8XX_EVTOUT5,
  539. .flags = IORESOURCE_IRQ,
  540. },
  541. {
  542. .start = IRQ_DA8XX_EVTOUT6,
  543. .end = IRQ_DA8XX_EVTOUT6,
  544. .flags = IORESOURCE_IRQ,
  545. },
  546. {
  547. .start = IRQ_DA8XX_EVTOUT7,
  548. .end = IRQ_DA8XX_EVTOUT7,
  549. .flags = IORESOURCE_IRQ,
  550. },
  551. };
  552. static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
  553. .pintc_base = 0x4000,
  554. };
  555. static struct platform_device da8xx_uio_pruss_dev = {
  556. .name = "pruss_uio",
  557. .id = -1,
  558. .num_resources = ARRAY_SIZE(da8xx_pruss_resources),
  559. .resource = da8xx_pruss_resources,
  560. .dev = {
  561. .coherent_dma_mask = DMA_BIT_MASK(32),
  562. .platform_data = &da8xx_uio_pruss_pdata,
  563. }
  564. };
  565. int __init da8xx_register_uio_pruss(void)
  566. {
  567. da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
  568. return platform_device_register(&da8xx_uio_pruss_dev);
  569. }
  570. static struct lcd_ctrl_config lcd_cfg = {
  571. .panel_shade = COLOR_ACTIVE,
  572. .bpp = 16,
  573. };
  574. struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
  575. .manu_name = "sharp",
  576. .controller_data = &lcd_cfg,
  577. .type = "Sharp_LCD035Q3DG01",
  578. };
  579. struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
  580. .manu_name = "sharp",
  581. .controller_data = &lcd_cfg,
  582. .type = "Sharp_LK043T1DG01",
  583. };
  584. static struct resource da8xx_lcdc_resources[] = {
  585. [0] = { /* registers */
  586. .start = DA8XX_LCD_CNTRL_BASE,
  587. .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
  588. .flags = IORESOURCE_MEM,
  589. },
  590. [1] = { /* interrupt */
  591. .start = IRQ_DA8XX_LCDINT,
  592. .end = IRQ_DA8XX_LCDINT,
  593. .flags = IORESOURCE_IRQ,
  594. },
  595. };
  596. static struct platform_device da8xx_lcdc_device = {
  597. .name = "da8xx_lcdc",
  598. .id = 0,
  599. .num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
  600. .resource = da8xx_lcdc_resources,
  601. };
  602. int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
  603. {
  604. da8xx_lcdc_device.dev.platform_data = pdata;
  605. return platform_device_register(&da8xx_lcdc_device);
  606. }
  607. static struct resource da8xx_gpio_resources[] = {
  608. { /* registers */
  609. .start = DA8XX_GPIO_BASE,
  610. .end = DA8XX_GPIO_BASE + SZ_4K - 1,
  611. .flags = IORESOURCE_MEM,
  612. },
  613. { /* interrupt */
  614. .start = IRQ_DA8XX_GPIO0,
  615. .end = IRQ_DA8XX_GPIO8,
  616. .flags = IORESOURCE_IRQ,
  617. },
  618. };
  619. static struct platform_device da8xx_gpio_device = {
  620. .name = "davinci_gpio",
  621. .id = -1,
  622. .num_resources = ARRAY_SIZE(da8xx_gpio_resources),
  623. .resource = da8xx_gpio_resources,
  624. };
  625. int __init da8xx_register_gpio(void *pdata)
  626. {
  627. da8xx_gpio_device.dev.platform_data = pdata;
  628. return platform_device_register(&da8xx_gpio_device);
  629. }
  630. static struct resource da8xx_mmcsd0_resources[] = {
  631. { /* registers */
  632. .start = DA8XX_MMCSD0_BASE,
  633. .end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
  634. .flags = IORESOURCE_MEM,
  635. },
  636. { /* interrupt */
  637. .start = IRQ_DA8XX_MMCSDINT0,
  638. .end = IRQ_DA8XX_MMCSDINT0,
  639. .flags = IORESOURCE_IRQ,
  640. },
  641. { /* DMA RX */
  642. .start = DA8XX_DMA_MMCSD0_RX,
  643. .end = DA8XX_DMA_MMCSD0_RX,
  644. .flags = IORESOURCE_DMA,
  645. },
  646. { /* DMA TX */
  647. .start = DA8XX_DMA_MMCSD0_TX,
  648. .end = DA8XX_DMA_MMCSD0_TX,
  649. .flags = IORESOURCE_DMA,
  650. },
  651. };
  652. static struct platform_device da8xx_mmcsd0_device = {
  653. .name = "da830-mmc",
  654. .id = 0,
  655. .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
  656. .resource = da8xx_mmcsd0_resources,
  657. };
  658. int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
  659. {
  660. da8xx_mmcsd0_device.dev.platform_data = config;
  661. return platform_device_register(&da8xx_mmcsd0_device);
  662. }
  663. #ifdef CONFIG_ARCH_DAVINCI_DA850
  664. static struct resource da850_mmcsd1_resources[] = {
  665. { /* registers */
  666. .start = DA850_MMCSD1_BASE,
  667. .end = DA850_MMCSD1_BASE + SZ_4K - 1,
  668. .flags = IORESOURCE_MEM,
  669. },
  670. { /* interrupt */
  671. .start = IRQ_DA850_MMCSDINT0_1,
  672. .end = IRQ_DA850_MMCSDINT0_1,
  673. .flags = IORESOURCE_IRQ,
  674. },
  675. { /* DMA RX */
  676. .start = DA850_DMA_MMCSD1_RX,
  677. .end = DA850_DMA_MMCSD1_RX,
  678. .flags = IORESOURCE_DMA,
  679. },
  680. { /* DMA TX */
  681. .start = DA850_DMA_MMCSD1_TX,
  682. .end = DA850_DMA_MMCSD1_TX,
  683. .flags = IORESOURCE_DMA,
  684. },
  685. };
  686. static struct platform_device da850_mmcsd1_device = {
  687. .name = "da830-mmc",
  688. .id = 1,
  689. .num_resources = ARRAY_SIZE(da850_mmcsd1_resources),
  690. .resource = da850_mmcsd1_resources,
  691. };
  692. int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
  693. {
  694. da850_mmcsd1_device.dev.platform_data = config;
  695. return platform_device_register(&da850_mmcsd1_device);
  696. }
  697. #endif
  698. static struct resource da8xx_rproc_resources[] = {
  699. { /* DSP boot address */
  700. .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
  701. .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
  702. .flags = IORESOURCE_MEM,
  703. },
  704. { /* DSP interrupt registers */
  705. .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
  706. .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
  707. .flags = IORESOURCE_MEM,
  708. },
  709. { /* dsp irq */
  710. .start = IRQ_DA8XX_CHIPINT0,
  711. .end = IRQ_DA8XX_CHIPINT0,
  712. .flags = IORESOURCE_IRQ,
  713. },
  714. };
  715. static struct platform_device da8xx_dsp = {
  716. .name = "davinci-rproc",
  717. .dev = {
  718. .coherent_dma_mask = DMA_BIT_MASK(32),
  719. },
  720. .num_resources = ARRAY_SIZE(da8xx_rproc_resources),
  721. .resource = da8xx_rproc_resources,
  722. };
  723. #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
  724. static phys_addr_t rproc_base __initdata;
  725. static unsigned long rproc_size __initdata;
  726. static int __init early_rproc_mem(char *p)
  727. {
  728. char *endp;
  729. if (p == NULL)
  730. return 0;
  731. rproc_size = memparse(p, &endp);
  732. if (*endp == '@')
  733. rproc_base = memparse(endp + 1, NULL);
  734. return 0;
  735. }
  736. early_param("rproc_mem", early_rproc_mem);
  737. void __init da8xx_rproc_reserve_cma(void)
  738. {
  739. int ret;
  740. if (!rproc_base || !rproc_size) {
  741. pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
  742. " 'nn' and 'address' must both be non-zero\n",
  743. __func__);
  744. return;
  745. }
  746. pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
  747. __func__, rproc_size, (unsigned long)rproc_base);
  748. ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0);
  749. if (ret)
  750. pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret);
  751. }
  752. #else
  753. void __init da8xx_rproc_reserve_cma(void)
  754. {
  755. }
  756. #endif
  757. int __init da8xx_register_rproc(void)
  758. {
  759. int ret;
  760. ret = platform_device_register(&da8xx_dsp);
  761. if (ret)
  762. pr_err("%s: can't register DSP device: %d\n", __func__, ret);
  763. return ret;
  764. };
  765. static struct resource da8xx_rtc_resources[] = {
  766. {
  767. .start = DA8XX_RTC_BASE,
  768. .end = DA8XX_RTC_BASE + SZ_4K - 1,
  769. .flags = IORESOURCE_MEM,
  770. },
  771. { /* timer irq */
  772. .start = IRQ_DA8XX_RTC,
  773. .end = IRQ_DA8XX_RTC,
  774. .flags = IORESOURCE_IRQ,
  775. },
  776. { /* alarm irq */
  777. .start = IRQ_DA8XX_RTC,
  778. .end = IRQ_DA8XX_RTC,
  779. .flags = IORESOURCE_IRQ,
  780. },
  781. };
  782. static struct platform_device da8xx_rtc_device = {
  783. .name = "da830-rtc",
  784. .id = -1,
  785. .num_resources = ARRAY_SIZE(da8xx_rtc_resources),
  786. .resource = da8xx_rtc_resources,
  787. };
  788. int da8xx_register_rtc(void)
  789. {
  790. return platform_device_register(&da8xx_rtc_device);
  791. }
  792. static void __iomem *da8xx_ddr2_ctlr_base;
  793. void __iomem * __init da8xx_get_mem_ctlr(void)
  794. {
  795. if (da8xx_ddr2_ctlr_base)
  796. return da8xx_ddr2_ctlr_base;
  797. da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
  798. if (!da8xx_ddr2_ctlr_base)
  799. pr_warn("%s: Unable to map DDR2 controller", __func__);
  800. return da8xx_ddr2_ctlr_base;
  801. }
  802. static struct resource da8xx_cpuidle_resources[] = {
  803. {
  804. .start = DA8XX_DDR2_CTL_BASE,
  805. .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
  806. .flags = IORESOURCE_MEM,
  807. },
  808. };
  809. /* DA8XX devices support DDR2 power down */
  810. static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
  811. .ddr2_pdown = 1,
  812. };
  813. static struct platform_device da8xx_cpuidle_device = {
  814. .name = "cpuidle-davinci",
  815. .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
  816. .resource = da8xx_cpuidle_resources,
  817. .dev = {
  818. .platform_data = &da8xx_cpuidle_pdata,
  819. },
  820. };
  821. int __init da8xx_register_cpuidle(void)
  822. {
  823. da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
  824. return platform_device_register(&da8xx_cpuidle_device);
  825. }
  826. static struct resource da8xx_spi0_resources[] = {
  827. [0] = {
  828. .start = DA8XX_SPI0_BASE,
  829. .end = DA8XX_SPI0_BASE + SZ_4K - 1,
  830. .flags = IORESOURCE_MEM,
  831. },
  832. [1] = {
  833. .start = IRQ_DA8XX_SPINT0,
  834. .end = IRQ_DA8XX_SPINT0,
  835. .flags = IORESOURCE_IRQ,
  836. },
  837. [2] = {
  838. .start = DA8XX_DMA_SPI0_RX,
  839. .end = DA8XX_DMA_SPI0_RX,
  840. .flags = IORESOURCE_DMA,
  841. },
  842. [3] = {
  843. .start = DA8XX_DMA_SPI0_TX,
  844. .end = DA8XX_DMA_SPI0_TX,
  845. .flags = IORESOURCE_DMA,
  846. },
  847. };
  848. static struct resource da8xx_spi1_resources[] = {
  849. [0] = {
  850. .start = DA830_SPI1_BASE,
  851. .end = DA830_SPI1_BASE + SZ_4K - 1,
  852. .flags = IORESOURCE_MEM,
  853. },
  854. [1] = {
  855. .start = IRQ_DA8XX_SPINT1,
  856. .end = IRQ_DA8XX_SPINT1,
  857. .flags = IORESOURCE_IRQ,
  858. },
  859. [2] = {
  860. .start = DA8XX_DMA_SPI1_RX,
  861. .end = DA8XX_DMA_SPI1_RX,
  862. .flags = IORESOURCE_DMA,
  863. },
  864. [3] = {
  865. .start = DA8XX_DMA_SPI1_TX,
  866. .end = DA8XX_DMA_SPI1_TX,
  867. .flags = IORESOURCE_DMA,
  868. },
  869. };
  870. static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
  871. [0] = {
  872. .version = SPI_VERSION_2,
  873. .intr_line = 1,
  874. .dma_event_q = EVENTQ_0,
  875. },
  876. [1] = {
  877. .version = SPI_VERSION_2,
  878. .intr_line = 1,
  879. .dma_event_q = EVENTQ_0,
  880. },
  881. };
  882. static struct platform_device da8xx_spi_device[] = {
  883. [0] = {
  884. .name = "spi_davinci",
  885. .id = 0,
  886. .num_resources = ARRAY_SIZE(da8xx_spi0_resources),
  887. .resource = da8xx_spi0_resources,
  888. .dev = {
  889. .platform_data = &da8xx_spi_pdata[0],
  890. },
  891. },
  892. [1] = {
  893. .name = "spi_davinci",
  894. .id = 1,
  895. .num_resources = ARRAY_SIZE(da8xx_spi1_resources),
  896. .resource = da8xx_spi1_resources,
  897. .dev = {
  898. .platform_data = &da8xx_spi_pdata[1],
  899. },
  900. },
  901. };
  902. int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
  903. {
  904. if (instance < 0 || instance > 1)
  905. return -EINVAL;
  906. da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
  907. if (instance == 1 && cpu_is_davinci_da850()) {
  908. da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
  909. da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
  910. }
  911. return platform_device_register(&da8xx_spi_device[instance]);
  912. }
  913. #ifdef CONFIG_ARCH_DAVINCI_DA850
  914. static struct resource da850_sata_resources[] = {
  915. {
  916. .start = DA850_SATA_BASE,
  917. .end = DA850_SATA_BASE + 0x1fff,
  918. .flags = IORESOURCE_MEM,
  919. },
  920. {
  921. .start = IRQ_DA850_SATAINT,
  922. .flags = IORESOURCE_IRQ,
  923. },
  924. };
  925. /* SATA PHY Control Register offset from AHCI base */
  926. #define SATA_P0PHYCR_REG 0x178
  927. #define SATA_PHY_MPY(x) ((x) << 0)
  928. #define SATA_PHY_LOS(x) ((x) << 6)
  929. #define SATA_PHY_RXCDR(x) ((x) << 10)
  930. #define SATA_PHY_RXEQ(x) ((x) << 13)
  931. #define SATA_PHY_TXSWING(x) ((x) << 19)
  932. #define SATA_PHY_ENPLL(x) ((x) << 31)
  933. static struct clk *da850_sata_clk;
  934. static unsigned long da850_sata_refclkpn;
  935. /* Supported DA850 SATA crystal frequencies */
  936. #define KHZ_TO_HZ(freq) ((freq) * 1000)
  937. static unsigned long da850_sata_xtal[] = {
  938. KHZ_TO_HZ(300000),
  939. KHZ_TO_HZ(250000),
  940. 0, /* Reserved */
  941. KHZ_TO_HZ(187500),
  942. KHZ_TO_HZ(150000),
  943. KHZ_TO_HZ(125000),
  944. KHZ_TO_HZ(120000),
  945. KHZ_TO_HZ(100000),
  946. KHZ_TO_HZ(75000),
  947. KHZ_TO_HZ(60000),
  948. };
  949. static int da850_sata_init(struct device *dev, void __iomem *addr)
  950. {
  951. int i, ret;
  952. unsigned int val;
  953. da850_sata_clk = clk_get(dev, NULL);
  954. if (IS_ERR(da850_sata_clk))
  955. return PTR_ERR(da850_sata_clk);
  956. ret = clk_prepare_enable(da850_sata_clk);
  957. if (ret)
  958. goto err0;
  959. /* Enable SATA clock receiver */
  960. val = __raw_readl(DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
  961. val &= ~BIT(0);
  962. __raw_writel(val, DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
  963. /* Get the multiplier needed for 1.5GHz PLL output */
  964. for (i = 0; i < ARRAY_SIZE(da850_sata_xtal); i++)
  965. if (da850_sata_xtal[i] == da850_sata_refclkpn)
  966. break;
  967. if (i == ARRAY_SIZE(da850_sata_xtal)) {
  968. ret = -EINVAL;
  969. goto err1;
  970. }
  971. val = SATA_PHY_MPY(i + 1) |
  972. SATA_PHY_LOS(1) |
  973. SATA_PHY_RXCDR(4) |
  974. SATA_PHY_RXEQ(1) |
  975. SATA_PHY_TXSWING(3) |
  976. SATA_PHY_ENPLL(1);
  977. __raw_writel(val, addr + SATA_P0PHYCR_REG);
  978. return 0;
  979. err1:
  980. clk_disable_unprepare(da850_sata_clk);
  981. err0:
  982. clk_put(da850_sata_clk);
  983. return ret;
  984. }
  985. static void da850_sata_exit(struct device *dev)
  986. {
  987. clk_disable_unprepare(da850_sata_clk);
  988. clk_put(da850_sata_clk);
  989. }
  990. static struct ahci_platform_data da850_sata_pdata = {
  991. .init = da850_sata_init,
  992. .exit = da850_sata_exit,
  993. };
  994. static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
  995. static struct platform_device da850_sata_device = {
  996. .name = "ahci",
  997. .id = -1,
  998. .dev = {
  999. .platform_data = &da850_sata_pdata,
  1000. .dma_mask = &da850_sata_dmamask,
  1001. .coherent_dma_mask = DMA_BIT_MASK(32),
  1002. },
  1003. .num_resources = ARRAY_SIZE(da850_sata_resources),
  1004. .resource = da850_sata_resources,
  1005. };
  1006. int __init da850_register_sata(unsigned long refclkpn)
  1007. {
  1008. da850_sata_refclkpn = refclkpn;
  1009. if (!da850_sata_refclkpn)
  1010. return -EINVAL;
  1011. return platform_device_register(&da850_sata_device);
  1012. }
  1013. #endif