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mach-at91
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at91_adc.h

at91_adc.h 4.2 KB
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  1. /*
    2. 

  2.  * arch/arm/mach-at91/include/mach/at91_adc.h
    3. 

  3.  *
    4. 

  4.  * Copyright (C) SAN People
    5. 

  5.  *
    6. 

  6.  * Analog-to-Digital Converter (ADC) registers.
    7. 

  7.  * Based on AT91SAM9260 datasheet revision D.
    8. 

  8.  *
    9. 

  9.  * This program is free software; you can redistribute it and/or modify
    10. 

  10.  * it under the terms of the GNU General Public License as published by
    11. 

  11.  * the Free Software Foundation; either version 2 of the License, or
    12. 

  12.  * (at your option) any later version.
    13. 

  13.  */
    14. 

  14. 

  15. #ifndef AT91_ADC_H
    16. 

  16. #define AT91_ADC_H
    17. 

  17. 

  18. #define AT91_ADC_CR		0x00		/* Control Register */
    19. 

  19. #define		AT91_ADC_SWRST		(1 << 0)	/* Software Reset */
    20. 

  20. #define		AT91_ADC_START		(1 << 1)	/* Start Conversion */
    21. 

  21. 

  22. #define AT91_ADC_MR		0x04		/* Mode Register */
    23. 

  23. #define		AT91_ADC_TRGEN		(1 << 0)	/* Trigger Enable */
    24. 

  24. #define		AT91_ADC_TRGSEL		(7 << 1)	/* Trigger Selection */
    25. 

  25. #define			AT91_ADC_TRGSEL_TC0		(0 << 1)
    26. 

  26. #define			AT91_ADC_TRGSEL_TC1		(1 << 1)
    27. 

  27. #define			AT91_ADC_TRGSEL_TC2		(2 << 1)
    28. 

  28. #define			AT91_ADC_TRGSEL_EXTERNAL	(6 << 1)
    29. 

  29. #define		AT91_ADC_LOWRES		(1 << 4)	/* Low Resolution */
    30. 

  30. #define		AT91_ADC_SLEEP		(1 << 5)	/* Sleep Mode */
    31. 

  31. #define		AT91_ADC_PRESCAL_9260	(0x3f << 8)	/* Prescalar Rate Selection */
    32. 

  32. #define		AT91_ADC_PRESCAL_9G45	(0xff << 8)
    33. 

  33. #define			AT91_ADC_PRESCAL_(x)	((x) << 8)
    34. 

  34. #define		AT91_ADC_STARTUP_9260	(0x1f << 16)	/* Startup Up Time */
    35. 

  35. #define		AT91_ADC_STARTUP_9G45	(0x7f << 16)
    36. 

  36. #define		AT91_ADC_STARTUP_9X5	(0xf << 16)
    37. 

  37. #define			AT91_ADC_STARTUP_(x)	((x) << 16)
    38. 

  38. #define		AT91_ADC_SHTIM		(0xf  << 24)	/* Sample & Hold Time */
    39. 

  39. #define			AT91_ADC_SHTIM_(x)	((x) << 24)
    40. 

  40. 

  41. #define AT91_ADC_CHER		0x10		/* Channel Enable Register */
    42. 

  42. #define AT91_ADC_CHDR		0x14		/* Channel Disable Register */
    43. 

  43. #define AT91_ADC_CHSR		0x18		/* Channel Status Register */
    44. 

  44. #define		AT91_ADC_CH(n)		(1 << (n))	/* Channel Number */
    45. 

  45. 

  46. #define AT91_ADC_SR		0x1C		/* Status Register */
    47. 

  47. #define		AT91_ADC_EOC(n)		(1 << (n))	/* End of Conversion on Channel N */
    48. 

  48. #define		AT91_ADC_OVRE(n)	(1 << ((n) + 8))/* Overrun Error on Channel N */
    49. 

  49. #define		AT91_ADC_DRDY		(1 << 16)	/* Data Ready */
    50. 

  50. #define		AT91_ADC_GOVRE		(1 << 17)	/* General Overrun Error */
    51. 

  51. #define		AT91_ADC_ENDRX		(1 << 18)	/* End of RX Buffer */
    52. 

  52. #define		AT91_ADC_RXFUFF		(1 << 19)	/* RX Buffer Full */
    53. 

  53. 

  54. #define AT91_ADC_SR_9X5		0x30		/* Status Register for 9x5 */
    55. 

  55. #define		AT91_ADC_SR_DRDY_9X5	(1 << 24)	/* Data Ready */
    56. 

  56. 

  57. #define AT91_ADC_LCDR		0x20		/* Last Converted Data Register */
    58. 

  58. #define		AT91_ADC_LDATA		(0x3ff)
    59. 

  59. 

  60. #define AT91_ADC_IER		0x24		/* Interrupt Enable Register */
    61. 

  61. #define AT91_ADC_IDR		0x28		/* Interrupt Disable Register */
    62. 

  62. #define AT91_ADC_IMR		0x2C		/* Interrupt Mask Register */
    63. 

  63. #define		AT91_ADC_IER_PEN	(1 << 29)
    64. 

  64. #define		AT91_ADC_IER_NOPEN	(1 << 30)
    65. 

  65. #define		AT91_ADC_IER_XRDY	(1 << 20)
    66. 

  66. #define		AT91_ADC_IER_YRDY	(1 << 21)
    67. 

  67. #define		AT91_ADC_IER_PRDY	(1 << 22)
    68. 

  68. #define		AT91_ADC_ISR_PENS	(1 << 31)
    69. 

  69. 

  70. #define AT91_ADC_CHR(n)		(0x30 + ((n) * 4))	/* Channel Data Register N */
    71. 

  71. #define		AT91_ADC_DATA		(0x3ff)
    72. 

  72. 

  73. #define AT91_ADC_CDR0_9X5	(0x50)			/* Channel Data Register 0 for 9X5 */
    74. 

  74. 

  75. #define AT91_ADC_ACR		0x94	/* Analog Control Register */
    76. 

  76. #define		AT91_ADC_ACR_PENDETSENS	(0x3 << 0)	/* pull-up resistor */
    77. 

  77. 

  78. #define AT91_ADC_TSMR		0xB0
    79. 

  79. #define		AT91_ADC_TSMR_TSMODE	(3 << 0)	/* Touch Screen Mode */
    80. 

  80. #define			AT91_ADC_TSMR_TSMODE_NONE		(0 << 0)
    81. 

  81. #define			AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS	(1 << 0)
    82. 

  82. #define			AT91_ADC_TSMR_TSMODE_4WIRE_PRESS	(2 << 0)
    83. 

  83. #define			AT91_ADC_TSMR_TSMODE_5WIRE		(3 << 0)
    84. 

  84. #define		AT91_ADC_TSMR_TSAV	(3 << 4)	/* Averages samples */
    85. 

  85. #define			AT91_ADC_TSMR_TSAV_(x)		((x) << 4)
    86. 

  86. #define		AT91_ADC_TSMR_SCTIM	(0x0f << 16)	/* Switch closure time */
    87. 

  87. #define		AT91_ADC_TSMR_PENDBC	(0x0f << 28)	/* Pen Debounce time */
    88. 

  88. #define			AT91_ADC_TSMR_PENDBC_(x)	((x) << 28)
    89. 

  89. #define		AT91_ADC_TSMR_NOTSDMA	(1 << 22)	/* No Touchscreen DMA */
    90. 

  90. #define		AT91_ADC_TSMR_PENDET_DIS	(0 << 24)	/* Pen contact detection disable */
    91. 

  91. #define		AT91_ADC_TSMR_PENDET_ENA	(1 << 24)	/* Pen contact detection enable */
    92. 

  92. 

  93. #define AT91_ADC_TSXPOSR	0xB4
    94. 

  94. #define AT91_ADC_TSYPOSR	0xB8
    95. 

  95. #define AT91_ADC_TSPRESSR	0xBC
    96. 

  96. 

  97. #define AT91_ADC_TRGR_9260	AT91_ADC_MR
    98. 

  98. #define AT91_ADC_TRGR_9G45	0x08
    99. 

  99. #define AT91_ADC_TRGR_9X5	0xC0
    100. 

  100. 

  101. /* Trigger Register bit field */
    102. 

  102. #define		AT91_ADC_TRGR_TRGPER	(0xffff << 16)
    103. 

  103. #define			AT91_ADC_TRGR_TRGPER_(x)	((x) << 16)
    104. 

  104. #define		AT91_ADC_TRGR_TRGMOD	(0x7 << 0)
    105. 

  105. #define			AT91_ADC_TRGR_MOD_PERIOD_TRIG	(5 << 0)
    106. 

  106. 

  107. #endif
    108.