tegra114-dalmore.dts 28 KB

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  1. /dts-v1/;
  2. #include <dt-bindings/input/input.h>
  3. #include "tegra114.dtsi"
  4. / {
  5. model = "NVIDIA Tegra114 Dalmore evaluation board";
  6. compatible = "nvidia,dalmore", "nvidia,tegra114";
  7. memory {
  8. reg = <0x80000000 0x40000000>;
  9. };
  10. pinmux {
  11. pinctrl-names = "default";
  12. pinctrl-0 = <&state_default>;
  13. state_default: pinmux {
  14. clk1_out_pw4 {
  15. nvidia,pins = "clk1_out_pw4";
  16. nvidia,function = "extperiph1";
  17. nvidia,pull = <0>;
  18. nvidia,tristate = <0>;
  19. nvidia,enable-input = <0>;
  20. };
  21. dap1_din_pn1 {
  22. nvidia,pins = "dap1_din_pn1";
  23. nvidia,function = "i2s0";
  24. nvidia,pull = <0>;
  25. nvidia,tristate = <1>;
  26. nvidia,enable-input = <1>;
  27. };
  28. dap1_dout_pn2 {
  29. nvidia,pins = "dap1_dout_pn2",
  30. "dap1_fs_pn0",
  31. "dap1_sclk_pn3";
  32. nvidia,function = "i2s0";
  33. nvidia,pull = <0>;
  34. nvidia,tristate = <0>;
  35. nvidia,enable-input = <1>;
  36. };
  37. dap2_din_pa4 {
  38. nvidia,pins = "dap2_din_pa4";
  39. nvidia,function = "i2s1";
  40. nvidia,pull = <0>;
  41. nvidia,tristate = <1>;
  42. nvidia,enable-input = <1>;
  43. };
  44. dap2_dout_pa5 {
  45. nvidia,pins = "dap2_dout_pa5",
  46. "dap2_fs_pa2",
  47. "dap2_sclk_pa3";
  48. nvidia,function = "i2s1";
  49. nvidia,pull = <0>;
  50. nvidia,tristate = <0>;
  51. nvidia,enable-input = <1>;
  52. };
  53. dap4_din_pp5 {
  54. nvidia,pins = "dap4_din_pp5",
  55. "dap4_dout_pp6",
  56. "dap4_fs_pp4",
  57. "dap4_sclk_pp7";
  58. nvidia,function = "i2s3";
  59. nvidia,pull = <0>;
  60. nvidia,tristate = <0>;
  61. nvidia,enable-input = <1>;
  62. };
  63. dvfs_pwm_px0 {
  64. nvidia,pins = "dvfs_pwm_px0",
  65. "dvfs_clk_px2";
  66. nvidia,function = "cldvfs";
  67. nvidia,pull = <0>;
  68. nvidia,tristate = <0>;
  69. nvidia,enable-input = <0>;
  70. };
  71. ulpi_clk_py0 {
  72. nvidia,pins = "ulpi_clk_py0",
  73. "ulpi_data0_po1",
  74. "ulpi_data1_po2",
  75. "ulpi_data2_po3",
  76. "ulpi_data3_po4",
  77. "ulpi_data4_po5",
  78. "ulpi_data5_po6",
  79. "ulpi_data6_po7",
  80. "ulpi_data7_po0";
  81. nvidia,function = "ulpi";
  82. nvidia,pull = <0>;
  83. nvidia,tristate = <0>;
  84. nvidia,enable-input = <1>;
  85. };
  86. ulpi_dir_py1 {
  87. nvidia,pins = "ulpi_dir_py1",
  88. "ulpi_nxt_py2";
  89. nvidia,function = "ulpi";
  90. nvidia,pull = <0>;
  91. nvidia,tristate = <1>;
  92. nvidia,enable-input = <1>;
  93. };
  94. ulpi_stp_py3 {
  95. nvidia,pins = "ulpi_stp_py3";
  96. nvidia,function = "ulpi";
  97. nvidia,pull = <0>;
  98. nvidia,tristate = <0>;
  99. nvidia,enable-input = <0>;
  100. };
  101. cam_i2c_scl_pbb1 {
  102. nvidia,pins = "cam_i2c_scl_pbb1",
  103. "cam_i2c_sda_pbb2";
  104. nvidia,function = "i2c3";
  105. nvidia,pull = <0>;
  106. nvidia,tristate = <0>;
  107. nvidia,enable-input = <1>;
  108. nvidia,lock = <0>;
  109. nvidia,open-drain = <0>;
  110. };
  111. cam_mclk_pcc0 {
  112. nvidia,pins = "cam_mclk_pcc0",
  113. "pbb0";
  114. nvidia,function = "vi_alt3";
  115. nvidia,pull = <0>;
  116. nvidia,tristate = <0>;
  117. nvidia,enable-input = <0>;
  118. nvidia,lock = <0>;
  119. };
  120. gen2_i2c_scl_pt5 {
  121. nvidia,pins = "gen2_i2c_scl_pt5",
  122. "gen2_i2c_sda_pt6";
  123. nvidia,function = "i2c2";
  124. nvidia,pull = <0>;
  125. nvidia,tristate = <0>;
  126. nvidia,enable-input = <1>;
  127. nvidia,lock = <0>;
  128. nvidia,open-drain = <0>;
  129. };
  130. gmi_a16_pj7 {
  131. nvidia,pins = "gmi_a16_pj7";
  132. nvidia,function = "uartd";
  133. nvidia,pull = <0>;
  134. nvidia,tristate = <0>;
  135. nvidia,enable-input = <0>;
  136. };
  137. gmi_a17_pb0 {
  138. nvidia,pins = "gmi_a17_pb0",
  139. "gmi_a18_pb1";
  140. nvidia,function = "uartd";
  141. nvidia,pull = <0>;
  142. nvidia,tristate = <1>;
  143. nvidia,enable-input = <1>;
  144. };
  145. gmi_a19_pk7 {
  146. nvidia,pins = "gmi_a19_pk7";
  147. nvidia,function = "uartd";
  148. nvidia,pull = <0>;
  149. nvidia,tristate = <0>;
  150. nvidia,enable-input = <0>;
  151. };
  152. gmi_ad5_pg5 {
  153. nvidia,pins = "gmi_ad5_pg5",
  154. "gmi_cs6_n_pi3",
  155. "gmi_wr_n_pi0";
  156. nvidia,function = "spi4";
  157. nvidia,pull = <0>;
  158. nvidia,tristate = <0>;
  159. nvidia,enable-input = <1>;
  160. };
  161. gmi_ad6_pg6 {
  162. nvidia,pins = "gmi_ad6_pg6",
  163. "gmi_ad7_pg7";
  164. nvidia,function = "spi4";
  165. nvidia,pull = <2>;
  166. nvidia,tristate = <0>;
  167. nvidia,enable-input = <1>;
  168. };
  169. gmi_ad12_ph4 {
  170. nvidia,pins = "gmi_ad12_ph4";
  171. nvidia,function = "rsvd4";
  172. nvidia,pull = <0>;
  173. nvidia,tristate = <0>;
  174. nvidia,enable-input = <0>;
  175. };
  176. gmi_ad9_ph1 {
  177. nvidia,pins = "gmi_ad9_ph1";
  178. nvidia,function = "pwm1";
  179. nvidia,pull = <0>;
  180. nvidia,tristate = <0>;
  181. nvidia,enable-input = <0>;
  182. };
  183. gmi_cs1_n_pj2 {
  184. nvidia,pins = "gmi_cs1_n_pj2",
  185. "gmi_oe_n_pi1";
  186. nvidia,function = "soc";
  187. nvidia,pull = <0>;
  188. nvidia,tristate = <1>;
  189. nvidia,enable-input = <1>;
  190. };
  191. clk2_out_pw5 {
  192. nvidia,pins = "clk2_out_pw5";
  193. nvidia,function = "extperiph2";
  194. nvidia,pull = <0>;
  195. nvidia,tristate = <0>;
  196. nvidia,enable-input = <0>;
  197. };
  198. sdmmc1_clk_pz0 {
  199. nvidia,pins = "sdmmc1_clk_pz0";
  200. nvidia,function = "sdmmc1";
  201. nvidia,pull = <0>;
  202. nvidia,tristate = <0>;
  203. nvidia,enable-input = <1>;
  204. };
  205. sdmmc1_cmd_pz1 {
  206. nvidia,pins = "sdmmc1_cmd_pz1",
  207. "sdmmc1_dat0_py7",
  208. "sdmmc1_dat1_py6",
  209. "sdmmc1_dat2_py5",
  210. "sdmmc1_dat3_py4";
  211. nvidia,function = "sdmmc1";
  212. nvidia,pull = <2>;
  213. nvidia,tristate = <0>;
  214. nvidia,enable-input = <1>;
  215. };
  216. sdmmc1_wp_n_pv3 {
  217. nvidia,pins = "sdmmc1_wp_n_pv3";
  218. nvidia,function = "spi4";
  219. nvidia,pull = <2>;
  220. nvidia,tristate = <0>;
  221. nvidia,enable-input = <0>;
  222. };
  223. sdmmc3_clk_pa6 {
  224. nvidia,pins = "sdmmc3_clk_pa6";
  225. nvidia,function = "sdmmc3";
  226. nvidia,pull = <0>;
  227. nvidia,tristate = <0>;
  228. nvidia,enable-input = <1>;
  229. };
  230. sdmmc3_cmd_pa7 {
  231. nvidia,pins = "sdmmc3_cmd_pa7",
  232. "sdmmc3_dat0_pb7",
  233. "sdmmc3_dat1_pb6",
  234. "sdmmc3_dat2_pb5",
  235. "sdmmc3_dat3_pb4",
  236. "kb_col4_pq4",
  237. "sdmmc3_clk_lb_out_pee4",
  238. "sdmmc3_clk_lb_in_pee5";
  239. nvidia,function = "sdmmc3";
  240. nvidia,pull = <2>;
  241. nvidia,tristate = <0>;
  242. nvidia,enable-input = <1>;
  243. };
  244. sdmmc4_clk_pcc4 {
  245. nvidia,pins = "sdmmc4_clk_pcc4";
  246. nvidia,function = "sdmmc4";
  247. nvidia,pull = <0>;
  248. nvidia,tristate = <0>;
  249. nvidia,enable-input = <1>;
  250. };
  251. sdmmc4_cmd_pt7 {
  252. nvidia,pins = "sdmmc4_cmd_pt7",
  253. "sdmmc4_dat0_paa0",
  254. "sdmmc4_dat1_paa1",
  255. "sdmmc4_dat2_paa2",
  256. "sdmmc4_dat3_paa3",
  257. "sdmmc4_dat4_paa4",
  258. "sdmmc4_dat5_paa5",
  259. "sdmmc4_dat6_paa6",
  260. "sdmmc4_dat7_paa7";
  261. nvidia,function = "sdmmc4";
  262. nvidia,pull = <2>;
  263. nvidia,tristate = <0>;
  264. nvidia,enable-input = <1>;
  265. };
  266. clk_32k_out_pa0 {
  267. nvidia,pins = "clk_32k_out_pa0";
  268. nvidia,function = "blink";
  269. nvidia,pull = <0>;
  270. nvidia,tristate = <0>;
  271. nvidia,enable-input = <0>;
  272. };
  273. kb_col0_pq0 {
  274. nvidia,pins = "kb_col0_pq0",
  275. "kb_col1_pq1",
  276. "kb_col2_pq2",
  277. "kb_row0_pr0",
  278. "kb_row1_pr1",
  279. "kb_row2_pr2";
  280. nvidia,function = "kbc";
  281. nvidia,pull = <2>;
  282. nvidia,tristate = <0>;
  283. nvidia,enable-input = <1>;
  284. };
  285. dap3_din_pp1 {
  286. nvidia,pins = "dap3_din_pp1",
  287. "dap3_sclk_pp3";
  288. nvidia,function = "displayb";
  289. nvidia,pull = <0>;
  290. nvidia,tristate = <1>;
  291. nvidia,enable-input = <0>;
  292. };
  293. pv0 {
  294. nvidia,pins = "pv0";
  295. nvidia,function = "rsvd4";
  296. nvidia,pull = <0>;
  297. nvidia,tristate = <1>;
  298. nvidia,enable-input = <0>;
  299. };
  300. kb_row7_pr7 {
  301. nvidia,pins = "kb_row7_pr7";
  302. nvidia,function = "rsvd2";
  303. nvidia,pull = <2>;
  304. nvidia,tristate = <0>;
  305. nvidia,enable-input = <1>;
  306. };
  307. kb_row10_ps2 {
  308. nvidia,pins = "kb_row10_ps2";
  309. nvidia,function = "uarta";
  310. nvidia,pull = <0>;
  311. nvidia,tristate = <1>;
  312. nvidia,enable-input = <1>;
  313. };
  314. kb_row9_ps1 {
  315. nvidia,pins = "kb_row9_ps1";
  316. nvidia,function = "uarta";
  317. nvidia,pull = <0>;
  318. nvidia,tristate = <0>;
  319. nvidia,enable-input = <0>;
  320. };
  321. pwr_i2c_scl_pz6 {
  322. nvidia,pins = "pwr_i2c_scl_pz6",
  323. "pwr_i2c_sda_pz7";
  324. nvidia,function = "i2cpwr";
  325. nvidia,pull = <0>;
  326. nvidia,tristate = <0>;
  327. nvidia,enable-input = <1>;
  328. nvidia,lock = <0>;
  329. nvidia,open-drain = <0>;
  330. };
  331. sys_clk_req_pz5 {
  332. nvidia,pins = "sys_clk_req_pz5";
  333. nvidia,function = "sysclk";
  334. nvidia,pull = <0>;
  335. nvidia,tristate = <0>;
  336. nvidia,enable-input = <0>;
  337. };
  338. core_pwr_req {
  339. nvidia,pins = "core_pwr_req";
  340. nvidia,function = "pwron";
  341. nvidia,pull = <0>;
  342. nvidia,tristate = <0>;
  343. nvidia,enable-input = <0>;
  344. };
  345. cpu_pwr_req {
  346. nvidia,pins = "cpu_pwr_req";
  347. nvidia,function = "cpu";
  348. nvidia,pull = <0>;
  349. nvidia,tristate = <0>;
  350. nvidia,enable-input = <0>;
  351. };
  352. pwr_int_n {
  353. nvidia,pins = "pwr_int_n";
  354. nvidia,function = "pmi";
  355. nvidia,pull = <0>;
  356. nvidia,tristate = <1>;
  357. nvidia,enable-input = <1>;
  358. };
  359. reset_out_n {
  360. nvidia,pins = "reset_out_n";
  361. nvidia,function = "reset_out_n";
  362. nvidia,pull = <0>;
  363. nvidia,tristate = <0>;
  364. nvidia,enable-input = <0>;
  365. };
  366. clk3_out_pee0 {
  367. nvidia,pins = "clk3_out_pee0";
  368. nvidia,function = "extperiph3";
  369. nvidia,pull = <0>;
  370. nvidia,tristate = <0>;
  371. nvidia,enable-input = <0>;
  372. };
  373. gen1_i2c_scl_pc4 {
  374. nvidia,pins = "gen1_i2c_scl_pc4",
  375. "gen1_i2c_sda_pc5";
  376. nvidia,function = "i2c1";
  377. nvidia,pull = <0>;
  378. nvidia,tristate = <0>;
  379. nvidia,enable-input = <1>;
  380. nvidia,lock = <0>;
  381. nvidia,open-drain = <0>;
  382. };
  383. uart2_cts_n_pj5 {
  384. nvidia,pins = "uart2_cts_n_pj5";
  385. nvidia,function = "uartb";
  386. nvidia,pull = <0>;
  387. nvidia,tristate = <1>;
  388. nvidia,enable-input = <1>;
  389. };
  390. uart2_rts_n_pj6 {
  391. nvidia,pins = "uart2_rts_n_pj6";
  392. nvidia,function = "uartb";
  393. nvidia,pull = <0>;
  394. nvidia,tristate = <0>;
  395. nvidia,enable-input = <0>;
  396. };
  397. uart2_rxd_pc3 {
  398. nvidia,pins = "uart2_rxd_pc3";
  399. nvidia,function = "irda";
  400. nvidia,pull = <0>;
  401. nvidia,tristate = <1>;
  402. nvidia,enable-input = <1>;
  403. };
  404. uart2_txd_pc2 {
  405. nvidia,pins = "uart2_txd_pc2";
  406. nvidia,function = "irda";
  407. nvidia,pull = <0>;
  408. nvidia,tristate = <0>;
  409. nvidia,enable-input = <0>;
  410. };
  411. uart3_cts_n_pa1 {
  412. nvidia,pins = "uart3_cts_n_pa1",
  413. "uart3_rxd_pw7";
  414. nvidia,function = "uartc";
  415. nvidia,pull = <0>;
  416. nvidia,tristate = <1>;
  417. nvidia,enable-input = <1>;
  418. };
  419. uart3_rts_n_pc0 {
  420. nvidia,pins = "uart3_rts_n_pc0",
  421. "uart3_txd_pw6";
  422. nvidia,function = "uartc";
  423. nvidia,pull = <0>;
  424. nvidia,tristate = <0>;
  425. nvidia,enable-input = <0>;
  426. };
  427. owr {
  428. nvidia,pins = "owr";
  429. nvidia,function = "owr";
  430. nvidia,pull = <0>;
  431. nvidia,tristate = <0>;
  432. nvidia,enable-input = <1>;
  433. };
  434. hdmi_cec_pee3 {
  435. nvidia,pins = "hdmi_cec_pee3";
  436. nvidia,function = "cec";
  437. nvidia,pull = <0>;
  438. nvidia,tristate = <0>;
  439. nvidia,enable-input = <1>;
  440. nvidia,lock = <0>;
  441. nvidia,open-drain = <0>;
  442. };
  443. ddc_scl_pv4 {
  444. nvidia,pins = "ddc_scl_pv4",
  445. "ddc_sda_pv5";
  446. nvidia,function = "i2c4";
  447. nvidia,pull = <0>;
  448. nvidia,tristate = <0>;
  449. nvidia,enable-input = <1>;
  450. nvidia,lock = <0>;
  451. nvidia,rcv-sel = <1>;
  452. };
  453. spdif_in_pk6 {
  454. nvidia,pins = "spdif_in_pk6";
  455. nvidia,function = "usb";
  456. nvidia,pull = <2>;
  457. nvidia,tristate = <0>;
  458. nvidia,enable-input = <1>;
  459. nvidia,lock = <0>;
  460. };
  461. usb_vbus_en0_pn4 {
  462. nvidia,pins = "usb_vbus_en0_pn4";
  463. nvidia,function = "usb";
  464. nvidia,pull = <2>;
  465. nvidia,tristate = <0>;
  466. nvidia,enable-input = <1>;
  467. nvidia,lock = <0>;
  468. nvidia,open-drain = <1>;
  469. };
  470. gpio_x6_aud_px6 {
  471. nvidia,pins = "gpio_x6_aud_px6";
  472. nvidia,function = "spi6";
  473. nvidia,pull = <2>;
  474. nvidia,tristate = <1>;
  475. nvidia,enable-input = <1>;
  476. };
  477. gpio_x4_aud_px4 {
  478. nvidia,pins = "gpio_x4_aud_px4",
  479. "gpio_x7_aud_px7";
  480. nvidia,function = "rsvd1";
  481. nvidia,pull = <1>;
  482. nvidia,tristate = <0>;
  483. nvidia,enable-input = <0>;
  484. };
  485. gpio_x5_aud_px5 {
  486. nvidia,pins = "gpio_x5_aud_px5";
  487. nvidia,function = "rsvd1";
  488. nvidia,pull = <2>;
  489. nvidia,tristate = <0>;
  490. nvidia,enable-input = <1>;
  491. };
  492. gpio_w2_aud_pw2 {
  493. nvidia,pins = "gpio_w2_aud_pw2";
  494. nvidia,function = "rsvd2";
  495. nvidia,pull = <2>;
  496. nvidia,tristate = <0>;
  497. nvidia,enable-input = <1>;
  498. };
  499. gpio_w3_aud_pw3 {
  500. nvidia,pins = "gpio_w3_aud_pw3";
  501. nvidia,function = "spi6";
  502. nvidia,pull = <2>;
  503. nvidia,tristate = <0>;
  504. nvidia,enable-input = <1>;
  505. };
  506. gpio_x1_aud_px1 {
  507. nvidia,pins = "gpio_x1_aud_px1";
  508. nvidia,function = "rsvd4";
  509. nvidia,pull = <1>;
  510. nvidia,tristate = <0>;
  511. nvidia,enable-input = <1>;
  512. };
  513. gpio_x3_aud_px3 {
  514. nvidia,pins = "gpio_x3_aud_px3";
  515. nvidia,function = "rsvd4";
  516. nvidia,pull = <2>;
  517. nvidia,tristate = <0>;
  518. nvidia,enable-input = <1>;
  519. };
  520. dap3_fs_pp0 {
  521. nvidia,pins = "dap3_fs_pp0";
  522. nvidia,function = "i2s2";
  523. nvidia,pull = <1>;
  524. nvidia,tristate = <0>;
  525. nvidia,enable-input = <0>;
  526. };
  527. dap3_dout_pp2 {
  528. nvidia,pins = "dap3_dout_pp2";
  529. nvidia,function = "i2s2";
  530. nvidia,pull = <1>;
  531. nvidia,tristate = <0>;
  532. nvidia,enable-input = <0>;
  533. };
  534. pv1 {
  535. nvidia,pins = "pv1";
  536. nvidia,function = "rsvd1";
  537. nvidia,pull = <0>;
  538. nvidia,tristate = <0>;
  539. nvidia,enable-input = <1>;
  540. };
  541. pbb3 {
  542. nvidia,pins = "pbb3",
  543. "pbb5",
  544. "pbb6",
  545. "pbb7";
  546. nvidia,function = "rsvd4";
  547. nvidia,pull = <1>;
  548. nvidia,tristate = <0>;
  549. nvidia,enable-input = <0>;
  550. };
  551. pcc1 {
  552. nvidia,pins = "pcc1",
  553. "pcc2";
  554. nvidia,function = "rsvd4";
  555. nvidia,pull = <1>;
  556. nvidia,tristate = <0>;
  557. nvidia,enable-input = <1>;
  558. };
  559. gmi_ad0_pg0 {
  560. nvidia,pins = "gmi_ad0_pg0",
  561. "gmi_ad1_pg1";
  562. nvidia,function = "gmi";
  563. nvidia,pull = <0>;
  564. nvidia,tristate = <0>;
  565. nvidia,enable-input = <0>;
  566. };
  567. gmi_ad10_ph2 {
  568. nvidia,pins = "gmi_ad10_ph2",
  569. "gmi_ad11_ph3",
  570. "gmi_ad13_ph5",
  571. "gmi_ad8_ph0",
  572. "gmi_clk_pk1";
  573. nvidia,function = "gmi";
  574. nvidia,pull = <1>;
  575. nvidia,tristate = <0>;
  576. nvidia,enable-input = <0>;
  577. };
  578. gmi_ad2_pg2 {
  579. nvidia,pins = "gmi_ad2_pg2",
  580. "gmi_ad3_pg3";
  581. nvidia,function = "gmi";
  582. nvidia,pull = <0>;
  583. nvidia,tristate = <0>;
  584. nvidia,enable-input = <1>;
  585. };
  586. gmi_adv_n_pk0 {
  587. nvidia,pins = "gmi_adv_n_pk0",
  588. "gmi_cs0_n_pj0",
  589. "gmi_cs2_n_pk3",
  590. "gmi_cs4_n_pk2",
  591. "gmi_cs7_n_pi6",
  592. "gmi_dqs_p_pj3",
  593. "gmi_iordy_pi5",
  594. "gmi_wp_n_pc7";
  595. nvidia,function = "gmi";
  596. nvidia,pull = <2>;
  597. nvidia,tristate = <0>;
  598. nvidia,enable-input = <1>;
  599. };
  600. gmi_cs3_n_pk4 {
  601. nvidia,pins = "gmi_cs3_n_pk4";
  602. nvidia,function = "gmi";
  603. nvidia,pull = <2>;
  604. nvidia,tristate = <0>;
  605. nvidia,enable-input = <0>;
  606. };
  607. clk2_req_pcc5 {
  608. nvidia,pins = "clk2_req_pcc5";
  609. nvidia,function = "rsvd4";
  610. nvidia,pull = <0>;
  611. nvidia,tristate = <0>;
  612. nvidia,enable-input = <0>;
  613. };
  614. kb_col3_pq3 {
  615. nvidia,pins = "kb_col3_pq3",
  616. "kb_col6_pq6",
  617. "kb_col7_pq7";
  618. nvidia,function = "kbc";
  619. nvidia,pull = <2>;
  620. nvidia,tristate = <0>;
  621. nvidia,enable-input = <0>;
  622. };
  623. kb_col5_pq5 {
  624. nvidia,pins = "kb_col5_pq5";
  625. nvidia,function = "kbc";
  626. nvidia,pull = <2>;
  627. nvidia,tristate = <0>;
  628. nvidia,enable-input = <1>;
  629. };
  630. kb_row3_pr3 {
  631. nvidia,pins = "kb_row3_pr3",
  632. "kb_row4_pr4",
  633. "kb_row6_pr6",
  634. "kb_row8_ps0";
  635. nvidia,function = "kbc";
  636. nvidia,pull = <1>;
  637. nvidia,tristate = <0>;
  638. nvidia,enable-input = <1>;
  639. };
  640. clk3_req_pee1 {
  641. nvidia,pins = "clk3_req_pee1";
  642. nvidia,function = "rsvd4";
  643. nvidia,pull = <0>;
  644. nvidia,tristate = <0>;
  645. nvidia,enable-input = <0>;
  646. };
  647. pu4 {
  648. nvidia,pins = "pu4";
  649. nvidia,function = "displayb";
  650. nvidia,pull = <0>;
  651. nvidia,tristate = <0>;
  652. nvidia,enable-input = <0>;
  653. };
  654. pu5 {
  655. nvidia,pins = "pu5",
  656. "pu6";
  657. nvidia,function = "displayb";
  658. nvidia,pull = <0>;
  659. nvidia,tristate = <0>;
  660. nvidia,enable-input = <1>;
  661. };
  662. hdmi_int_pn7 {
  663. nvidia,pins = "hdmi_int_pn7";
  664. nvidia,function = "rsvd1";
  665. nvidia,pull = <1>;
  666. nvidia,tristate = <0>;
  667. nvidia,enable-input = <1>;
  668. };
  669. clk1_req_pee2 {
  670. nvidia,pins = "clk1_req_pee2",
  671. "usb_vbus_en1_pn5";
  672. nvidia,function = "rsvd4";
  673. nvidia,pull = <1>;
  674. nvidia,tristate = <1>;
  675. nvidia,enable-input = <0>;
  676. };
  677. drive_sdio1 {
  678. nvidia,pins = "drive_sdio1";
  679. nvidia,high-speed-mode = <1>;
  680. nvidia,schmitt = <0>;
  681. nvidia,low-power-mode = <3>;
  682. nvidia,pull-down-strength = <36>;
  683. nvidia,pull-up-strength = <20>;
  684. nvidia,slew-rate-rising = <2>;
  685. nvidia,slew-rate-falling = <2>;
  686. };
  687. drive_sdio3 {
  688. nvidia,pins = "drive_sdio3";
  689. nvidia,high-speed-mode = <1>;
  690. nvidia,schmitt = <0>;
  691. nvidia,low-power-mode = <3>;
  692. nvidia,pull-down-strength = <22>;
  693. nvidia,pull-up-strength = <36>;
  694. nvidia,slew-rate-rising = <0>;
  695. nvidia,slew-rate-falling = <0>;
  696. };
  697. drive_gma {
  698. nvidia,pins = "drive_gma";
  699. nvidia,high-speed-mode = <1>;
  700. nvidia,schmitt = <0>;
  701. nvidia,low-power-mode = <3>;
  702. nvidia,pull-down-strength = <2>;
  703. nvidia,pull-up-strength = <1>;
  704. nvidia,slew-rate-rising = <0>;
  705. nvidia,slew-rate-falling = <0>;
  706. nvidia,drive-type = <1>;
  707. };
  708. };
  709. };
  710. serial@70006300 {
  711. status = "okay";
  712. };
  713. i2c@7000c000 {
  714. status = "okay";
  715. clock-frequency = <100000>;
  716. battery: smart-battery {
  717. compatible = "ti,bq20z45", "sbs,sbs-battery";
  718. reg = <0xb>;
  719. battery-name = "battery";
  720. sbs,i2c-retry-count = <2>;
  721. sbs,poll-retry-count = <100>;
  722. power-supplies = <&charger>;
  723. };
  724. rt5640: rt5640 {
  725. compatible = "realtek,rt5640";
  726. reg = <0x1c>;
  727. interrupt-parent = <&gpio>;
  728. interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
  729. realtek,ldo1-en-gpios =
  730. <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
  731. };
  732. temperature-sensor@4c {
  733. compatible = "onnn,nct1008";
  734. reg = <0x4c>;
  735. vcc-supply = <&palmas_ldo6_reg>;
  736. interrupt-parent = <&gpio>;
  737. interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_LOW>;
  738. };
  739. };
  740. i2c@7000d000 {
  741. status = "okay";
  742. clock-frequency = <400000>;
  743. tps51632 {
  744. compatible = "ti,tps51632";
  745. reg = <0x43>;
  746. regulator-name = "vdd-cpu";
  747. regulator-min-microvolt = <500000>;
  748. regulator-max-microvolt = <1520000>;
  749. regulator-boot-on;
  750. regulator-always-on;
  751. };
  752. tps65090 {
  753. compatible = "ti,tps65090";
  754. reg = <0x48>;
  755. interrupt-parent = <&gpio>;
  756. interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>;
  757. vsys1-supply = <&vdd_ac_bat_reg>;
  758. vsys2-supply = <&vdd_ac_bat_reg>;
  759. vsys3-supply = <&vdd_ac_bat_reg>;
  760. infet1-supply = <&vdd_ac_bat_reg>;
  761. infet2-supply = <&vdd_ac_bat_reg>;
  762. infet3-supply = <&tps65090_dcdc2_reg>;
  763. infet4-supply = <&tps65090_dcdc2_reg>;
  764. infet5-supply = <&tps65090_dcdc2_reg>;
  765. infet6-supply = <&tps65090_dcdc2_reg>;
  766. infet7-supply = <&tps65090_dcdc2_reg>;
  767. vsys-l1-supply = <&vdd_ac_bat_reg>;
  768. vsys-l2-supply = <&vdd_ac_bat_reg>;
  769. charger: charger {
  770. compatible = "ti,tps65090-charger";
  771. ti,enable-low-current-chrg;
  772. };
  773. regulators {
  774. tps65090_dcdc1_reg: dcdc1 {
  775. regulator-name = "vdd-sys-5v0";
  776. regulator-always-on;
  777. regulator-boot-on;
  778. };
  779. tps65090_dcdc2_reg: dcdc2 {
  780. regulator-name = "vdd-sys-3v3";
  781. regulator-always-on;
  782. regulator-boot-on;
  783. };
  784. tps65090_dcdc3_reg: dcdc3 {
  785. regulator-name = "vdd-ao";
  786. regulator-always-on;
  787. regulator-boot-on;
  788. };
  789. fet1 {
  790. regulator-name = "vdd-lcd-bl";
  791. };
  792. fet3 {
  793. regulator-name = "vdd-modem-3v3";
  794. };
  795. fet4 {
  796. regulator-name = "avdd-lcd";
  797. };
  798. fet5 {
  799. regulator-name = "vdd-lvds";
  800. };
  801. fet6 {
  802. regulator-name = "vdd-sd-slot";
  803. regulator-always-on;
  804. regulator-boot-on;
  805. };
  806. fet7 {
  807. regulator-name = "vdd-com-3v3";
  808. };
  809. ldo1 {
  810. regulator-name = "vdd-sby-5v0";
  811. regulator-always-on;
  812. regulator-boot-on;
  813. };
  814. ldo2 {
  815. regulator-name = "vdd-sby-3v3";
  816. regulator-always-on;
  817. regulator-boot-on;
  818. };
  819. };
  820. };
  821. palmas: tps65913 {
  822. compatible = "ti,palmas";
  823. reg = <0x58>;
  824. interrupts = <0 86 IRQ_TYPE_LEVEL_LOW>;
  825. #interrupt-cells = <2>;
  826. interrupt-controller;
  827. ti,system-power-controller;
  828. palmas_gpio: gpio {
  829. compatible = "ti,palmas-gpio";
  830. gpio-controller;
  831. #gpio-cells = <2>;
  832. };
  833. pmic {
  834. compatible = "ti,tps65913-pmic", "ti,palmas-pmic";
  835. smps1-in-supply = <&tps65090_dcdc3_reg>;
  836. smps3-in-supply = <&tps65090_dcdc3_reg>;
  837. smps4-in-supply = <&tps65090_dcdc2_reg>;
  838. smps7-in-supply = <&tps65090_dcdc2_reg>;
  839. smps8-in-supply = <&tps65090_dcdc2_reg>;
  840. smps9-in-supply = <&tps65090_dcdc2_reg>;
  841. ldo1-in-supply = <&tps65090_dcdc2_reg>;
  842. ldo2-in-supply = <&tps65090_dcdc2_reg>;
  843. ldo3-in-supply = <&palmas_smps3_reg>;
  844. ldo4-in-supply = <&tps65090_dcdc2_reg>;
  845. ldo5-in-supply = <&vdd_ac_bat_reg>;
  846. ldo6-in-supply = <&tps65090_dcdc2_reg>;
  847. ldo7-in-supply = <&tps65090_dcdc2_reg>;
  848. ldo8-in-supply = <&tps65090_dcdc3_reg>;
  849. ldo9-in-supply = <&palmas_smps9_reg>;
  850. ldoln-in-supply = <&tps65090_dcdc1_reg>;
  851. ldousb-in-supply = <&tps65090_dcdc1_reg>;
  852. regulators {
  853. smps12 {
  854. regulator-name = "vddio-ddr";
  855. regulator-min-microvolt = <1350000>;
  856. regulator-max-microvolt = <1350000>;
  857. regulator-always-on;
  858. regulator-boot-on;
  859. };
  860. palmas_smps3_reg: smps3 {
  861. regulator-name = "vddio-1v8";
  862. regulator-min-microvolt = <1800000>;
  863. regulator-max-microvolt = <1800000>;
  864. regulator-always-on;
  865. regulator-boot-on;
  866. };
  867. smps45 {
  868. regulator-name = "vdd-core";
  869. regulator-min-microvolt = <900000>;
  870. regulator-max-microvolt = <1400000>;
  871. regulator-always-on;
  872. regulator-boot-on;
  873. };
  874. smps457 {
  875. regulator-name = "vdd-core";
  876. regulator-min-microvolt = <900000>;
  877. regulator-max-microvolt = <1400000>;
  878. regulator-always-on;
  879. regulator-boot-on;
  880. };
  881. smps8 {
  882. regulator-name = "avdd-pll";
  883. regulator-min-microvolt = <1050000>;
  884. regulator-max-microvolt = <1050000>;
  885. regulator-always-on;
  886. regulator-boot-on;
  887. };
  888. palmas_smps9_reg: smps9 {
  889. regulator-name = "sdhci-vdd-sd-slot";
  890. regulator-min-microvolt = <2800000>;
  891. regulator-max-microvolt = <2800000>;
  892. regulator-always-on;
  893. };
  894. ldo1 {
  895. regulator-name = "avdd-cam1";
  896. regulator-min-microvolt = <2800000>;
  897. regulator-max-microvolt = <2800000>;
  898. };
  899. ldo2 {
  900. regulator-name = "avdd-cam2";
  901. regulator-min-microvolt = <2800000>;
  902. regulator-max-microvolt = <2800000>;
  903. };
  904. ldo3 {
  905. regulator-name = "avdd-dsi-csi";
  906. regulator-min-microvolt = <1200000>;
  907. regulator-max-microvolt = <1200000>;
  908. regulator-always-on;
  909. regulator-boot-on;
  910. };
  911. ldo4 {
  912. regulator-name = "vpp-fuse";
  913. regulator-min-microvolt = <1800000>;
  914. regulator-max-microvolt = <1800000>;
  915. };
  916. palmas_ldo6_reg: ldo6 {
  917. regulator-name = "vdd-sensor-2v85";
  918. regulator-min-microvolt = <2850000>;
  919. regulator-max-microvolt = <2850000>;
  920. };
  921. ldo7 {
  922. regulator-name = "vdd-af-cam1";
  923. regulator-min-microvolt = <2800000>;
  924. regulator-max-microvolt = <2800000>;
  925. };
  926. ldo8 {
  927. regulator-name = "vdd-rtc";
  928. regulator-min-microvolt = <900000>;
  929. regulator-max-microvolt = <900000>;
  930. regulator-always-on;
  931. regulator-boot-on;
  932. ti,enable-ldo8-tracking;
  933. };
  934. ldo9 {
  935. regulator-name = "vddio-sdmmc-2";
  936. regulator-min-microvolt = <1800000>;
  937. regulator-max-microvolt = <3300000>;
  938. regulator-always-on;
  939. regulator-boot-on;
  940. };
  941. ldoln {
  942. regulator-name = "hvdd-usb";
  943. regulator-min-microvolt = <3300000>;
  944. regulator-max-microvolt = <3300000>;
  945. };
  946. ldousb {
  947. regulator-name = "avdd-usb";
  948. regulator-min-microvolt = <3300000>;
  949. regulator-max-microvolt = <3300000>;
  950. regulator-always-on;
  951. regulator-boot-on;
  952. };
  953. regen1 {
  954. regulator-name = "rail-3v3";
  955. regulator-max-microvolt = <3300000>;
  956. regulator-always-on;
  957. regulator-boot-on;
  958. };
  959. regen2 {
  960. regulator-name = "rail-5v0";
  961. regulator-max-microvolt = <5000000>;
  962. regulator-always-on;
  963. regulator-boot-on;
  964. };
  965. };
  966. };
  967. rtc {
  968. compatible = "ti,palmas-rtc";
  969. interrupt-parent = <&palmas>;
  970. interrupts = <8 0>;
  971. };
  972. pinmux {
  973. compatible = "ti,tps65913-pinctrl";
  974. pinctrl-names = "default";
  975. pinctrl-0 = <&palmas_default>;
  976. palmas_default: pinmux {
  977. pin_gpio6 {
  978. pins = "gpio6";
  979. function = "gpio";
  980. };
  981. };
  982. };
  983. };
  984. };
  985. spi@7000da00 {
  986. status = "okay";
  987. spi-max-frequency = <25000000>;
  988. spi-flash@0 {
  989. compatible = "winbond,w25q32dw";
  990. reg = <0>;
  991. spi-max-frequency = <20000000>;
  992. };
  993. };
  994. pmc {
  995. nvidia,invert-interrupt;
  996. nvidia,suspend-mode = <1>;
  997. nvidia,cpu-pwr-good-time = <500>;
  998. nvidia,cpu-pwr-off-time = <300>;
  999. nvidia,core-pwr-good-time = <641 3845>;
  1000. nvidia,core-pwr-off-time = <61036>;
  1001. nvidia,core-power-req-active-high;
  1002. nvidia,sys-clock-req-active-high;
  1003. };
  1004. ahub {
  1005. i2s@70080400 {
  1006. status = "okay";
  1007. };
  1008. };
  1009. sdhci@78000400 {
  1010. cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  1011. bus-width = <4>;
  1012. status = "okay";
  1013. };
  1014. sdhci@78000600 {
  1015. bus-width = <8>;
  1016. status = "okay";
  1017. non-removable;
  1018. };
  1019. usb@7d008000 {
  1020. status = "okay";
  1021. };
  1022. usb-phy@7d008000 {
  1023. status = "okay";
  1024. vbus-supply = <&usb3_vbus_reg>;
  1025. };
  1026. clocks {
  1027. compatible = "simple-bus";
  1028. #address-cells = <1>;
  1029. #size-cells = <0>;
  1030. clk32k_in: clock {
  1031. compatible = "fixed-clock";
  1032. reg=<0>;
  1033. #clock-cells = <0>;
  1034. clock-frequency = <32768>;
  1035. };
  1036. };
  1037. gpio-keys {
  1038. compatible = "gpio-keys";
  1039. home {
  1040. label = "Home";
  1041. gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  1042. linux,code = <KEY_HOME>;
  1043. };
  1044. power {
  1045. label = "Power";
  1046. gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
  1047. linux,code = <KEY_POWER>;
  1048. gpio-key,wakeup;
  1049. };
  1050. volume_down {
  1051. label = "Volume Down";
  1052. gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
  1053. linux,code = <KEY_VOLUMEDOWN>;
  1054. };
  1055. volume_up {
  1056. label = "Volume Up";
  1057. gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
  1058. linux,code = <KEY_VOLUMEUP>;
  1059. };
  1060. };
  1061. regulators {
  1062. compatible = "simple-bus";
  1063. #address-cells = <1>;
  1064. #size-cells = <0>;
  1065. vdd_ac_bat_reg: regulator@0 {
  1066. compatible = "regulator-fixed";
  1067. reg = <0>;
  1068. regulator-name = "vdd_ac_bat";
  1069. regulator-min-microvolt = <5000000>;
  1070. regulator-max-microvolt = <5000000>;
  1071. regulator-always-on;
  1072. };
  1073. dvdd_ts_reg: regulator@1 {
  1074. compatible = "regulator-fixed";
  1075. reg = <1>;
  1076. regulator-name = "dvdd_ts";
  1077. regulator-min-microvolt = <1800000>;
  1078. regulator-max-microvolt = <1800000>;
  1079. enable-active-high;
  1080. gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
  1081. };
  1082. lcd_bl_en_reg: regulator@2 {
  1083. compatible = "regulator-fixed";
  1084. reg = <2>;
  1085. regulator-name = "lcd_bl_en";
  1086. regulator-min-microvolt = <5000000>;
  1087. regulator-max-microvolt = <5000000>;
  1088. enable-active-high;
  1089. gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
  1090. };
  1091. usb1_vbus_reg: regulator@3 {
  1092. compatible = "regulator-fixed";
  1093. reg = <3>;
  1094. regulator-name = "usb1_vbus";
  1095. regulator-min-microvolt = <5000000>;
  1096. regulator-max-microvolt = <5000000>;
  1097. enable-active-high;
  1098. gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
  1099. gpio-open-drain;
  1100. vin-supply = <&tps65090_dcdc1_reg>;
  1101. };
  1102. usb3_vbus_reg: regulator@4 {
  1103. compatible = "regulator-fixed";
  1104. reg = <4>;
  1105. regulator-name = "usb2_vbus";
  1106. regulator-min-microvolt = <5000000>;
  1107. regulator-max-microvolt = <5000000>;
  1108. enable-active-high;
  1109. gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
  1110. gpio-open-drain;
  1111. vin-supply = <&tps65090_dcdc1_reg>;
  1112. };
  1113. vdd_hdmi_reg: regulator@5 {
  1114. compatible = "regulator-fixed";
  1115. reg = <5>;
  1116. regulator-name = "vdd_hdmi_5v0";
  1117. regulator-min-microvolt = <5000000>;
  1118. regulator-max-microvolt = <5000000>;
  1119. enable-active-high;
  1120. gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
  1121. vin-supply = <&tps65090_dcdc1_reg>;
  1122. };
  1123. vdd_cam_1v8_reg: regulator@6 {
  1124. compatible = "regulator-fixed";
  1125. reg = <6>;
  1126. regulator-name = "vdd_cam_1v8_reg";
  1127. regulator-min-microvolt = <1800000>;
  1128. regulator-max-microvolt = <1800000>;
  1129. enable-active-high;
  1130. gpio = <&palmas_gpio 6 0>;
  1131. };
  1132. };
  1133. sound {
  1134. compatible = "nvidia,tegra-audio-rt5640-dalmore",
  1135. "nvidia,tegra-audio-rt5640";
  1136. nvidia,model = "NVIDIA Tegra Dalmore";
  1137. nvidia,audio-routing =
  1138. "Headphones", "HPOR",
  1139. "Headphones", "HPOL",
  1140. "Speakers", "SPORP",
  1141. "Speakers", "SPORN",
  1142. "Speakers", "SPOLP",
  1143. "Speakers", "SPOLN",
  1144. "Mic Jack", "MICBIAS1",
  1145. "IN2P", "Mic Jack";
  1146. nvidia,i2s-controller = <&tegra_i2s1>;
  1147. nvidia,audio-codec = <&rt5640>;
  1148. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
  1149. clocks = <&tegra_car TEGRA114_CLK_PLL_A>,
  1150. <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
  1151. <&tegra_car TEGRA114_CLK_EXTERN1>;
  1152. clock-names = "pll_a", "pll_a_out0", "mclk";
  1153. };
  1154. };