sh73a0.dtsi 4.9 KB

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  1. /*
  2. * Device Tree Source for the SH73A0 SoC
  3. *
  4. * Copyright (C) 2012 Renesas Solutions Corp.
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. */
  10. /include/ "skeleton.dtsi"
  11. / {
  12. compatible = "renesas,sh73a0";
  13. cpus {
  14. #address-cells = <1>;
  15. #size-cells = <0>;
  16. cpu@0 {
  17. device_type = "cpu";
  18. compatible = "arm,cortex-a9";
  19. reg = <0>;
  20. };
  21. cpu@1 {
  22. device_type = "cpu";
  23. compatible = "arm,cortex-a9";
  24. reg = <1>;
  25. };
  26. };
  27. gic: interrupt-controller@f0001000 {
  28. compatible = "arm,cortex-a9-gic";
  29. #interrupt-cells = <3>;
  30. #address-cells = <1>;
  31. interrupt-controller;
  32. reg = <0xf0001000 0x1000>,
  33. <0xf0000100 0x100>;
  34. };
  35. pmu {
  36. compatible = "arm,cortex-a9-pmu";
  37. interrupts = <0 55 4>,
  38. <0 56 4>;
  39. };
  40. irqpin0: irqpin@e6900000 {
  41. compatible = "renesas,intc-irqpin";
  42. #interrupt-cells = <2>;
  43. interrupt-controller;
  44. reg = <0xe6900000 4>,
  45. <0xe6900010 4>,
  46. <0xe6900020 1>,
  47. <0xe6900040 1>,
  48. <0xe6900060 1>;
  49. interrupt-parent = <&gic>;
  50. interrupts = <0 1 0x4
  51. 0 2 0x4
  52. 0 3 0x4
  53. 0 4 0x4
  54. 0 5 0x4
  55. 0 6 0x4
  56. 0 7 0x4
  57. 0 8 0x4>;
  58. };
  59. irqpin1: irqpin@e6900004 {
  60. compatible = "renesas,intc-irqpin";
  61. #interrupt-cells = <2>;
  62. interrupt-controller;
  63. reg = <0xe6900004 4>,
  64. <0xe6900014 4>,
  65. <0xe6900024 1>,
  66. <0xe6900044 1>,
  67. <0xe6900064 1>;
  68. interrupt-parent = <&gic>;
  69. interrupts = <0 9 0x4
  70. 0 10 0x4
  71. 0 11 0x4
  72. 0 12 0x4
  73. 0 13 0x4
  74. 0 14 0x4
  75. 0 15 0x4
  76. 0 16 0x4>;
  77. control-parent;
  78. };
  79. irqpin2: irqpin@e6900008 {
  80. compatible = "renesas,intc-irqpin";
  81. #interrupt-cells = <2>;
  82. interrupt-controller;
  83. reg = <0xe6900008 4>,
  84. <0xe6900018 4>,
  85. <0xe6900028 1>,
  86. <0xe6900048 1>,
  87. <0xe6900068 1>;
  88. interrupt-parent = <&gic>;
  89. interrupts = <0 17 0x4
  90. 0 18 0x4
  91. 0 19 0x4
  92. 0 20 0x4
  93. 0 21 0x4
  94. 0 22 0x4
  95. 0 23 0x4
  96. 0 24 0x4>;
  97. };
  98. irqpin3: irqpin@e690000c {
  99. compatible = "renesas,intc-irqpin";
  100. #interrupt-cells = <2>;
  101. interrupt-controller;
  102. reg = <0xe690000c 4>,
  103. <0xe690001c 4>,
  104. <0xe690002c 1>,
  105. <0xe690004c 1>,
  106. <0xe690006c 1>;
  107. interrupt-parent = <&gic>;
  108. interrupts = <0 25 0x4
  109. 0 26 0x4
  110. 0 27 0x4
  111. 0 28 0x4
  112. 0 29 0x4
  113. 0 30 0x4
  114. 0 31 0x4
  115. 0 32 0x4>;
  116. };
  117. i2c0: i2c@e6820000 {
  118. #address-cells = <1>;
  119. #size-cells = <0>;
  120. compatible = "renesas,rmobile-iic";
  121. reg = <0xe6820000 0x425>;
  122. interrupt-parent = <&gic>;
  123. interrupts = <0 167 0x4
  124. 0 168 0x4
  125. 0 169 0x4
  126. 0 170 0x4>;
  127. status = "disabled";
  128. };
  129. i2c1: i2c@e6822000 {
  130. #address-cells = <1>;
  131. #size-cells = <0>;
  132. compatible = "renesas,rmobile-iic";
  133. reg = <0xe6822000 0x425>;
  134. interrupt-parent = <&gic>;
  135. interrupts = <0 51 0x4
  136. 0 52 0x4
  137. 0 53 0x4
  138. 0 54 0x4>;
  139. status = "disabled";
  140. };
  141. i2c2: i2c@e6824000 {
  142. #address-cells = <1>;
  143. #size-cells = <0>;
  144. compatible = "renesas,rmobile-iic";
  145. reg = <0xe6824000 0x425>;
  146. interrupt-parent = <&gic>;
  147. interrupts = <0 171 0x4
  148. 0 172 0x4
  149. 0 173 0x4
  150. 0 174 0x4>;
  151. status = "disabled";
  152. };
  153. i2c3: i2c@e6826000 {
  154. #address-cells = <1>;
  155. #size-cells = <0>;
  156. compatible = "renesas,rmobile-iic";
  157. reg = <0xe6826000 0x425>;
  158. interrupt-parent = <&gic>;
  159. interrupts = <0 183 0x4
  160. 0 184 0x4
  161. 0 185 0x4
  162. 0 186 0x4>;
  163. status = "disabled";
  164. };
  165. i2c4: i2c@e6828000 {
  166. #address-cells = <1>;
  167. #size-cells = <0>;
  168. compatible = "renesas,rmobile-iic";
  169. reg = <0xe6828000 0x425>;
  170. interrupt-parent = <&gic>;
  171. interrupts = <0 187 0x4
  172. 0 188 0x4
  173. 0 189 0x4
  174. 0 190 0x4>;
  175. status = "disabled";
  176. };
  177. mmcif: mmcif@e6bd0000 {
  178. compatible = "renesas,sh-mmcif";
  179. reg = <0xe6bd0000 0x100>;
  180. interrupt-parent = <&gic>;
  181. interrupts = <0 140 0x4
  182. 0 141 0x4>;
  183. reg-io-width = <4>;
  184. status = "disabled";
  185. };
  186. sdhi0: sdhi@ee100000 {
  187. compatible = "renesas,sdhi-r8a7740";
  188. reg = <0xee100000 0x100>;
  189. interrupt-parent = <&gic>;
  190. interrupts = <0 83 4
  191. 0 84 4
  192. 0 85 4>;
  193. cap-sd-highspeed;
  194. status = "disabled";
  195. };
  196. /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
  197. sdhi1: sdhi@ee120000 {
  198. compatible = "renesas,sdhi-r8a7740";
  199. reg = <0xee120000 0x100>;
  200. interrupt-parent = <&gic>;
  201. interrupts = <0 88 4
  202. 0 89 4>;
  203. toshiba,mmc-wrprotect-disable;
  204. cap-sd-highspeed;
  205. status = "disabled";
  206. };
  207. sdhi2: sdhi@ee140000 {
  208. compatible = "renesas,sdhi-r8a7740";
  209. reg = <0xee140000 0x100>;
  210. interrupt-parent = <&gic>;
  211. interrupts = <0 104 4
  212. 0 105 4>;
  213. toshiba,mmc-wrprotect-disable;
  214. cap-sd-highspeed;
  215. status = "disabled";
  216. };
  217. pfc: pfc@e6050000 {
  218. compatible = "renesas,pfc-sh73a0";
  219. reg = <0xe6050000 0x8000>,
  220. <0xe605801c 0x1c>;
  221. gpio-controller;
  222. #gpio-cells = <2>;
  223. };
  224. };