s3c64xx.dtsi 5.0 KB

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  1. /*
  2. * Samsung's S3C64xx SoC series common device tree source
  3. *
  4. * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
  5. *
  6. * Samsung's S3C64xx SoC series device nodes are listed in this file.
  7. * Particular SoCs from S3C64xx series can include this file and provide
  8. * values for SoCs specfic bindings.
  9. *
  10. * Note: This file does not include device nodes for all the controllers in
  11. * S3C64xx SoCs. As device tree coverage for S3C64xx increases, additional
  12. * nodes can be added to this file.
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License version 2 as
  16. * published by the Free Software Foundation.
  17. */
  18. #include "skeleton.dtsi"
  19. #include <dt-bindings/clock/samsung,s3c64xx-clock.h>
  20. / {
  21. aliases {
  22. i2c0 = &i2c0;
  23. pinctrl0 = &pinctrl0;
  24. };
  25. cpus {
  26. #address-cells = <1>;
  27. #size-cells = <0>;
  28. cpu@0 {
  29. device_type = "cpu";
  30. compatible = "arm,arm1176jzf-s", "arm,arm1176";
  31. reg = <0x0>;
  32. };
  33. };
  34. soc: soc {
  35. compatible = "simple-bus";
  36. #address-cells = <1>;
  37. #size-cells = <1>;
  38. ranges;
  39. vic0: interrupt-controller@71200000 {
  40. compatible = "arm,pl192-vic";
  41. interrupt-controller;
  42. reg = <0x71200000 0x1000>;
  43. #interrupt-cells = <1>;
  44. };
  45. vic1: interrupt-controller@71300000 {
  46. compatible = "arm,pl192-vic";
  47. interrupt-controller;
  48. reg = <0x71300000 0x1000>;
  49. #interrupt-cells = <1>;
  50. };
  51. sdhci0: sdhci@7c200000 {
  52. compatible = "samsung,s3c6410-sdhci";
  53. reg = <0x7c200000 0x100>;
  54. interrupt-parent = <&vic1>;
  55. interrupts = <24>;
  56. clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
  57. clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
  58. <&clocks SCLK_MMC0>;
  59. status = "disabled";
  60. };
  61. sdhci1: sdhci@7c300000 {
  62. compatible = "samsung,s3c6410-sdhci";
  63. reg = <0x7c300000 0x100>;
  64. interrupt-parent = <&vic1>;
  65. interrupts = <25>;
  66. clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
  67. clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
  68. <&clocks SCLK_MMC1>;
  69. status = "disabled";
  70. };
  71. sdhci2: sdhci@7c400000 {
  72. compatible = "samsung,s3c6410-sdhci";
  73. reg = <0x7c400000 0x100>;
  74. interrupt-parent = <&vic1>;
  75. interrupts = <17>;
  76. clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
  77. clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>,
  78. <&clocks SCLK_MMC2>;
  79. status = "disabled";
  80. };
  81. watchdog: watchdog@7e004000 {
  82. compatible = "samsung,s3c2410-wdt";
  83. reg = <0x7e004000 0x1000>;
  84. interrupt-parent = <&vic0>;
  85. interrupts = <26>;
  86. clock-names = "watchdog";
  87. clocks = <&clocks PCLK_WDT>;
  88. status = "disabled";
  89. };
  90. i2c0: i2c@7f004000 {
  91. compatible = "samsung,s3c2440-i2c";
  92. reg = <0x7f004000 0x1000>;
  93. interrupt-parent = <&vic1>;
  94. interrupts = <18>;
  95. clock-names = "i2c";
  96. clocks = <&clocks PCLK_IIC0>;
  97. status = "disabled";
  98. #address-cells = <1>;
  99. #size-cells = <0>;
  100. };
  101. uart0: serial@7f005000 {
  102. compatible = "samsung,s3c6400-uart";
  103. reg = <0x7f005000 0x100>;
  104. interrupt-parent = <&vic1>;
  105. interrupts = <5>;
  106. clock-names = "uart", "clk_uart_baud2",
  107. "clk_uart_baud3";
  108. clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
  109. <&clocks SCLK_UART>;
  110. status = "disabled";
  111. };
  112. uart1: serial@7f005400 {
  113. compatible = "samsung,s3c6400-uart";
  114. reg = <0x7f005400 0x100>;
  115. interrupt-parent = <&vic1>;
  116. interrupts = <6>;
  117. clock-names = "uart", "clk_uart_baud2",
  118. "clk_uart_baud3";
  119. clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
  120. <&clocks SCLK_UART>;
  121. status = "disabled";
  122. };
  123. uart2: serial@7f005800 {
  124. compatible = "samsung,s3c6400-uart";
  125. reg = <0x7f005800 0x100>;
  126. interrupt-parent = <&vic1>;
  127. interrupts = <7>;
  128. clock-names = "uart", "clk_uart_baud2",
  129. "clk_uart_baud3";
  130. clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
  131. <&clocks SCLK_UART>;
  132. status = "disabled";
  133. };
  134. uart3: serial@7f005c00 {
  135. compatible = "samsung,s3c6400-uart";
  136. reg = <0x7f005c00 0x100>;
  137. interrupt-parent = <&vic1>;
  138. interrupts = <8>;
  139. clock-names = "uart", "clk_uart_baud2",
  140. "clk_uart_baud3";
  141. clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
  142. <&clocks SCLK_UART>;
  143. status = "disabled";
  144. };
  145. pwm: pwm@7f006000 {
  146. compatible = "samsung,s3c6400-pwm";
  147. reg = <0x7f006000 0x1000>;
  148. interrupt-parent = <&vic0>;
  149. interrupts = <23>, <24>, <25>, <27>, <28>;
  150. clock-names = "timers";
  151. clocks = <&clocks PCLK_PWM>;
  152. samsung,pwm-outputs = <0>, <1>;
  153. #pwm-cells = <3>;
  154. status = "disabled";
  155. };
  156. pinctrl0: pinctrl@7f008000 {
  157. compatible = "samsung,s3c64xx-pinctrl";
  158. reg = <0x7f008000 0x1000>;
  159. interrupt-parent = <&vic1>;
  160. interrupts = <21>;
  161. pctrl_int_map: pinctrl-interrupt-map {
  162. interrupt-map = <0 &vic0 0>,
  163. <1 &vic0 1>,
  164. <2 &vic1 0>,
  165. <3 &vic1 1>;
  166. #address-cells = <0>;
  167. #size-cells = <0>;
  168. #interrupt-cells = <1>;
  169. };
  170. wakeup-interrupt-controller {
  171. compatible = "samsung,s3c64xx-wakeup-eint";
  172. interrupts = <0>, <1>, <2>, <3>;
  173. interrupt-parent = <&pctrl_int_map>;
  174. };
  175. };
  176. };
  177. };
  178. #include "s3c64xx-pinctrl.dtsi"