r8a7790.dtsi 6.0 KB

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  1. /*
  2. * Device Tree Source for the r8a7790 SoC
  3. *
  4. * Copyright (C) 2013 Renesas Solutions Corp.
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. */
  10. / {
  11. compatible = "renesas,r8a7790";
  12. interrupt-parent = <&gic>;
  13. #address-cells = <2>;
  14. #size-cells = <2>;
  15. cpus {
  16. #address-cells = <1>;
  17. #size-cells = <0>;
  18. cpu0: cpu@0 {
  19. device_type = "cpu";
  20. compatible = "arm,cortex-a15";
  21. reg = <0>;
  22. clock-frequency = <1300000000>;
  23. };
  24. cpu1: cpu@1 {
  25. device_type = "cpu";
  26. compatible = "arm,cortex-a15";
  27. reg = <1>;
  28. clock-frequency = <1300000000>;
  29. };
  30. cpu2: cpu@2 {
  31. device_type = "cpu";
  32. compatible = "arm,cortex-a15";
  33. reg = <2>;
  34. clock-frequency = <1300000000>;
  35. };
  36. cpu3: cpu@3 {
  37. device_type = "cpu";
  38. compatible = "arm,cortex-a15";
  39. reg = <3>;
  40. clock-frequency = <1300000000>;
  41. };
  42. cpu4: cpu@4 {
  43. device_type = "cpu";
  44. compatible = "arm,cortex-a7";
  45. reg = <0x100>;
  46. clock-frequency = <780000000>;
  47. };
  48. cpu5: cpu@5 {
  49. device_type = "cpu";
  50. compatible = "arm,cortex-a7";
  51. reg = <0x101>;
  52. clock-frequency = <780000000>;
  53. };
  54. cpu6: cpu@6 {
  55. device_type = "cpu";
  56. compatible = "arm,cortex-a7";
  57. reg = <0x102>;
  58. clock-frequency = <780000000>;
  59. };
  60. cpu7: cpu@7 {
  61. device_type = "cpu";
  62. compatible = "arm,cortex-a7";
  63. reg = <0x103>;
  64. clock-frequency = <780000000>;
  65. };
  66. };
  67. gic: interrupt-controller@f1001000 {
  68. compatible = "arm,cortex-a15-gic";
  69. #interrupt-cells = <3>;
  70. #address-cells = <0>;
  71. interrupt-controller;
  72. reg = <0 0xf1001000 0 0x1000>,
  73. <0 0xf1002000 0 0x1000>,
  74. <0 0xf1004000 0 0x2000>,
  75. <0 0xf1006000 0 0x2000>;
  76. interrupts = <1 9 0xf04>;
  77. };
  78. gpio0: gpio@ffc40000 {
  79. compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
  80. reg = <0 0xffc40000 0 0x2c>;
  81. interrupt-parent = <&gic>;
  82. interrupts = <0 4 0x4>;
  83. #gpio-cells = <2>;
  84. gpio-controller;
  85. gpio-ranges = <&pfc 0 0 32>;
  86. #interrupt-cells = <2>;
  87. interrupt-controller;
  88. };
  89. gpio1: gpio@ffc41000 {
  90. compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
  91. reg = <0 0xffc41000 0 0x2c>;
  92. interrupt-parent = <&gic>;
  93. interrupts = <0 5 0x4>;
  94. #gpio-cells = <2>;
  95. gpio-controller;
  96. gpio-ranges = <&pfc 0 32 32>;
  97. #interrupt-cells = <2>;
  98. interrupt-controller;
  99. };
  100. gpio2: gpio@ffc42000 {
  101. compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
  102. reg = <0 0xffc42000 0 0x2c>;
  103. interrupt-parent = <&gic>;
  104. interrupts = <0 6 0x4>;
  105. #gpio-cells = <2>;
  106. gpio-controller;
  107. gpio-ranges = <&pfc 0 64 32>;
  108. #interrupt-cells = <2>;
  109. interrupt-controller;
  110. };
  111. gpio3: gpio@ffc43000 {
  112. compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
  113. reg = <0 0xffc43000 0 0x2c>;
  114. interrupt-parent = <&gic>;
  115. interrupts = <0 7 0x4>;
  116. #gpio-cells = <2>;
  117. gpio-controller;
  118. gpio-ranges = <&pfc 0 96 32>;
  119. #interrupt-cells = <2>;
  120. interrupt-controller;
  121. };
  122. gpio4: gpio@ffc44000 {
  123. compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
  124. reg = <0 0xffc44000 0 0x2c>;
  125. interrupt-parent = <&gic>;
  126. interrupts = <0 8 0x4>;
  127. #gpio-cells = <2>;
  128. gpio-controller;
  129. gpio-ranges = <&pfc 0 128 32>;
  130. #interrupt-cells = <2>;
  131. interrupt-controller;
  132. };
  133. gpio5: gpio@ffc45000 {
  134. compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
  135. reg = <0 0xffc45000 0 0x2c>;
  136. interrupt-parent = <&gic>;
  137. interrupts = <0 9 0x4>;
  138. #gpio-cells = <2>;
  139. gpio-controller;
  140. gpio-ranges = <&pfc 0 160 32>;
  141. #interrupt-cells = <2>;
  142. interrupt-controller;
  143. };
  144. timer {
  145. compatible = "arm,armv7-timer";
  146. interrupts = <1 13 0xf08>,
  147. <1 14 0xf08>,
  148. <1 11 0xf08>,
  149. <1 10 0xf08>;
  150. };
  151. irqc0: interrupt-controller@e61c0000 {
  152. compatible = "renesas,irqc";
  153. #interrupt-cells = <2>;
  154. interrupt-controller;
  155. reg = <0 0xe61c0000 0 0x200>;
  156. interrupt-parent = <&gic>;
  157. interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>;
  158. };
  159. i2c0: i2c@e6508000 {
  160. #address-cells = <1>;
  161. #size-cells = <0>;
  162. compatible = "renesas,i2c-r8a7790";
  163. reg = <0 0xe6508000 0 0x40>;
  164. interrupt-parent = <&gic>;
  165. interrupts = <0 287 0x4>;
  166. status = "disabled";
  167. };
  168. i2c1: i2c@e6518000 {
  169. #address-cells = <1>;
  170. #size-cells = <0>;
  171. compatible = "renesas,i2c-r8a7790";
  172. reg = <0 0xe6518000 0 0x40>;
  173. interrupt-parent = <&gic>;
  174. interrupts = <0 288 0x4>;
  175. status = "disabled";
  176. };
  177. i2c2: i2c@e6530000 {
  178. #address-cells = <1>;
  179. #size-cells = <0>;
  180. compatible = "renesas,i2c-r8a7790";
  181. reg = <0 0xe6530000 0 0x40>;
  182. interrupt-parent = <&gic>;
  183. interrupts = <0 286 0x4>;
  184. status = "disabled";
  185. };
  186. i2c3: i2c@e6540000 {
  187. #address-cells = <1>;
  188. #size-cells = <0>;
  189. compatible = "renesas,i2c-r8a7790";
  190. reg = <0 0xe6540000 0 0x40>;
  191. interrupt-parent = <&gic>;
  192. interrupts = <0 290 0x4>;
  193. status = "disabled";
  194. };
  195. mmcif0: mmcif@ee200000 {
  196. compatible = "renesas,sh-mmcif";
  197. reg = <0 0xee200000 0 0x80>;
  198. interrupt-parent = <&gic>;
  199. interrupts = <0 169 0x4>;
  200. reg-io-width = <4>;
  201. status = "disabled";
  202. };
  203. mmcif1: mmcif@ee220000 {
  204. compatible = "renesas,sh-mmcif";
  205. reg = <0 0xee220000 0 0x80>;
  206. interrupt-parent = <&gic>;
  207. interrupts = <0 170 0x4>;
  208. reg-io-width = <4>;
  209. status = "disabled";
  210. };
  211. pfc: pfc@e6060000 {
  212. compatible = "renesas,pfc-r8a7790";
  213. reg = <0 0xe6060000 0 0x250>;
  214. };
  215. sdhi0: sdhi@ee100000 {
  216. compatible = "renesas,sdhi-r8a7790";
  217. reg = <0 0xee100000 0 0x100>;
  218. interrupt-parent = <&gic>;
  219. interrupts = <0 165 4>;
  220. cap-sd-highspeed;
  221. status = "disabled";
  222. };
  223. sdhi1: sdhi@ee120000 {
  224. compatible = "renesas,sdhi-r8a7790";
  225. reg = <0 0xee120000 0 0x100>;
  226. interrupt-parent = <&gic>;
  227. interrupts = <0 166 4>;
  228. cap-sd-highspeed;
  229. status = "disabled";
  230. };
  231. sdhi2: sdhi@ee140000 {
  232. compatible = "renesas,sdhi-r8a7790";
  233. reg = <0 0xee140000 0 0x100>;
  234. interrupt-parent = <&gic>;
  235. interrupts = <0 167 4>;
  236. cap-sd-highspeed;
  237. status = "disabled";
  238. };
  239. sdhi3: sdhi@ee160000 {
  240. compatible = "renesas,sdhi-r8a7790";
  241. reg = <0 0xee160000 0 0x100>;
  242. interrupt-parent = <&gic>;
  243. interrupts = <0 168 4>;
  244. cap-sd-highspeed;
  245. status = "disabled";
  246. };
  247. };