kirkwood.dtsi 6.4 KB

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  1. /include/ "skeleton.dtsi"
  2. #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
  3. / {
  4. compatible = "marvell,kirkwood";
  5. interrupt-parent = <&intc>;
  6. cpus {
  7. #address-cells = <1>;
  8. #size-cells = <0>;
  9. cpu@0 {
  10. device_type = "cpu";
  11. compatible = "marvell,feroceon";
  12. reg = <0>;
  13. clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
  14. clock-names = "cpu_clk", "ddrclk", "powersave";
  15. };
  16. };
  17. aliases {
  18. gpio0 = &gpio0;
  19. gpio1 = &gpio1;
  20. };
  21. mbus {
  22. compatible = "marvell,kirkwood-mbus", "simple-bus";
  23. #address-cells = <2>;
  24. #size-cells = <1>;
  25. /* If a board file needs to change this ranges it must replace it completely */
  26. ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */
  27. MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */
  28. MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */
  29. >;
  30. controller = <&mbusc>;
  31. pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
  32. pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
  33. crypto@0301 {
  34. compatible = "marvell,orion-crypto";
  35. reg = <MBUS_ID(0xf0, 0x01) 0x30000 0x10000>,
  36. <MBUS_ID(0x03, 0x01) 0 0x800>;
  37. reg-names = "regs", "sram";
  38. interrupts = <22>;
  39. clocks = <&gate_clk 17>;
  40. status = "okay";
  41. };
  42. nand: nand@012f {
  43. #address-cells = <1>;
  44. #size-cells = <1>;
  45. cle = <0>;
  46. ale = <1>;
  47. bank-width = <1>;
  48. compatible = "marvell,orion-nand";
  49. reg = <MBUS_ID(0x01, 0x2f) 0 0x400>;
  50. chip-delay = <25>;
  51. /* set partition map and/or chip-delay in board dts */
  52. clocks = <&gate_clk 7>;
  53. status = "disabled";
  54. };
  55. };
  56. ocp@f1000000 {
  57. compatible = "simple-bus";
  58. ranges = <0x00000000 0xf1000000 0x0100000>;
  59. #address-cells = <1>;
  60. #size-cells = <1>;
  61. mbusc: mbus-controller@20000 {
  62. compatible = "marvell,mbus-controller";
  63. reg = <0x20000 0x80>, <0x1500 0x20>;
  64. };
  65. timer: timer@20300 {
  66. compatible = "marvell,orion-timer";
  67. reg = <0x20300 0x20>;
  68. interrupt-parent = <&bridge_intc>;
  69. interrupts = <1>, <2>;
  70. clocks = <&core_clk 0>;
  71. };
  72. intc: main-interrupt-ctrl@20200 {
  73. compatible = "marvell,orion-intc";
  74. interrupt-controller;
  75. #interrupt-cells = <1>;
  76. reg = <0x20200 0x10>, <0x20210 0x10>;
  77. };
  78. bridge_intc: bridge-interrupt-ctrl@20110 {
  79. compatible = "marvell,orion-bridge-intc";
  80. interrupt-controller;
  81. #interrupt-cells = <1>;
  82. reg = <0x20110 0x8>;
  83. interrupts = <1>;
  84. marvell,#interrupts = <6>;
  85. };
  86. core_clk: core-clocks@10030 {
  87. compatible = "marvell,kirkwood-core-clock";
  88. reg = <0x10030 0x4>;
  89. #clock-cells = <1>;
  90. };
  91. gpio0: gpio@10100 {
  92. compatible = "marvell,orion-gpio";
  93. #gpio-cells = <2>;
  94. gpio-controller;
  95. reg = <0x10100 0x40>;
  96. ngpios = <32>;
  97. interrupt-controller;
  98. #interrupt-cells = <2>;
  99. interrupts = <35>, <36>, <37>, <38>;
  100. clocks = <&gate_clk 7>;
  101. };
  102. gpio1: gpio@10140 {
  103. compatible = "marvell,orion-gpio";
  104. #gpio-cells = <2>;
  105. gpio-controller;
  106. reg = <0x10140 0x40>;
  107. ngpios = <18>;
  108. interrupt-controller;
  109. #interrupt-cells = <2>;
  110. interrupts = <39>, <40>, <41>;
  111. clocks = <&gate_clk 7>;
  112. };
  113. serial@12000 {
  114. compatible = "ns16550a";
  115. reg = <0x12000 0x100>;
  116. reg-shift = <2>;
  117. interrupts = <33>;
  118. clocks = <&gate_clk 7>;
  119. status = "disabled";
  120. };
  121. serial@12100 {
  122. compatible = "ns16550a";
  123. reg = <0x12100 0x100>;
  124. reg-shift = <2>;
  125. interrupts = <34>;
  126. clocks = <&gate_clk 7>;
  127. status = "disabled";
  128. };
  129. spi@10600 {
  130. compatible = "marvell,orion-spi";
  131. #address-cells = <1>;
  132. #size-cells = <0>;
  133. cell-index = <0>;
  134. interrupts = <23>;
  135. reg = <0x10600 0x28>;
  136. clocks = <&gate_clk 7>;
  137. status = "disabled";
  138. };
  139. gate_clk: clock-gating-control@2011c {
  140. compatible = "marvell,kirkwood-gating-clock";
  141. reg = <0x2011c 0x4>;
  142. clocks = <&core_clk 0>;
  143. #clock-cells = <1>;
  144. };
  145. wdt: watchdog-timer@20300 {
  146. compatible = "marvell,orion-wdt";
  147. reg = <0x20300 0x28>;
  148. interrupt-parent = <&bridge_intc>;
  149. interrupts = <3>;
  150. clocks = <&gate_clk 7>;
  151. status = "okay";
  152. };
  153. xor@60800 {
  154. compatible = "marvell,orion-xor";
  155. reg = <0x60800 0x100
  156. 0x60A00 0x100>;
  157. status = "okay";
  158. clocks = <&gate_clk 8>;
  159. xor00 {
  160. interrupts = <5>;
  161. dmacap,memcpy;
  162. dmacap,xor;
  163. };
  164. xor01 {
  165. interrupts = <6>;
  166. dmacap,memcpy;
  167. dmacap,xor;
  168. dmacap,memset;
  169. };
  170. };
  171. xor@60900 {
  172. compatible = "marvell,orion-xor";
  173. reg = <0x60900 0x100
  174. 0x60B00 0x100>;
  175. status = "okay";
  176. clocks = <&gate_clk 16>;
  177. xor00 {
  178. interrupts = <7>;
  179. dmacap,memcpy;
  180. dmacap,xor;
  181. };
  182. xor01 {
  183. interrupts = <8>;
  184. dmacap,memcpy;
  185. dmacap,xor;
  186. dmacap,memset;
  187. };
  188. };
  189. ehci@50000 {
  190. compatible = "marvell,orion-ehci";
  191. reg = <0x50000 0x1000>;
  192. interrupts = <19>;
  193. clocks = <&gate_clk 3>;
  194. status = "okay";
  195. };
  196. i2c@11000 {
  197. compatible = "marvell,mv64xxx-i2c";
  198. reg = <0x11000 0x20>;
  199. #address-cells = <1>;
  200. #size-cells = <0>;
  201. interrupts = <29>;
  202. clock-frequency = <100000>;
  203. clocks = <&gate_clk 7>;
  204. status = "disabled";
  205. };
  206. mdio: mdio-bus@72004 {
  207. compatible = "marvell,orion-mdio";
  208. #address-cells = <1>;
  209. #size-cells = <0>;
  210. reg = <0x72004 0x84>;
  211. interrupts = <46>;
  212. clocks = <&gate_clk 0>;
  213. status = "disabled";
  214. /* add phy nodes in board file */
  215. };
  216. eth0: ethernet-controller@72000 {
  217. compatible = "marvell,kirkwood-eth";
  218. #address-cells = <1>;
  219. #size-cells = <0>;
  220. reg = <0x72000 0x4000>;
  221. clocks = <&gate_clk 0>;
  222. marvell,tx-checksum-limit = <1600>;
  223. status = "disabled";
  224. ethernet0-port@0 {
  225. device_type = "network";
  226. compatible = "marvell,kirkwood-eth-port";
  227. reg = <0>;
  228. interrupts = <11>;
  229. /* overwrite MAC address in bootloader */
  230. local-mac-address = [00 00 00 00 00 00];
  231. /* set phy-handle property in board file */
  232. };
  233. };
  234. eth1: ethernet-controller@76000 {
  235. compatible = "marvell,kirkwood-eth";
  236. #address-cells = <1>;
  237. #size-cells = <0>;
  238. reg = <0x76000 0x4000>;
  239. clocks = <&gate_clk 19>;
  240. marvell,tx-checksum-limit = <1600>;
  241. status = "disabled";
  242. ethernet1-port@0 {
  243. device_type = "network";
  244. compatible = "marvell,kirkwood-eth-port";
  245. reg = <0>;
  246. interrupts = <15>;
  247. /* overwrite MAC address in bootloader */
  248. local-mac-address = [00 00 00 00 00 00];
  249. /* set phy-handle property in board file */
  250. };
  251. };
  252. };
  253. };