imx23.dtsi 12 KB

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  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. #include "skeleton.dtsi"
  12. #include "imx23-pinfunc.h"
  13. / {
  14. interrupt-parent = <&icoll>;
  15. aliases {
  16. gpio0 = &gpio0;
  17. gpio1 = &gpio1;
  18. gpio2 = &gpio2;
  19. serial0 = &auart0;
  20. serial1 = &auart1;
  21. spi0 = &ssp0;
  22. spi1 = &ssp1;
  23. };
  24. cpus {
  25. #address-cells = <0>;
  26. #size-cells = <0>;
  27. cpu {
  28. compatible = "arm,arm926ej-s";
  29. device_type = "cpu";
  30. };
  31. };
  32. apb@80000000 {
  33. compatible = "simple-bus";
  34. #address-cells = <1>;
  35. #size-cells = <1>;
  36. reg = <0x80000000 0x80000>;
  37. ranges;
  38. apbh@80000000 {
  39. compatible = "simple-bus";
  40. #address-cells = <1>;
  41. #size-cells = <1>;
  42. reg = <0x80000000 0x40000>;
  43. ranges;
  44. icoll: interrupt-controller@80000000 {
  45. compatible = "fsl,imx23-icoll", "fsl,icoll";
  46. interrupt-controller;
  47. #interrupt-cells = <1>;
  48. reg = <0x80000000 0x2000>;
  49. };
  50. dma_apbh: dma-apbh@80004000 {
  51. compatible = "fsl,imx23-dma-apbh";
  52. reg = <0x80004000 0x2000>;
  53. interrupts = <0 14 20 0
  54. 13 13 13 13>;
  55. interrupt-names = "empty", "ssp0", "ssp1", "empty",
  56. "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  57. #dma-cells = <1>;
  58. dma-channels = <8>;
  59. clocks = <&clks 15>;
  60. };
  61. ecc@80008000 {
  62. reg = <0x80008000 0x2000>;
  63. status = "disabled";
  64. };
  65. gpmi-nand@8000c000 {
  66. compatible = "fsl,imx23-gpmi-nand";
  67. #address-cells = <1>;
  68. #size-cells = <1>;
  69. reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
  70. reg-names = "gpmi-nand", "bch";
  71. interrupts = <56>;
  72. interrupt-names = "bch";
  73. clocks = <&clks 34>;
  74. clock-names = "gpmi_io";
  75. dmas = <&dma_apbh 4>;
  76. dma-names = "rx-tx";
  77. status = "disabled";
  78. };
  79. ssp0: ssp@80010000 {
  80. reg = <0x80010000 0x2000>;
  81. interrupts = <15>;
  82. clocks = <&clks 33>;
  83. dmas = <&dma_apbh 1>;
  84. dma-names = "rx-tx";
  85. status = "disabled";
  86. };
  87. etm@80014000 {
  88. reg = <0x80014000 0x2000>;
  89. status = "disabled";
  90. };
  91. pinctrl@80018000 {
  92. #address-cells = <1>;
  93. #size-cells = <0>;
  94. compatible = "fsl,imx23-pinctrl", "simple-bus";
  95. reg = <0x80018000 0x2000>;
  96. gpio0: gpio@0 {
  97. compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
  98. interrupts = <16>;
  99. gpio-controller;
  100. #gpio-cells = <2>;
  101. interrupt-controller;
  102. #interrupt-cells = <2>;
  103. };
  104. gpio1: gpio@1 {
  105. compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
  106. interrupts = <17>;
  107. gpio-controller;
  108. #gpio-cells = <2>;
  109. interrupt-controller;
  110. #interrupt-cells = <2>;
  111. };
  112. gpio2: gpio@2 {
  113. compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
  114. interrupts = <18>;
  115. gpio-controller;
  116. #gpio-cells = <2>;
  117. interrupt-controller;
  118. #interrupt-cells = <2>;
  119. };
  120. duart_pins_a: duart@0 {
  121. reg = <0>;
  122. fsl,pinmux-ids = <
  123. MX23_PAD_PWM0__DUART_RX
  124. MX23_PAD_PWM1__DUART_TX
  125. >;
  126. fsl,drive-strength = <MXS_DRIVE_4mA>;
  127. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  128. fsl,pull-up = <MXS_PULL_DISABLE>;
  129. };
  130. auart0_pins_a: auart0@0 {
  131. reg = <0>;
  132. fsl,pinmux-ids = <
  133. MX23_PAD_AUART1_RX__AUART1_RX
  134. MX23_PAD_AUART1_TX__AUART1_TX
  135. MX23_PAD_AUART1_CTS__AUART1_CTS
  136. MX23_PAD_AUART1_RTS__AUART1_RTS
  137. >;
  138. fsl,drive-strength = <MXS_DRIVE_4mA>;
  139. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  140. fsl,pull-up = <MXS_PULL_DISABLE>;
  141. };
  142. auart0_2pins_a: auart0-2pins@0 {
  143. reg = <0>;
  144. fsl,pinmux-ids = <
  145. MX23_PAD_I2C_SCL__AUART1_TX
  146. MX23_PAD_I2C_SDA__AUART1_RX
  147. >;
  148. fsl,drive-strength = <MXS_DRIVE_4mA>;
  149. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  150. fsl,pull-up = <MXS_PULL_DISABLE>;
  151. };
  152. gpmi_pins_a: gpmi-nand@0 {
  153. reg = <0>;
  154. fsl,pinmux-ids = <
  155. MX23_PAD_GPMI_D00__GPMI_D00
  156. MX23_PAD_GPMI_D01__GPMI_D01
  157. MX23_PAD_GPMI_D02__GPMI_D02
  158. MX23_PAD_GPMI_D03__GPMI_D03
  159. MX23_PAD_GPMI_D04__GPMI_D04
  160. MX23_PAD_GPMI_D05__GPMI_D05
  161. MX23_PAD_GPMI_D06__GPMI_D06
  162. MX23_PAD_GPMI_D07__GPMI_D07
  163. MX23_PAD_GPMI_CLE__GPMI_CLE
  164. MX23_PAD_GPMI_ALE__GPMI_ALE
  165. MX23_PAD_GPMI_RDY0__GPMI_RDY0
  166. MX23_PAD_GPMI_RDY1__GPMI_RDY1
  167. MX23_PAD_GPMI_WPN__GPMI_WPN
  168. MX23_PAD_GPMI_WRN__GPMI_WRN
  169. MX23_PAD_GPMI_RDN__GPMI_RDN
  170. MX23_PAD_GPMI_CE1N__GPMI_CE1N
  171. MX23_PAD_GPMI_CE0N__GPMI_CE0N
  172. >;
  173. fsl,drive-strength = <MXS_DRIVE_4mA>;
  174. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  175. fsl,pull-up = <MXS_PULL_DISABLE>;
  176. };
  177. gpmi_pins_fixup: gpmi-pins-fixup {
  178. fsl,pinmux-ids = <
  179. MX23_PAD_GPMI_WPN__GPMI_WPN
  180. MX23_PAD_GPMI_WRN__GPMI_WRN
  181. MX23_PAD_GPMI_RDN__GPMI_RDN
  182. >;
  183. fsl,drive-strength = <MXS_DRIVE_12mA>;
  184. };
  185. mmc0_4bit_pins_a: mmc0-4bit@0 {
  186. reg = <0>;
  187. fsl,pinmux-ids = <
  188. MX23_PAD_SSP1_DATA0__SSP1_DATA0
  189. MX23_PAD_SSP1_DATA1__SSP1_DATA1
  190. MX23_PAD_SSP1_DATA2__SSP1_DATA2
  191. MX23_PAD_SSP1_DATA3__SSP1_DATA3
  192. MX23_PAD_SSP1_CMD__SSP1_CMD
  193. MX23_PAD_SSP1_SCK__SSP1_SCK
  194. >;
  195. fsl,drive-strength = <MXS_DRIVE_8mA>;
  196. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  197. fsl,pull-up = <MXS_PULL_ENABLE>;
  198. };
  199. mmc0_8bit_pins_a: mmc0-8bit@0 {
  200. reg = <0>;
  201. fsl,pinmux-ids = <
  202. MX23_PAD_SSP1_DATA0__SSP1_DATA0
  203. MX23_PAD_SSP1_DATA1__SSP1_DATA1
  204. MX23_PAD_SSP1_DATA2__SSP1_DATA2
  205. MX23_PAD_SSP1_DATA3__SSP1_DATA3
  206. MX23_PAD_GPMI_D08__SSP1_DATA4
  207. MX23_PAD_GPMI_D09__SSP1_DATA5
  208. MX23_PAD_GPMI_D10__SSP1_DATA6
  209. MX23_PAD_GPMI_D11__SSP1_DATA7
  210. MX23_PAD_SSP1_CMD__SSP1_CMD
  211. MX23_PAD_SSP1_DETECT__SSP1_DETECT
  212. MX23_PAD_SSP1_SCK__SSP1_SCK
  213. >;
  214. fsl,drive-strength = <MXS_DRIVE_8mA>;
  215. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  216. fsl,pull-up = <MXS_PULL_ENABLE>;
  217. };
  218. mmc0_pins_fixup: mmc0-pins-fixup {
  219. fsl,pinmux-ids = <
  220. MX23_PAD_SSP1_DETECT__SSP1_DETECT
  221. MX23_PAD_SSP1_SCK__SSP1_SCK
  222. >;
  223. fsl,pull-up = <MXS_PULL_DISABLE>;
  224. };
  225. pwm2_pins_a: pwm2@0 {
  226. reg = <0>;
  227. fsl,pinmux-ids = <
  228. MX23_PAD_PWM2__PWM2
  229. >;
  230. fsl,drive-strength = <MXS_DRIVE_4mA>;
  231. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  232. fsl,pull-up = <MXS_PULL_DISABLE>;
  233. };
  234. lcdif_24bit_pins_a: lcdif-24bit@0 {
  235. reg = <0>;
  236. fsl,pinmux-ids = <
  237. MX23_PAD_LCD_D00__LCD_D00
  238. MX23_PAD_LCD_D01__LCD_D01
  239. MX23_PAD_LCD_D02__LCD_D02
  240. MX23_PAD_LCD_D03__LCD_D03
  241. MX23_PAD_LCD_D04__LCD_D04
  242. MX23_PAD_LCD_D05__LCD_D05
  243. MX23_PAD_LCD_D06__LCD_D06
  244. MX23_PAD_LCD_D07__LCD_D07
  245. MX23_PAD_LCD_D08__LCD_D08
  246. MX23_PAD_LCD_D09__LCD_D09
  247. MX23_PAD_LCD_D10__LCD_D10
  248. MX23_PAD_LCD_D11__LCD_D11
  249. MX23_PAD_LCD_D12__LCD_D12
  250. MX23_PAD_LCD_D13__LCD_D13
  251. MX23_PAD_LCD_D14__LCD_D14
  252. MX23_PAD_LCD_D15__LCD_D15
  253. MX23_PAD_LCD_D16__LCD_D16
  254. MX23_PAD_LCD_D17__LCD_D17
  255. MX23_PAD_GPMI_D08__LCD_D18
  256. MX23_PAD_GPMI_D09__LCD_D19
  257. MX23_PAD_GPMI_D10__LCD_D20
  258. MX23_PAD_GPMI_D11__LCD_D21
  259. MX23_PAD_GPMI_D12__LCD_D22
  260. MX23_PAD_GPMI_D13__LCD_D23
  261. MX23_PAD_LCD_DOTCK__LCD_DOTCK
  262. MX23_PAD_LCD_ENABLE__LCD_ENABLE
  263. MX23_PAD_LCD_HSYNC__LCD_HSYNC
  264. MX23_PAD_LCD_VSYNC__LCD_VSYNC
  265. >;
  266. fsl,drive-strength = <MXS_DRIVE_4mA>;
  267. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  268. fsl,pull-up = <MXS_PULL_DISABLE>;
  269. };
  270. spi2_pins_a: spi2@0 {
  271. reg = <0>;
  272. fsl,pinmux-ids = <
  273. MX23_PAD_GPMI_WRN__SSP2_SCK
  274. MX23_PAD_GPMI_RDY1__SSP2_CMD
  275. MX23_PAD_GPMI_D00__SSP2_DATA0
  276. MX23_PAD_GPMI_D03__SSP2_DATA3
  277. >;
  278. fsl,drive-strength = <MXS_DRIVE_8mA>;
  279. fsl,voltage = <MXS_VOLTAGE_HIGH>;
  280. fsl,pull-up = <MXS_PULL_ENABLE>;
  281. };
  282. };
  283. digctl@8001c000 {
  284. compatible = "fsl,imx23-digctl";
  285. reg = <0x8001c000 2000>;
  286. status = "disabled";
  287. };
  288. emi@80020000 {
  289. reg = <0x80020000 0x2000>;
  290. status = "disabled";
  291. };
  292. dma_apbx: dma-apbx@80024000 {
  293. compatible = "fsl,imx23-dma-apbx";
  294. reg = <0x80024000 0x2000>;
  295. interrupts = <7 5 9 26
  296. 19 0 25 23
  297. 60 58 9 0
  298. 0 0 0 0>;
  299. interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c",
  300. "saif0", "empty", "auart0-rx", "auart0-tx",
  301. "auart1-rx", "auart1-tx", "saif1", "empty",
  302. "empty", "empty", "empty", "empty";
  303. #dma-cells = <1>;
  304. dma-channels = <16>;
  305. clocks = <&clks 16>;
  306. };
  307. dcp@80028000 {
  308. reg = <0x80028000 0x2000>;
  309. status = "disabled";
  310. };
  311. pxp@8002a000 {
  312. reg = <0x8002a000 0x2000>;
  313. status = "disabled";
  314. };
  315. ocotp@8002c000 {
  316. compatible = "fsl,ocotp";
  317. reg = <0x8002c000 0x2000>;
  318. status = "disabled";
  319. };
  320. axi-ahb@8002e000 {
  321. reg = <0x8002e000 0x2000>;
  322. status = "disabled";
  323. };
  324. lcdif@80030000 {
  325. compatible = "fsl,imx23-lcdif";
  326. reg = <0x80030000 2000>;
  327. interrupts = <46 45>;
  328. clocks = <&clks 38>;
  329. status = "disabled";
  330. };
  331. ssp1: ssp@80034000 {
  332. reg = <0x80034000 0x2000>;
  333. interrupts = <2>;
  334. clocks = <&clks 33>;
  335. dmas = <&dma_apbh 2>;
  336. dma-names = "rx-tx";
  337. status = "disabled";
  338. };
  339. tvenc@80038000 {
  340. reg = <0x80038000 0x2000>;
  341. status = "disabled";
  342. };
  343. };
  344. apbx@80040000 {
  345. compatible = "simple-bus";
  346. #address-cells = <1>;
  347. #size-cells = <1>;
  348. reg = <0x80040000 0x40000>;
  349. ranges;
  350. clks: clkctrl@80040000 {
  351. compatible = "fsl,imx23-clkctrl", "fsl,clkctrl";
  352. reg = <0x80040000 0x2000>;
  353. #clock-cells = <1>;
  354. };
  355. saif0: saif@80042000 {
  356. reg = <0x80042000 0x2000>;
  357. dmas = <&dma_apbx 4>;
  358. dma-names = "rx-tx";
  359. status = "disabled";
  360. };
  361. power@80044000 {
  362. reg = <0x80044000 0x2000>;
  363. status = "disabled";
  364. };
  365. saif1: saif@80046000 {
  366. reg = <0x80046000 0x2000>;
  367. dmas = <&dma_apbx 10>;
  368. dma-names = "rx-tx";
  369. status = "disabled";
  370. };
  371. audio-out@80048000 {
  372. reg = <0x80048000 0x2000>;
  373. dmas = <&dma_apbx 1>;
  374. dma-names = "tx";
  375. status = "disabled";
  376. };
  377. audio-in@8004c000 {
  378. reg = <0x8004c000 0x2000>;
  379. dmas = <&dma_apbx 0>;
  380. dma-names = "rx";
  381. status = "disabled";
  382. };
  383. lradc@80050000 {
  384. compatible = "fsl,imx23-lradc";
  385. reg = <0x80050000 0x2000>;
  386. interrupts = <36 37 38 39 40 41 42 43 44>;
  387. status = "disabled";
  388. clocks = <&clks 26>;
  389. };
  390. spdif@80054000 {
  391. reg = <0x80054000 2000>;
  392. dmas = <&dma_apbx 2>;
  393. dma-names = "tx";
  394. status = "disabled";
  395. };
  396. i2c@80058000 {
  397. reg = <0x80058000 0x2000>;
  398. dmas = <&dma_apbx 3>;
  399. dma-names = "rx-tx";
  400. status = "disabled";
  401. };
  402. rtc@8005c000 {
  403. compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc";
  404. reg = <0x8005c000 0x2000>;
  405. interrupts = <22>;
  406. };
  407. pwm: pwm@80064000 {
  408. compatible = "fsl,imx23-pwm";
  409. reg = <0x80064000 0x2000>;
  410. clocks = <&clks 30>;
  411. #pwm-cells = <2>;
  412. fsl,pwm-number = <5>;
  413. status = "disabled";
  414. };
  415. timrot@80068000 {
  416. compatible = "fsl,imx23-timrot", "fsl,timrot";
  417. reg = <0x80068000 0x2000>;
  418. interrupts = <28 29 30 31>;
  419. clocks = <&clks 28>;
  420. };
  421. auart0: serial@8006c000 {
  422. compatible = "fsl,imx23-auart";
  423. reg = <0x8006c000 0x2000>;
  424. interrupts = <24>;
  425. clocks = <&clks 32>;
  426. dmas = <&dma_apbx 6>, <&dma_apbx 7>;
  427. dma-names = "rx", "tx";
  428. status = "disabled";
  429. };
  430. auart1: serial@8006e000 {
  431. compatible = "fsl,imx23-auart";
  432. reg = <0x8006e000 0x2000>;
  433. interrupts = <59>;
  434. clocks = <&clks 32>;
  435. dmas = <&dma_apbx 8>, <&dma_apbx 9>;
  436. dma-names = "rx", "tx";
  437. status = "disabled";
  438. };
  439. duart: serial@80070000 {
  440. compatible = "arm,pl011", "arm,primecell";
  441. reg = <0x80070000 0x2000>;
  442. interrupts = <0>;
  443. clocks = <&clks 32>, <&clks 16>;
  444. clock-names = "uart", "apb_pclk";
  445. status = "disabled";
  446. };
  447. usbphy0: usbphy@8007c000 {
  448. compatible = "fsl,imx23-usbphy";
  449. reg = <0x8007c000 0x2000>;
  450. clocks = <&clks 41>;
  451. status = "disabled";
  452. };
  453. };
  454. };
  455. ahb@80080000 {
  456. compatible = "simple-bus";
  457. #address-cells = <1>;
  458. #size-cells = <1>;
  459. reg = <0x80080000 0x80000>;
  460. ranges;
  461. usb0: usb@80080000 {
  462. compatible = "fsl,imx23-usb", "fsl,imx27-usb";
  463. reg = <0x80080000 0x40000>;
  464. interrupts = <11>;
  465. fsl,usbphy = <&usbphy0>;
  466. clocks = <&clks 40>;
  467. status = "disabled";
  468. };
  469. };
  470. };