i915_drv.h 40 KB

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  1. /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
  2. */
  3. /*
  4. *
  5. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  6. * All Rights Reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the
  10. * "Software"), to deal in the Software without restriction, including
  11. * without limitation the rights to use, copy, modify, merge, publish,
  12. * distribute, sub license, and/or sell copies of the Software, and to
  13. * permit persons to whom the Software is furnished to do so, subject to
  14. * the following conditions:
  15. *
  16. * The above copyright notice and this permission notice (including the
  17. * next paragraph) shall be included in all copies or substantial portions
  18. * of the Software.
  19. *
  20. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27. *
  28. */
  29. #ifndef _I915_DRV_H_
  30. #define _I915_DRV_H_
  31. #include "i915_reg.h"
  32. #include "intel_bios.h"
  33. #include "intel_ringbuffer.h"
  34. #include <linux/io-mapping.h>
  35. #include <linux/i2c.h>
  36. #include <drm/intel-gtt.h>
  37. /* General customization:
  38. */
  39. #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
  40. #define DRIVER_NAME "i915"
  41. #define DRIVER_DESC "Intel Graphics"
  42. #define DRIVER_DATE "20080730"
  43. enum pipe {
  44. PIPE_A = 0,
  45. PIPE_B,
  46. };
  47. enum plane {
  48. PLANE_A = 0,
  49. PLANE_B,
  50. };
  51. #define I915_NUM_PIPE 2
  52. #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  53. /* Interface history:
  54. *
  55. * 1.1: Original.
  56. * 1.2: Add Power Management
  57. * 1.3: Add vblank support
  58. * 1.4: Fix cmdbuffer path, add heap destroy
  59. * 1.5: Add vblank pipe configuration
  60. * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  61. * - Support vertical blank on secondary display pipe
  62. */
  63. #define DRIVER_MAJOR 1
  64. #define DRIVER_MINOR 6
  65. #define DRIVER_PATCHLEVEL 0
  66. #define WATCH_COHERENCY 0
  67. #define WATCH_EXEC 0
  68. #define WATCH_RELOC 0
  69. #define WATCH_LISTS 0
  70. #define WATCH_PWRITE 0
  71. #define I915_GEM_PHYS_CURSOR_0 1
  72. #define I915_GEM_PHYS_CURSOR_1 2
  73. #define I915_GEM_PHYS_OVERLAY_REGS 3
  74. #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
  75. struct drm_i915_gem_phys_object {
  76. int id;
  77. struct page **page_list;
  78. drm_dma_handle_t *handle;
  79. struct drm_gem_object *cur_obj;
  80. };
  81. struct mem_block {
  82. struct mem_block *next;
  83. struct mem_block *prev;
  84. int start;
  85. int size;
  86. struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
  87. };
  88. struct opregion_header;
  89. struct opregion_acpi;
  90. struct opregion_swsci;
  91. struct opregion_asle;
  92. struct intel_opregion {
  93. struct opregion_header *header;
  94. struct opregion_acpi *acpi;
  95. struct opregion_swsci *swsci;
  96. struct opregion_asle *asle;
  97. void *vbt;
  98. };
  99. #define OPREGION_SIZE (8*1024)
  100. struct intel_overlay;
  101. struct intel_overlay_error_state;
  102. struct drm_i915_master_private {
  103. drm_local_map_t *sarea;
  104. struct _drm_i915_sarea *sarea_priv;
  105. };
  106. #define I915_FENCE_REG_NONE -1
  107. struct drm_i915_fence_reg {
  108. struct drm_gem_object *obj;
  109. struct list_head lru_list;
  110. bool gpu;
  111. };
  112. struct sdvo_device_mapping {
  113. u8 initialized;
  114. u8 dvo_port;
  115. u8 slave_addr;
  116. u8 dvo_wiring;
  117. u8 i2c_pin;
  118. u8 i2c_speed;
  119. u8 ddc_pin;
  120. };
  121. struct drm_i915_error_state {
  122. u32 eir;
  123. u32 pgtbl_er;
  124. u32 pipeastat;
  125. u32 pipebstat;
  126. u32 ipeir;
  127. u32 ipehr;
  128. u32 instdone;
  129. u32 acthd;
  130. u32 instpm;
  131. u32 instps;
  132. u32 instdone1;
  133. u32 seqno;
  134. u64 bbaddr;
  135. struct timeval time;
  136. struct drm_i915_error_object {
  137. int page_count;
  138. u32 gtt_offset;
  139. u32 *pages[0];
  140. } *ringbuffer, *batchbuffer[2];
  141. struct drm_i915_error_buffer {
  142. size_t size;
  143. u32 name;
  144. u32 seqno;
  145. u32 gtt_offset;
  146. u32 read_domains;
  147. u32 write_domain;
  148. u32 fence_reg;
  149. s32 pinned:2;
  150. u32 tiling:2;
  151. u32 dirty:1;
  152. u32 purgeable:1;
  153. } *active_bo;
  154. u32 active_bo_count;
  155. struct intel_overlay_error_state *overlay;
  156. };
  157. struct drm_i915_display_funcs {
  158. void (*dpms)(struct drm_crtc *crtc, int mode);
  159. bool (*fbc_enabled)(struct drm_device *dev);
  160. void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
  161. void (*disable_fbc)(struct drm_device *dev);
  162. int (*get_display_clock_speed)(struct drm_device *dev);
  163. int (*get_fifo_size)(struct drm_device *dev, int plane);
  164. void (*update_wm)(struct drm_device *dev, int planea_clock,
  165. int planeb_clock, int sr_hdisplay, int sr_htotal,
  166. int pixel_size);
  167. /* clock updates for mode set */
  168. /* cursor updates */
  169. /* render clock increase/decrease */
  170. /* display clock increase/decrease */
  171. /* pll clock increase/decrease */
  172. /* clock gating init */
  173. };
  174. struct intel_device_info {
  175. u8 gen;
  176. u8 is_mobile : 1;
  177. u8 is_i85x : 1;
  178. u8 is_i915g : 1;
  179. u8 is_i945gm : 1;
  180. u8 is_g33 : 1;
  181. u8 need_gfx_hws : 1;
  182. u8 is_g4x : 1;
  183. u8 is_pineview : 1;
  184. u8 is_broadwater : 1;
  185. u8 is_crestline : 1;
  186. u8 is_ironlake : 1;
  187. u8 has_fbc : 1;
  188. u8 has_rc6 : 1;
  189. u8 has_pipe_cxsr : 1;
  190. u8 has_hotplug : 1;
  191. u8 cursor_needs_physical : 1;
  192. u8 has_overlay : 1;
  193. u8 overlay_needs_physical : 1;
  194. u8 supports_tv : 1;
  195. u8 has_bsd_ring : 1;
  196. u8 has_blt_ring : 1;
  197. };
  198. enum no_fbc_reason {
  199. FBC_NO_OUTPUT, /* no outputs enabled to compress */
  200. FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
  201. FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
  202. FBC_MODE_TOO_LARGE, /* mode too large for compression */
  203. FBC_BAD_PLANE, /* fbc not supported on plane */
  204. FBC_NOT_TILED, /* buffer not tiled */
  205. FBC_MULTIPLE_PIPES, /* more than one pipe active */
  206. };
  207. enum intel_pch {
  208. PCH_IBX, /* Ibexpeak PCH */
  209. PCH_CPT, /* Cougarpoint PCH */
  210. };
  211. #define QUIRK_PIPEA_FORCE (1<<0)
  212. struct intel_fbdev;
  213. typedef struct drm_i915_private {
  214. struct drm_device *dev;
  215. const struct intel_device_info *info;
  216. int has_gem;
  217. void __iomem *regs;
  218. struct intel_gmbus {
  219. struct i2c_adapter adapter;
  220. struct i2c_adapter *force_bit;
  221. u32 reg0;
  222. } *gmbus;
  223. struct pci_dev *bridge_dev;
  224. struct intel_ring_buffer render_ring;
  225. struct intel_ring_buffer bsd_ring;
  226. struct intel_ring_buffer blt_ring;
  227. uint32_t next_seqno;
  228. drm_dma_handle_t *status_page_dmah;
  229. void *seqno_page;
  230. dma_addr_t dma_status_page;
  231. uint32_t counter;
  232. unsigned int seqno_gfx_addr;
  233. drm_local_map_t hws_map;
  234. struct drm_gem_object *seqno_obj;
  235. struct drm_gem_object *pwrctx;
  236. struct drm_gem_object *renderctx;
  237. struct resource mch_res;
  238. unsigned int cpp;
  239. int back_offset;
  240. int front_offset;
  241. int current_page;
  242. int page_flipping;
  243. #define I915_DEBUG_READ (1<<0)
  244. #define I915_DEBUG_WRITE (1<<1)
  245. unsigned long debug_flags;
  246. wait_queue_head_t irq_queue;
  247. atomic_t irq_received;
  248. /** Protects user_irq_refcount and irq_mask_reg */
  249. spinlock_t user_irq_lock;
  250. u32 trace_irq_seqno;
  251. /** Cached value of IMR to avoid reads in updating the bitfield */
  252. u32 irq_mask_reg;
  253. u32 pipestat[2];
  254. /** splitted irq regs for graphics and display engine on Ironlake,
  255. irq_mask_reg is still used for display irq. */
  256. u32 gt_irq_mask_reg;
  257. u32 gt_irq_enable_reg;
  258. u32 de_irq_enable_reg;
  259. u32 pch_irq_mask_reg;
  260. u32 pch_irq_enable_reg;
  261. u32 hotplug_supported_mask;
  262. struct work_struct hotplug_work;
  263. int tex_lru_log_granularity;
  264. int allow_batchbuffer;
  265. struct mem_block *agp_heap;
  266. unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
  267. int vblank_pipe;
  268. int num_pipe;
  269. /* For hangcheck timer */
  270. #define DRM_I915_HANGCHECK_PERIOD 250 /* in ms */
  271. struct timer_list hangcheck_timer;
  272. int hangcheck_count;
  273. uint32_t last_acthd;
  274. uint32_t last_instdone;
  275. uint32_t last_instdone1;
  276. unsigned long cfb_size;
  277. unsigned long cfb_pitch;
  278. unsigned long cfb_offset;
  279. int cfb_fence;
  280. int cfb_plane;
  281. int cfb_y;
  282. int irq_enabled;
  283. struct intel_opregion opregion;
  284. /* overlay */
  285. struct intel_overlay *overlay;
  286. /* LVDS info */
  287. int backlight_level; /* restore backlight to this value */
  288. struct drm_display_mode *panel_fixed_mode;
  289. struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
  290. struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
  291. /* Feature bits from the VBIOS */
  292. unsigned int int_tv_support:1;
  293. unsigned int lvds_dither:1;
  294. unsigned int lvds_vbt:1;
  295. unsigned int int_crt_support:1;
  296. unsigned int lvds_use_ssc:1;
  297. int lvds_ssc_freq;
  298. struct {
  299. int rate;
  300. int lanes;
  301. int preemphasis;
  302. int vswing;
  303. bool initialized;
  304. bool support;
  305. int bpp;
  306. struct edp_power_seq pps;
  307. } edp;
  308. bool no_aux_handshake;
  309. struct notifier_block lid_notifier;
  310. int crt_ddc_pin;
  311. struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
  312. int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
  313. int num_fence_regs; /* 8 on pre-965, 16 otherwise */
  314. unsigned int fsb_freq, mem_freq, is_ddr3;
  315. spinlock_t error_lock;
  316. struct drm_i915_error_state *first_error;
  317. struct work_struct error_work;
  318. struct completion error_completion;
  319. struct workqueue_struct *wq;
  320. /* Display functions */
  321. struct drm_i915_display_funcs display;
  322. /* PCH chipset type */
  323. enum intel_pch pch_type;
  324. unsigned long quirks;
  325. /* Register state */
  326. bool modeset_on_lid;
  327. u8 saveLBB;
  328. u32 saveDSPACNTR;
  329. u32 saveDSPBCNTR;
  330. u32 saveDSPARB;
  331. u32 saveHWS;
  332. u32 savePIPEACONF;
  333. u32 savePIPEBCONF;
  334. u32 savePIPEASRC;
  335. u32 savePIPEBSRC;
  336. u32 saveFPA0;
  337. u32 saveFPA1;
  338. u32 saveDPLL_A;
  339. u32 saveDPLL_A_MD;
  340. u32 saveHTOTAL_A;
  341. u32 saveHBLANK_A;
  342. u32 saveHSYNC_A;
  343. u32 saveVTOTAL_A;
  344. u32 saveVBLANK_A;
  345. u32 saveVSYNC_A;
  346. u32 saveBCLRPAT_A;
  347. u32 saveTRANSACONF;
  348. u32 saveTRANS_HTOTAL_A;
  349. u32 saveTRANS_HBLANK_A;
  350. u32 saveTRANS_HSYNC_A;
  351. u32 saveTRANS_VTOTAL_A;
  352. u32 saveTRANS_VBLANK_A;
  353. u32 saveTRANS_VSYNC_A;
  354. u32 savePIPEASTAT;
  355. u32 saveDSPASTRIDE;
  356. u32 saveDSPASIZE;
  357. u32 saveDSPAPOS;
  358. u32 saveDSPAADDR;
  359. u32 saveDSPASURF;
  360. u32 saveDSPATILEOFF;
  361. u32 savePFIT_PGM_RATIOS;
  362. u32 saveBLC_HIST_CTL;
  363. u32 saveBLC_PWM_CTL;
  364. u32 saveBLC_PWM_CTL2;
  365. u32 saveBLC_CPU_PWM_CTL;
  366. u32 saveBLC_CPU_PWM_CTL2;
  367. u32 saveFPB0;
  368. u32 saveFPB1;
  369. u32 saveDPLL_B;
  370. u32 saveDPLL_B_MD;
  371. u32 saveHTOTAL_B;
  372. u32 saveHBLANK_B;
  373. u32 saveHSYNC_B;
  374. u32 saveVTOTAL_B;
  375. u32 saveVBLANK_B;
  376. u32 saveVSYNC_B;
  377. u32 saveBCLRPAT_B;
  378. u32 saveTRANSBCONF;
  379. u32 saveTRANS_HTOTAL_B;
  380. u32 saveTRANS_HBLANK_B;
  381. u32 saveTRANS_HSYNC_B;
  382. u32 saveTRANS_VTOTAL_B;
  383. u32 saveTRANS_VBLANK_B;
  384. u32 saveTRANS_VSYNC_B;
  385. u32 savePIPEBSTAT;
  386. u32 saveDSPBSTRIDE;
  387. u32 saveDSPBSIZE;
  388. u32 saveDSPBPOS;
  389. u32 saveDSPBADDR;
  390. u32 saveDSPBSURF;
  391. u32 saveDSPBTILEOFF;
  392. u32 saveVGA0;
  393. u32 saveVGA1;
  394. u32 saveVGA_PD;
  395. u32 saveVGACNTRL;
  396. u32 saveADPA;
  397. u32 saveLVDS;
  398. u32 savePP_ON_DELAYS;
  399. u32 savePP_OFF_DELAYS;
  400. u32 saveDVOA;
  401. u32 saveDVOB;
  402. u32 saveDVOC;
  403. u32 savePP_ON;
  404. u32 savePP_OFF;
  405. u32 savePP_CONTROL;
  406. u32 savePP_DIVISOR;
  407. u32 savePFIT_CONTROL;
  408. u32 save_palette_a[256];
  409. u32 save_palette_b[256];
  410. u32 saveDPFC_CB_BASE;
  411. u32 saveFBC_CFB_BASE;
  412. u32 saveFBC_LL_BASE;
  413. u32 saveFBC_CONTROL;
  414. u32 saveFBC_CONTROL2;
  415. u32 saveIER;
  416. u32 saveIIR;
  417. u32 saveIMR;
  418. u32 saveDEIER;
  419. u32 saveDEIMR;
  420. u32 saveGTIER;
  421. u32 saveGTIMR;
  422. u32 saveFDI_RXA_IMR;
  423. u32 saveFDI_RXB_IMR;
  424. u32 saveCACHE_MODE_0;
  425. u32 saveMI_ARB_STATE;
  426. u32 saveSWF0[16];
  427. u32 saveSWF1[16];
  428. u32 saveSWF2[3];
  429. u8 saveMSR;
  430. u8 saveSR[8];
  431. u8 saveGR[25];
  432. u8 saveAR_INDEX;
  433. u8 saveAR[21];
  434. u8 saveDACMASK;
  435. u8 saveCR[37];
  436. uint64_t saveFENCE[16];
  437. u32 saveCURACNTR;
  438. u32 saveCURAPOS;
  439. u32 saveCURABASE;
  440. u32 saveCURBCNTR;
  441. u32 saveCURBPOS;
  442. u32 saveCURBBASE;
  443. u32 saveCURSIZE;
  444. u32 saveDP_B;
  445. u32 saveDP_C;
  446. u32 saveDP_D;
  447. u32 savePIPEA_GMCH_DATA_M;
  448. u32 savePIPEB_GMCH_DATA_M;
  449. u32 savePIPEA_GMCH_DATA_N;
  450. u32 savePIPEB_GMCH_DATA_N;
  451. u32 savePIPEA_DP_LINK_M;
  452. u32 savePIPEB_DP_LINK_M;
  453. u32 savePIPEA_DP_LINK_N;
  454. u32 savePIPEB_DP_LINK_N;
  455. u32 saveFDI_RXA_CTL;
  456. u32 saveFDI_TXA_CTL;
  457. u32 saveFDI_RXB_CTL;
  458. u32 saveFDI_TXB_CTL;
  459. u32 savePFA_CTL_1;
  460. u32 savePFB_CTL_1;
  461. u32 savePFA_WIN_SZ;
  462. u32 savePFB_WIN_SZ;
  463. u32 savePFA_WIN_POS;
  464. u32 savePFB_WIN_POS;
  465. u32 savePCH_DREF_CONTROL;
  466. u32 saveDISP_ARB_CTL;
  467. u32 savePIPEA_DATA_M1;
  468. u32 savePIPEA_DATA_N1;
  469. u32 savePIPEA_LINK_M1;
  470. u32 savePIPEA_LINK_N1;
  471. u32 savePIPEB_DATA_M1;
  472. u32 savePIPEB_DATA_N1;
  473. u32 savePIPEB_LINK_M1;
  474. u32 savePIPEB_LINK_N1;
  475. u32 saveMCHBAR_RENDER_STANDBY;
  476. struct {
  477. /** Bridge to intel-gtt-ko */
  478. struct intel_gtt *gtt;
  479. /** Memory allocator for GTT stolen memory */
  480. struct drm_mm vram;
  481. /** Memory allocator for GTT */
  482. struct drm_mm gtt_space;
  483. struct io_mapping *gtt_mapping;
  484. int gtt_mtrr;
  485. /**
  486. * Membership on list of all loaded devices, used to evict
  487. * inactive buffers under memory pressure.
  488. *
  489. * Modifications should only be done whilst holding the
  490. * shrink_list_lock spinlock.
  491. */
  492. struct list_head shrink_list;
  493. /**
  494. * List of objects currently involved in rendering.
  495. *
  496. * Includes buffers having the contents of their GPU caches
  497. * flushed, not necessarily primitives. last_rendering_seqno
  498. * represents when the rendering involved will be completed.
  499. *
  500. * A reference is held on the buffer while on this list.
  501. */
  502. struct list_head active_list;
  503. /**
  504. * List of objects which are not in the ringbuffer but which
  505. * still have a write_domain which needs to be flushed before
  506. * unbinding.
  507. *
  508. * last_rendering_seqno is 0 while an object is in this list.
  509. *
  510. * A reference is held on the buffer while on this list.
  511. */
  512. struct list_head flushing_list;
  513. /**
  514. * List of objects currently pending a GPU write flush.
  515. *
  516. * All elements on this list will belong to either the
  517. * active_list or flushing_list, last_rendering_seqno can
  518. * be used to differentiate between the two elements.
  519. */
  520. struct list_head gpu_write_list;
  521. /**
  522. * LRU list of objects which are not in the ringbuffer and
  523. * are ready to unbind, but are still in the GTT.
  524. *
  525. * last_rendering_seqno is 0 while an object is in this list.
  526. *
  527. * A reference is not held on the buffer while on this list,
  528. * as merely being GTT-bound shouldn't prevent its being
  529. * freed, and we'll pull it off the list in the free path.
  530. */
  531. struct list_head inactive_list;
  532. /**
  533. * LRU list of objects which are not in the ringbuffer but
  534. * are still pinned in the GTT.
  535. */
  536. struct list_head pinned_list;
  537. /** LRU list of objects with fence regs on them. */
  538. struct list_head fence_list;
  539. /**
  540. * List of objects currently pending being freed.
  541. *
  542. * These objects are no longer in use, but due to a signal
  543. * we were prevented from freeing them at the appointed time.
  544. */
  545. struct list_head deferred_free_list;
  546. /**
  547. * We leave the user IRQ off as much as possible,
  548. * but this means that requests will finish and never
  549. * be retired once the system goes idle. Set a timer to
  550. * fire periodically while the ring is running. When it
  551. * fires, go retire requests.
  552. */
  553. struct delayed_work retire_work;
  554. /**
  555. * Waiting sequence number, if any
  556. */
  557. uint32_t waiting_gem_seqno;
  558. /**
  559. * Last seq seen at irq time
  560. */
  561. uint32_t irq_gem_seqno;
  562. /**
  563. * Flag if the X Server, and thus DRM, is not currently in
  564. * control of the device.
  565. *
  566. * This is set between LeaveVT and EnterVT. It needs to be
  567. * replaced with a semaphore. It also needs to be
  568. * transitioned away from for kernel modesetting.
  569. */
  570. int suspended;
  571. /**
  572. * Flag if the hardware appears to be wedged.
  573. *
  574. * This is set when attempts to idle the device timeout.
  575. * It prevents command submission from occuring and makes
  576. * every pending request fail
  577. */
  578. atomic_t wedged;
  579. /** Bit 6 swizzling required for X tiling */
  580. uint32_t bit_6_swizzle_x;
  581. /** Bit 6 swizzling required for Y tiling */
  582. uint32_t bit_6_swizzle_y;
  583. /* storage for physical objects */
  584. struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
  585. uint32_t flush_rings;
  586. /* accounting, useful for userland debugging */
  587. size_t object_memory;
  588. size_t pin_memory;
  589. size_t gtt_memory;
  590. size_t gtt_total;
  591. u32 object_count;
  592. u32 pin_count;
  593. u32 gtt_count;
  594. } mm;
  595. struct sdvo_device_mapping sdvo_mappings[2];
  596. /* indicate whether the LVDS_BORDER should be enabled or not */
  597. unsigned int lvds_border_bits;
  598. /* Panel fitter placement and size for Ironlake+ */
  599. u32 pch_pf_pos, pch_pf_size;
  600. struct drm_crtc *plane_to_crtc_mapping[2];
  601. struct drm_crtc *pipe_to_crtc_mapping[2];
  602. wait_queue_head_t pending_flip_queue;
  603. bool flip_pending_is_done;
  604. /* Reclocking support */
  605. bool render_reclock_avail;
  606. bool lvds_downclock_avail;
  607. /* indicates the reduced downclock for LVDS*/
  608. int lvds_downclock;
  609. struct work_struct idle_work;
  610. struct timer_list idle_timer;
  611. bool busy;
  612. u16 orig_clock;
  613. int child_dev_num;
  614. struct child_device_config *child_dev;
  615. struct drm_connector *int_lvds_connector;
  616. bool mchbar_need_disable;
  617. u8 cur_delay;
  618. u8 min_delay;
  619. u8 max_delay;
  620. u8 fmax;
  621. u8 fstart;
  622. u64 last_count1;
  623. unsigned long last_time1;
  624. u64 last_count2;
  625. struct timespec last_time2;
  626. unsigned long gfx_power;
  627. int c_m;
  628. int r_t;
  629. u8 corr;
  630. spinlock_t *mchdev_lock;
  631. enum no_fbc_reason no_fbc_reason;
  632. struct drm_mm_node *compressed_fb;
  633. struct drm_mm_node *compressed_llb;
  634. unsigned long last_gpu_reset;
  635. /* list of fbdev register on this device */
  636. struct intel_fbdev *fbdev;
  637. } drm_i915_private_t;
  638. /** driver private structure attached to each drm_gem_object */
  639. struct drm_i915_gem_object {
  640. struct drm_gem_object base;
  641. /** Current space allocated to this object in the GTT, if any. */
  642. struct drm_mm_node *gtt_space;
  643. /** This object's place on the active/flushing/inactive lists */
  644. struct list_head ring_list;
  645. struct list_head mm_list;
  646. /** This object's place on GPU write list */
  647. struct list_head gpu_write_list;
  648. /** This object's place on eviction list */
  649. struct list_head evict_list;
  650. /**
  651. * This is set if the object is on the active or flushing lists
  652. * (has pending rendering), and is not set if it's on inactive (ready
  653. * to be unbound).
  654. */
  655. unsigned int active : 1;
  656. /**
  657. * This is set if the object has been written to since last bound
  658. * to the GTT
  659. */
  660. unsigned int dirty : 1;
  661. /**
  662. * Fence register bits (if any) for this object. Will be set
  663. * as needed when mapped into the GTT.
  664. * Protected by dev->struct_mutex.
  665. *
  666. * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
  667. */
  668. signed int fence_reg : 5;
  669. /**
  670. * Used for checking the object doesn't appear more than once
  671. * in an execbuffer object list.
  672. */
  673. unsigned int in_execbuffer : 1;
  674. /**
  675. * Advice: are the backing pages purgeable?
  676. */
  677. unsigned int madv : 2;
  678. /**
  679. * Refcount for the pages array. With the current locking scheme, there
  680. * are at most two concurrent users: Binding a bo to the gtt and
  681. * pwrite/pread using physical addresses. So two bits for a maximum
  682. * of two users are enough.
  683. */
  684. unsigned int pages_refcount : 2;
  685. #define DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT 0x3
  686. /**
  687. * Current tiling mode for the object.
  688. */
  689. unsigned int tiling_mode : 2;
  690. /** How many users have pinned this object in GTT space. The following
  691. * users can each hold at most one reference: pwrite/pread, pin_ioctl
  692. * (via user_pin_count), execbuffer (objects are not allowed multiple
  693. * times for the same batchbuffer), and the framebuffer code. When
  694. * switching/pageflipping, the framebuffer code has at most two buffers
  695. * pinned per crtc.
  696. *
  697. * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
  698. * bits with absolutely no headroom. So use 4 bits. */
  699. unsigned int pin_count : 4;
  700. #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
  701. /** AGP memory structure for our GTT binding. */
  702. DRM_AGP_MEM *agp_mem;
  703. struct page **pages;
  704. /**
  705. * Current offset of the object in GTT space.
  706. *
  707. * This is the same as gtt_space->start
  708. */
  709. uint32_t gtt_offset;
  710. /* Which ring is refering to is this object */
  711. struct intel_ring_buffer *ring;
  712. /**
  713. * Fake offset for use by mmap(2)
  714. */
  715. uint64_t mmap_offset;
  716. /** Breadcrumb of last rendering to the buffer. */
  717. uint32_t last_rendering_seqno;
  718. /** Current tiling stride for the object, if it's tiled. */
  719. uint32_t stride;
  720. /** Record of address bit 17 of each page at last unbind. */
  721. unsigned long *bit_17;
  722. /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
  723. uint32_t agp_type;
  724. /**
  725. * If present, while GEM_DOMAIN_CPU is in the read domain this array
  726. * flags which individual pages are valid.
  727. */
  728. uint8_t *page_cpu_valid;
  729. /** User space pin count and filp owning the pin */
  730. uint32_t user_pin_count;
  731. struct drm_file *pin_filp;
  732. /** for phy allocated objects */
  733. struct drm_i915_gem_phys_object *phys_obj;
  734. /**
  735. * Number of crtcs where this object is currently the fb, but
  736. * will be page flipped away on the next vblank. When it
  737. * reaches 0, dev_priv->pending_flip_queue will be woken up.
  738. */
  739. atomic_t pending_flip;
  740. };
  741. #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
  742. /**
  743. * Request queue structure.
  744. *
  745. * The request queue allows us to note sequence numbers that have been emitted
  746. * and may be associated with active buffers to be retired.
  747. *
  748. * By keeping this list, we can avoid having to do questionable
  749. * sequence-number comparisons on buffer last_rendering_seqnos, and associate
  750. * an emission time with seqnos for tracking how far ahead of the GPU we are.
  751. */
  752. struct drm_i915_gem_request {
  753. /** On Which ring this request was generated */
  754. struct intel_ring_buffer *ring;
  755. /** GEM sequence number associated with this request. */
  756. uint32_t seqno;
  757. /** Time at which this request was emitted, in jiffies. */
  758. unsigned long emitted_jiffies;
  759. /** global list entry for this request */
  760. struct list_head list;
  761. struct drm_i915_file_private *file_priv;
  762. /** file_priv list entry for this request */
  763. struct list_head client_list;
  764. };
  765. struct drm_i915_file_private {
  766. struct {
  767. struct spinlock lock;
  768. struct list_head request_list;
  769. } mm;
  770. };
  771. enum intel_chip_family {
  772. CHIP_I8XX = 0x01,
  773. CHIP_I9XX = 0x02,
  774. CHIP_I915 = 0x04,
  775. CHIP_I965 = 0x08,
  776. };
  777. extern struct drm_ioctl_desc i915_ioctls[];
  778. extern int i915_max_ioctl;
  779. extern unsigned int i915_fbpercrtc;
  780. extern unsigned int i915_powersave;
  781. extern unsigned int i915_lvds_downclock;
  782. extern int i915_suspend(struct drm_device *dev, pm_message_t state);
  783. extern int i915_resume(struct drm_device *dev);
  784. extern void i915_save_display(struct drm_device *dev);
  785. extern void i915_restore_display(struct drm_device *dev);
  786. extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
  787. extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
  788. /* i915_dma.c */
  789. extern void i915_kernel_lost_context(struct drm_device * dev);
  790. extern int i915_driver_load(struct drm_device *, unsigned long flags);
  791. extern int i915_driver_unload(struct drm_device *);
  792. extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
  793. extern void i915_driver_lastclose(struct drm_device * dev);
  794. extern void i915_driver_preclose(struct drm_device *dev,
  795. struct drm_file *file_priv);
  796. extern void i915_driver_postclose(struct drm_device *dev,
  797. struct drm_file *file_priv);
  798. extern int i915_driver_device_is_agp(struct drm_device * dev);
  799. extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
  800. unsigned long arg);
  801. extern int i915_emit_box(struct drm_device *dev,
  802. struct drm_clip_rect *boxes,
  803. int i, int DR1, int DR4);
  804. extern int i915_reset(struct drm_device *dev, u8 flags);
  805. extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
  806. extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
  807. extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
  808. extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
  809. /* i915_irq.c */
  810. void i915_hangcheck_elapsed(unsigned long data);
  811. extern int i915_irq_emit(struct drm_device *dev, void *data,
  812. struct drm_file *file_priv);
  813. extern int i915_irq_wait(struct drm_device *dev, void *data,
  814. struct drm_file *file_priv);
  815. void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
  816. extern void i915_enable_interrupt (struct drm_device *dev);
  817. extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
  818. extern void i915_driver_irq_preinstall(struct drm_device * dev);
  819. extern int i915_driver_irq_postinstall(struct drm_device *dev);
  820. extern void i915_driver_irq_uninstall(struct drm_device * dev);
  821. extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
  822. struct drm_file *file_priv);
  823. extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
  824. struct drm_file *file_priv);
  825. extern int i915_enable_vblank(struct drm_device *dev, int crtc);
  826. extern void i915_disable_vblank(struct drm_device *dev, int crtc);
  827. extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
  828. extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
  829. extern int i915_vblank_swap(struct drm_device *dev, void *data,
  830. struct drm_file *file_priv);
  831. extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
  832. extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask);
  833. extern void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv,
  834. u32 mask);
  835. extern void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv,
  836. u32 mask);
  837. void
  838. i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
  839. void
  840. i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
  841. void intel_enable_asle (struct drm_device *dev);
  842. #ifdef CONFIG_DEBUG_FS
  843. extern void i915_destroy_error_state(struct drm_device *dev);
  844. #else
  845. #define i915_destroy_error_state(x)
  846. #endif
  847. /* i915_mem.c */
  848. extern int i915_mem_alloc(struct drm_device *dev, void *data,
  849. struct drm_file *file_priv);
  850. extern int i915_mem_free(struct drm_device *dev, void *data,
  851. struct drm_file *file_priv);
  852. extern int i915_mem_init_heap(struct drm_device *dev, void *data,
  853. struct drm_file *file_priv);
  854. extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
  855. struct drm_file *file_priv);
  856. extern void i915_mem_takedown(struct mem_block **heap);
  857. extern void i915_mem_release(struct drm_device * dev,
  858. struct drm_file *file_priv, struct mem_block *heap);
  859. /* i915_gem.c */
  860. int i915_gem_check_is_wedged(struct drm_device *dev);
  861. int i915_gem_init_ioctl(struct drm_device *dev, void *data,
  862. struct drm_file *file_priv);
  863. int i915_gem_create_ioctl(struct drm_device *dev, void *data,
  864. struct drm_file *file_priv);
  865. int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
  866. struct drm_file *file_priv);
  867. int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
  868. struct drm_file *file_priv);
  869. int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
  870. struct drm_file *file_priv);
  871. int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
  872. struct drm_file *file_priv);
  873. int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
  874. struct drm_file *file_priv);
  875. int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
  876. struct drm_file *file_priv);
  877. int i915_gem_execbuffer(struct drm_device *dev, void *data,
  878. struct drm_file *file_priv);
  879. int i915_gem_execbuffer2(struct drm_device *dev, void *data,
  880. struct drm_file *file_priv);
  881. int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
  882. struct drm_file *file_priv);
  883. int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
  884. struct drm_file *file_priv);
  885. int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
  886. struct drm_file *file_priv);
  887. int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
  888. struct drm_file *file_priv);
  889. int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
  890. struct drm_file *file_priv);
  891. int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
  892. struct drm_file *file_priv);
  893. int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
  894. struct drm_file *file_priv);
  895. int i915_gem_set_tiling(struct drm_device *dev, void *data,
  896. struct drm_file *file_priv);
  897. int i915_gem_get_tiling(struct drm_device *dev, void *data,
  898. struct drm_file *file_priv);
  899. int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  900. struct drm_file *file_priv);
  901. void i915_gem_load(struct drm_device *dev);
  902. int i915_gem_init_object(struct drm_gem_object *obj);
  903. struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
  904. size_t size);
  905. void i915_gem_free_object(struct drm_gem_object *obj);
  906. int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
  907. void i915_gem_object_unpin(struct drm_gem_object *obj);
  908. int i915_gem_object_unbind(struct drm_gem_object *obj);
  909. void i915_gem_release_mmap(struct drm_gem_object *obj);
  910. void i915_gem_lastclose(struct drm_device *dev);
  911. /**
  912. * Returns true if seq1 is later than seq2.
  913. */
  914. static inline bool
  915. i915_seqno_passed(uint32_t seq1, uint32_t seq2)
  916. {
  917. return (int32_t)(seq1 - seq2) >= 0;
  918. }
  919. int i915_gem_object_get_fence_reg(struct drm_gem_object *obj,
  920. bool interruptible);
  921. int i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
  922. bool interruptible);
  923. void i915_gem_retire_requests(struct drm_device *dev);
  924. void i915_gem_reset(struct drm_device *dev);
  925. void i915_gem_clflush_object(struct drm_gem_object *obj);
  926. int i915_gem_object_set_domain(struct drm_gem_object *obj,
  927. uint32_t read_domains,
  928. uint32_t write_domain);
  929. int i915_gem_init_ringbuffer(struct drm_device *dev);
  930. void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
  931. int i915_gem_do_init(struct drm_device *dev, unsigned long start,
  932. unsigned long end);
  933. int i915_gpu_idle(struct drm_device *dev);
  934. int i915_gem_idle(struct drm_device *dev);
  935. uint32_t i915_add_request(struct drm_device *dev,
  936. struct drm_file *file_priv,
  937. struct drm_i915_gem_request *request,
  938. struct intel_ring_buffer *ring);
  939. int i915_do_wait_request(struct drm_device *dev,
  940. uint32_t seqno,
  941. bool interruptible,
  942. struct intel_ring_buffer *ring);
  943. int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
  944. int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
  945. int write);
  946. int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
  947. bool pipelined);
  948. int i915_gem_attach_phys_object(struct drm_device *dev,
  949. struct drm_gem_object *obj,
  950. int id,
  951. int align);
  952. void i915_gem_detach_phys_object(struct drm_device *dev,
  953. struct drm_gem_object *obj);
  954. void i915_gem_free_all_phys_object(struct drm_device *dev);
  955. void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
  956. void i915_gem_shrinker_init(void);
  957. void i915_gem_shrinker_exit(void);
  958. /* i915_gem_evict.c */
  959. int i915_gem_evict_something(struct drm_device *dev, int min_size, unsigned alignment);
  960. int i915_gem_evict_everything(struct drm_device *dev);
  961. int i915_gem_evict_inactive(struct drm_device *dev);
  962. /* i915_gem_tiling.c */
  963. void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
  964. void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
  965. void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
  966. bool i915_tiling_ok(struct drm_device *dev, int stride, int size,
  967. int tiling_mode);
  968. bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj,
  969. int tiling_mode);
  970. /* i915_gem_debug.c */
  971. void i915_gem_dump_object(struct drm_gem_object *obj, int len,
  972. const char *where, uint32_t mark);
  973. #if WATCH_LISTS
  974. int i915_verify_lists(struct drm_device *dev);
  975. #else
  976. #define i915_verify_lists(dev) 0
  977. #endif
  978. void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
  979. void i915_gem_dump_object(struct drm_gem_object *obj, int len,
  980. const char *where, uint32_t mark);
  981. /* i915_debugfs.c */
  982. int i915_debugfs_init(struct drm_minor *minor);
  983. void i915_debugfs_cleanup(struct drm_minor *minor);
  984. /* i915_suspend.c */
  985. extern int i915_save_state(struct drm_device *dev);
  986. extern int i915_restore_state(struct drm_device *dev);
  987. /* i915_suspend.c */
  988. extern int i915_save_state(struct drm_device *dev);
  989. extern int i915_restore_state(struct drm_device *dev);
  990. /* intel_i2c.c */
  991. extern int intel_setup_gmbus(struct drm_device *dev);
  992. extern void intel_teardown_gmbus(struct drm_device *dev);
  993. extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
  994. extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
  995. extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
  996. {
  997. return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
  998. }
  999. extern void intel_i2c_reset(struct drm_device *dev);
  1000. /* intel_opregion.c */
  1001. extern int intel_opregion_setup(struct drm_device *dev);
  1002. #ifdef CONFIG_ACPI
  1003. extern void intel_opregion_init(struct drm_device *dev);
  1004. extern void intel_opregion_fini(struct drm_device *dev);
  1005. extern void intel_opregion_asle_intr(struct drm_device *dev);
  1006. extern void intel_opregion_gse_intr(struct drm_device *dev);
  1007. extern void intel_opregion_enable_asle(struct drm_device *dev);
  1008. #else
  1009. static inline void intel_opregion_init(struct drm_device *dev) { return; }
  1010. static inline void intel_opregion_fini(struct drm_device *dev) { return; }
  1011. static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
  1012. static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
  1013. static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
  1014. #endif
  1015. /* intel_acpi.c */
  1016. #ifdef CONFIG_ACPI
  1017. extern void intel_register_dsm_handler(void);
  1018. extern void intel_unregister_dsm_handler(void);
  1019. #else
  1020. static inline void intel_register_dsm_handler(void) { return; }
  1021. static inline void intel_unregister_dsm_handler(void) { return; }
  1022. #endif /* CONFIG_ACPI */
  1023. /* modesetting */
  1024. extern void intel_modeset_init(struct drm_device *dev);
  1025. extern void intel_modeset_cleanup(struct drm_device *dev);
  1026. extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
  1027. extern void i8xx_disable_fbc(struct drm_device *dev);
  1028. extern void g4x_disable_fbc(struct drm_device *dev);
  1029. extern void ironlake_disable_fbc(struct drm_device *dev);
  1030. extern void intel_disable_fbc(struct drm_device *dev);
  1031. extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
  1032. extern bool intel_fbc_enabled(struct drm_device *dev);
  1033. extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
  1034. extern void intel_detect_pch (struct drm_device *dev);
  1035. extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
  1036. /* overlay */
  1037. #ifdef CONFIG_DEBUG_FS
  1038. extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
  1039. extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
  1040. #endif
  1041. /**
  1042. * Lock test for when it's just for synchronization of ring access.
  1043. *
  1044. * In that case, we don't need to do it when GEM is initialized as nobody else
  1045. * has access to the ring.
  1046. */
  1047. #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
  1048. if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \
  1049. == NULL) \
  1050. LOCK_TEST_WITH_RETURN(dev, file_priv); \
  1051. } while (0)
  1052. static inline u32 i915_read(struct drm_i915_private *dev_priv, u32 reg)
  1053. {
  1054. u32 val;
  1055. val = readl(dev_priv->regs + reg);
  1056. if (dev_priv->debug_flags & I915_DEBUG_READ)
  1057. printk(KERN_ERR "read 0x%08x from 0x%08x\n", val, reg);
  1058. return val;
  1059. }
  1060. static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg,
  1061. u32 val)
  1062. {
  1063. writel(val, dev_priv->regs + reg);
  1064. if (dev_priv->debug_flags & I915_DEBUG_WRITE)
  1065. printk(KERN_ERR "wrote 0x%08x to 0x%08x\n", val, reg);
  1066. }
  1067. #define I915_READ(reg) i915_read(dev_priv, (reg))
  1068. #define I915_WRITE(reg, val) i915_write(dev_priv, (reg), (val))
  1069. #define I915_READ16(reg) readw(dev_priv->regs + (reg))
  1070. #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
  1071. #define I915_READ8(reg) readb(dev_priv->regs + (reg))
  1072. #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
  1073. #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
  1074. #define I915_READ64(reg) readq(dev_priv->regs + (reg))
  1075. #define POSTING_READ(reg) (void)I915_READ(reg)
  1076. #define POSTING_READ16(reg) (void)I915_READ16(reg)
  1077. #define I915_DEBUG_ENABLE_IO() (dev_priv->debug_flags |= I915_DEBUG_READ | \
  1078. I915_DEBUG_WRITE)
  1079. #define I915_DEBUG_DISABLE_IO() (dev_priv->debug_flags &= ~(I915_DEBUG_READ | \
  1080. I915_DEBUG_WRITE))
  1081. #define I915_VERBOSE 0
  1082. #define BEGIN_LP_RING(n) do { \
  1083. drm_i915_private_t *dev_priv__ = dev->dev_private; \
  1084. if (I915_VERBOSE) \
  1085. DRM_DEBUG(" BEGIN_LP_RING %x\n", (int)(n)); \
  1086. intel_ring_begin(dev, &dev_priv__->render_ring, (n)); \
  1087. } while (0)
  1088. #define OUT_RING(x) do { \
  1089. drm_i915_private_t *dev_priv__ = dev->dev_private; \
  1090. if (I915_VERBOSE) \
  1091. DRM_DEBUG(" OUT_RING %x\n", (int)(x)); \
  1092. intel_ring_emit(dev, &dev_priv__->render_ring, x); \
  1093. } while (0)
  1094. #define ADVANCE_LP_RING() do { \
  1095. drm_i915_private_t *dev_priv__ = dev->dev_private; \
  1096. if (I915_VERBOSE) \
  1097. DRM_DEBUG("ADVANCE_LP_RING %x\n", \
  1098. dev_priv__->render_ring.tail); \
  1099. intel_ring_advance(dev, &dev_priv__->render_ring); \
  1100. } while(0)
  1101. /**
  1102. * Reads a dword out of the status page, which is written to from the command
  1103. * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
  1104. * MI_STORE_DATA_IMM.
  1105. *
  1106. * The following dwords have a reserved meaning:
  1107. * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
  1108. * 0x04: ring 0 head pointer
  1109. * 0x05: ring 1 head pointer (915-class)
  1110. * 0x06: ring 2 head pointer (915-class)
  1111. * 0x10-0x1b: Context status DWords (GM45)
  1112. * 0x1f: Last written status offset. (GM45)
  1113. *
  1114. * The area from dword 0x20 to 0x3ff is available for driver usage.
  1115. */
  1116. #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
  1117. (dev_priv->render_ring.status_page.page_addr))[reg])
  1118. #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
  1119. #define I915_GEM_HWS_INDEX 0x20
  1120. #define I915_BREADCRUMB_INDEX 0x21
  1121. #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
  1122. #define IS_I830(dev) ((dev)->pci_device == 0x3577)
  1123. #define IS_845G(dev) ((dev)->pci_device == 0x2562)
  1124. #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
  1125. #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
  1126. #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
  1127. #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
  1128. #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
  1129. #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
  1130. #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
  1131. #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
  1132. #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
  1133. #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
  1134. #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
  1135. #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
  1136. #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
  1137. #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
  1138. #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
  1139. #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
  1140. #define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake)
  1141. #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
  1142. #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
  1143. #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
  1144. #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
  1145. #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
  1146. #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
  1147. #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
  1148. #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
  1149. #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
  1150. #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
  1151. #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
  1152. /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  1153. * rows, which changed the alignment requirements and fence programming.
  1154. */
  1155. #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
  1156. IS_I915GM(dev)))
  1157. #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
  1158. #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
  1159. #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
  1160. #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
  1161. #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
  1162. #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
  1163. /* dsparb controlled by hw only */
  1164. #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
  1165. #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
  1166. #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
  1167. #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
  1168. #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
  1169. #define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \
  1170. IS_GEN6(dev))
  1171. #define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev))
  1172. #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
  1173. #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
  1174. #define PRIMARY_RINGBUFFER_SIZE (128*1024)
  1175. #endif