fbdev.c 60 KB

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  1. /*
  2. * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
  3. *
  4. * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
  5. *
  6. * Copyright 1999-2000 Jeff Garzik
  7. *
  8. * Contributors:
  9. *
  10. * Ani Joshi: Lots of debugging and cleanup work, really helped
  11. * get the driver going
  12. *
  13. * Ferenc Bakonyi: Bug fixes, cleanup, modularization
  14. *
  15. * Jindrich Makovicka: Accel code help, hw cursor, mtrr
  16. *
  17. * Paul Richards: Bug fixes, updates
  18. *
  19. * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
  20. * Includes riva_hw.c from nVidia, see copyright below.
  21. * KGI code provided the basis for state storage, init, and mode switching.
  22. *
  23. * This file is subject to the terms and conditions of the GNU General Public
  24. * License. See the file COPYING in the main directory of this archive
  25. * for more details.
  26. *
  27. * Known bugs and issues:
  28. * restoring text mode fails
  29. * doublescan modes are broken
  30. */
  31. #include <linux/config.h>
  32. #include <linux/module.h>
  33. #include <linux/kernel.h>
  34. #include <linux/errno.h>
  35. #include <linux/string.h>
  36. #include <linux/mm.h>
  37. #include <linux/tty.h>
  38. #include <linux/slab.h>
  39. #include <linux/delay.h>
  40. #include <linux/fb.h>
  41. #include <linux/init.h>
  42. #include <linux/pci.h>
  43. #include <linux/backlight.h>
  44. #ifdef CONFIG_MTRR
  45. #include <asm/mtrr.h>
  46. #endif
  47. #ifdef CONFIG_PPC_OF
  48. #include <asm/prom.h>
  49. #include <asm/pci-bridge.h>
  50. #endif
  51. #ifdef CONFIG_PMAC_BACKLIGHT
  52. #include <asm/machdep.h>
  53. #include <asm/backlight.h>
  54. #endif
  55. #include "rivafb.h"
  56. #include "nvreg.h"
  57. #ifndef CONFIG_PCI /* sanity check */
  58. #error This driver requires PCI support.
  59. #endif
  60. /* version number of this driver */
  61. #define RIVAFB_VERSION "0.9.5b"
  62. /* ------------------------------------------------------------------------- *
  63. *
  64. * various helpful macros and constants
  65. *
  66. * ------------------------------------------------------------------------- */
  67. #ifdef CONFIG_FB_RIVA_DEBUG
  68. #define NVTRACE printk
  69. #else
  70. #define NVTRACE if(0) printk
  71. #endif
  72. #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
  73. #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
  74. #ifdef CONFIG_FB_RIVA_DEBUG
  75. #define assert(expr) \
  76. if(!(expr)) { \
  77. printk( "Assertion failed! %s,%s,%s,line=%d\n",\
  78. #expr,__FILE__,__FUNCTION__,__LINE__); \
  79. BUG(); \
  80. }
  81. #else
  82. #define assert(expr)
  83. #endif
  84. #define PFX "rivafb: "
  85. /* macro that allows you to set overflow bits */
  86. #define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
  87. #define SetBit(n) (1<<(n))
  88. #define Set8Bits(value) ((value)&0xff)
  89. /* HW cursor parameters */
  90. #define MAX_CURS 32
  91. /* ------------------------------------------------------------------------- *
  92. *
  93. * prototypes
  94. *
  95. * ------------------------------------------------------------------------- */
  96. static int rivafb_blank(int blank, struct fb_info *info);
  97. /* ------------------------------------------------------------------------- *
  98. *
  99. * card identification
  100. *
  101. * ------------------------------------------------------------------------- */
  102. static struct pci_device_id rivafb_pci_tbl[] = {
  103. { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
  104. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  105. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
  106. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  107. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
  108. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  109. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
  110. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  111. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
  112. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  113. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
  114. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  115. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
  116. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  117. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
  118. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  119. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
  120. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  121. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
  122. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  123. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
  124. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  125. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
  126. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  127. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
  128. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  129. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
  130. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  131. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
  132. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  133. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
  134. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  135. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
  136. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  137. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
  138. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  139. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
  140. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  141. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
  142. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  143. // NF2/IGP version, GeForce 4 MX, NV18
  144. { PCI_VENDOR_ID_NVIDIA, 0x01f0,
  145. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  146. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
  147. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  148. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
  149. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  150. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
  151. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  152. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
  153. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  154. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
  155. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  156. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
  157. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  158. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
  159. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  160. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
  161. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  162. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
  163. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  164. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
  165. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  166. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
  167. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  168. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
  169. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  170. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
  171. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  172. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
  173. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  174. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
  175. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  176. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
  177. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  178. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
  179. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  180. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
  181. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  182. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
  183. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  184. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
  185. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  186. { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
  187. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  188. { 0, } /* terminate list */
  189. };
  190. MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
  191. /* ------------------------------------------------------------------------- *
  192. *
  193. * global variables
  194. *
  195. * ------------------------------------------------------------------------- */
  196. /* command line data, set in rivafb_setup() */
  197. static int flatpanel __devinitdata = -1; /* Autodetect later */
  198. static int forceCRTC __devinitdata = -1;
  199. static int noaccel __devinitdata = 0;
  200. #ifdef CONFIG_MTRR
  201. static int nomtrr __devinitdata = 0;
  202. #endif
  203. static char *mode_option __devinitdata = NULL;
  204. static int strictmode = 0;
  205. static struct fb_fix_screeninfo __devinitdata rivafb_fix = {
  206. .type = FB_TYPE_PACKED_PIXELS,
  207. .xpanstep = 1,
  208. .ypanstep = 1,
  209. };
  210. static struct fb_var_screeninfo __devinitdata rivafb_default_var = {
  211. .xres = 640,
  212. .yres = 480,
  213. .xres_virtual = 640,
  214. .yres_virtual = 480,
  215. .bits_per_pixel = 8,
  216. .red = {0, 8, 0},
  217. .green = {0, 8, 0},
  218. .blue = {0, 8, 0},
  219. .transp = {0, 0, 0},
  220. .activate = FB_ACTIVATE_NOW,
  221. .height = -1,
  222. .width = -1,
  223. .pixclock = 39721,
  224. .left_margin = 40,
  225. .right_margin = 24,
  226. .upper_margin = 32,
  227. .lower_margin = 11,
  228. .hsync_len = 96,
  229. .vsync_len = 2,
  230. .vmode = FB_VMODE_NONINTERLACED
  231. };
  232. /* from GGI */
  233. static const struct riva_regs reg_template = {
  234. {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
  235. 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
  236. 0x41, 0x01, 0x0F, 0x00, 0x00},
  237. {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */
  238. 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
  239. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */
  240. 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  241. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */
  242. 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  243. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */
  244. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  245. 0x00, /* 0x40 */
  246. },
  247. {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */
  248. 0xFF},
  249. {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */
  250. 0xEB /* MISC */
  251. };
  252. /*
  253. * Backlight control
  254. */
  255. #ifdef CONFIG_FB_RIVA_BACKLIGHT
  256. /* We do not have any information about which values are allowed, thus
  257. * we used safe values.
  258. */
  259. #define MIN_LEVEL 0x158
  260. #define MAX_LEVEL 0x534
  261. static struct backlight_properties riva_bl_data;
  262. static int riva_bl_get_level_brightness(struct riva_par *par,
  263. int level)
  264. {
  265. struct fb_info *info = pci_get_drvdata(par->pdev);
  266. int nlevel;
  267. /* Get and convert the value */
  268. mutex_lock(&info->bl_mutex);
  269. nlevel = info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL;
  270. mutex_unlock(&info->bl_mutex);
  271. if (nlevel < 0)
  272. nlevel = 0;
  273. else if (nlevel < MIN_LEVEL)
  274. nlevel = MIN_LEVEL;
  275. else if (nlevel > MAX_LEVEL)
  276. nlevel = MAX_LEVEL;
  277. return nlevel;
  278. }
  279. static int riva_bl_update_status(struct backlight_device *bd)
  280. {
  281. struct riva_par *par = class_get_devdata(&bd->class_dev);
  282. U032 tmp_pcrt, tmp_pmc;
  283. int level;
  284. if (bd->props->power != FB_BLANK_UNBLANK ||
  285. bd->props->fb_blank != FB_BLANK_UNBLANK)
  286. level = 0;
  287. else
  288. level = bd->props->brightness;
  289. tmp_pmc = par->riva.PMC[0x10F0/4] & 0x0000FFFF;
  290. tmp_pcrt = par->riva.PCRTC0[0x081C/4] & 0xFFFFFFFC;
  291. if(level > 0) {
  292. tmp_pcrt |= 0x1;
  293. tmp_pmc |= (1 << 31); /* backlight bit */
  294. tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */
  295. }
  296. par->riva.PCRTC0[0x081C/4] = tmp_pcrt;
  297. par->riva.PMC[0x10F0/4] = tmp_pmc;
  298. return 0;
  299. }
  300. static int riva_bl_get_brightness(struct backlight_device *bd)
  301. {
  302. return bd->props->brightness;
  303. }
  304. static struct backlight_properties riva_bl_data = {
  305. .owner = THIS_MODULE,
  306. .get_brightness = riva_bl_get_brightness,
  307. .update_status = riva_bl_update_status,
  308. .max_brightness = (FB_BACKLIGHT_LEVELS - 1),
  309. };
  310. static void riva_bl_init(struct riva_par *par)
  311. {
  312. struct fb_info *info = pci_get_drvdata(par->pdev);
  313. struct backlight_device *bd;
  314. char name[12];
  315. if (!par->FlatPanel)
  316. return;
  317. #ifdef CONFIG_PMAC_BACKLIGHT
  318. if (!machine_is(powermac) ||
  319. !pmac_has_backlight_type("mnca"))
  320. return;
  321. #endif
  322. snprintf(name, sizeof(name), "rivabl%d", info->node);
  323. bd = backlight_device_register(name, par, &riva_bl_data);
  324. if (IS_ERR(bd)) {
  325. info->bl_dev = NULL;
  326. printk("riva: Backlight registration failed\n");
  327. goto error;
  328. }
  329. mutex_lock(&info->bl_mutex);
  330. info->bl_dev = bd;
  331. fb_bl_default_curve(info, 0,
  332. 0x158 * FB_BACKLIGHT_MAX / MAX_LEVEL,
  333. 0x534 * FB_BACKLIGHT_MAX / MAX_LEVEL);
  334. mutex_unlock(&info->bl_mutex);
  335. up(&bd->sem);
  336. bd->props->brightness = riva_bl_data.max_brightness;
  337. bd->props->power = FB_BLANK_UNBLANK;
  338. bd->props->update_status(bd);
  339. down(&bd->sem);
  340. #ifdef CONFIG_PMAC_BACKLIGHT
  341. mutex_lock(&pmac_backlight_mutex);
  342. if (!pmac_backlight)
  343. pmac_backlight = bd;
  344. mutex_unlock(&pmac_backlight_mutex);
  345. #endif
  346. printk("riva: Backlight initialized (%s)\n", name);
  347. return;
  348. error:
  349. return;
  350. }
  351. static void riva_bl_exit(struct riva_par *par)
  352. {
  353. struct fb_info *info = pci_get_drvdata(par->pdev);
  354. #ifdef CONFIG_PMAC_BACKLIGHT
  355. mutex_lock(&pmac_backlight_mutex);
  356. #endif
  357. mutex_lock(&info->bl_mutex);
  358. if (info->bl_dev) {
  359. #ifdef CONFIG_PMAC_BACKLIGHT
  360. if (pmac_backlight == info->bl_dev)
  361. pmac_backlight = NULL;
  362. #endif
  363. backlight_device_unregister(info->bl_dev);
  364. printk("riva: Backlight unloaded\n");
  365. }
  366. mutex_unlock(&info->bl_mutex);
  367. #ifdef CONFIG_PMAC_BACKLIGHT
  368. mutex_unlock(&pmac_backlight_mutex);
  369. #endif
  370. }
  371. #else
  372. static inline void riva_bl_init(struct riva_par *par) {}
  373. static inline void riva_bl_exit(struct riva_par *par) {}
  374. #endif /* CONFIG_FB_RIVA_BACKLIGHT */
  375. /* ------------------------------------------------------------------------- *
  376. *
  377. * MMIO access macros
  378. *
  379. * ------------------------------------------------------------------------- */
  380. static inline void CRTCout(struct riva_par *par, unsigned char index,
  381. unsigned char val)
  382. {
  383. VGA_WR08(par->riva.PCIO, 0x3d4, index);
  384. VGA_WR08(par->riva.PCIO, 0x3d5, val);
  385. }
  386. static inline unsigned char CRTCin(struct riva_par *par,
  387. unsigned char index)
  388. {
  389. VGA_WR08(par->riva.PCIO, 0x3d4, index);
  390. return (VGA_RD08(par->riva.PCIO, 0x3d5));
  391. }
  392. static inline void GRAout(struct riva_par *par, unsigned char index,
  393. unsigned char val)
  394. {
  395. VGA_WR08(par->riva.PVIO, 0x3ce, index);
  396. VGA_WR08(par->riva.PVIO, 0x3cf, val);
  397. }
  398. static inline unsigned char GRAin(struct riva_par *par,
  399. unsigned char index)
  400. {
  401. VGA_WR08(par->riva.PVIO, 0x3ce, index);
  402. return (VGA_RD08(par->riva.PVIO, 0x3cf));
  403. }
  404. static inline void SEQout(struct riva_par *par, unsigned char index,
  405. unsigned char val)
  406. {
  407. VGA_WR08(par->riva.PVIO, 0x3c4, index);
  408. VGA_WR08(par->riva.PVIO, 0x3c5, val);
  409. }
  410. static inline unsigned char SEQin(struct riva_par *par,
  411. unsigned char index)
  412. {
  413. VGA_WR08(par->riva.PVIO, 0x3c4, index);
  414. return (VGA_RD08(par->riva.PVIO, 0x3c5));
  415. }
  416. static inline void ATTRout(struct riva_par *par, unsigned char index,
  417. unsigned char val)
  418. {
  419. VGA_WR08(par->riva.PCIO, 0x3c0, index);
  420. VGA_WR08(par->riva.PCIO, 0x3c0, val);
  421. }
  422. static inline unsigned char ATTRin(struct riva_par *par,
  423. unsigned char index)
  424. {
  425. VGA_WR08(par->riva.PCIO, 0x3c0, index);
  426. return (VGA_RD08(par->riva.PCIO, 0x3c1));
  427. }
  428. static inline void MISCout(struct riva_par *par, unsigned char val)
  429. {
  430. VGA_WR08(par->riva.PVIO, 0x3c2, val);
  431. }
  432. static inline unsigned char MISCin(struct riva_par *par)
  433. {
  434. return (VGA_RD08(par->riva.PVIO, 0x3cc));
  435. }
  436. static u8 byte_rev[256] = {
  437. 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
  438. 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
  439. 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
  440. 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
  441. 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
  442. 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
  443. 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
  444. 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
  445. 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
  446. 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
  447. 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
  448. 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
  449. 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
  450. 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
  451. 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
  452. 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
  453. 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
  454. 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
  455. 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
  456. 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
  457. 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
  458. 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
  459. 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
  460. 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
  461. 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
  462. 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
  463. 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
  464. 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
  465. 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
  466. 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
  467. 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
  468. 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
  469. };
  470. static inline void reverse_order(u32 *l)
  471. {
  472. u8 *a = (u8 *)l;
  473. *a = byte_rev[*a], a++;
  474. *a = byte_rev[*a], a++;
  475. *a = byte_rev[*a], a++;
  476. *a = byte_rev[*a];
  477. }
  478. /* ------------------------------------------------------------------------- *
  479. *
  480. * cursor stuff
  481. *
  482. * ------------------------------------------------------------------------- */
  483. /**
  484. * rivafb_load_cursor_image - load cursor image to hardware
  485. * @data: address to monochrome bitmap (1 = foreground color, 0 = background)
  486. * @par: pointer to private data
  487. * @w: width of cursor image in pixels
  488. * @h: height of cursor image in scanlines
  489. * @bg: background color (ARGB1555) - alpha bit determines opacity
  490. * @fg: foreground color (ARGB1555)
  491. *
  492. * DESCRIPTiON:
  493. * Loads cursor image based on a monochrome source and mask bitmap. The
  494. * image bits determines the color of the pixel, 0 for background, 1 for
  495. * foreground. Only the affected region (as determined by @w and @h
  496. * parameters) will be updated.
  497. *
  498. * CALLED FROM:
  499. * rivafb_cursor()
  500. */
  501. static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
  502. u16 bg, u16 fg, u32 w, u32 h)
  503. {
  504. int i, j, k = 0;
  505. u32 b, tmp;
  506. u32 *data = (u32 *)data8;
  507. bg = le16_to_cpu(bg);
  508. fg = le16_to_cpu(fg);
  509. w = (w + 1) & ~1;
  510. for (i = 0; i < h; i++) {
  511. b = *data++;
  512. reverse_order(&b);
  513. for (j = 0; j < w/2; j++) {
  514. tmp = 0;
  515. #if defined (__BIG_ENDIAN)
  516. tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
  517. b <<= 1;
  518. tmp |= (b & (1 << 31)) ? fg : bg;
  519. b <<= 1;
  520. #else
  521. tmp = (b & 1) ? fg : bg;
  522. b >>= 1;
  523. tmp |= (b & 1) ? fg << 16 : bg << 16;
  524. b >>= 1;
  525. #endif
  526. writel(tmp, &par->riva.CURSOR[k++]);
  527. }
  528. k += (MAX_CURS - w)/2;
  529. }
  530. }
  531. /* ------------------------------------------------------------------------- *
  532. *
  533. * general utility functions
  534. *
  535. * ------------------------------------------------------------------------- */
  536. /**
  537. * riva_wclut - set CLUT entry
  538. * @chip: pointer to RIVA_HW_INST object
  539. * @regnum: register number
  540. * @red: red component
  541. * @green: green component
  542. * @blue: blue component
  543. *
  544. * DESCRIPTION:
  545. * Sets color register @regnum.
  546. *
  547. * CALLED FROM:
  548. * rivafb_setcolreg()
  549. */
  550. static void riva_wclut(RIVA_HW_INST *chip,
  551. unsigned char regnum, unsigned char red,
  552. unsigned char green, unsigned char blue)
  553. {
  554. VGA_WR08(chip->PDIO, 0x3c8, regnum);
  555. VGA_WR08(chip->PDIO, 0x3c9, red);
  556. VGA_WR08(chip->PDIO, 0x3c9, green);
  557. VGA_WR08(chip->PDIO, 0x3c9, blue);
  558. }
  559. /**
  560. * riva_rclut - read fromCLUT register
  561. * @chip: pointer to RIVA_HW_INST object
  562. * @regnum: register number
  563. * @red: red component
  564. * @green: green component
  565. * @blue: blue component
  566. *
  567. * DESCRIPTION:
  568. * Reads red, green, and blue from color register @regnum.
  569. *
  570. * CALLED FROM:
  571. * rivafb_setcolreg()
  572. */
  573. static void riva_rclut(RIVA_HW_INST *chip,
  574. unsigned char regnum, unsigned char *red,
  575. unsigned char *green, unsigned char *blue)
  576. {
  577. VGA_WR08(chip->PDIO, 0x3c7, regnum);
  578. *red = VGA_RD08(chip->PDIO, 0x3c9);
  579. *green = VGA_RD08(chip->PDIO, 0x3c9);
  580. *blue = VGA_RD08(chip->PDIO, 0x3c9);
  581. }
  582. /**
  583. * riva_save_state - saves current chip state
  584. * @par: pointer to riva_par object containing info for current riva board
  585. * @regs: pointer to riva_regs object
  586. *
  587. * DESCRIPTION:
  588. * Saves current chip state to @regs.
  589. *
  590. * CALLED FROM:
  591. * rivafb_probe()
  592. */
  593. /* from GGI */
  594. static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
  595. {
  596. int i;
  597. NVTRACE_ENTER();
  598. par->riva.LockUnlock(&par->riva, 0);
  599. par->riva.UnloadStateExt(&par->riva, &regs->ext);
  600. regs->misc_output = MISCin(par);
  601. for (i = 0; i < NUM_CRT_REGS; i++)
  602. regs->crtc[i] = CRTCin(par, i);
  603. for (i = 0; i < NUM_ATC_REGS; i++)
  604. regs->attr[i] = ATTRin(par, i);
  605. for (i = 0; i < NUM_GRC_REGS; i++)
  606. regs->gra[i] = GRAin(par, i);
  607. for (i = 0; i < NUM_SEQ_REGS; i++)
  608. regs->seq[i] = SEQin(par, i);
  609. NVTRACE_LEAVE();
  610. }
  611. /**
  612. * riva_load_state - loads current chip state
  613. * @par: pointer to riva_par object containing info for current riva board
  614. * @regs: pointer to riva_regs object
  615. *
  616. * DESCRIPTION:
  617. * Loads chip state from @regs.
  618. *
  619. * CALLED FROM:
  620. * riva_load_video_mode()
  621. * rivafb_probe()
  622. * rivafb_remove()
  623. */
  624. /* from GGI */
  625. static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
  626. {
  627. RIVA_HW_STATE *state = &regs->ext;
  628. int i;
  629. NVTRACE_ENTER();
  630. CRTCout(par, 0x11, 0x00);
  631. par->riva.LockUnlock(&par->riva, 0);
  632. par->riva.LoadStateExt(&par->riva, state);
  633. MISCout(par, regs->misc_output);
  634. for (i = 0; i < NUM_CRT_REGS; i++) {
  635. switch (i) {
  636. case 0x19:
  637. case 0x20 ... 0x40:
  638. break;
  639. default:
  640. CRTCout(par, i, regs->crtc[i]);
  641. }
  642. }
  643. for (i = 0; i < NUM_ATC_REGS; i++)
  644. ATTRout(par, i, regs->attr[i]);
  645. for (i = 0; i < NUM_GRC_REGS; i++)
  646. GRAout(par, i, regs->gra[i]);
  647. for (i = 0; i < NUM_SEQ_REGS; i++)
  648. SEQout(par, i, regs->seq[i]);
  649. NVTRACE_LEAVE();
  650. }
  651. /**
  652. * riva_load_video_mode - calculate timings
  653. * @info: pointer to fb_info object containing info for current riva board
  654. *
  655. * DESCRIPTION:
  656. * Calculate some timings and then send em off to riva_load_state().
  657. *
  658. * CALLED FROM:
  659. * rivafb_set_par()
  660. */
  661. static void riva_load_video_mode(struct fb_info *info)
  662. {
  663. int bpp, width, hDisplaySize, hDisplay, hStart,
  664. hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
  665. int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
  666. struct riva_par *par = info->par;
  667. struct riva_regs newmode;
  668. NVTRACE_ENTER();
  669. /* time to calculate */
  670. rivafb_blank(1, info);
  671. bpp = info->var.bits_per_pixel;
  672. if (bpp == 16 && info->var.green.length == 5)
  673. bpp = 15;
  674. width = info->var.xres_virtual;
  675. hDisplaySize = info->var.xres;
  676. hDisplay = (hDisplaySize / 8) - 1;
  677. hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
  678. hEnd = (hDisplaySize + info->var.right_margin +
  679. info->var.hsync_len) / 8 - 1;
  680. hTotal = (hDisplaySize + info->var.right_margin +
  681. info->var.hsync_len + info->var.left_margin) / 8 - 5;
  682. hBlankStart = hDisplay;
  683. hBlankEnd = hTotal + 4;
  684. height = info->var.yres_virtual;
  685. vDisplay = info->var.yres - 1;
  686. vStart = info->var.yres + info->var.lower_margin - 1;
  687. vEnd = info->var.yres + info->var.lower_margin +
  688. info->var.vsync_len - 1;
  689. vTotal = info->var.yres + info->var.lower_margin +
  690. info->var.vsync_len + info->var.upper_margin + 2;
  691. vBlankStart = vDisplay;
  692. vBlankEnd = vTotal + 1;
  693. dotClock = 1000000000 / info->var.pixclock;
  694. memcpy(&newmode, &reg_template, sizeof(struct riva_regs));
  695. if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
  696. vTotal |= 1;
  697. if (par->FlatPanel) {
  698. vStart = vTotal - 3;
  699. vEnd = vTotal - 2;
  700. vBlankStart = vStart;
  701. hStart = hTotal - 3;
  702. hEnd = hTotal - 2;
  703. hBlankEnd = hTotal + 4;
  704. }
  705. newmode.crtc[0x0] = Set8Bits (hTotal);
  706. newmode.crtc[0x1] = Set8Bits (hDisplay);
  707. newmode.crtc[0x2] = Set8Bits (hBlankStart);
  708. newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
  709. newmode.crtc[0x4] = Set8Bits (hStart);
  710. newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
  711. | SetBitField (hEnd, 4: 0, 4:0);
  712. newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
  713. newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
  714. | SetBitField (vDisplay, 8: 8, 1:1)
  715. | SetBitField (vStart, 8: 8, 2:2)
  716. | SetBitField (vBlankStart, 8: 8, 3:3)
  717. | SetBit (4)
  718. | SetBitField (vTotal, 9: 9, 5:5)
  719. | SetBitField (vDisplay, 9: 9, 6:6)
  720. | SetBitField (vStart, 9: 9, 7:7);
  721. newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
  722. | SetBit (6);
  723. newmode.crtc[0x10] = Set8Bits (vStart);
  724. newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
  725. | SetBit (5);
  726. newmode.crtc[0x12] = Set8Bits (vDisplay);
  727. newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
  728. newmode.crtc[0x15] = Set8Bits (vBlankStart);
  729. newmode.crtc[0x16] = Set8Bits (vBlankEnd);
  730. newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
  731. | SetBitField(vBlankStart,10:10,3:3)
  732. | SetBitField(vStart,10:10,2:2)
  733. | SetBitField(vDisplay,10:10,1:1)
  734. | SetBitField(vTotal,10:10,0:0);
  735. newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
  736. | SetBitField(hDisplay,8:8,1:1)
  737. | SetBitField(hBlankStart,8:8,2:2)
  738. | SetBitField(hStart,8:8,3:3);
  739. newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
  740. | SetBitField(vDisplay,11:11,2:2)
  741. | SetBitField(vStart,11:11,4:4)
  742. | SetBitField(vBlankStart,11:11,6:6);
  743. if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
  744. int tmp = (hTotal >> 1) & ~1;
  745. newmode.ext.interlace = Set8Bits(tmp);
  746. newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
  747. } else
  748. newmode.ext.interlace = 0xff; /* interlace off */
  749. if (par->riva.Architecture >= NV_ARCH_10)
  750. par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart);
  751. if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
  752. newmode.misc_output &= ~0x40;
  753. else
  754. newmode.misc_output |= 0x40;
  755. if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
  756. newmode.misc_output &= ~0x80;
  757. else
  758. newmode.misc_output |= 0x80;
  759. par->riva.CalcStateExt(&par->riva, &newmode.ext, bpp, width,
  760. hDisplaySize, height, dotClock);
  761. newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
  762. 0xfff000ff;
  763. if (par->FlatPanel == 1) {
  764. newmode.ext.pixel |= (1 << 7);
  765. newmode.ext.scale |= (1 << 8);
  766. }
  767. if (par->SecondCRTC) {
  768. newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) &
  769. ~0x00001000;
  770. newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
  771. 0x00001000;
  772. newmode.ext.crtcOwner = 3;
  773. newmode.ext.pllsel |= 0x20000800;
  774. newmode.ext.vpll2 = newmode.ext.vpll;
  775. } else if (par->riva.twoHeads) {
  776. newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) |
  777. 0x00001000;
  778. newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) &
  779. ~0x00001000;
  780. newmode.ext.crtcOwner = 0;
  781. newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
  782. }
  783. if (par->FlatPanel == 1) {
  784. newmode.ext.pixel |= (1 << 7);
  785. newmode.ext.scale |= (1 << 8);
  786. }
  787. newmode.ext.cursorConfig = 0x02000100;
  788. par->current_state = newmode;
  789. riva_load_state(par, &par->current_state);
  790. par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
  791. rivafb_blank(0, info);
  792. NVTRACE_LEAVE();
  793. }
  794. static void riva_update_var(struct fb_var_screeninfo *var, struct fb_videomode *modedb)
  795. {
  796. NVTRACE_ENTER();
  797. var->xres = var->xres_virtual = modedb->xres;
  798. var->yres = modedb->yres;
  799. if (var->yres_virtual < var->yres)
  800. var->yres_virtual = var->yres;
  801. var->xoffset = var->yoffset = 0;
  802. var->pixclock = modedb->pixclock;
  803. var->left_margin = modedb->left_margin;
  804. var->right_margin = modedb->right_margin;
  805. var->upper_margin = modedb->upper_margin;
  806. var->lower_margin = modedb->lower_margin;
  807. var->hsync_len = modedb->hsync_len;
  808. var->vsync_len = modedb->vsync_len;
  809. var->sync = modedb->sync;
  810. var->vmode = modedb->vmode;
  811. NVTRACE_LEAVE();
  812. }
  813. /**
  814. * rivafb_do_maximize -
  815. * @info: pointer to fb_info object containing info for current riva board
  816. * @var:
  817. * @nom:
  818. * @den:
  819. *
  820. * DESCRIPTION:
  821. * .
  822. *
  823. * RETURNS:
  824. * -EINVAL on failure, 0 on success
  825. *
  826. *
  827. * CALLED FROM:
  828. * rivafb_check_var()
  829. */
  830. static int rivafb_do_maximize(struct fb_info *info,
  831. struct fb_var_screeninfo *var,
  832. int nom, int den)
  833. {
  834. static struct {
  835. int xres, yres;
  836. } modes[] = {
  837. {1600, 1280},
  838. {1280, 1024},
  839. {1024, 768},
  840. {800, 600},
  841. {640, 480},
  842. {-1, -1}
  843. };
  844. int i;
  845. NVTRACE_ENTER();
  846. /* use highest possible virtual resolution */
  847. if (var->xres_virtual == -1 && var->yres_virtual == -1) {
  848. printk(KERN_WARNING PFX
  849. "using maximum available virtual resolution\n");
  850. for (i = 0; modes[i].xres != -1; i++) {
  851. if (modes[i].xres * nom / den * modes[i].yres <
  852. info->fix.smem_len)
  853. break;
  854. }
  855. if (modes[i].xres == -1) {
  856. printk(KERN_ERR PFX
  857. "could not find a virtual resolution that fits into video memory!!\n");
  858. NVTRACE("EXIT - EINVAL error\n");
  859. return -EINVAL;
  860. }
  861. var->xres_virtual = modes[i].xres;
  862. var->yres_virtual = modes[i].yres;
  863. printk(KERN_INFO PFX
  864. "virtual resolution set to maximum of %dx%d\n",
  865. var->xres_virtual, var->yres_virtual);
  866. } else if (var->xres_virtual == -1) {
  867. var->xres_virtual = (info->fix.smem_len * den /
  868. (nom * var->yres_virtual)) & ~15;
  869. printk(KERN_WARNING PFX
  870. "setting virtual X resolution to %d\n", var->xres_virtual);
  871. } else if (var->yres_virtual == -1) {
  872. var->xres_virtual = (var->xres_virtual + 15) & ~15;
  873. var->yres_virtual = info->fix.smem_len * den /
  874. (nom * var->xres_virtual);
  875. printk(KERN_WARNING PFX
  876. "setting virtual Y resolution to %d\n", var->yres_virtual);
  877. } else {
  878. var->xres_virtual = (var->xres_virtual + 15) & ~15;
  879. if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
  880. printk(KERN_ERR PFX
  881. "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
  882. var->xres, var->yres, var->bits_per_pixel);
  883. NVTRACE("EXIT - EINVAL error\n");
  884. return -EINVAL;
  885. }
  886. }
  887. if (var->xres_virtual * nom / den >= 8192) {
  888. printk(KERN_WARNING PFX
  889. "virtual X resolution (%d) is too high, lowering to %d\n",
  890. var->xres_virtual, 8192 * den / nom - 16);
  891. var->xres_virtual = 8192 * den / nom - 16;
  892. }
  893. if (var->xres_virtual < var->xres) {
  894. printk(KERN_ERR PFX
  895. "virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
  896. return -EINVAL;
  897. }
  898. if (var->yres_virtual < var->yres) {
  899. printk(KERN_ERR PFX
  900. "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
  901. return -EINVAL;
  902. }
  903. if (var->yres_virtual > 0x7fff/nom)
  904. var->yres_virtual = 0x7fff/nom;
  905. if (var->xres_virtual > 0x7fff/nom)
  906. var->xres_virtual = 0x7fff/nom;
  907. NVTRACE_LEAVE();
  908. return 0;
  909. }
  910. static void
  911. riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
  912. {
  913. RIVA_FIFO_FREE(par->riva, Patt, 4);
  914. NV_WR32(&par->riva.Patt->Color0, 0, clr0);
  915. NV_WR32(&par->riva.Patt->Color1, 0, clr1);
  916. NV_WR32(par->riva.Patt->Monochrome, 0, pat0);
  917. NV_WR32(par->riva.Patt->Monochrome, 4, pat1);
  918. }
  919. /* acceleration routines */
  920. static inline void wait_for_idle(struct riva_par *par)
  921. {
  922. while (par->riva.Busy(&par->riva));
  923. }
  924. /*
  925. * Set ROP. Translate X rop into ROP3. Internal routine.
  926. */
  927. static void
  928. riva_set_rop_solid(struct riva_par *par, int rop)
  929. {
  930. riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
  931. RIVA_FIFO_FREE(par->riva, Rop, 1);
  932. NV_WR32(&par->riva.Rop->Rop3, 0, rop);
  933. }
  934. static void riva_setup_accel(struct fb_info *info)
  935. {
  936. struct riva_par *par = info->par;
  937. RIVA_FIFO_FREE(par->riva, Clip, 2);
  938. NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0);
  939. NV_WR32(&par->riva.Clip->WidthHeight, 0,
  940. (info->var.xres_virtual & 0xffff) |
  941. (info->var.yres_virtual << 16));
  942. riva_set_rop_solid(par, 0xcc);
  943. wait_for_idle(par);
  944. }
  945. /**
  946. * riva_get_cmap_len - query current color map length
  947. * @var: standard kernel fb changeable data
  948. *
  949. * DESCRIPTION:
  950. * Get current color map length.
  951. *
  952. * RETURNS:
  953. * Length of color map
  954. *
  955. * CALLED FROM:
  956. * rivafb_setcolreg()
  957. */
  958. static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
  959. {
  960. int rc = 256; /* reasonable default */
  961. switch (var->green.length) {
  962. case 8:
  963. rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */
  964. break;
  965. case 5:
  966. rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */
  967. break;
  968. case 6:
  969. rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */
  970. break;
  971. default:
  972. /* should not occur */
  973. break;
  974. }
  975. return rc;
  976. }
  977. /* ------------------------------------------------------------------------- *
  978. *
  979. * framebuffer operations
  980. *
  981. * ------------------------------------------------------------------------- */
  982. static int rivafb_open(struct fb_info *info, int user)
  983. {
  984. struct riva_par *par = info->par;
  985. int cnt = atomic_read(&par->ref_count);
  986. NVTRACE_ENTER();
  987. if (!cnt) {
  988. #ifdef CONFIG_X86
  989. memset(&par->state, 0, sizeof(struct vgastate));
  990. par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
  991. /* save the DAC for Riva128 */
  992. if (par->riva.Architecture == NV_ARCH_03)
  993. par->state.flags |= VGA_SAVE_CMAP;
  994. save_vga(&par->state);
  995. #endif
  996. /* vgaHWunlock() + riva unlock (0x7F) */
  997. CRTCout(par, 0x11, 0xFF);
  998. par->riva.LockUnlock(&par->riva, 0);
  999. riva_save_state(par, &par->initial_state);
  1000. }
  1001. atomic_inc(&par->ref_count);
  1002. NVTRACE_LEAVE();
  1003. return 0;
  1004. }
  1005. static int rivafb_release(struct fb_info *info, int user)
  1006. {
  1007. struct riva_par *par = info->par;
  1008. int cnt = atomic_read(&par->ref_count);
  1009. NVTRACE_ENTER();
  1010. if (!cnt)
  1011. return -EINVAL;
  1012. if (cnt == 1) {
  1013. par->riva.LockUnlock(&par->riva, 0);
  1014. par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
  1015. riva_load_state(par, &par->initial_state);
  1016. #ifdef CONFIG_X86
  1017. restore_vga(&par->state);
  1018. #endif
  1019. par->riva.LockUnlock(&par->riva, 1);
  1020. }
  1021. atomic_dec(&par->ref_count);
  1022. NVTRACE_LEAVE();
  1023. return 0;
  1024. }
  1025. static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
  1026. {
  1027. struct fb_videomode *mode;
  1028. struct riva_par *par = info->par;
  1029. int nom, den; /* translating from pixels->bytes */
  1030. int mode_valid = 0;
  1031. NVTRACE_ENTER();
  1032. switch (var->bits_per_pixel) {
  1033. case 1 ... 8:
  1034. var->red.offset = var->green.offset = var->blue.offset = 0;
  1035. var->red.length = var->green.length = var->blue.length = 8;
  1036. var->bits_per_pixel = 8;
  1037. nom = den = 1;
  1038. break;
  1039. case 9 ... 15:
  1040. var->green.length = 5;
  1041. /* fall through */
  1042. case 16:
  1043. var->bits_per_pixel = 16;
  1044. /* The Riva128 supports RGB555 only */
  1045. if (par->riva.Architecture == NV_ARCH_03)
  1046. var->green.length = 5;
  1047. if (var->green.length == 5) {
  1048. /* 0rrrrrgg gggbbbbb */
  1049. var->red.offset = 10;
  1050. var->green.offset = 5;
  1051. var->blue.offset = 0;
  1052. var->red.length = 5;
  1053. var->green.length = 5;
  1054. var->blue.length = 5;
  1055. } else {
  1056. /* rrrrrggg gggbbbbb */
  1057. var->red.offset = 11;
  1058. var->green.offset = 5;
  1059. var->blue.offset = 0;
  1060. var->red.length = 5;
  1061. var->green.length = 6;
  1062. var->blue.length = 5;
  1063. }
  1064. nom = 2;
  1065. den = 1;
  1066. break;
  1067. case 17 ... 32:
  1068. var->red.length = var->green.length = var->blue.length = 8;
  1069. var->bits_per_pixel = 32;
  1070. var->red.offset = 16;
  1071. var->green.offset = 8;
  1072. var->blue.offset = 0;
  1073. nom = 4;
  1074. den = 1;
  1075. break;
  1076. default:
  1077. printk(KERN_ERR PFX
  1078. "mode %dx%dx%d rejected...color depth not supported.\n",
  1079. var->xres, var->yres, var->bits_per_pixel);
  1080. NVTRACE("EXIT, returning -EINVAL\n");
  1081. return -EINVAL;
  1082. }
  1083. if (!strictmode) {
  1084. if (!info->monspecs.vfmax || !info->monspecs.hfmax ||
  1085. !info->monspecs.dclkmax || !fb_validate_mode(var, info))
  1086. mode_valid = 1;
  1087. }
  1088. /* calculate modeline if supported by monitor */
  1089. if (!mode_valid && info->monspecs.gtf) {
  1090. if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
  1091. mode_valid = 1;
  1092. }
  1093. if (!mode_valid) {
  1094. mode = fb_find_best_mode(var, &info->modelist);
  1095. if (mode) {
  1096. riva_update_var(var, mode);
  1097. mode_valid = 1;
  1098. }
  1099. }
  1100. if (!mode_valid && info->monspecs.modedb_len)
  1101. return -EINVAL;
  1102. if (var->xres_virtual < var->xres)
  1103. var->xres_virtual = var->xres;
  1104. if (var->yres_virtual <= var->yres)
  1105. var->yres_virtual = -1;
  1106. if (rivafb_do_maximize(info, var, nom, den) < 0)
  1107. return -EINVAL;
  1108. if (var->xoffset < 0)
  1109. var->xoffset = 0;
  1110. if (var->yoffset < 0)
  1111. var->yoffset = 0;
  1112. /* truncate xoffset and yoffset to maximum if too high */
  1113. if (var->xoffset > var->xres_virtual - var->xres)
  1114. var->xoffset = var->xres_virtual - var->xres - 1;
  1115. if (var->yoffset > var->yres_virtual - var->yres)
  1116. var->yoffset = var->yres_virtual - var->yres - 1;
  1117. var->red.msb_right =
  1118. var->green.msb_right =
  1119. var->blue.msb_right =
  1120. var->transp.offset = var->transp.length = var->transp.msb_right = 0;
  1121. NVTRACE_LEAVE();
  1122. return 0;
  1123. }
  1124. static int rivafb_set_par(struct fb_info *info)
  1125. {
  1126. struct riva_par *par = info->par;
  1127. NVTRACE_ENTER();
  1128. /* vgaHWunlock() + riva unlock (0x7F) */
  1129. CRTCout(par, 0x11, 0xFF);
  1130. par->riva.LockUnlock(&par->riva, 0);
  1131. riva_load_video_mode(info);
  1132. if(!(info->flags & FBINFO_HWACCEL_DISABLED))
  1133. riva_setup_accel(info);
  1134. par->cursor_reset = 1;
  1135. info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
  1136. info->fix.visual = (info->var.bits_per_pixel == 8) ?
  1137. FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
  1138. if (info->flags & FBINFO_HWACCEL_DISABLED)
  1139. info->pixmap.scan_align = 1;
  1140. else
  1141. info->pixmap.scan_align = 4;
  1142. NVTRACE_LEAVE();
  1143. return 0;
  1144. }
  1145. /**
  1146. * rivafb_pan_display
  1147. * @var: standard kernel fb changeable data
  1148. * @con: TODO
  1149. * @info: pointer to fb_info object containing info for current riva board
  1150. *
  1151. * DESCRIPTION:
  1152. * Pan (or wrap, depending on the `vmode' field) the display using the
  1153. * `xoffset' and `yoffset' fields of the `var' structure.
  1154. * If the values don't fit, return -EINVAL.
  1155. *
  1156. * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
  1157. */
  1158. static int rivafb_pan_display(struct fb_var_screeninfo *var,
  1159. struct fb_info *info)
  1160. {
  1161. struct riva_par *par = info->par;
  1162. unsigned int base;
  1163. NVTRACE_ENTER();
  1164. base = var->yoffset * info->fix.line_length + var->xoffset;
  1165. par->riva.SetStartAddress(&par->riva, base);
  1166. NVTRACE_LEAVE();
  1167. return 0;
  1168. }
  1169. static int rivafb_blank(int blank, struct fb_info *info)
  1170. {
  1171. struct riva_par *par= info->par;
  1172. unsigned char tmp, vesa;
  1173. tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
  1174. vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
  1175. NVTRACE_ENTER();
  1176. if (blank)
  1177. tmp |= 0x20;
  1178. switch (blank) {
  1179. case FB_BLANK_UNBLANK:
  1180. case FB_BLANK_NORMAL:
  1181. break;
  1182. case FB_BLANK_VSYNC_SUSPEND:
  1183. vesa |= 0x80;
  1184. break;
  1185. case FB_BLANK_HSYNC_SUSPEND:
  1186. vesa |= 0x40;
  1187. break;
  1188. case FB_BLANK_POWERDOWN:
  1189. vesa |= 0xc0;
  1190. break;
  1191. }
  1192. SEQout(par, 0x01, tmp);
  1193. CRTCout(par, 0x1a, vesa);
  1194. #ifdef CONFIG_FB_RIVA_BACKLIGHT
  1195. mutex_lock(&info->bl_mutex);
  1196. if (info->bl_dev) {
  1197. down(&info->bl_dev->sem);
  1198. info->bl_dev->props->power = blank;
  1199. info->bl_dev->props->update_status(info->bl_dev);
  1200. up(&info->bl_dev->sem);
  1201. }
  1202. mutex_unlock(&info->bl_mutex);
  1203. #endif
  1204. NVTRACE_LEAVE();
  1205. return 0;
  1206. }
  1207. /**
  1208. * rivafb_setcolreg
  1209. * @regno: register index
  1210. * @red: red component
  1211. * @green: green component
  1212. * @blue: blue component
  1213. * @transp: transparency
  1214. * @info: pointer to fb_info object containing info for current riva board
  1215. *
  1216. * DESCRIPTION:
  1217. * Set a single color register. The values supplied have a 16 bit
  1218. * magnitude.
  1219. *
  1220. * RETURNS:
  1221. * Return != 0 for invalid regno.
  1222. *
  1223. * CALLED FROM:
  1224. * fbcmap.c:fb_set_cmap()
  1225. */
  1226. static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
  1227. unsigned blue, unsigned transp,
  1228. struct fb_info *info)
  1229. {
  1230. struct riva_par *par = info->par;
  1231. RIVA_HW_INST *chip = &par->riva;
  1232. int i;
  1233. if (regno >= riva_get_cmap_len(&info->var))
  1234. return -EINVAL;
  1235. if (info->var.grayscale) {
  1236. /* gray = 0.30*R + 0.59*G + 0.11*B */
  1237. red = green = blue =
  1238. (red * 77 + green * 151 + blue * 28) >> 8;
  1239. }
  1240. if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
  1241. ((u32 *) info->pseudo_palette)[regno] =
  1242. (regno << info->var.red.offset) |
  1243. (regno << info->var.green.offset) |
  1244. (regno << info->var.blue.offset);
  1245. /*
  1246. * The Riva128 2D engine requires color information in
  1247. * TrueColor format even if framebuffer is in DirectColor
  1248. */
  1249. if (par->riva.Architecture == NV_ARCH_03) {
  1250. switch (info->var.bits_per_pixel) {
  1251. case 16:
  1252. par->palette[regno] = ((red & 0xf800) >> 1) |
  1253. ((green & 0xf800) >> 6) |
  1254. ((blue & 0xf800) >> 11);
  1255. break;
  1256. case 32:
  1257. par->palette[regno] = ((red & 0xff00) << 8) |
  1258. ((green & 0xff00)) |
  1259. ((blue & 0xff00) >> 8);
  1260. break;
  1261. }
  1262. }
  1263. }
  1264. switch (info->var.bits_per_pixel) {
  1265. case 8:
  1266. /* "transparent" stuff is completely ignored. */
  1267. riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
  1268. break;
  1269. case 16:
  1270. if (info->var.green.length == 5) {
  1271. for (i = 0; i < 8; i++) {
  1272. riva_wclut(chip, regno*8+i, red >> 8,
  1273. green >> 8, blue >> 8);
  1274. }
  1275. } else {
  1276. u8 r, g, b;
  1277. if (regno < 32) {
  1278. for (i = 0; i < 8; i++) {
  1279. riva_wclut(chip, regno*8+i,
  1280. red >> 8, green >> 8,
  1281. blue >> 8);
  1282. }
  1283. }
  1284. riva_rclut(chip, regno*4, &r, &g, &b);
  1285. for (i = 0; i < 4; i++)
  1286. riva_wclut(chip, regno*4+i, r,
  1287. green >> 8, b);
  1288. }
  1289. break;
  1290. case 32:
  1291. riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
  1292. break;
  1293. default:
  1294. /* do nothing */
  1295. break;
  1296. }
  1297. return 0;
  1298. }
  1299. /**
  1300. * rivafb_fillrect - hardware accelerated color fill function
  1301. * @info: pointer to fb_info structure
  1302. * @rect: pointer to fb_fillrect structure
  1303. *
  1304. * DESCRIPTION:
  1305. * This function fills up a region of framebuffer memory with a solid
  1306. * color with a choice of two different ROP's, copy or invert.
  1307. *
  1308. * CALLED FROM:
  1309. * framebuffer hook
  1310. */
  1311. static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
  1312. {
  1313. struct riva_par *par = info->par;
  1314. u_int color, rop = 0;
  1315. if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
  1316. cfb_fillrect(info, rect);
  1317. return;
  1318. }
  1319. if (info->var.bits_per_pixel == 8)
  1320. color = rect->color;
  1321. else {
  1322. if (par->riva.Architecture != NV_ARCH_03)
  1323. color = ((u32 *)info->pseudo_palette)[rect->color];
  1324. else
  1325. color = par->palette[rect->color];
  1326. }
  1327. switch (rect->rop) {
  1328. case ROP_XOR:
  1329. rop = 0x66;
  1330. break;
  1331. case ROP_COPY:
  1332. default:
  1333. rop = 0xCC;
  1334. break;
  1335. }
  1336. riva_set_rop_solid(par, rop);
  1337. RIVA_FIFO_FREE(par->riva, Bitmap, 1);
  1338. NV_WR32(&par->riva.Bitmap->Color1A, 0, color);
  1339. RIVA_FIFO_FREE(par->riva, Bitmap, 2);
  1340. NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0,
  1341. (rect->dx << 16) | rect->dy);
  1342. mb();
  1343. NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0,
  1344. (rect->width << 16) | rect->height);
  1345. mb();
  1346. riva_set_rop_solid(par, 0xcc);
  1347. }
  1348. /**
  1349. * rivafb_copyarea - hardware accelerated blit function
  1350. * @info: pointer to fb_info structure
  1351. * @region: pointer to fb_copyarea structure
  1352. *
  1353. * DESCRIPTION:
  1354. * This copies an area of pixels from one location to another
  1355. *
  1356. * CALLED FROM:
  1357. * framebuffer hook
  1358. */
  1359. static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
  1360. {
  1361. struct riva_par *par = info->par;
  1362. if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
  1363. cfb_copyarea(info, region);
  1364. return;
  1365. }
  1366. RIVA_FIFO_FREE(par->riva, Blt, 3);
  1367. NV_WR32(&par->riva.Blt->TopLeftSrc, 0,
  1368. (region->sy << 16) | region->sx);
  1369. NV_WR32(&par->riva.Blt->TopLeftDst, 0,
  1370. (region->dy << 16) | region->dx);
  1371. mb();
  1372. NV_WR32(&par->riva.Blt->WidthHeight, 0,
  1373. (region->height << 16) | region->width);
  1374. mb();
  1375. }
  1376. static inline void convert_bgcolor_16(u32 *col)
  1377. {
  1378. *col = ((*col & 0x0000F800) << 8)
  1379. | ((*col & 0x00007E0) << 5)
  1380. | ((*col & 0x0000001F) << 3)
  1381. | 0xFF000000;
  1382. mb();
  1383. }
  1384. /**
  1385. * rivafb_imageblit: hardware accelerated color expand function
  1386. * @info: pointer to fb_info structure
  1387. * @image: pointer to fb_image structure
  1388. *
  1389. * DESCRIPTION:
  1390. * If the source is a monochrome bitmap, the function fills up a a region
  1391. * of framebuffer memory with pixels whose color is determined by the bit
  1392. * setting of the bitmap, 1 - foreground, 0 - background.
  1393. *
  1394. * If the source is not a monochrome bitmap, color expansion is not done.
  1395. * In this case, it is channeled to a software function.
  1396. *
  1397. * CALLED FROM:
  1398. * framebuffer hook
  1399. */
  1400. static void rivafb_imageblit(struct fb_info *info,
  1401. const struct fb_image *image)
  1402. {
  1403. struct riva_par *par = info->par;
  1404. u32 fgx = 0, bgx = 0, width, tmp;
  1405. u8 *cdat = (u8 *) image->data;
  1406. volatile u32 __iomem *d;
  1407. int i, size;
  1408. if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) {
  1409. cfb_imageblit(info, image);
  1410. return;
  1411. }
  1412. switch (info->var.bits_per_pixel) {
  1413. case 8:
  1414. fgx = image->fg_color;
  1415. bgx = image->bg_color;
  1416. break;
  1417. case 16:
  1418. case 32:
  1419. if (par->riva.Architecture != NV_ARCH_03) {
  1420. fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
  1421. bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
  1422. } else {
  1423. fgx = par->palette[image->fg_color];
  1424. bgx = par->palette[image->bg_color];
  1425. }
  1426. if (info->var.green.length == 6)
  1427. convert_bgcolor_16(&bgx);
  1428. break;
  1429. }
  1430. RIVA_FIFO_FREE(par->riva, Bitmap, 7);
  1431. NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0,
  1432. (image->dy << 16) | (image->dx & 0xFFFF));
  1433. NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0,
  1434. (((image->dy + image->height) << 16) |
  1435. ((image->dx + image->width) & 0xffff)));
  1436. NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx);
  1437. NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx);
  1438. NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0,
  1439. (image->height << 16) | ((image->width + 31) & ~31));
  1440. NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0,
  1441. (image->height << 16) | ((image->width + 31) & ~31));
  1442. NV_WR32(&par->riva.Bitmap->PointE, 0,
  1443. (image->dy << 16) | (image->dx & 0xFFFF));
  1444. d = &par->riva.Bitmap->MonochromeData01E;
  1445. width = (image->width + 31)/32;
  1446. size = width * image->height;
  1447. while (size >= 16) {
  1448. RIVA_FIFO_FREE(par->riva, Bitmap, 16);
  1449. for (i = 0; i < 16; i++) {
  1450. tmp = *((u32 *)cdat);
  1451. cdat = (u8 *)((u32 *)cdat + 1);
  1452. reverse_order(&tmp);
  1453. NV_WR32(d, i*4, tmp);
  1454. }
  1455. size -= 16;
  1456. }
  1457. if (size) {
  1458. RIVA_FIFO_FREE(par->riva, Bitmap, size);
  1459. for (i = 0; i < size; i++) {
  1460. tmp = *((u32 *) cdat);
  1461. cdat = (u8 *)((u32 *)cdat + 1);
  1462. reverse_order(&tmp);
  1463. NV_WR32(d, i*4, tmp);
  1464. }
  1465. }
  1466. }
  1467. /**
  1468. * rivafb_cursor - hardware cursor function
  1469. * @info: pointer to info structure
  1470. * @cursor: pointer to fbcursor structure
  1471. *
  1472. * DESCRIPTION:
  1473. * A cursor function that supports displaying a cursor image via hardware.
  1474. * Within the kernel, copy and invert rops are supported. If exported
  1475. * to user space, only the copy rop will be supported.
  1476. *
  1477. * CALLED FROM
  1478. * framebuffer hook
  1479. */
  1480. static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
  1481. {
  1482. struct riva_par *par = info->par;
  1483. u8 data[MAX_CURS * MAX_CURS/8];
  1484. int i, set = cursor->set;
  1485. u16 fg, bg;
  1486. if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
  1487. return -ENXIO;
  1488. par->riva.ShowHideCursor(&par->riva, 0);
  1489. if (par->cursor_reset) {
  1490. set = FB_CUR_SETALL;
  1491. par->cursor_reset = 0;
  1492. }
  1493. if (set & FB_CUR_SETSIZE)
  1494. memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
  1495. if (set & FB_CUR_SETPOS) {
  1496. u32 xx, yy, temp;
  1497. yy = cursor->image.dy - info->var.yoffset;
  1498. xx = cursor->image.dx - info->var.xoffset;
  1499. temp = xx & 0xFFFF;
  1500. temp |= yy << 16;
  1501. NV_WR32(par->riva.PRAMDAC, 0x0000300, temp);
  1502. }
  1503. if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
  1504. u32 bg_idx = cursor->image.bg_color;
  1505. u32 fg_idx = cursor->image.fg_color;
  1506. u32 s_pitch = (cursor->image.width+7) >> 3;
  1507. u32 d_pitch = MAX_CURS/8;
  1508. u8 *dat = (u8 *) cursor->image.data;
  1509. u8 *msk = (u8 *) cursor->mask;
  1510. u8 *src;
  1511. src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
  1512. if (src) {
  1513. switch (cursor->rop) {
  1514. case ROP_XOR:
  1515. for (i = 0; i < s_pitch * cursor->image.height; i++)
  1516. src[i] = dat[i] ^ msk[i];
  1517. break;
  1518. case ROP_COPY:
  1519. default:
  1520. for (i = 0; i < s_pitch * cursor->image.height; i++)
  1521. src[i] = dat[i] & msk[i];
  1522. break;
  1523. }
  1524. fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
  1525. cursor->image.height);
  1526. bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
  1527. ((info->cmap.green[bg_idx] & 0xf8) << 2) |
  1528. ((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
  1529. 1 << 15;
  1530. fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
  1531. ((info->cmap.green[fg_idx] & 0xf8) << 2) |
  1532. ((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
  1533. 1 << 15;
  1534. par->riva.LockUnlock(&par->riva, 0);
  1535. rivafb_load_cursor_image(par, data, bg, fg,
  1536. cursor->image.width,
  1537. cursor->image.height);
  1538. kfree(src);
  1539. }
  1540. }
  1541. if (cursor->enable)
  1542. par->riva.ShowHideCursor(&par->riva, 1);
  1543. return 0;
  1544. }
  1545. static int rivafb_sync(struct fb_info *info)
  1546. {
  1547. struct riva_par *par = info->par;
  1548. wait_for_idle(par);
  1549. return 0;
  1550. }
  1551. /* ------------------------------------------------------------------------- *
  1552. *
  1553. * initialization helper functions
  1554. *
  1555. * ------------------------------------------------------------------------- */
  1556. /* kernel interface */
  1557. static struct fb_ops riva_fb_ops = {
  1558. .owner = THIS_MODULE,
  1559. .fb_open = rivafb_open,
  1560. .fb_release = rivafb_release,
  1561. .fb_check_var = rivafb_check_var,
  1562. .fb_set_par = rivafb_set_par,
  1563. .fb_setcolreg = rivafb_setcolreg,
  1564. .fb_pan_display = rivafb_pan_display,
  1565. .fb_blank = rivafb_blank,
  1566. .fb_fillrect = rivafb_fillrect,
  1567. .fb_copyarea = rivafb_copyarea,
  1568. .fb_imageblit = rivafb_imageblit,
  1569. .fb_cursor = rivafb_cursor,
  1570. .fb_sync = rivafb_sync,
  1571. };
  1572. static int __devinit riva_set_fbinfo(struct fb_info *info)
  1573. {
  1574. unsigned int cmap_len;
  1575. struct riva_par *par = info->par;
  1576. NVTRACE_ENTER();
  1577. info->flags = FBINFO_DEFAULT
  1578. | FBINFO_HWACCEL_XPAN
  1579. | FBINFO_HWACCEL_YPAN
  1580. | FBINFO_HWACCEL_COPYAREA
  1581. | FBINFO_HWACCEL_FILLRECT
  1582. | FBINFO_HWACCEL_IMAGEBLIT;
  1583. /* Accel seems to not work properly on NV30 yet...*/
  1584. if ((par->riva.Architecture == NV_ARCH_30) || noaccel) {
  1585. printk(KERN_DEBUG PFX "disabling acceleration\n");
  1586. info->flags |= FBINFO_HWACCEL_DISABLED;
  1587. }
  1588. info->var = rivafb_default_var;
  1589. info->fix.visual = (info->var.bits_per_pixel == 8) ?
  1590. FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
  1591. info->pseudo_palette = par->pseudo_palette;
  1592. cmap_len = riva_get_cmap_len(&info->var);
  1593. fb_alloc_cmap(&info->cmap, cmap_len, 0);
  1594. info->pixmap.size = 8 * 1024;
  1595. info->pixmap.buf_align = 4;
  1596. info->pixmap.access_align = 32;
  1597. info->pixmap.flags = FB_PIXMAP_SYSTEM;
  1598. info->var.yres_virtual = -1;
  1599. NVTRACE_LEAVE();
  1600. return (rivafb_check_var(&info->var, info));
  1601. }
  1602. #ifdef CONFIG_PPC_OF
  1603. static int __devinit riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd)
  1604. {
  1605. struct riva_par *par = info->par;
  1606. struct device_node *dp;
  1607. unsigned char *pedid = NULL;
  1608. unsigned char *disptype = NULL;
  1609. static char *propnames[] = {
  1610. "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
  1611. int i;
  1612. NVTRACE_ENTER();
  1613. dp = pci_device_to_OF_node(pd);
  1614. for (; dp != NULL; dp = dp->child) {
  1615. disptype = (unsigned char *)get_property(dp, "display-type", NULL);
  1616. if (disptype == NULL)
  1617. continue;
  1618. if (strncmp(disptype, "LCD", 3) != 0)
  1619. continue;
  1620. for (i = 0; propnames[i] != NULL; ++i) {
  1621. pedid = (unsigned char *)
  1622. get_property(dp, propnames[i], NULL);
  1623. if (pedid != NULL) {
  1624. par->EDID = pedid;
  1625. NVTRACE("LCD found.\n");
  1626. return 1;
  1627. }
  1628. }
  1629. }
  1630. NVTRACE_LEAVE();
  1631. return 0;
  1632. }
  1633. #endif /* CONFIG_PPC_OF */
  1634. #if defined(CONFIG_FB_RIVA_I2C) && !defined(CONFIG_PPC_OF)
  1635. static int __devinit riva_get_EDID_i2c(struct fb_info *info)
  1636. {
  1637. struct riva_par *par = info->par;
  1638. struct fb_var_screeninfo var;
  1639. int i;
  1640. NVTRACE_ENTER();
  1641. riva_create_i2c_busses(par);
  1642. for (i = 0; i < par->bus; i++) {
  1643. riva_probe_i2c_connector(par, i+1, &par->EDID);
  1644. if (par->EDID && !fb_parse_edid(par->EDID, &var)) {
  1645. printk(PFX "Found EDID Block from BUS %i\n", i);
  1646. break;
  1647. }
  1648. }
  1649. NVTRACE_LEAVE();
  1650. return (par->EDID) ? 1 : 0;
  1651. }
  1652. #endif /* CONFIG_FB_RIVA_I2C */
  1653. static void __devinit riva_update_default_var(struct fb_var_screeninfo *var,
  1654. struct fb_info *info)
  1655. {
  1656. struct fb_monspecs *specs = &info->monspecs;
  1657. struct fb_videomode modedb;
  1658. NVTRACE_ENTER();
  1659. /* respect mode options */
  1660. if (mode_option) {
  1661. fb_find_mode(var, info, mode_option,
  1662. specs->modedb, specs->modedb_len,
  1663. NULL, 8);
  1664. } else if (specs->modedb != NULL) {
  1665. /* get preferred timing */
  1666. if (info->monspecs.misc & FB_MISC_1ST_DETAIL) {
  1667. int i;
  1668. for (i = 0; i < specs->modedb_len; i++) {
  1669. if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
  1670. modedb = specs->modedb[i];
  1671. break;
  1672. }
  1673. }
  1674. } else {
  1675. /* otherwise, get first mode in database */
  1676. modedb = specs->modedb[0];
  1677. }
  1678. var->bits_per_pixel = 8;
  1679. riva_update_var(var, &modedb);
  1680. }
  1681. NVTRACE_LEAVE();
  1682. }
  1683. static void __devinit riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
  1684. {
  1685. NVTRACE_ENTER();
  1686. #ifdef CONFIG_PPC_OF
  1687. if (!riva_get_EDID_OF(info, pdev))
  1688. printk(PFX "could not retrieve EDID from OF\n");
  1689. #elif defined(CONFIG_FB_RIVA_I2C)
  1690. if (!riva_get_EDID_i2c(info))
  1691. printk(PFX "could not retrieve EDID from DDC/I2C\n");
  1692. #endif
  1693. NVTRACE_LEAVE();
  1694. }
  1695. static void __devinit riva_get_edidinfo(struct fb_info *info)
  1696. {
  1697. struct fb_var_screeninfo *var = &rivafb_default_var;
  1698. struct riva_par *par = info->par;
  1699. fb_edid_to_monspecs(par->EDID, &info->monspecs);
  1700. fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len,
  1701. &info->modelist);
  1702. riva_update_default_var(var, info);
  1703. /* if user specified flatpanel, we respect that */
  1704. if (info->monspecs.input & FB_DISP_DDI)
  1705. par->FlatPanel = 1;
  1706. }
  1707. /* ------------------------------------------------------------------------- *
  1708. *
  1709. * PCI bus
  1710. *
  1711. * ------------------------------------------------------------------------- */
  1712. static u32 __devinit riva_get_arch(struct pci_dev *pd)
  1713. {
  1714. u32 arch = 0;
  1715. switch (pd->device & 0x0ff0) {
  1716. case 0x0100: /* GeForce 256 */
  1717. case 0x0110: /* GeForce2 MX */
  1718. case 0x0150: /* GeForce2 */
  1719. case 0x0170: /* GeForce4 MX */
  1720. case 0x0180: /* GeForce4 MX (8x AGP) */
  1721. case 0x01A0: /* nForce */
  1722. case 0x01F0: /* nForce2 */
  1723. arch = NV_ARCH_10;
  1724. break;
  1725. case 0x0200: /* GeForce3 */
  1726. case 0x0250: /* GeForce4 Ti */
  1727. case 0x0280: /* GeForce4 Ti (8x AGP) */
  1728. arch = NV_ARCH_20;
  1729. break;
  1730. case 0x0300: /* GeForceFX 5800 */
  1731. case 0x0310: /* GeForceFX 5600 */
  1732. case 0x0320: /* GeForceFX 5200 */
  1733. case 0x0330: /* GeForceFX 5900 */
  1734. case 0x0340: /* GeForceFX 5700 */
  1735. arch = NV_ARCH_30;
  1736. break;
  1737. case 0x0020: /* TNT, TNT2 */
  1738. arch = NV_ARCH_04;
  1739. break;
  1740. case 0x0010: /* Riva128 */
  1741. arch = NV_ARCH_03;
  1742. break;
  1743. default: /* unknown architecture */
  1744. break;
  1745. }
  1746. return arch;
  1747. }
  1748. static int __devinit rivafb_probe(struct pci_dev *pd,
  1749. const struct pci_device_id *ent)
  1750. {
  1751. struct riva_par *default_par;
  1752. struct fb_info *info;
  1753. int ret;
  1754. NVTRACE_ENTER();
  1755. assert(pd != NULL);
  1756. info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev);
  1757. if (!info) {
  1758. printk (KERN_ERR PFX "could not allocate memory\n");
  1759. ret = -ENOMEM;
  1760. goto err_ret;
  1761. }
  1762. default_par = info->par;
  1763. default_par->pdev = pd;
  1764. info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
  1765. if (info->pixmap.addr == NULL) {
  1766. ret = -ENOMEM;
  1767. goto err_framebuffer_release;
  1768. }
  1769. memset(info->pixmap.addr, 0, 8 * 1024);
  1770. ret = pci_enable_device(pd);
  1771. if (ret < 0) {
  1772. printk(KERN_ERR PFX "cannot enable PCI device\n");
  1773. goto err_free_pixmap;
  1774. }
  1775. ret = pci_request_regions(pd, "rivafb");
  1776. if (ret < 0) {
  1777. printk(KERN_ERR PFX "cannot request PCI regions\n");
  1778. goto err_disable_device;
  1779. }
  1780. default_par->riva.Architecture = riva_get_arch(pd);
  1781. default_par->Chipset = (pd->vendor << 16) | pd->device;
  1782. printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
  1783. if(default_par->riva.Architecture == 0) {
  1784. printk(KERN_ERR PFX "unknown NV_ARCH\n");
  1785. ret=-ENODEV;
  1786. goto err_release_region;
  1787. }
  1788. if(default_par->riva.Architecture == NV_ARCH_10 ||
  1789. default_par->riva.Architecture == NV_ARCH_20 ||
  1790. default_par->riva.Architecture == NV_ARCH_30) {
  1791. sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
  1792. } else {
  1793. sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture);
  1794. }
  1795. default_par->FlatPanel = flatpanel;
  1796. if (flatpanel == 1)
  1797. printk(KERN_INFO PFX "flatpanel support enabled\n");
  1798. default_par->forceCRTC = forceCRTC;
  1799. rivafb_fix.mmio_len = pci_resource_len(pd, 0);
  1800. rivafb_fix.smem_len = pci_resource_len(pd, 1);
  1801. {
  1802. /* enable IO and mem if not already done */
  1803. unsigned short cmd;
  1804. pci_read_config_word(pd, PCI_COMMAND, &cmd);
  1805. cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
  1806. pci_write_config_word(pd, PCI_COMMAND, cmd);
  1807. }
  1808. rivafb_fix.mmio_start = pci_resource_start(pd, 0);
  1809. rivafb_fix.smem_start = pci_resource_start(pd, 1);
  1810. default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
  1811. rivafb_fix.mmio_len);
  1812. if (!default_par->ctrl_base) {
  1813. printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
  1814. ret = -EIO;
  1815. goto err_release_region;
  1816. }
  1817. switch (default_par->riva.Architecture) {
  1818. case NV_ARCH_03:
  1819. /* Riva128's PRAMIN is in the "framebuffer" space
  1820. * Since these cards were never made with more than 8 megabytes
  1821. * we can safely allocate this separately.
  1822. */
  1823. default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
  1824. if (!default_par->riva.PRAMIN) {
  1825. printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
  1826. ret = -EIO;
  1827. goto err_iounmap_ctrl_base;
  1828. }
  1829. break;
  1830. case NV_ARCH_04:
  1831. case NV_ARCH_10:
  1832. case NV_ARCH_20:
  1833. case NV_ARCH_30:
  1834. default_par->riva.PCRTC0 =
  1835. (u32 __iomem *)(default_par->ctrl_base + 0x00600000);
  1836. default_par->riva.PRAMIN =
  1837. (u32 __iomem *)(default_par->ctrl_base + 0x00710000);
  1838. break;
  1839. }
  1840. riva_common_setup(default_par);
  1841. if (default_par->riva.Architecture == NV_ARCH_03) {
  1842. default_par->riva.PCRTC = default_par->riva.PCRTC0
  1843. = default_par->riva.PGRAPH;
  1844. }
  1845. rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
  1846. default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
  1847. info->screen_base = ioremap(rivafb_fix.smem_start,
  1848. rivafb_fix.smem_len);
  1849. if (!info->screen_base) {
  1850. printk(KERN_ERR PFX "cannot ioremap FB base\n");
  1851. ret = -EIO;
  1852. goto err_iounmap_pramin;
  1853. }
  1854. #ifdef CONFIG_MTRR
  1855. if (!nomtrr) {
  1856. default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start,
  1857. rivafb_fix.smem_len,
  1858. MTRR_TYPE_WRCOMB, 1);
  1859. if (default_par->mtrr.vram < 0) {
  1860. printk(KERN_ERR PFX "unable to setup MTRR\n");
  1861. } else {
  1862. default_par->mtrr.vram_valid = 1;
  1863. /* let there be speed */
  1864. printk(KERN_INFO PFX "RIVA MTRR set to ON\n");
  1865. }
  1866. }
  1867. #endif /* CONFIG_MTRR */
  1868. info->fbops = &riva_fb_ops;
  1869. info->fix = rivafb_fix;
  1870. riva_get_EDID(info, pd);
  1871. riva_get_edidinfo(info);
  1872. ret=riva_set_fbinfo(info);
  1873. if (ret < 0) {
  1874. printk(KERN_ERR PFX "error setting initial video mode\n");
  1875. goto err_iounmap_screen_base;
  1876. }
  1877. fb_destroy_modedb(info->monspecs.modedb);
  1878. info->monspecs.modedb = NULL;
  1879. ret = register_framebuffer(info);
  1880. if (ret < 0) {
  1881. printk(KERN_ERR PFX
  1882. "error registering riva framebuffer\n");
  1883. goto err_iounmap_screen_base;
  1884. }
  1885. pci_set_drvdata(pd, info);
  1886. printk(KERN_INFO PFX
  1887. "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n",
  1888. info->fix.id,
  1889. RIVAFB_VERSION,
  1890. info->fix.smem_len / (1024 * 1024),
  1891. info->fix.smem_start);
  1892. riva_bl_init(info->par);
  1893. NVTRACE_LEAVE();
  1894. return 0;
  1895. err_iounmap_screen_base:
  1896. #ifdef CONFIG_FB_RIVA_I2C
  1897. riva_delete_i2c_busses(info->par);
  1898. #endif
  1899. iounmap(info->screen_base);
  1900. err_iounmap_pramin:
  1901. if (default_par->riva.Architecture == NV_ARCH_03)
  1902. iounmap(default_par->riva.PRAMIN);
  1903. err_iounmap_ctrl_base:
  1904. iounmap(default_par->ctrl_base);
  1905. err_release_region:
  1906. pci_release_regions(pd);
  1907. err_disable_device:
  1908. pci_disable_device(pd);
  1909. err_free_pixmap:
  1910. kfree(info->pixmap.addr);
  1911. err_framebuffer_release:
  1912. framebuffer_release(info);
  1913. err_ret:
  1914. return ret;
  1915. }
  1916. static void __exit rivafb_remove(struct pci_dev *pd)
  1917. {
  1918. struct fb_info *info = pci_get_drvdata(pd);
  1919. struct riva_par *par = info->par;
  1920. NVTRACE_ENTER();
  1921. riva_bl_exit(par);
  1922. #ifdef CONFIG_FB_RIVA_I2C
  1923. riva_delete_i2c_busses(par);
  1924. kfree(par->EDID);
  1925. #endif
  1926. unregister_framebuffer(info);
  1927. #ifdef CONFIG_MTRR
  1928. if (par->mtrr.vram_valid)
  1929. mtrr_del(par->mtrr.vram, info->fix.smem_start,
  1930. info->fix.smem_len);
  1931. #endif /* CONFIG_MTRR */
  1932. iounmap(par->ctrl_base);
  1933. iounmap(info->screen_base);
  1934. if (par->riva.Architecture == NV_ARCH_03)
  1935. iounmap(par->riva.PRAMIN);
  1936. pci_release_regions(pd);
  1937. pci_disable_device(pd);
  1938. kfree(info->pixmap.addr);
  1939. framebuffer_release(info);
  1940. pci_set_drvdata(pd, NULL);
  1941. NVTRACE_LEAVE();
  1942. }
  1943. /* ------------------------------------------------------------------------- *
  1944. *
  1945. * initialization
  1946. *
  1947. * ------------------------------------------------------------------------- */
  1948. #ifndef MODULE
  1949. static int __init rivafb_setup(char *options)
  1950. {
  1951. char *this_opt;
  1952. NVTRACE_ENTER();
  1953. if (!options || !*options)
  1954. return 0;
  1955. while ((this_opt = strsep(&options, ",")) != NULL) {
  1956. if (!strncmp(this_opt, "forceCRTC", 9)) {
  1957. char *p;
  1958. p = this_opt + 9;
  1959. if (!*p || !*(++p)) continue;
  1960. forceCRTC = *p - '0';
  1961. if (forceCRTC < 0 || forceCRTC > 1)
  1962. forceCRTC = -1;
  1963. } else if (!strncmp(this_opt, "flatpanel", 9)) {
  1964. flatpanel = 1;
  1965. #ifdef CONFIG_MTRR
  1966. } else if (!strncmp(this_opt, "nomtrr", 6)) {
  1967. nomtrr = 1;
  1968. #endif
  1969. } else if (!strncmp(this_opt, "strictmode", 10)) {
  1970. strictmode = 1;
  1971. } else if (!strncmp(this_opt, "noaccel", 7)) {
  1972. noaccel = 1;
  1973. } else
  1974. mode_option = this_opt;
  1975. }
  1976. NVTRACE_LEAVE();
  1977. return 0;
  1978. }
  1979. #endif /* !MODULE */
  1980. static struct pci_driver rivafb_driver = {
  1981. .name = "rivafb",
  1982. .id_table = rivafb_pci_tbl,
  1983. .probe = rivafb_probe,
  1984. .remove = __exit_p(rivafb_remove),
  1985. };
  1986. /* ------------------------------------------------------------------------- *
  1987. *
  1988. * modularization
  1989. *
  1990. * ------------------------------------------------------------------------- */
  1991. static int __devinit rivafb_init(void)
  1992. {
  1993. #ifndef MODULE
  1994. char *option = NULL;
  1995. if (fb_get_options("rivafb", &option))
  1996. return -ENODEV;
  1997. rivafb_setup(option);
  1998. #endif
  1999. return pci_register_driver(&rivafb_driver);
  2000. }
  2001. module_init(rivafb_init);
  2002. #ifdef MODULE
  2003. static void __exit rivafb_exit(void)
  2004. {
  2005. pci_unregister_driver(&rivafb_driver);
  2006. }
  2007. module_exit(rivafb_exit);
  2008. #endif /* MODULE */
  2009. module_param(noaccel, bool, 0);
  2010. MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
  2011. module_param(flatpanel, int, 0);
  2012. MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
  2013. module_param(forceCRTC, int, 0);
  2014. MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
  2015. #ifdef CONFIG_MTRR
  2016. module_param(nomtrr, bool, 0);
  2017. MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
  2018. #endif
  2019. module_param(strictmode, bool, 0);
  2020. MODULE_PARM_DESC(strictmode, "Only use video modes from EDID");
  2021. MODULE_AUTHOR("Ani Joshi, maintainer");
  2022. MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
  2023. MODULE_LICENSE("GPL");