sh73a0.dtsi 3.0 KB

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  1. /*
  2. * Device Tree Source for the SH73A0 SoC
  3. *
  4. * Copyright (C) 2012 Renesas Solutions Corp.
  5. *
  6. * This file is licensed under the terms of the GNU General Public License
  7. * version 2. This program is licensed "as is" without any warranty of any
  8. * kind, whether express or implied.
  9. */
  10. /include/ "skeleton.dtsi"
  11. / {
  12. compatible = "renesas,sh73a0";
  13. cpus {
  14. #address-cells = <1>;
  15. #size-cells = <0>;
  16. cpu@0 {
  17. device_type = "cpu";
  18. compatible = "arm,cortex-a9";
  19. reg = <0>;
  20. };
  21. cpu@1 {
  22. device_type = "cpu";
  23. compatible = "arm,cortex-a9";
  24. reg = <1>;
  25. };
  26. };
  27. gic: interrupt-controller@f0001000 {
  28. compatible = "arm,cortex-a9-gic";
  29. #interrupt-cells = <3>;
  30. #address-cells = <1>;
  31. interrupt-controller;
  32. reg = <0xf0001000 0x1000>,
  33. <0xf0000100 0x100>;
  34. };
  35. i2c0: i2c@0xe6820000 {
  36. #address-cells = <1>;
  37. #size-cells = <0>;
  38. compatible = "renesas,rmobile-iic";
  39. reg = <0xe6820000 0x425>;
  40. interrupt-parent = <&gic>;
  41. interrupts = <0 167 0x4
  42. 0 168 0x4
  43. 0 169 0x4
  44. 0 170 0x4>;
  45. };
  46. i2c1: i2c@0xe6822000 {
  47. #address-cells = <1>;
  48. #size-cells = <0>;
  49. compatible = "renesas,rmobile-iic";
  50. reg = <0xe6822000 0x425>;
  51. interrupt-parent = <&gic>;
  52. interrupts = <0 51 0x4
  53. 0 52 0x4
  54. 0 53 0x4
  55. 0 54 0x4>;
  56. };
  57. i2c2: i2c@0xe6824000 {
  58. #address-cells = <1>;
  59. #size-cells = <0>;
  60. compatible = "renesas,rmobile-iic";
  61. reg = <0xe6824000 0x425>;
  62. interrupt-parent = <&gic>;
  63. interrupts = <0 171 0x4
  64. 0 172 0x4
  65. 0 173 0x4
  66. 0 174 0x4>;
  67. };
  68. i2c3: i2c@0xe6826000 {
  69. #address-cells = <1>;
  70. #size-cells = <0>;
  71. compatible = "renesas,rmobile-iic";
  72. reg = <0xe6826000 0x425>;
  73. interrupt-parent = <&gic>;
  74. interrupts = <0 183 0x4
  75. 0 184 0x4
  76. 0 185 0x4
  77. 0 186 0x4>;
  78. };
  79. i2c4: i2c@0xe6828000 {
  80. #address-cells = <1>;
  81. #size-cells = <0>;
  82. compatible = "renesas,rmobile-iic";
  83. reg = <0xe6828000 0x425>;
  84. interrupt-parent = <&gic>;
  85. interrupts = <0 187 0x4
  86. 0 188 0x4
  87. 0 189 0x4
  88. 0 190 0x4>;
  89. };
  90. mmcif: mmcif@0x10010000 {
  91. compatible = "renesas,sh-mmcif";
  92. reg = <0xe6bd0000 0x100>;
  93. interrupt-parent = <&gic>;
  94. interrupts = <0 140 0x4
  95. 0 141 0x4>;
  96. reg-io-width = <4>;
  97. status = "disabled";
  98. };
  99. sdhi0: sdhi@0xee100000 {
  100. compatible = "renesas,shmobile-sdhi";
  101. reg = <0xee100000 0x100>;
  102. interrupt-parent = <&gic>;
  103. interrupts = <0 83 4
  104. 0 84 4
  105. 0 85 4>;
  106. toshiba,mmc-has-idle-wait;
  107. status = "disabled";
  108. };
  109. /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
  110. sdhi1: sdhi@0xee120000 {
  111. compatible = "renesas,shmobile-sdhi";
  112. reg = <0xee120000 0x100>;
  113. interrupt-parent = <&gic>;
  114. interrupts = <0 88 4
  115. 0 89 4>;
  116. toshiba,mmc-wrprotect-disable;
  117. toshiba,mmc-has-idle-wait;
  118. status = "disabled";
  119. };
  120. sdhi2: sdhi@0xee140000 {
  121. compatible = "renesas,shmobile-sdhi";
  122. reg = <0xee140000 0x100>;
  123. interrupt-parent = <&gic>;
  124. interrupts = <0 104 4
  125. 0 105 4>;
  126. toshiba,mmc-wrprotect-disable;
  127. toshiba,mmc-has-idle-wait;
  128. status = "disabled";
  129. };
  130. };