smsc75xx.c 56 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286
  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2007-2010 SMSC
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18. *
  19. *****************************************************************************/
  20. #include <linux/module.h>
  21. #include <linux/kmod.h>
  22. #include <linux/init.h>
  23. #include <linux/netdevice.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/mii.h>
  27. #include <linux/usb.h>
  28. #include <linux/bitrev.h>
  29. #include <linux/crc16.h>
  30. #include <linux/crc32.h>
  31. #include <linux/usb/usbnet.h>
  32. #include <linux/slab.h>
  33. #include "smsc75xx.h"
  34. #define SMSC_CHIPNAME "smsc75xx"
  35. #define SMSC_DRIVER_VERSION "1.0.0"
  36. #define HS_USB_PKT_SIZE (512)
  37. #define FS_USB_PKT_SIZE (64)
  38. #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
  39. #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
  40. #define DEFAULT_BULK_IN_DELAY (0x00002000)
  41. #define MAX_SINGLE_PACKET_SIZE (9000)
  42. #define LAN75XX_EEPROM_MAGIC (0x7500)
  43. #define EEPROM_MAC_OFFSET (0x01)
  44. #define DEFAULT_TX_CSUM_ENABLE (true)
  45. #define DEFAULT_RX_CSUM_ENABLE (true)
  46. #define DEFAULT_TSO_ENABLE (true)
  47. #define SMSC75XX_INTERNAL_PHY_ID (1)
  48. #define SMSC75XX_TX_OVERHEAD (8)
  49. #define MAX_RX_FIFO_SIZE (20 * 1024)
  50. #define MAX_TX_FIFO_SIZE (12 * 1024)
  51. #define USB_VENDOR_ID_SMSC (0x0424)
  52. #define USB_PRODUCT_ID_LAN7500 (0x7500)
  53. #define USB_PRODUCT_ID_LAN7505 (0x7505)
  54. #define RXW_PADDING 2
  55. #define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
  56. WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
  57. #define SUSPEND_SUSPEND0 (0x01)
  58. #define SUSPEND_SUSPEND1 (0x02)
  59. #define SUSPEND_SUSPEND2 (0x04)
  60. #define SUSPEND_SUSPEND3 (0x08)
  61. #define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
  62. SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
  63. struct smsc75xx_priv {
  64. struct usbnet *dev;
  65. u32 rfe_ctl;
  66. u32 wolopts;
  67. u32 multicast_hash_table[DP_SEL_VHF_HASH_LEN];
  68. struct mutex dataport_mutex;
  69. spinlock_t rfe_ctl_lock;
  70. struct work_struct set_multicast;
  71. u8 suspend_flags;
  72. };
  73. struct usb_context {
  74. struct usb_ctrlrequest req;
  75. struct usbnet *dev;
  76. };
  77. static bool turbo_mode = true;
  78. module_param(turbo_mode, bool, 0644);
  79. MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
  80. static int __must_check __smsc75xx_read_reg(struct usbnet *dev, u32 index,
  81. u32 *data, int in_pm)
  82. {
  83. u32 buf;
  84. int ret;
  85. int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
  86. BUG_ON(!dev);
  87. if (!in_pm)
  88. fn = usbnet_read_cmd;
  89. else
  90. fn = usbnet_read_cmd_nopm;
  91. ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
  92. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  93. 0, index, &buf, 4);
  94. if (unlikely(ret < 0))
  95. netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
  96. index, ret);
  97. le32_to_cpus(&buf);
  98. *data = buf;
  99. return ret;
  100. }
  101. static int __must_check __smsc75xx_write_reg(struct usbnet *dev, u32 index,
  102. u32 data, int in_pm)
  103. {
  104. u32 buf;
  105. int ret;
  106. int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
  107. BUG_ON(!dev);
  108. if (!in_pm)
  109. fn = usbnet_write_cmd;
  110. else
  111. fn = usbnet_write_cmd_nopm;
  112. buf = data;
  113. cpu_to_le32s(&buf);
  114. ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
  115. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  116. 0, index, &buf, 4);
  117. if (unlikely(ret < 0))
  118. netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
  119. index, ret);
  120. return ret;
  121. }
  122. static int __must_check smsc75xx_read_reg_nopm(struct usbnet *dev, u32 index,
  123. u32 *data)
  124. {
  125. return __smsc75xx_read_reg(dev, index, data, 1);
  126. }
  127. static int __must_check smsc75xx_write_reg_nopm(struct usbnet *dev, u32 index,
  128. u32 data)
  129. {
  130. return __smsc75xx_write_reg(dev, index, data, 1);
  131. }
  132. static int __must_check smsc75xx_read_reg(struct usbnet *dev, u32 index,
  133. u32 *data)
  134. {
  135. return __smsc75xx_read_reg(dev, index, data, 0);
  136. }
  137. static int __must_check smsc75xx_write_reg(struct usbnet *dev, u32 index,
  138. u32 data)
  139. {
  140. return __smsc75xx_write_reg(dev, index, data, 0);
  141. }
  142. /* Loop until the read is completed with timeout
  143. * called with phy_mutex held */
  144. static __must_check int __smsc75xx_phy_wait_not_busy(struct usbnet *dev,
  145. int in_pm)
  146. {
  147. unsigned long start_time = jiffies;
  148. u32 val;
  149. int ret;
  150. do {
  151. ret = __smsc75xx_read_reg(dev, MII_ACCESS, &val, in_pm);
  152. if (ret < 0) {
  153. netdev_warn(dev->net, "Error reading MII_ACCESS\n");
  154. return ret;
  155. }
  156. if (!(val & MII_ACCESS_BUSY))
  157. return 0;
  158. } while (!time_after(jiffies, start_time + HZ));
  159. return -EIO;
  160. }
  161. static int __smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
  162. int in_pm)
  163. {
  164. struct usbnet *dev = netdev_priv(netdev);
  165. u32 val, addr;
  166. int ret;
  167. mutex_lock(&dev->phy_mutex);
  168. /* confirm MII not busy */
  169. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  170. if (ret < 0) {
  171. netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_read\n");
  172. goto done;
  173. }
  174. /* set the address, index & direction (read from PHY) */
  175. phy_id &= dev->mii.phy_id_mask;
  176. idx &= dev->mii.reg_num_mask;
  177. addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
  178. | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
  179. | MII_ACCESS_READ | MII_ACCESS_BUSY;
  180. ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
  181. if (ret < 0) {
  182. netdev_warn(dev->net, "Error writing MII_ACCESS\n");
  183. goto done;
  184. }
  185. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  186. if (ret < 0) {
  187. netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
  188. goto done;
  189. }
  190. ret = __smsc75xx_read_reg(dev, MII_DATA, &val, in_pm);
  191. if (ret < 0) {
  192. netdev_warn(dev->net, "Error reading MII_DATA\n");
  193. goto done;
  194. }
  195. ret = (u16)(val & 0xFFFF);
  196. done:
  197. mutex_unlock(&dev->phy_mutex);
  198. return ret;
  199. }
  200. static void __smsc75xx_mdio_write(struct net_device *netdev, int phy_id,
  201. int idx, int regval, int in_pm)
  202. {
  203. struct usbnet *dev = netdev_priv(netdev);
  204. u32 val, addr;
  205. int ret;
  206. mutex_lock(&dev->phy_mutex);
  207. /* confirm MII not busy */
  208. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  209. if (ret < 0) {
  210. netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_write\n");
  211. goto done;
  212. }
  213. val = regval;
  214. ret = __smsc75xx_write_reg(dev, MII_DATA, val, in_pm);
  215. if (ret < 0) {
  216. netdev_warn(dev->net, "Error writing MII_DATA\n");
  217. goto done;
  218. }
  219. /* set the address, index & direction (write to PHY) */
  220. phy_id &= dev->mii.phy_id_mask;
  221. idx &= dev->mii.reg_num_mask;
  222. addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
  223. | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
  224. | MII_ACCESS_WRITE | MII_ACCESS_BUSY;
  225. ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
  226. if (ret < 0) {
  227. netdev_warn(dev->net, "Error writing MII_ACCESS\n");
  228. goto done;
  229. }
  230. ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
  231. if (ret < 0) {
  232. netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
  233. goto done;
  234. }
  235. done:
  236. mutex_unlock(&dev->phy_mutex);
  237. }
  238. static int smsc75xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
  239. int idx)
  240. {
  241. return __smsc75xx_mdio_read(netdev, phy_id, idx, 1);
  242. }
  243. static void smsc75xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
  244. int idx, int regval)
  245. {
  246. __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 1);
  247. }
  248. static int smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
  249. {
  250. return __smsc75xx_mdio_read(netdev, phy_id, idx, 0);
  251. }
  252. static void smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
  253. int regval)
  254. {
  255. __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 0);
  256. }
  257. static int smsc75xx_wait_eeprom(struct usbnet *dev)
  258. {
  259. unsigned long start_time = jiffies;
  260. u32 val;
  261. int ret;
  262. do {
  263. ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
  264. if (ret < 0) {
  265. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  266. return ret;
  267. }
  268. if (!(val & E2P_CMD_BUSY) || (val & E2P_CMD_TIMEOUT))
  269. break;
  270. udelay(40);
  271. } while (!time_after(jiffies, start_time + HZ));
  272. if (val & (E2P_CMD_TIMEOUT | E2P_CMD_BUSY)) {
  273. netdev_warn(dev->net, "EEPROM read operation timeout\n");
  274. return -EIO;
  275. }
  276. return 0;
  277. }
  278. static int smsc75xx_eeprom_confirm_not_busy(struct usbnet *dev)
  279. {
  280. unsigned long start_time = jiffies;
  281. u32 val;
  282. int ret;
  283. do {
  284. ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
  285. if (ret < 0) {
  286. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  287. return ret;
  288. }
  289. if (!(val & E2P_CMD_BUSY))
  290. return 0;
  291. udelay(40);
  292. } while (!time_after(jiffies, start_time + HZ));
  293. netdev_warn(dev->net, "EEPROM is busy\n");
  294. return -EIO;
  295. }
  296. static int smsc75xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
  297. u8 *data)
  298. {
  299. u32 val;
  300. int i, ret;
  301. BUG_ON(!dev);
  302. BUG_ON(!data);
  303. ret = smsc75xx_eeprom_confirm_not_busy(dev);
  304. if (ret)
  305. return ret;
  306. for (i = 0; i < length; i++) {
  307. val = E2P_CMD_BUSY | E2P_CMD_READ | (offset & E2P_CMD_ADDR);
  308. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  309. if (ret < 0) {
  310. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  311. return ret;
  312. }
  313. ret = smsc75xx_wait_eeprom(dev);
  314. if (ret < 0)
  315. return ret;
  316. ret = smsc75xx_read_reg(dev, E2P_DATA, &val);
  317. if (ret < 0) {
  318. netdev_warn(dev->net, "Error reading E2P_DATA\n");
  319. return ret;
  320. }
  321. data[i] = val & 0xFF;
  322. offset++;
  323. }
  324. return 0;
  325. }
  326. static int smsc75xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
  327. u8 *data)
  328. {
  329. u32 val;
  330. int i, ret;
  331. BUG_ON(!dev);
  332. BUG_ON(!data);
  333. ret = smsc75xx_eeprom_confirm_not_busy(dev);
  334. if (ret)
  335. return ret;
  336. /* Issue write/erase enable command */
  337. val = E2P_CMD_BUSY | E2P_CMD_EWEN;
  338. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  339. if (ret < 0) {
  340. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  341. return ret;
  342. }
  343. ret = smsc75xx_wait_eeprom(dev);
  344. if (ret < 0)
  345. return ret;
  346. for (i = 0; i < length; i++) {
  347. /* Fill data register */
  348. val = data[i];
  349. ret = smsc75xx_write_reg(dev, E2P_DATA, val);
  350. if (ret < 0) {
  351. netdev_warn(dev->net, "Error writing E2P_DATA\n");
  352. return ret;
  353. }
  354. /* Send "write" command */
  355. val = E2P_CMD_BUSY | E2P_CMD_WRITE | (offset & E2P_CMD_ADDR);
  356. ret = smsc75xx_write_reg(dev, E2P_CMD, val);
  357. if (ret < 0) {
  358. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  359. return ret;
  360. }
  361. ret = smsc75xx_wait_eeprom(dev);
  362. if (ret < 0)
  363. return ret;
  364. offset++;
  365. }
  366. return 0;
  367. }
  368. static int smsc75xx_dataport_wait_not_busy(struct usbnet *dev)
  369. {
  370. int i, ret;
  371. for (i = 0; i < 100; i++) {
  372. u32 dp_sel;
  373. ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
  374. if (ret < 0) {
  375. netdev_warn(dev->net, "Error reading DP_SEL\n");
  376. return ret;
  377. }
  378. if (dp_sel & DP_SEL_DPRDY)
  379. return 0;
  380. udelay(40);
  381. }
  382. netdev_warn(dev->net, "smsc75xx_dataport_wait_not_busy timed out\n");
  383. return -EIO;
  384. }
  385. static int smsc75xx_dataport_write(struct usbnet *dev, u32 ram_select, u32 addr,
  386. u32 length, u32 *buf)
  387. {
  388. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  389. u32 dp_sel;
  390. int i, ret;
  391. mutex_lock(&pdata->dataport_mutex);
  392. ret = smsc75xx_dataport_wait_not_busy(dev);
  393. if (ret < 0) {
  394. netdev_warn(dev->net, "smsc75xx_dataport_write busy on entry\n");
  395. goto done;
  396. }
  397. ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
  398. if (ret < 0) {
  399. netdev_warn(dev->net, "Error reading DP_SEL\n");
  400. goto done;
  401. }
  402. dp_sel &= ~DP_SEL_RSEL;
  403. dp_sel |= ram_select;
  404. ret = smsc75xx_write_reg(dev, DP_SEL, dp_sel);
  405. if (ret < 0) {
  406. netdev_warn(dev->net, "Error writing DP_SEL\n");
  407. goto done;
  408. }
  409. for (i = 0; i < length; i++) {
  410. ret = smsc75xx_write_reg(dev, DP_ADDR, addr + i);
  411. if (ret < 0) {
  412. netdev_warn(dev->net, "Error writing DP_ADDR\n");
  413. goto done;
  414. }
  415. ret = smsc75xx_write_reg(dev, DP_DATA, buf[i]);
  416. if (ret < 0) {
  417. netdev_warn(dev->net, "Error writing DP_DATA\n");
  418. goto done;
  419. }
  420. ret = smsc75xx_write_reg(dev, DP_CMD, DP_CMD_WRITE);
  421. if (ret < 0) {
  422. netdev_warn(dev->net, "Error writing DP_CMD\n");
  423. goto done;
  424. }
  425. ret = smsc75xx_dataport_wait_not_busy(dev);
  426. if (ret < 0) {
  427. netdev_warn(dev->net, "smsc75xx_dataport_write timeout\n");
  428. goto done;
  429. }
  430. }
  431. done:
  432. mutex_unlock(&pdata->dataport_mutex);
  433. return ret;
  434. }
  435. /* returns hash bit number for given MAC address */
  436. static u32 smsc75xx_hash(char addr[ETH_ALEN])
  437. {
  438. return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff;
  439. }
  440. static void smsc75xx_deferred_multicast_write(struct work_struct *param)
  441. {
  442. struct smsc75xx_priv *pdata =
  443. container_of(param, struct smsc75xx_priv, set_multicast);
  444. struct usbnet *dev = pdata->dev;
  445. int ret;
  446. netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x\n",
  447. pdata->rfe_ctl);
  448. smsc75xx_dataport_write(dev, DP_SEL_VHF, DP_SEL_VHF_VLAN_LEN,
  449. DP_SEL_VHF_HASH_LEN, pdata->multicast_hash_table);
  450. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  451. if (ret < 0)
  452. netdev_warn(dev->net, "Error writing RFE_CRL\n");
  453. }
  454. static void smsc75xx_set_multicast(struct net_device *netdev)
  455. {
  456. struct usbnet *dev = netdev_priv(netdev);
  457. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  458. unsigned long flags;
  459. int i;
  460. spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
  461. pdata->rfe_ctl &=
  462. ~(RFE_CTL_AU | RFE_CTL_AM | RFE_CTL_DPF | RFE_CTL_MHF);
  463. pdata->rfe_ctl |= RFE_CTL_AB;
  464. for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++)
  465. pdata->multicast_hash_table[i] = 0;
  466. if (dev->net->flags & IFF_PROMISC) {
  467. netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
  468. pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_AU;
  469. } else if (dev->net->flags & IFF_ALLMULTI) {
  470. netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
  471. pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_DPF;
  472. } else if (!netdev_mc_empty(dev->net)) {
  473. struct netdev_hw_addr *ha;
  474. netif_dbg(dev, drv, dev->net, "receive multicast hash filter\n");
  475. pdata->rfe_ctl |= RFE_CTL_MHF | RFE_CTL_DPF;
  476. netdev_for_each_mc_addr(ha, netdev) {
  477. u32 bitnum = smsc75xx_hash(ha->addr);
  478. pdata->multicast_hash_table[bitnum / 32] |=
  479. (1 << (bitnum % 32));
  480. }
  481. } else {
  482. netif_dbg(dev, drv, dev->net, "receive own packets only\n");
  483. pdata->rfe_ctl |= RFE_CTL_DPF;
  484. }
  485. spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
  486. /* defer register writes to a sleepable context */
  487. schedule_work(&pdata->set_multicast);
  488. }
  489. static int smsc75xx_update_flowcontrol(struct usbnet *dev, u8 duplex,
  490. u16 lcladv, u16 rmtadv)
  491. {
  492. u32 flow = 0, fct_flow = 0;
  493. int ret;
  494. if (duplex == DUPLEX_FULL) {
  495. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  496. if (cap & FLOW_CTRL_TX) {
  497. flow = (FLOW_TX_FCEN | 0xFFFF);
  498. /* set fct_flow thresholds to 20% and 80% */
  499. fct_flow = (8 << 8) | 32;
  500. }
  501. if (cap & FLOW_CTRL_RX)
  502. flow |= FLOW_RX_FCEN;
  503. netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
  504. (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
  505. (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
  506. } else {
  507. netif_dbg(dev, link, dev->net, "half duplex\n");
  508. }
  509. ret = smsc75xx_write_reg(dev, FLOW, flow);
  510. if (ret < 0) {
  511. netdev_warn(dev->net, "Error writing FLOW\n");
  512. return ret;
  513. }
  514. ret = smsc75xx_write_reg(dev, FCT_FLOW, fct_flow);
  515. if (ret < 0) {
  516. netdev_warn(dev->net, "Error writing FCT_FLOW\n");
  517. return ret;
  518. }
  519. return 0;
  520. }
  521. static int smsc75xx_link_reset(struct usbnet *dev)
  522. {
  523. struct mii_if_info *mii = &dev->mii;
  524. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  525. u16 lcladv, rmtadv;
  526. int ret;
  527. /* write to clear phy interrupt status */
  528. smsc75xx_mdio_write(dev->net, mii->phy_id, PHY_INT_SRC,
  529. PHY_INT_SRC_CLEAR_ALL);
  530. ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
  531. if (ret < 0) {
  532. netdev_warn(dev->net, "Error writing INT_STS\n");
  533. return ret;
  534. }
  535. mii_check_media(mii, 1, 1);
  536. mii_ethtool_gset(&dev->mii, &ecmd);
  537. lcladv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
  538. rmtadv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
  539. netif_dbg(dev, link, dev->net, "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
  540. ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
  541. return smsc75xx_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
  542. }
  543. static void smsc75xx_status(struct usbnet *dev, struct urb *urb)
  544. {
  545. u32 intdata;
  546. if (urb->actual_length != 4) {
  547. netdev_warn(dev->net, "unexpected urb length %d\n",
  548. urb->actual_length);
  549. return;
  550. }
  551. memcpy(&intdata, urb->transfer_buffer, 4);
  552. le32_to_cpus(&intdata);
  553. netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
  554. if (intdata & INT_ENP_PHY_INT)
  555. usbnet_defer_kevent(dev, EVENT_LINK_RESET);
  556. else
  557. netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
  558. intdata);
  559. }
  560. static int smsc75xx_ethtool_get_eeprom_len(struct net_device *net)
  561. {
  562. return MAX_EEPROM_SIZE;
  563. }
  564. static int smsc75xx_ethtool_get_eeprom(struct net_device *netdev,
  565. struct ethtool_eeprom *ee, u8 *data)
  566. {
  567. struct usbnet *dev = netdev_priv(netdev);
  568. ee->magic = LAN75XX_EEPROM_MAGIC;
  569. return smsc75xx_read_eeprom(dev, ee->offset, ee->len, data);
  570. }
  571. static int smsc75xx_ethtool_set_eeprom(struct net_device *netdev,
  572. struct ethtool_eeprom *ee, u8 *data)
  573. {
  574. struct usbnet *dev = netdev_priv(netdev);
  575. if (ee->magic != LAN75XX_EEPROM_MAGIC) {
  576. netdev_warn(dev->net, "EEPROM: magic value mismatch: 0x%x\n",
  577. ee->magic);
  578. return -EINVAL;
  579. }
  580. return smsc75xx_write_eeprom(dev, ee->offset, ee->len, data);
  581. }
  582. static void smsc75xx_ethtool_get_wol(struct net_device *net,
  583. struct ethtool_wolinfo *wolinfo)
  584. {
  585. struct usbnet *dev = netdev_priv(net);
  586. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  587. wolinfo->supported = SUPPORTED_WAKE;
  588. wolinfo->wolopts = pdata->wolopts;
  589. }
  590. static int smsc75xx_ethtool_set_wol(struct net_device *net,
  591. struct ethtool_wolinfo *wolinfo)
  592. {
  593. struct usbnet *dev = netdev_priv(net);
  594. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  595. int ret;
  596. pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
  597. ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
  598. if (ret < 0)
  599. netdev_warn(dev->net, "device_set_wakeup_enable error %d\n", ret);
  600. return ret;
  601. }
  602. static const struct ethtool_ops smsc75xx_ethtool_ops = {
  603. .get_link = usbnet_get_link,
  604. .nway_reset = usbnet_nway_reset,
  605. .get_drvinfo = usbnet_get_drvinfo,
  606. .get_msglevel = usbnet_get_msglevel,
  607. .set_msglevel = usbnet_set_msglevel,
  608. .get_settings = usbnet_get_settings,
  609. .set_settings = usbnet_set_settings,
  610. .get_eeprom_len = smsc75xx_ethtool_get_eeprom_len,
  611. .get_eeprom = smsc75xx_ethtool_get_eeprom,
  612. .set_eeprom = smsc75xx_ethtool_set_eeprom,
  613. .get_wol = smsc75xx_ethtool_get_wol,
  614. .set_wol = smsc75xx_ethtool_set_wol,
  615. };
  616. static int smsc75xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  617. {
  618. struct usbnet *dev = netdev_priv(netdev);
  619. if (!netif_running(netdev))
  620. return -EINVAL;
  621. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  622. }
  623. static void smsc75xx_init_mac_address(struct usbnet *dev)
  624. {
  625. /* try reading mac address from EEPROM */
  626. if (smsc75xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
  627. dev->net->dev_addr) == 0) {
  628. if (is_valid_ether_addr(dev->net->dev_addr)) {
  629. /* eeprom values are valid so use them */
  630. netif_dbg(dev, ifup, dev->net,
  631. "MAC address read from EEPROM\n");
  632. return;
  633. }
  634. }
  635. /* no eeprom, or eeprom values are invalid. generate random MAC */
  636. eth_hw_addr_random(dev->net);
  637. netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
  638. }
  639. static int smsc75xx_set_mac_address(struct usbnet *dev)
  640. {
  641. u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
  642. dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
  643. u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
  644. int ret = smsc75xx_write_reg(dev, RX_ADDRH, addr_hi);
  645. if (ret < 0) {
  646. netdev_warn(dev->net, "Failed to write RX_ADDRH: %d\n", ret);
  647. return ret;
  648. }
  649. ret = smsc75xx_write_reg(dev, RX_ADDRL, addr_lo);
  650. if (ret < 0) {
  651. netdev_warn(dev->net, "Failed to write RX_ADDRL: %d\n", ret);
  652. return ret;
  653. }
  654. addr_hi |= ADDR_FILTX_FB_VALID;
  655. ret = smsc75xx_write_reg(dev, ADDR_FILTX, addr_hi);
  656. if (ret < 0) {
  657. netdev_warn(dev->net, "Failed to write ADDR_FILTX: %d\n", ret);
  658. return ret;
  659. }
  660. ret = smsc75xx_write_reg(dev, ADDR_FILTX + 4, addr_lo);
  661. if (ret < 0)
  662. netdev_warn(dev->net, "Failed to write ADDR_FILTX+4: %d\n", ret);
  663. return ret;
  664. }
  665. static int smsc75xx_phy_initialize(struct usbnet *dev)
  666. {
  667. int bmcr, ret, timeout = 0;
  668. /* Initialize MII structure */
  669. dev->mii.dev = dev->net;
  670. dev->mii.mdio_read = smsc75xx_mdio_read;
  671. dev->mii.mdio_write = smsc75xx_mdio_write;
  672. dev->mii.phy_id_mask = 0x1f;
  673. dev->mii.reg_num_mask = 0x1f;
  674. dev->mii.supports_gmii = 1;
  675. dev->mii.phy_id = SMSC75XX_INTERNAL_PHY_ID;
  676. /* reset phy and wait for reset to complete */
  677. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  678. do {
  679. msleep(10);
  680. bmcr = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
  681. if (bmcr < 0) {
  682. netdev_warn(dev->net, "Error reading MII_BMCR\n");
  683. return bmcr;
  684. }
  685. timeout++;
  686. } while ((bmcr & BMCR_RESET) && (timeout < 100));
  687. if (timeout >= 100) {
  688. netdev_warn(dev->net, "timeout on PHY Reset\n");
  689. return -EIO;
  690. }
  691. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  692. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
  693. ADVERTISE_PAUSE_ASYM);
  694. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
  695. ADVERTISE_1000FULL);
  696. /* read and write to clear phy interrupt status */
  697. ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
  698. if (ret < 0) {
  699. netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
  700. return ret;
  701. }
  702. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_SRC, 0xffff);
  703. smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
  704. PHY_INT_MASK_DEFAULT);
  705. mii_nway_restart(&dev->mii);
  706. netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
  707. return 0;
  708. }
  709. static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size)
  710. {
  711. int ret = 0;
  712. u32 buf;
  713. bool rxenabled;
  714. ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
  715. if (ret < 0) {
  716. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  717. return ret;
  718. }
  719. rxenabled = ((buf & MAC_RX_RXEN) != 0);
  720. if (rxenabled) {
  721. buf &= ~MAC_RX_RXEN;
  722. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  723. if (ret < 0) {
  724. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  725. return ret;
  726. }
  727. }
  728. /* add 4 to size for FCS */
  729. buf &= ~MAC_RX_MAX_SIZE;
  730. buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT) & MAC_RX_MAX_SIZE);
  731. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  732. if (ret < 0) {
  733. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  734. return ret;
  735. }
  736. if (rxenabled) {
  737. buf |= MAC_RX_RXEN;
  738. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  739. if (ret < 0) {
  740. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  741. return ret;
  742. }
  743. }
  744. return 0;
  745. }
  746. static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu)
  747. {
  748. struct usbnet *dev = netdev_priv(netdev);
  749. int ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu);
  750. if (ret < 0) {
  751. netdev_warn(dev->net, "Failed to set mac rx frame length\n");
  752. return ret;
  753. }
  754. return usbnet_change_mtu(netdev, new_mtu);
  755. }
  756. /* Enable or disable Rx checksum offload engine */
  757. static int smsc75xx_set_features(struct net_device *netdev,
  758. netdev_features_t features)
  759. {
  760. struct usbnet *dev = netdev_priv(netdev);
  761. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  762. unsigned long flags;
  763. int ret;
  764. spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
  765. if (features & NETIF_F_RXCSUM)
  766. pdata->rfe_ctl |= RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM;
  767. else
  768. pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM);
  769. spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
  770. /* it's racing here! */
  771. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  772. if (ret < 0)
  773. netdev_warn(dev->net, "Error writing RFE_CTL\n");
  774. return ret;
  775. }
  776. static int smsc75xx_wait_ready(struct usbnet *dev, int in_pm)
  777. {
  778. int timeout = 0;
  779. do {
  780. u32 buf;
  781. int ret;
  782. ret = __smsc75xx_read_reg(dev, PMT_CTL, &buf, in_pm);
  783. if (ret < 0) {
  784. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  785. return ret;
  786. }
  787. if (buf & PMT_CTL_DEV_RDY)
  788. return 0;
  789. msleep(10);
  790. timeout++;
  791. } while (timeout < 100);
  792. netdev_warn(dev->net, "timeout waiting for device ready\n");
  793. return -EIO;
  794. }
  795. static int smsc75xx_reset(struct usbnet *dev)
  796. {
  797. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  798. u32 buf;
  799. int ret = 0, timeout;
  800. netif_dbg(dev, ifup, dev->net, "entering smsc75xx_reset\n");
  801. ret = smsc75xx_wait_ready(dev, 0);
  802. if (ret < 0) {
  803. netdev_warn(dev->net, "device not ready in smsc75xx_reset\n");
  804. return ret;
  805. }
  806. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  807. if (ret < 0) {
  808. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  809. return ret;
  810. }
  811. buf |= HW_CFG_LRST;
  812. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  813. if (ret < 0) {
  814. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  815. return ret;
  816. }
  817. timeout = 0;
  818. do {
  819. msleep(10);
  820. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  821. if (ret < 0) {
  822. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  823. return ret;
  824. }
  825. timeout++;
  826. } while ((buf & HW_CFG_LRST) && (timeout < 100));
  827. if (timeout >= 100) {
  828. netdev_warn(dev->net, "timeout on completion of Lite Reset\n");
  829. return -EIO;
  830. }
  831. netif_dbg(dev, ifup, dev->net, "Lite reset complete, resetting PHY\n");
  832. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  833. if (ret < 0) {
  834. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  835. return ret;
  836. }
  837. buf |= PMT_CTL_PHY_RST;
  838. ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
  839. if (ret < 0) {
  840. netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
  841. return ret;
  842. }
  843. timeout = 0;
  844. do {
  845. msleep(10);
  846. ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
  847. if (ret < 0) {
  848. netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
  849. return ret;
  850. }
  851. timeout++;
  852. } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
  853. if (timeout >= 100) {
  854. netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
  855. return -EIO;
  856. }
  857. netif_dbg(dev, ifup, dev->net, "PHY reset complete\n");
  858. ret = smsc75xx_set_mac_address(dev);
  859. if (ret < 0) {
  860. netdev_warn(dev->net, "Failed to set mac address\n");
  861. return ret;
  862. }
  863. netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
  864. dev->net->dev_addr);
  865. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  866. if (ret < 0) {
  867. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  868. return ret;
  869. }
  870. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
  871. buf);
  872. buf |= HW_CFG_BIR;
  873. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  874. if (ret < 0) {
  875. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  876. return ret;
  877. }
  878. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  879. if (ret < 0) {
  880. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  881. return ret;
  882. }
  883. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG after writing HW_CFG_BIR: 0x%08x\n",
  884. buf);
  885. if (!turbo_mode) {
  886. buf = 0;
  887. dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  888. } else if (dev->udev->speed == USB_SPEED_HIGH) {
  889. buf = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  890. dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  891. } else {
  892. buf = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  893. dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  894. }
  895. netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
  896. (ulong)dev->rx_urb_size);
  897. ret = smsc75xx_write_reg(dev, BURST_CAP, buf);
  898. if (ret < 0) {
  899. netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret);
  900. return ret;
  901. }
  902. ret = smsc75xx_read_reg(dev, BURST_CAP, &buf);
  903. if (ret < 0) {
  904. netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret);
  905. return ret;
  906. }
  907. netif_dbg(dev, ifup, dev->net,
  908. "Read Value from BURST_CAP after writing: 0x%08x\n", buf);
  909. ret = smsc75xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
  910. if (ret < 0) {
  911. netdev_warn(dev->net, "Failed to write BULK_IN_DLY: %d\n", ret);
  912. return ret;
  913. }
  914. ret = smsc75xx_read_reg(dev, BULK_IN_DLY, &buf);
  915. if (ret < 0) {
  916. netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret);
  917. return ret;
  918. }
  919. netif_dbg(dev, ifup, dev->net,
  920. "Read Value from BULK_IN_DLY after writing: 0x%08x\n", buf);
  921. if (turbo_mode) {
  922. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  923. if (ret < 0) {
  924. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  925. return ret;
  926. }
  927. netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
  928. buf |= (HW_CFG_MEF | HW_CFG_BCE);
  929. ret = smsc75xx_write_reg(dev, HW_CFG, buf);
  930. if (ret < 0) {
  931. netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
  932. return ret;
  933. }
  934. ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
  935. if (ret < 0) {
  936. netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
  937. return ret;
  938. }
  939. netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
  940. }
  941. /* set FIFO sizes */
  942. buf = (MAX_RX_FIFO_SIZE - 512) / 512;
  943. ret = smsc75xx_write_reg(dev, FCT_RX_FIFO_END, buf);
  944. if (ret < 0) {
  945. netdev_warn(dev->net, "Failed to write FCT_RX_FIFO_END: %d\n", ret);
  946. return ret;
  947. }
  948. netif_dbg(dev, ifup, dev->net, "FCT_RX_FIFO_END set to 0x%08x\n", buf);
  949. buf = (MAX_TX_FIFO_SIZE - 512) / 512;
  950. ret = smsc75xx_write_reg(dev, FCT_TX_FIFO_END, buf);
  951. if (ret < 0) {
  952. netdev_warn(dev->net, "Failed to write FCT_TX_FIFO_END: %d\n", ret);
  953. return ret;
  954. }
  955. netif_dbg(dev, ifup, dev->net, "FCT_TX_FIFO_END set to 0x%08x\n", buf);
  956. ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
  957. if (ret < 0) {
  958. netdev_warn(dev->net, "Failed to write INT_STS: %d\n", ret);
  959. return ret;
  960. }
  961. ret = smsc75xx_read_reg(dev, ID_REV, &buf);
  962. if (ret < 0) {
  963. netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret);
  964. return ret;
  965. }
  966. netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", buf);
  967. ret = smsc75xx_read_reg(dev, E2P_CMD, &buf);
  968. if (ret < 0) {
  969. netdev_warn(dev->net, "Failed to read E2P_CMD: %d\n", ret);
  970. return ret;
  971. }
  972. /* only set default GPIO/LED settings if no EEPROM is detected */
  973. if (!(buf & E2P_CMD_LOADED)) {
  974. ret = smsc75xx_read_reg(dev, LED_GPIO_CFG, &buf);
  975. if (ret < 0) {
  976. netdev_warn(dev->net, "Failed to read LED_GPIO_CFG: %d\n", ret);
  977. return ret;
  978. }
  979. buf &= ~(LED_GPIO_CFG_LED2_FUN_SEL | LED_GPIO_CFG_LED10_FUN_SEL);
  980. buf |= LED_GPIO_CFG_LEDGPIO_EN | LED_GPIO_CFG_LED2_FUN_SEL;
  981. ret = smsc75xx_write_reg(dev, LED_GPIO_CFG, buf);
  982. if (ret < 0) {
  983. netdev_warn(dev->net, "Failed to write LED_GPIO_CFG: %d\n", ret);
  984. return ret;
  985. }
  986. }
  987. ret = smsc75xx_write_reg(dev, FLOW, 0);
  988. if (ret < 0) {
  989. netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret);
  990. return ret;
  991. }
  992. ret = smsc75xx_write_reg(dev, FCT_FLOW, 0);
  993. if (ret < 0) {
  994. netdev_warn(dev->net, "Failed to write FCT_FLOW: %d\n", ret);
  995. return ret;
  996. }
  997. /* Don't need rfe_ctl_lock during initialisation */
  998. ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
  999. if (ret < 0) {
  1000. netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
  1001. return ret;
  1002. }
  1003. pdata->rfe_ctl |= RFE_CTL_AB | RFE_CTL_DPF;
  1004. ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
  1005. if (ret < 0) {
  1006. netdev_warn(dev->net, "Failed to write RFE_CTL: %d\n", ret);
  1007. return ret;
  1008. }
  1009. ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
  1010. if (ret < 0) {
  1011. netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
  1012. return ret;
  1013. }
  1014. netif_dbg(dev, ifup, dev->net, "RFE_CTL set to 0x%08x\n",
  1015. pdata->rfe_ctl);
  1016. /* Enable or disable checksum offload engines */
  1017. smsc75xx_set_features(dev->net, dev->net->features);
  1018. smsc75xx_set_multicast(dev->net);
  1019. ret = smsc75xx_phy_initialize(dev);
  1020. if (ret < 0) {
  1021. netdev_warn(dev->net, "Failed to initialize PHY: %d\n", ret);
  1022. return ret;
  1023. }
  1024. ret = smsc75xx_read_reg(dev, INT_EP_CTL, &buf);
  1025. if (ret < 0) {
  1026. netdev_warn(dev->net, "Failed to read INT_EP_CTL: %d\n", ret);
  1027. return ret;
  1028. }
  1029. /* enable PHY interrupts */
  1030. buf |= INT_ENP_PHY_INT;
  1031. ret = smsc75xx_write_reg(dev, INT_EP_CTL, buf);
  1032. if (ret < 0) {
  1033. netdev_warn(dev->net, "Failed to write INT_EP_CTL: %d\n", ret);
  1034. return ret;
  1035. }
  1036. /* allow mac to detect speed and duplex from phy */
  1037. ret = smsc75xx_read_reg(dev, MAC_CR, &buf);
  1038. if (ret < 0) {
  1039. netdev_warn(dev->net, "Failed to read MAC_CR: %d\n", ret);
  1040. return ret;
  1041. }
  1042. buf |= (MAC_CR_ADD | MAC_CR_ASD);
  1043. ret = smsc75xx_write_reg(dev, MAC_CR, buf);
  1044. if (ret < 0) {
  1045. netdev_warn(dev->net, "Failed to write MAC_CR: %d\n", ret);
  1046. return ret;
  1047. }
  1048. ret = smsc75xx_read_reg(dev, MAC_TX, &buf);
  1049. if (ret < 0) {
  1050. netdev_warn(dev->net, "Failed to read MAC_TX: %d\n", ret);
  1051. return ret;
  1052. }
  1053. buf |= MAC_TX_TXEN;
  1054. ret = smsc75xx_write_reg(dev, MAC_TX, buf);
  1055. if (ret < 0) {
  1056. netdev_warn(dev->net, "Failed to write MAC_TX: %d\n", ret);
  1057. return ret;
  1058. }
  1059. netif_dbg(dev, ifup, dev->net, "MAC_TX set to 0x%08x\n", buf);
  1060. ret = smsc75xx_read_reg(dev, FCT_TX_CTL, &buf);
  1061. if (ret < 0) {
  1062. netdev_warn(dev->net, "Failed to read FCT_TX_CTL: %d\n", ret);
  1063. return ret;
  1064. }
  1065. buf |= FCT_TX_CTL_EN;
  1066. ret = smsc75xx_write_reg(dev, FCT_TX_CTL, buf);
  1067. if (ret < 0) {
  1068. netdev_warn(dev->net, "Failed to write FCT_TX_CTL: %d\n", ret);
  1069. return ret;
  1070. }
  1071. netif_dbg(dev, ifup, dev->net, "FCT_TX_CTL set to 0x%08x\n", buf);
  1072. ret = smsc75xx_set_rx_max_frame_length(dev, 1514);
  1073. if (ret < 0) {
  1074. netdev_warn(dev->net, "Failed to set max rx frame length\n");
  1075. return ret;
  1076. }
  1077. ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
  1078. if (ret < 0) {
  1079. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  1080. return ret;
  1081. }
  1082. buf |= MAC_RX_RXEN;
  1083. ret = smsc75xx_write_reg(dev, MAC_RX, buf);
  1084. if (ret < 0) {
  1085. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  1086. return ret;
  1087. }
  1088. netif_dbg(dev, ifup, dev->net, "MAC_RX set to 0x%08x\n", buf);
  1089. ret = smsc75xx_read_reg(dev, FCT_RX_CTL, &buf);
  1090. if (ret < 0) {
  1091. netdev_warn(dev->net, "Failed to read FCT_RX_CTL: %d\n", ret);
  1092. return ret;
  1093. }
  1094. buf |= FCT_RX_CTL_EN;
  1095. ret = smsc75xx_write_reg(dev, FCT_RX_CTL, buf);
  1096. if (ret < 0) {
  1097. netdev_warn(dev->net, "Failed to write FCT_RX_CTL: %d\n", ret);
  1098. return ret;
  1099. }
  1100. netif_dbg(dev, ifup, dev->net, "FCT_RX_CTL set to 0x%08x\n", buf);
  1101. netif_dbg(dev, ifup, dev->net, "smsc75xx_reset, return 0\n");
  1102. return 0;
  1103. }
  1104. static const struct net_device_ops smsc75xx_netdev_ops = {
  1105. .ndo_open = usbnet_open,
  1106. .ndo_stop = usbnet_stop,
  1107. .ndo_start_xmit = usbnet_start_xmit,
  1108. .ndo_tx_timeout = usbnet_tx_timeout,
  1109. .ndo_change_mtu = smsc75xx_change_mtu,
  1110. .ndo_set_mac_address = eth_mac_addr,
  1111. .ndo_validate_addr = eth_validate_addr,
  1112. .ndo_do_ioctl = smsc75xx_ioctl,
  1113. .ndo_set_rx_mode = smsc75xx_set_multicast,
  1114. .ndo_set_features = smsc75xx_set_features,
  1115. };
  1116. static int smsc75xx_bind(struct usbnet *dev, struct usb_interface *intf)
  1117. {
  1118. struct smsc75xx_priv *pdata = NULL;
  1119. int ret;
  1120. printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
  1121. ret = usbnet_get_endpoints(dev, intf);
  1122. if (ret < 0) {
  1123. netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
  1124. return ret;
  1125. }
  1126. dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc75xx_priv),
  1127. GFP_KERNEL);
  1128. pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1129. if (!pdata)
  1130. return -ENOMEM;
  1131. pdata->dev = dev;
  1132. spin_lock_init(&pdata->rfe_ctl_lock);
  1133. mutex_init(&pdata->dataport_mutex);
  1134. INIT_WORK(&pdata->set_multicast, smsc75xx_deferred_multicast_write);
  1135. if (DEFAULT_TX_CSUM_ENABLE) {
  1136. dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
  1137. if (DEFAULT_TSO_ENABLE)
  1138. dev->net->features |= NETIF_F_SG |
  1139. NETIF_F_TSO | NETIF_F_TSO6;
  1140. }
  1141. if (DEFAULT_RX_CSUM_ENABLE)
  1142. dev->net->features |= NETIF_F_RXCSUM;
  1143. dev->net->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1144. NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_RXCSUM;
  1145. ret = smsc75xx_wait_ready(dev, 0);
  1146. if (ret < 0) {
  1147. netdev_warn(dev->net, "device not ready in smsc75xx_bind\n");
  1148. return ret;
  1149. }
  1150. smsc75xx_init_mac_address(dev);
  1151. /* Init all registers */
  1152. ret = smsc75xx_reset(dev);
  1153. if (ret < 0) {
  1154. netdev_warn(dev->net, "smsc75xx_reset error %d\n", ret);
  1155. return ret;
  1156. }
  1157. dev->net->netdev_ops = &smsc75xx_netdev_ops;
  1158. dev->net->ethtool_ops = &smsc75xx_ethtool_ops;
  1159. dev->net->flags |= IFF_MULTICAST;
  1160. dev->net->hard_header_len += SMSC75XX_TX_OVERHEAD;
  1161. dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
  1162. return 0;
  1163. }
  1164. static void smsc75xx_unbind(struct usbnet *dev, struct usb_interface *intf)
  1165. {
  1166. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1167. if (pdata) {
  1168. netif_dbg(dev, ifdown, dev->net, "free pdata\n");
  1169. kfree(pdata);
  1170. pdata = NULL;
  1171. dev->data[0] = 0;
  1172. }
  1173. }
  1174. static u16 smsc_crc(const u8 *buffer, size_t len)
  1175. {
  1176. return bitrev16(crc16(0xFFFF, buffer, len));
  1177. }
  1178. static int smsc75xx_write_wuff(struct usbnet *dev, int filter, u32 wuf_cfg,
  1179. u32 wuf_mask1)
  1180. {
  1181. int cfg_base = WUF_CFGX + filter * 4;
  1182. int mask_base = WUF_MASKX + filter * 16;
  1183. int ret;
  1184. ret = smsc75xx_write_reg(dev, cfg_base, wuf_cfg);
  1185. if (ret < 0) {
  1186. netdev_warn(dev->net, "Error writing WUF_CFGX\n");
  1187. return ret;
  1188. }
  1189. ret = smsc75xx_write_reg(dev, mask_base, wuf_mask1);
  1190. if (ret < 0) {
  1191. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1192. return ret;
  1193. }
  1194. ret = smsc75xx_write_reg(dev, mask_base + 4, 0);
  1195. if (ret < 0) {
  1196. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1197. return ret;
  1198. }
  1199. ret = smsc75xx_write_reg(dev, mask_base + 8, 0);
  1200. if (ret < 0) {
  1201. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1202. return ret;
  1203. }
  1204. ret = smsc75xx_write_reg(dev, mask_base + 12, 0);
  1205. if (ret < 0) {
  1206. netdev_warn(dev->net, "Error writing WUF_MASKX\n");
  1207. return ret;
  1208. }
  1209. return 0;
  1210. }
  1211. static int smsc75xx_enter_suspend0(struct usbnet *dev)
  1212. {
  1213. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1214. u32 val;
  1215. int ret;
  1216. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1217. if (ret < 0) {
  1218. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1219. return ret;
  1220. }
  1221. val &= (~(PMT_CTL_SUS_MODE | PMT_CTL_PHY_RST));
  1222. val |= PMT_CTL_SUS_MODE_0 | PMT_CTL_WOL_EN | PMT_CTL_WUPS;
  1223. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1224. if (ret < 0) {
  1225. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1226. return ret;
  1227. }
  1228. pdata->suspend_flags |= SUSPEND_SUSPEND0;
  1229. return 0;
  1230. }
  1231. static int smsc75xx_enter_suspend1(struct usbnet *dev)
  1232. {
  1233. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1234. u32 val;
  1235. int ret;
  1236. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1237. if (ret < 0) {
  1238. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1239. return ret;
  1240. }
  1241. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1242. val |= PMT_CTL_SUS_MODE_1;
  1243. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1244. if (ret < 0) {
  1245. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1246. return ret;
  1247. }
  1248. /* clear wol status, enable energy detection */
  1249. val &= ~PMT_CTL_WUPS;
  1250. val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
  1251. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1252. if (ret < 0) {
  1253. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1254. return ret;
  1255. }
  1256. pdata->suspend_flags |= SUSPEND_SUSPEND1;
  1257. return 0;
  1258. }
  1259. static int smsc75xx_enter_suspend2(struct usbnet *dev)
  1260. {
  1261. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1262. u32 val;
  1263. int ret;
  1264. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1265. if (ret < 0) {
  1266. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1267. return ret;
  1268. }
  1269. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1270. val |= PMT_CTL_SUS_MODE_2;
  1271. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1272. if (ret < 0) {
  1273. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1274. return ret;
  1275. }
  1276. pdata->suspend_flags |= SUSPEND_SUSPEND2;
  1277. return 0;
  1278. }
  1279. static int smsc75xx_enter_suspend3(struct usbnet *dev)
  1280. {
  1281. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1282. u32 val;
  1283. int ret;
  1284. ret = smsc75xx_read_reg_nopm(dev, FCT_RX_CTL, &val);
  1285. if (ret < 0) {
  1286. netdev_warn(dev->net, "Error reading FCT_RX_CTL\n");
  1287. return ret;
  1288. }
  1289. if (val & FCT_RX_CTL_RXUSED) {
  1290. netdev_dbg(dev->net, "rx fifo not empty in autosuspend\n");
  1291. return -EBUSY;
  1292. }
  1293. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1294. if (ret < 0) {
  1295. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1296. return ret;
  1297. }
  1298. val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
  1299. val |= PMT_CTL_SUS_MODE_3 | PMT_CTL_RES_CLR_WKP_EN;
  1300. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1301. if (ret < 0) {
  1302. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1303. return ret;
  1304. }
  1305. /* clear wol status */
  1306. val &= ~PMT_CTL_WUPS;
  1307. val |= PMT_CTL_WUPS_WOL;
  1308. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1309. if (ret < 0) {
  1310. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1311. return ret;
  1312. }
  1313. pdata->suspend_flags |= SUSPEND_SUSPEND3;
  1314. return 0;
  1315. }
  1316. static int smsc75xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask)
  1317. {
  1318. struct mii_if_info *mii = &dev->mii;
  1319. int ret;
  1320. netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n");
  1321. /* read to clear */
  1322. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
  1323. if (ret < 0) {
  1324. netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
  1325. return ret;
  1326. }
  1327. /* enable interrupt source */
  1328. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
  1329. if (ret < 0) {
  1330. netdev_warn(dev->net, "Error reading PHY_INT_MASK\n");
  1331. return ret;
  1332. }
  1333. ret |= mask;
  1334. smsc75xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
  1335. return 0;
  1336. }
  1337. static int smsc75xx_link_ok_nopm(struct usbnet *dev)
  1338. {
  1339. struct mii_if_info *mii = &dev->mii;
  1340. int ret;
  1341. /* first, a dummy read, needed to latch some MII phys */
  1342. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  1343. if (ret < 0) {
  1344. netdev_warn(dev->net, "Error reading MII_BMSR\n");
  1345. return ret;
  1346. }
  1347. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  1348. if (ret < 0) {
  1349. netdev_warn(dev->net, "Error reading MII_BMSR\n");
  1350. return ret;
  1351. }
  1352. return !!(ret & BMSR_LSTATUS);
  1353. }
  1354. static int smsc75xx_autosuspend(struct usbnet *dev, u32 link_up)
  1355. {
  1356. int ret;
  1357. if (!netif_running(dev->net)) {
  1358. /* interface is ifconfig down so fully power down hw */
  1359. netdev_dbg(dev->net, "autosuspend entering SUSPEND2\n");
  1360. return smsc75xx_enter_suspend2(dev);
  1361. }
  1362. if (!link_up) {
  1363. /* link is down so enter EDPD mode */
  1364. netdev_dbg(dev->net, "autosuspend entering SUSPEND1\n");
  1365. /* enable PHY wakeup events for if cable is attached */
  1366. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1367. PHY_INT_MASK_ANEG_COMP);
  1368. if (ret < 0) {
  1369. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1370. return ret;
  1371. }
  1372. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1373. return smsc75xx_enter_suspend1(dev);
  1374. }
  1375. /* enable PHY wakeup events so we remote wakeup if cable is pulled */
  1376. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1377. PHY_INT_MASK_LINK_DOWN);
  1378. if (ret < 0) {
  1379. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1380. return ret;
  1381. }
  1382. netdev_dbg(dev->net, "autosuspend entering SUSPEND3\n");
  1383. return smsc75xx_enter_suspend3(dev);
  1384. }
  1385. static int smsc75xx_suspend(struct usb_interface *intf, pm_message_t message)
  1386. {
  1387. struct usbnet *dev = usb_get_intfdata(intf);
  1388. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1389. u32 val, link_up;
  1390. int ret;
  1391. ret = usbnet_suspend(intf, message);
  1392. if (ret < 0) {
  1393. netdev_warn(dev->net, "usbnet_suspend error\n");
  1394. return ret;
  1395. }
  1396. if (pdata->suspend_flags) {
  1397. netdev_warn(dev->net, "error during last resume\n");
  1398. pdata->suspend_flags = 0;
  1399. }
  1400. /* determine if link is up using only _nopm functions */
  1401. link_up = smsc75xx_link_ok_nopm(dev);
  1402. if (message.event == PM_EVENT_AUTO_SUSPEND) {
  1403. ret = smsc75xx_autosuspend(dev, link_up);
  1404. goto done;
  1405. }
  1406. /* if we get this far we're not autosuspending */
  1407. /* if no wol options set, or if link is down and we're not waking on
  1408. * PHY activity, enter lowest power SUSPEND2 mode
  1409. */
  1410. if (!(pdata->wolopts & SUPPORTED_WAKE) ||
  1411. !(link_up || (pdata->wolopts & WAKE_PHY))) {
  1412. netdev_info(dev->net, "entering SUSPEND2 mode\n");
  1413. /* disable energy detect (link up) & wake up events */
  1414. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1415. if (ret < 0) {
  1416. netdev_warn(dev->net, "Error reading WUCSR\n");
  1417. goto done;
  1418. }
  1419. val &= ~(WUCSR_MPEN | WUCSR_WUEN);
  1420. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1421. if (ret < 0) {
  1422. netdev_warn(dev->net, "Error writing WUCSR\n");
  1423. goto done;
  1424. }
  1425. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1426. if (ret < 0) {
  1427. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1428. goto done;
  1429. }
  1430. val &= ~(PMT_CTL_ED_EN | PMT_CTL_WOL_EN);
  1431. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1432. if (ret < 0) {
  1433. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1434. goto done;
  1435. }
  1436. ret = smsc75xx_enter_suspend2(dev);
  1437. goto done;
  1438. }
  1439. if (pdata->wolopts & WAKE_PHY) {
  1440. ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
  1441. (PHY_INT_MASK_ANEG_COMP | PHY_INT_MASK_LINK_DOWN));
  1442. if (ret < 0) {
  1443. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1444. goto done;
  1445. }
  1446. /* if link is down then configure EDPD and enter SUSPEND1,
  1447. * otherwise enter SUSPEND0 below
  1448. */
  1449. if (!link_up) {
  1450. struct mii_if_info *mii = &dev->mii;
  1451. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1452. /* enable energy detect power-down mode */
  1453. ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id,
  1454. PHY_MODE_CTRL_STS);
  1455. if (ret < 0) {
  1456. netdev_warn(dev->net, "Error reading PHY_MODE_CTRL_STS\n");
  1457. goto done;
  1458. }
  1459. ret |= MODE_CTRL_STS_EDPWRDOWN;
  1460. smsc75xx_mdio_write_nopm(dev->net, mii->phy_id,
  1461. PHY_MODE_CTRL_STS, ret);
  1462. /* enter SUSPEND1 mode */
  1463. ret = smsc75xx_enter_suspend1(dev);
  1464. goto done;
  1465. }
  1466. }
  1467. if (pdata->wolopts & (WAKE_MCAST | WAKE_ARP)) {
  1468. int i, filter = 0;
  1469. /* disable all filters */
  1470. for (i = 0; i < WUF_NUM; i++) {
  1471. ret = smsc75xx_write_reg_nopm(dev, WUF_CFGX + i * 4, 0);
  1472. if (ret < 0) {
  1473. netdev_warn(dev->net, "Error writing WUF_CFGX\n");
  1474. goto done;
  1475. }
  1476. }
  1477. if (pdata->wolopts & WAKE_MCAST) {
  1478. const u8 mcast[] = {0x01, 0x00, 0x5E};
  1479. netdev_info(dev->net, "enabling multicast detection\n");
  1480. val = WUF_CFGX_EN | WUF_CFGX_ATYPE_MULTICAST
  1481. | smsc_crc(mcast, 3);
  1482. ret = smsc75xx_write_wuff(dev, filter++, val, 0x0007);
  1483. if (ret < 0) {
  1484. netdev_warn(dev->net, "Error writing wakeup filter\n");
  1485. goto done;
  1486. }
  1487. }
  1488. if (pdata->wolopts & WAKE_ARP) {
  1489. const u8 arp[] = {0x08, 0x06};
  1490. netdev_info(dev->net, "enabling ARP detection\n");
  1491. val = WUF_CFGX_EN | WUF_CFGX_ATYPE_ALL | (0x0C << 16)
  1492. | smsc_crc(arp, 2);
  1493. ret = smsc75xx_write_wuff(dev, filter++, val, 0x0003);
  1494. if (ret < 0) {
  1495. netdev_warn(dev->net, "Error writing wakeup filter\n");
  1496. goto done;
  1497. }
  1498. }
  1499. /* clear any pending pattern match packet status */
  1500. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1501. if (ret < 0) {
  1502. netdev_warn(dev->net, "Error reading WUCSR\n");
  1503. goto done;
  1504. }
  1505. val |= WUCSR_WUFR;
  1506. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1507. if (ret < 0) {
  1508. netdev_warn(dev->net, "Error writing WUCSR\n");
  1509. goto done;
  1510. }
  1511. netdev_info(dev->net, "enabling packet match detection\n");
  1512. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1513. if (ret < 0) {
  1514. netdev_warn(dev->net, "Error reading WUCSR\n");
  1515. goto done;
  1516. }
  1517. val |= WUCSR_WUEN;
  1518. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1519. if (ret < 0) {
  1520. netdev_warn(dev->net, "Error writing WUCSR\n");
  1521. goto done;
  1522. }
  1523. } else {
  1524. netdev_info(dev->net, "disabling packet match detection\n");
  1525. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1526. if (ret < 0) {
  1527. netdev_warn(dev->net, "Error reading WUCSR\n");
  1528. goto done;
  1529. }
  1530. val &= ~WUCSR_WUEN;
  1531. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1532. if (ret < 0) {
  1533. netdev_warn(dev->net, "Error writing WUCSR\n");
  1534. goto done;
  1535. }
  1536. }
  1537. /* disable magic, bcast & unicast wakeup sources */
  1538. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1539. if (ret < 0) {
  1540. netdev_warn(dev->net, "Error reading WUCSR\n");
  1541. goto done;
  1542. }
  1543. val &= ~(WUCSR_MPEN | WUCSR_BCST_EN | WUCSR_PFDA_EN);
  1544. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1545. if (ret < 0) {
  1546. netdev_warn(dev->net, "Error writing WUCSR\n");
  1547. goto done;
  1548. }
  1549. if (pdata->wolopts & WAKE_PHY) {
  1550. netdev_info(dev->net, "enabling PHY wakeup\n");
  1551. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1552. if (ret < 0) {
  1553. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1554. goto done;
  1555. }
  1556. /* clear wol status, enable energy detection */
  1557. val &= ~PMT_CTL_WUPS;
  1558. val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
  1559. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1560. if (ret < 0) {
  1561. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1562. goto done;
  1563. }
  1564. }
  1565. if (pdata->wolopts & WAKE_MAGIC) {
  1566. netdev_info(dev->net, "enabling magic packet wakeup\n");
  1567. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1568. if (ret < 0) {
  1569. netdev_warn(dev->net, "Error reading WUCSR\n");
  1570. goto done;
  1571. }
  1572. /* clear any pending magic packet status */
  1573. val |= WUCSR_MPR | WUCSR_MPEN;
  1574. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1575. if (ret < 0) {
  1576. netdev_warn(dev->net, "Error writing WUCSR\n");
  1577. goto done;
  1578. }
  1579. }
  1580. if (pdata->wolopts & WAKE_BCAST) {
  1581. netdev_info(dev->net, "enabling broadcast detection\n");
  1582. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1583. if (ret < 0) {
  1584. netdev_warn(dev->net, "Error reading WUCSR\n");
  1585. goto done;
  1586. }
  1587. val |= WUCSR_BCAST_FR | WUCSR_BCST_EN;
  1588. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1589. if (ret < 0) {
  1590. netdev_warn(dev->net, "Error writing WUCSR\n");
  1591. goto done;
  1592. }
  1593. }
  1594. if (pdata->wolopts & WAKE_UCAST) {
  1595. netdev_info(dev->net, "enabling unicast detection\n");
  1596. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1597. if (ret < 0) {
  1598. netdev_warn(dev->net, "Error reading WUCSR\n");
  1599. goto done;
  1600. }
  1601. val |= WUCSR_WUFR | WUCSR_PFDA_EN;
  1602. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1603. if (ret < 0) {
  1604. netdev_warn(dev->net, "Error writing WUCSR\n");
  1605. goto done;
  1606. }
  1607. }
  1608. /* enable receiver to enable frame reception */
  1609. ret = smsc75xx_read_reg_nopm(dev, MAC_RX, &val);
  1610. if (ret < 0) {
  1611. netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
  1612. goto done;
  1613. }
  1614. val |= MAC_RX_RXEN;
  1615. ret = smsc75xx_write_reg_nopm(dev, MAC_RX, val);
  1616. if (ret < 0) {
  1617. netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
  1618. goto done;
  1619. }
  1620. /* some wol options are enabled, so enter SUSPEND0 */
  1621. netdev_info(dev->net, "entering SUSPEND0 mode\n");
  1622. ret = smsc75xx_enter_suspend0(dev);
  1623. done:
  1624. /*
  1625. * TODO: resume() might need to handle the suspend failure
  1626. * in system sleep
  1627. */
  1628. if (ret && PMSG_IS_AUTO(message))
  1629. usbnet_resume(intf);
  1630. return ret;
  1631. }
  1632. static int smsc75xx_resume(struct usb_interface *intf)
  1633. {
  1634. struct usbnet *dev = usb_get_intfdata(intf);
  1635. struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
  1636. u8 suspend_flags = pdata->suspend_flags;
  1637. int ret;
  1638. u32 val;
  1639. netdev_dbg(dev->net, "resume suspend_flags=0x%02x\n", suspend_flags);
  1640. /* do this first to ensure it's cleared even in error case */
  1641. pdata->suspend_flags = 0;
  1642. if (suspend_flags & SUSPEND_ALLMODES) {
  1643. /* Disable wakeup sources */
  1644. ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
  1645. if (ret < 0) {
  1646. netdev_warn(dev->net, "Error reading WUCSR\n");
  1647. return ret;
  1648. }
  1649. val &= ~(WUCSR_WUEN | WUCSR_MPEN | WUCSR_PFDA_EN
  1650. | WUCSR_BCST_EN);
  1651. ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
  1652. if (ret < 0) {
  1653. netdev_warn(dev->net, "Error writing WUCSR\n");
  1654. return ret;
  1655. }
  1656. /* clear wake-up status */
  1657. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1658. if (ret < 0) {
  1659. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1660. return ret;
  1661. }
  1662. val &= ~PMT_CTL_WOL_EN;
  1663. val |= PMT_CTL_WUPS;
  1664. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1665. if (ret < 0) {
  1666. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1667. return ret;
  1668. }
  1669. }
  1670. if (suspend_flags & SUSPEND_SUSPEND2) {
  1671. netdev_info(dev->net, "resuming from SUSPEND2\n");
  1672. ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
  1673. if (ret < 0) {
  1674. netdev_warn(dev->net, "Error reading PMT_CTL\n");
  1675. return ret;
  1676. }
  1677. val |= PMT_CTL_PHY_PWRUP;
  1678. ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
  1679. if (ret < 0) {
  1680. netdev_warn(dev->net, "Error writing PMT_CTL\n");
  1681. return ret;
  1682. }
  1683. }
  1684. ret = smsc75xx_wait_ready(dev, 1);
  1685. if (ret < 0) {
  1686. netdev_warn(dev->net, "device not ready in smsc75xx_resume\n");
  1687. return ret;
  1688. }
  1689. return usbnet_resume(intf);
  1690. }
  1691. static void smsc75xx_rx_csum_offload(struct usbnet *dev, struct sk_buff *skb,
  1692. u32 rx_cmd_a, u32 rx_cmd_b)
  1693. {
  1694. if (!(dev->net->features & NETIF_F_RXCSUM) ||
  1695. unlikely(rx_cmd_a & RX_CMD_A_LCSM)) {
  1696. skb->ip_summed = CHECKSUM_NONE;
  1697. } else {
  1698. skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT));
  1699. skb->ip_summed = CHECKSUM_COMPLETE;
  1700. }
  1701. }
  1702. static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  1703. {
  1704. while (skb->len > 0) {
  1705. u32 rx_cmd_a, rx_cmd_b, align_count, size;
  1706. struct sk_buff *ax_skb;
  1707. unsigned char *packet;
  1708. memcpy(&rx_cmd_a, skb->data, sizeof(rx_cmd_a));
  1709. le32_to_cpus(&rx_cmd_a);
  1710. skb_pull(skb, 4);
  1711. memcpy(&rx_cmd_b, skb->data, sizeof(rx_cmd_b));
  1712. le32_to_cpus(&rx_cmd_b);
  1713. skb_pull(skb, 4 + RXW_PADDING);
  1714. packet = skb->data;
  1715. /* get the packet length */
  1716. size = (rx_cmd_a & RX_CMD_A_LEN) - RXW_PADDING;
  1717. align_count = (4 - ((size + RXW_PADDING) % 4)) % 4;
  1718. if (unlikely(rx_cmd_a & RX_CMD_A_RED)) {
  1719. netif_dbg(dev, rx_err, dev->net,
  1720. "Error rx_cmd_a=0x%08x\n", rx_cmd_a);
  1721. dev->net->stats.rx_errors++;
  1722. dev->net->stats.rx_dropped++;
  1723. if (rx_cmd_a & RX_CMD_A_FCS)
  1724. dev->net->stats.rx_crc_errors++;
  1725. else if (rx_cmd_a & (RX_CMD_A_LONG | RX_CMD_A_RUNT))
  1726. dev->net->stats.rx_frame_errors++;
  1727. } else {
  1728. /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */
  1729. if (unlikely(size > (ETH_FRAME_LEN + 12))) {
  1730. netif_dbg(dev, rx_err, dev->net,
  1731. "size err rx_cmd_a=0x%08x\n",
  1732. rx_cmd_a);
  1733. return 0;
  1734. }
  1735. /* last frame in this batch */
  1736. if (skb->len == size) {
  1737. smsc75xx_rx_csum_offload(dev, skb, rx_cmd_a,
  1738. rx_cmd_b);
  1739. skb_trim(skb, skb->len - 4); /* remove fcs */
  1740. skb->truesize = size + sizeof(struct sk_buff);
  1741. return 1;
  1742. }
  1743. ax_skb = skb_clone(skb, GFP_ATOMIC);
  1744. if (unlikely(!ax_skb)) {
  1745. netdev_warn(dev->net, "Error allocating skb\n");
  1746. return 0;
  1747. }
  1748. ax_skb->len = size;
  1749. ax_skb->data = packet;
  1750. skb_set_tail_pointer(ax_skb, size);
  1751. smsc75xx_rx_csum_offload(dev, ax_skb, rx_cmd_a,
  1752. rx_cmd_b);
  1753. skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
  1754. ax_skb->truesize = size + sizeof(struct sk_buff);
  1755. usbnet_skb_return(dev, ax_skb);
  1756. }
  1757. skb_pull(skb, size);
  1758. /* padding bytes before the next frame starts */
  1759. if (skb->len)
  1760. skb_pull(skb, align_count);
  1761. }
  1762. if (unlikely(skb->len < 0)) {
  1763. netdev_warn(dev->net, "invalid rx length<0 %d\n", skb->len);
  1764. return 0;
  1765. }
  1766. return 1;
  1767. }
  1768. static struct sk_buff *smsc75xx_tx_fixup(struct usbnet *dev,
  1769. struct sk_buff *skb, gfp_t flags)
  1770. {
  1771. u32 tx_cmd_a, tx_cmd_b;
  1772. skb_linearize(skb);
  1773. if (skb_headroom(skb) < SMSC75XX_TX_OVERHEAD) {
  1774. struct sk_buff *skb2 =
  1775. skb_copy_expand(skb, SMSC75XX_TX_OVERHEAD, 0, flags);
  1776. dev_kfree_skb_any(skb);
  1777. skb = skb2;
  1778. if (!skb)
  1779. return NULL;
  1780. }
  1781. tx_cmd_a = (u32)(skb->len & TX_CMD_A_LEN) | TX_CMD_A_FCS;
  1782. if (skb->ip_summed == CHECKSUM_PARTIAL)
  1783. tx_cmd_a |= TX_CMD_A_IPE | TX_CMD_A_TPE;
  1784. if (skb_is_gso(skb)) {
  1785. u16 mss = max(skb_shinfo(skb)->gso_size, TX_MSS_MIN);
  1786. tx_cmd_b = (mss << TX_CMD_B_MSS_SHIFT) & TX_CMD_B_MSS;
  1787. tx_cmd_a |= TX_CMD_A_LSO;
  1788. } else {
  1789. tx_cmd_b = 0;
  1790. }
  1791. skb_push(skb, 4);
  1792. cpu_to_le32s(&tx_cmd_b);
  1793. memcpy(skb->data, &tx_cmd_b, 4);
  1794. skb_push(skb, 4);
  1795. cpu_to_le32s(&tx_cmd_a);
  1796. memcpy(skb->data, &tx_cmd_a, 4);
  1797. return skb;
  1798. }
  1799. static int smsc75xx_manage_power(struct usbnet *dev, int on)
  1800. {
  1801. dev->intf->needs_remote_wakeup = on;
  1802. return 0;
  1803. }
  1804. static const struct driver_info smsc75xx_info = {
  1805. .description = "smsc75xx USB 2.0 Gigabit Ethernet",
  1806. .bind = smsc75xx_bind,
  1807. .unbind = smsc75xx_unbind,
  1808. .link_reset = smsc75xx_link_reset,
  1809. .reset = smsc75xx_reset,
  1810. .rx_fixup = smsc75xx_rx_fixup,
  1811. .tx_fixup = smsc75xx_tx_fixup,
  1812. .status = smsc75xx_status,
  1813. .manage_power = smsc75xx_manage_power,
  1814. .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
  1815. };
  1816. static const struct usb_device_id products[] = {
  1817. {
  1818. /* SMSC7500 USB Gigabit Ethernet Device */
  1819. USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7500),
  1820. .driver_info = (unsigned long) &smsc75xx_info,
  1821. },
  1822. {
  1823. /* SMSC7500 USB Gigabit Ethernet Device */
  1824. USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7505),
  1825. .driver_info = (unsigned long) &smsc75xx_info,
  1826. },
  1827. { }, /* END */
  1828. };
  1829. MODULE_DEVICE_TABLE(usb, products);
  1830. static struct usb_driver smsc75xx_driver = {
  1831. .name = SMSC_CHIPNAME,
  1832. .id_table = products,
  1833. .probe = usbnet_probe,
  1834. .suspend = smsc75xx_suspend,
  1835. .resume = smsc75xx_resume,
  1836. .reset_resume = smsc75xx_resume,
  1837. .disconnect = usbnet_disconnect,
  1838. .disable_hub_initiated_lpm = 1,
  1839. .supports_autosuspend = 1,
  1840. };
  1841. module_usb_driver(smsc75xx_driver);
  1842. MODULE_AUTHOR("Nancy Lin");
  1843. MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
  1844. MODULE_DESCRIPTION("SMSC75XX USB 2.0 Gigabit Ethernet Devices");
  1845. MODULE_LICENSE("GPL");