phy-rcar-gen2-usb.c 6.2 KB

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  1. /*
  2. * Renesas R-Car Gen2 USB phy driver
  3. *
  4. * Copyright (C) 2013 Renesas Solutions Corp.
  5. * Copyright (C) 2013 Cogent Embedded, Inc.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/delay.h>
  13. #include <linux/io.h>
  14. #include <linux/module.h>
  15. #include <linux/platform_data/usb-rcar-gen2-phy.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/spinlock.h>
  18. #include <linux/usb/otg.h>
  19. struct rcar_gen2_usb_phy_priv {
  20. struct usb_phy phy;
  21. void __iomem *base;
  22. struct clk *clk;
  23. spinlock_t lock;
  24. int usecount;
  25. u32 ugctrl2;
  26. };
  27. #define usb_phy_to_priv(p) container_of(p, struct rcar_gen2_usb_phy_priv, phy)
  28. /* Low Power Status register */
  29. #define USBHS_LPSTS_REG 0x02
  30. #define USBHS_LPSTS_SUSPM (1 << 14)
  31. /* USB General control register */
  32. #define USBHS_UGCTRL_REG 0x80
  33. #define USBHS_UGCTRL_CONNECT (1 << 2)
  34. #define USBHS_UGCTRL_PLLRESET (1 << 0)
  35. /* USB General control register 2 */
  36. #define USBHS_UGCTRL2_REG 0x84
  37. #define USBHS_UGCTRL2_USB0_PCI (1 << 4)
  38. #define USBHS_UGCTRL2_USB0_HS (3 << 4)
  39. #define USBHS_UGCTRL2_USB2_PCI (0 << 31)
  40. #define USBHS_UGCTRL2_USB2_SS (1 << 31)
  41. /* USB General status register */
  42. #define USBHS_UGSTS_REG 0x88
  43. #define USBHS_UGSTS_LOCK (3 << 8)
  44. /* Enable USBHS internal phy */
  45. static int __rcar_gen2_usbhs_phy_enable(void __iomem *base)
  46. {
  47. u32 val;
  48. int i;
  49. /* USBHS PHY power on */
  50. val = ioread32(base + USBHS_UGCTRL_REG);
  51. val &= ~USBHS_UGCTRL_PLLRESET;
  52. iowrite32(val, base + USBHS_UGCTRL_REG);
  53. val = ioread16(base + USBHS_LPSTS_REG);
  54. val |= USBHS_LPSTS_SUSPM;
  55. iowrite16(val, base + USBHS_LPSTS_REG);
  56. for (i = 0; i < 20; i++) {
  57. val = ioread32(base + USBHS_UGSTS_REG);
  58. if ((val & USBHS_UGSTS_LOCK) == USBHS_UGSTS_LOCK) {
  59. val = ioread32(base + USBHS_UGCTRL_REG);
  60. val |= USBHS_UGCTRL_CONNECT;
  61. iowrite32(val, base + USBHS_UGCTRL_REG);
  62. return 0;
  63. }
  64. udelay(1);
  65. }
  66. /* Timed out waiting for the PLL lock */
  67. return -ETIMEDOUT;
  68. }
  69. /* Disable USBHS internal phy */
  70. static int __rcar_gen2_usbhs_phy_disable(void __iomem *base)
  71. {
  72. u32 val;
  73. /* USBHS PHY power off */
  74. val = ioread32(base + USBHS_UGCTRL_REG);
  75. val &= ~USBHS_UGCTRL_CONNECT;
  76. iowrite32(val, base + USBHS_UGCTRL_REG);
  77. val = ioread16(base + USBHS_LPSTS_REG);
  78. val &= ~USBHS_LPSTS_SUSPM;
  79. iowrite16(val, base + USBHS_LPSTS_REG);
  80. val = ioread32(base + USBHS_UGCTRL_REG);
  81. val |= USBHS_UGCTRL_PLLRESET;
  82. iowrite32(val, base + USBHS_UGCTRL_REG);
  83. return 0;
  84. }
  85. /* Setup USB channels */
  86. static void __rcar_gen2_usb_phy_init(struct rcar_gen2_usb_phy_priv *priv)
  87. {
  88. u32 val;
  89. clk_prepare_enable(priv->clk);
  90. /* Set USB channels in the USBHS UGCTRL2 register */
  91. val = ioread32(priv->base);
  92. val &= ~(USBHS_UGCTRL2_USB0_HS | USBHS_UGCTRL2_USB2_SS);
  93. val |= priv->ugctrl2;
  94. iowrite32(val, priv->base);
  95. }
  96. /* Shutdown USB channels */
  97. static void __rcar_gen2_usb_phy_shutdown(struct rcar_gen2_usb_phy_priv *priv)
  98. {
  99. __rcar_gen2_usbhs_phy_disable(priv->base);
  100. clk_disable_unprepare(priv->clk);
  101. }
  102. static int rcar_gen2_usb_phy_set_suspend(struct usb_phy *phy, int suspend)
  103. {
  104. struct rcar_gen2_usb_phy_priv *priv = usb_phy_to_priv(phy);
  105. unsigned long flags;
  106. int retval;
  107. spin_lock_irqsave(&priv->lock, flags);
  108. retval = suspend ? __rcar_gen2_usbhs_phy_disable(priv->base) :
  109. __rcar_gen2_usbhs_phy_enable(priv->base);
  110. spin_unlock_irqrestore(&priv->lock, flags);
  111. return retval;
  112. }
  113. static int rcar_gen2_usb_phy_init(struct usb_phy *phy)
  114. {
  115. struct rcar_gen2_usb_phy_priv *priv = usb_phy_to_priv(phy);
  116. unsigned long flags;
  117. spin_lock_irqsave(&priv->lock, flags);
  118. /*
  119. * Enable the clock and setup USB channels
  120. * if it's the first user
  121. */
  122. if (!priv->usecount++)
  123. __rcar_gen2_usb_phy_init(priv);
  124. spin_unlock_irqrestore(&priv->lock, flags);
  125. return 0;
  126. }
  127. static void rcar_gen2_usb_phy_shutdown(struct usb_phy *phy)
  128. {
  129. struct rcar_gen2_usb_phy_priv *priv = usb_phy_to_priv(phy);
  130. unsigned long flags;
  131. spin_lock_irqsave(&priv->lock, flags);
  132. if (!priv->usecount) {
  133. dev_warn(phy->dev, "Trying to disable phy with 0 usecount\n");
  134. goto out;
  135. }
  136. /* Disable everything if it's the last user */
  137. if (!--priv->usecount)
  138. __rcar_gen2_usb_phy_shutdown(priv);
  139. out:
  140. spin_unlock_irqrestore(&priv->lock, flags);
  141. }
  142. static int rcar_gen2_usb_phy_probe(struct platform_device *pdev)
  143. {
  144. struct device *dev = &pdev->dev;
  145. struct rcar_gen2_phy_platform_data *pdata;
  146. struct rcar_gen2_usb_phy_priv *priv;
  147. struct resource *res;
  148. void __iomem *base;
  149. struct clk *clk;
  150. int retval;
  151. pdata = dev_get_platdata(&pdev->dev);
  152. if (!pdata) {
  153. dev_err(dev, "No platform data\n");
  154. return -EINVAL;
  155. }
  156. clk = devm_clk_get(&pdev->dev, "usbhs");
  157. if (IS_ERR(clk)) {
  158. dev_err(&pdev->dev, "Can't get the clock\n");
  159. return PTR_ERR(clk);
  160. }
  161. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  162. base = devm_ioremap_resource(dev, res);
  163. if (IS_ERR(base))
  164. return PTR_ERR(base);
  165. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  166. if (!priv) {
  167. dev_err(dev, "Memory allocation failed\n");
  168. return -ENOMEM;
  169. }
  170. spin_lock_init(&priv->lock);
  171. priv->clk = clk;
  172. priv->base = base;
  173. priv->ugctrl2 = pdata->chan0_pci ?
  174. USBHS_UGCTRL2_USB0_PCI : USBHS_UGCTRL2_USB0_HS;
  175. priv->ugctrl2 |= pdata->chan2_pci ?
  176. USBHS_UGCTRL2_USB2_PCI : USBHS_UGCTRL2_USB2_SS;
  177. priv->phy.dev = dev;
  178. priv->phy.label = dev_name(dev);
  179. priv->phy.init = rcar_gen2_usb_phy_init;
  180. priv->phy.shutdown = rcar_gen2_usb_phy_shutdown;
  181. priv->phy.set_suspend = rcar_gen2_usb_phy_set_suspend;
  182. retval = usb_add_phy(&priv->phy, USB_PHY_TYPE_USB2);
  183. if (retval < 0) {
  184. dev_err(dev, "Failed to add USB phy\n");
  185. return retval;
  186. }
  187. platform_set_drvdata(pdev, priv);
  188. return retval;
  189. }
  190. static int rcar_gen2_usb_phy_remove(struct platform_device *pdev)
  191. {
  192. struct rcar_gen2_usb_phy_priv *priv = platform_get_drvdata(pdev);
  193. usb_remove_phy(&priv->phy);
  194. return 0;
  195. }
  196. static struct platform_driver rcar_gen2_usb_phy_driver = {
  197. .driver = {
  198. .name = "usb_phy_rcar_gen2",
  199. },
  200. .probe = rcar_gen2_usb_phy_probe,
  201. .remove = rcar_gen2_usb_phy_remove,
  202. };
  203. module_platform_driver(rcar_gen2_usb_phy_driver);
  204. MODULE_LICENSE("GPL v2");
  205. MODULE_DESCRIPTION("Renesas R-Car Gen2 USB phy");
  206. MODULE_AUTHOR("Valentine Barshak <valentine.barshak@cogentembedded.com>");