at91sam9x5.dtsi 7.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355
  1. /*
  2. * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
  3. * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
  4. * AT91SAM9X25, AT91SAM9X35 SoC
  5. *
  6. * Copyright (C) 2012 Atmel,
  7. * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. model = "Atmel AT91SAM9x5 family SoC";
  14. compatible = "atmel,at91sam9x5";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. gpio0 = &pioA;
  22. gpio1 = &pioB;
  23. gpio2 = &pioC;
  24. gpio3 = &pioD;
  25. tcb0 = &tcb0;
  26. tcb1 = &tcb1;
  27. i2c0 = &i2c0;
  28. i2c1 = &i2c1;
  29. i2c2 = &i2c2;
  30. };
  31. cpus {
  32. cpu@0 {
  33. compatible = "arm,arm926ejs";
  34. };
  35. };
  36. memory {
  37. reg = <0x20000000 0x10000000>;
  38. };
  39. ahb {
  40. compatible = "simple-bus";
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. ranges;
  44. apb {
  45. compatible = "simple-bus";
  46. #address-cells = <1>;
  47. #size-cells = <1>;
  48. ranges;
  49. aic: interrupt-controller@fffff000 {
  50. #interrupt-cells = <3>;
  51. compatible = "atmel,at91rm9200-aic";
  52. interrupt-controller;
  53. reg = <0xfffff000 0x200>;
  54. atmel,external-irqs = <31>;
  55. };
  56. ramc0: ramc@ffffe800 {
  57. compatible = "atmel,at91sam9g45-ddramc";
  58. reg = <0xffffe800 0x200>;
  59. };
  60. pmc: pmc@fffffc00 {
  61. compatible = "atmel,at91rm9200-pmc";
  62. reg = <0xfffffc00 0x100>;
  63. };
  64. rstc@fffffe00 {
  65. compatible = "atmel,at91sam9g45-rstc";
  66. reg = <0xfffffe00 0x10>;
  67. };
  68. shdwc@fffffe10 {
  69. compatible = "atmel,at91sam9x5-shdwc";
  70. reg = <0xfffffe10 0x10>;
  71. };
  72. pit: timer@fffffe30 {
  73. compatible = "atmel,at91sam9260-pit";
  74. reg = <0xfffffe30 0xf>;
  75. interrupts = <1 4 7>;
  76. };
  77. tcb0: timer@f8008000 {
  78. compatible = "atmel,at91sam9x5-tcb";
  79. reg = <0xf8008000 0x100>;
  80. interrupts = <17 4 0>;
  81. };
  82. tcb1: timer@f800c000 {
  83. compatible = "atmel,at91sam9x5-tcb";
  84. reg = <0xf800c000 0x100>;
  85. interrupts = <17 4 0>;
  86. };
  87. dma0: dma-controller@ffffec00 {
  88. compatible = "atmel,at91sam9g45-dma";
  89. reg = <0xffffec00 0x200>;
  90. interrupts = <20 4 0>;
  91. };
  92. dma1: dma-controller@ffffee00 {
  93. compatible = "atmel,at91sam9g45-dma";
  94. reg = <0xffffee00 0x200>;
  95. interrupts = <21 4 0>;
  96. };
  97. pinctrl@fffff200 {
  98. #address-cells = <1>;
  99. #size-cells = <1>;
  100. compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
  101. ranges = <0xfffff400 0xfffff400 0x800>;
  102. atmel,mux-mask = <
  103. /* A B C */
  104. 0xffffffff 0xffe0399f 0xc000001c /* pioA */
  105. 0xffffffff 0xffc003ff 0xffc003ff /* pioB */
  106. 0xffffffff 0xffc003ff 0xffc003ff /* pioC */
  107. 0xffffffff 0xffc003ff 0xffc003ff /* pioD */
  108. >;
  109. /* shared pinctrl settings */
  110. pioA: gpio@fffff400 {
  111. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  112. reg = <0xfffff400 0x200>;
  113. interrupts = <2 4 1>;
  114. #gpio-cells = <2>;
  115. gpio-controller;
  116. interrupt-controller;
  117. #interrupt-cells = <2>;
  118. };
  119. pioB: gpio@fffff600 {
  120. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  121. reg = <0xfffff600 0x200>;
  122. interrupts = <2 4 1>;
  123. #gpio-cells = <2>;
  124. gpio-controller;
  125. #gpio-lines = <19>;
  126. interrupt-controller;
  127. #interrupt-cells = <2>;
  128. };
  129. pioC: gpio@fffff800 {
  130. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  131. reg = <0xfffff800 0x200>;
  132. interrupts = <3 4 1>;
  133. #gpio-cells = <2>;
  134. gpio-controller;
  135. interrupt-controller;
  136. #interrupt-cells = <2>;
  137. };
  138. pioD: gpio@fffffa00 {
  139. compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
  140. reg = <0xfffffa00 0x200>;
  141. interrupts = <3 4 1>;
  142. #gpio-cells = <2>;
  143. gpio-controller;
  144. #gpio-lines = <22>;
  145. interrupt-controller;
  146. #interrupt-cells = <2>;
  147. };
  148. };
  149. dbgu: serial@fffff200 {
  150. compatible = "atmel,at91sam9260-usart";
  151. reg = <0xfffff200 0x200>;
  152. interrupts = <1 4 7>;
  153. status = "disabled";
  154. };
  155. usart0: serial@f801c000 {
  156. compatible = "atmel,at91sam9260-usart";
  157. reg = <0xf801c000 0x200>;
  158. interrupts = <5 4 5>;
  159. atmel,use-dma-rx;
  160. atmel,use-dma-tx;
  161. status = "disabled";
  162. };
  163. usart1: serial@f8020000 {
  164. compatible = "atmel,at91sam9260-usart";
  165. reg = <0xf8020000 0x200>;
  166. interrupts = <6 4 5>;
  167. atmel,use-dma-rx;
  168. atmel,use-dma-tx;
  169. status = "disabled";
  170. };
  171. usart2: serial@f8024000 {
  172. compatible = "atmel,at91sam9260-usart";
  173. reg = <0xf8024000 0x200>;
  174. interrupts = <7 4 5>;
  175. atmel,use-dma-rx;
  176. atmel,use-dma-tx;
  177. status = "disabled";
  178. };
  179. macb0: ethernet@f802c000 {
  180. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  181. reg = <0xf802c000 0x100>;
  182. interrupts = <24 4 3>;
  183. status = "disabled";
  184. };
  185. macb1: ethernet@f8030000 {
  186. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  187. reg = <0xf8030000 0x100>;
  188. interrupts = <27 4 3>;
  189. status = "disabled";
  190. };
  191. i2c0: i2c@f8010000 {
  192. compatible = "atmel,at91sam9x5-i2c";
  193. reg = <0xf8010000 0x100>;
  194. interrupts = <9 4 6>;
  195. #address-cells = <1>;
  196. #size-cells = <0>;
  197. status = "disabled";
  198. };
  199. i2c1: i2c@f8014000 {
  200. compatible = "atmel,at91sam9x5-i2c";
  201. reg = <0xf8014000 0x100>;
  202. interrupts = <10 4 6>;
  203. #address-cells = <1>;
  204. #size-cells = <0>;
  205. status = "disabled";
  206. };
  207. i2c2: i2c@f8018000 {
  208. compatible = "atmel,at91sam9x5-i2c";
  209. reg = <0xf8018000 0x100>;
  210. interrupts = <11 4 6>;
  211. #address-cells = <1>;
  212. #size-cells = <0>;
  213. status = "disabled";
  214. };
  215. adc0: adc@f804c000 {
  216. compatible = "atmel,at91sam9260-adc";
  217. reg = <0xf804c000 0x100>;
  218. interrupts = <19 4 0>;
  219. atmel,adc-use-external;
  220. atmel,adc-channels-used = <0xffff>;
  221. atmel,adc-vref = <3300>;
  222. atmel,adc-num-channels = <12>;
  223. atmel,adc-startup-time = <40>;
  224. atmel,adc-channel-base = <0x50>;
  225. atmel,adc-drdy-mask = <0x1000000>;
  226. atmel,adc-status-register = <0x30>;
  227. atmel,adc-trigger-register = <0xc0>;
  228. trigger@0 {
  229. trigger-name = "external-rising";
  230. trigger-value = <0x1>;
  231. trigger-external;
  232. };
  233. trigger@1 {
  234. trigger-name = "external-falling";
  235. trigger-value = <0x2>;
  236. trigger-external;
  237. };
  238. trigger@2 {
  239. trigger-name = "external-any";
  240. trigger-value = <0x3>;
  241. trigger-external;
  242. };
  243. trigger@3 {
  244. trigger-name = "continuous";
  245. trigger-value = <0x6>;
  246. };
  247. };
  248. };
  249. nand0: nand@40000000 {
  250. compatible = "atmel,at91rm9200-nand";
  251. #address-cells = <1>;
  252. #size-cells = <1>;
  253. reg = <0x40000000 0x10000000
  254. >;
  255. atmel,nand-addr-offset = <21>;
  256. atmel,nand-cmd-offset = <22>;
  257. gpios = <&pioD 5 0
  258. &pioD 4 0
  259. 0
  260. >;
  261. status = "disabled";
  262. };
  263. usb0: ohci@00600000 {
  264. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  265. reg = <0x00600000 0x100000>;
  266. interrupts = <22 4 2>;
  267. status = "disabled";
  268. };
  269. usb1: ehci@00700000 {
  270. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  271. reg = <0x00700000 0x100000>;
  272. interrupts = <22 4 2>;
  273. status = "disabled";
  274. };
  275. };
  276. i2c@0 {
  277. compatible = "i2c-gpio";
  278. gpios = <&pioA 30 0 /* sda */
  279. &pioA 31 0 /* scl */
  280. >;
  281. i2c-gpio,sda-open-drain;
  282. i2c-gpio,scl-open-drain;
  283. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  284. #address-cells = <1>;
  285. #size-cells = <0>;
  286. status = "disabled";
  287. };
  288. i2c@1 {
  289. compatible = "i2c-gpio";
  290. gpios = <&pioC 0 0 /* sda */
  291. &pioC 1 0 /* scl */
  292. >;
  293. i2c-gpio,sda-open-drain;
  294. i2c-gpio,scl-open-drain;
  295. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  296. #address-cells = <1>;
  297. #size-cells = <0>;
  298. status = "disabled";
  299. };
  300. i2c@2 {
  301. compatible = "i2c-gpio";
  302. gpios = <&pioB 4 0 /* sda */
  303. &pioB 5 0 /* scl */
  304. >;
  305. i2c-gpio,sda-open-drain;
  306. i2c-gpio,scl-open-drain;
  307. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  308. #address-cells = <1>;
  309. #size-cells = <0>;
  310. status = "disabled";
  311. };
  312. };