at91sam9g45.dtsi 7.1 KB

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  1. /*
  2. * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
  3. * applies to AT91SAM9G45, AT91SAM9M10,
  4. * AT91SAM9G46, AT91SAM9M11 SoC
  5. *
  6. * Copyright (C) 2011 Atmel,
  7. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. model = "Atmel AT91SAM9G45 family SoC";
  14. compatible = "atmel,at91sam9g45";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. serial4 = &usart3;
  22. gpio0 = &pioA;
  23. gpio1 = &pioB;
  24. gpio2 = &pioC;
  25. gpio3 = &pioD;
  26. gpio4 = &pioE;
  27. tcb0 = &tcb0;
  28. tcb1 = &tcb1;
  29. i2c0 = &i2c0;
  30. i2c1 = &i2c1;
  31. };
  32. cpus {
  33. cpu@0 {
  34. compatible = "arm,arm926ejs";
  35. };
  36. };
  37. memory {
  38. reg = <0x70000000 0x10000000>;
  39. };
  40. ahb {
  41. compatible = "simple-bus";
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. ranges;
  45. apb {
  46. compatible = "simple-bus";
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. ranges;
  50. aic: interrupt-controller@fffff000 {
  51. #interrupt-cells = <3>;
  52. compatible = "atmel,at91rm9200-aic";
  53. interrupt-controller;
  54. reg = <0xfffff000 0x200>;
  55. atmel,external-irqs = <31>;
  56. };
  57. ramc0: ramc@ffffe400 {
  58. compatible = "atmel,at91sam9g45-ddramc";
  59. reg = <0xffffe400 0x200
  60. 0xffffe600 0x200>;
  61. };
  62. pmc: pmc@fffffc00 {
  63. compatible = "atmel,at91rm9200-pmc";
  64. reg = <0xfffffc00 0x100>;
  65. };
  66. rstc@fffffd00 {
  67. compatible = "atmel,at91sam9g45-rstc";
  68. reg = <0xfffffd00 0x10>;
  69. };
  70. pit: timer@fffffd30 {
  71. compatible = "atmel,at91sam9260-pit";
  72. reg = <0xfffffd30 0xf>;
  73. interrupts = <1 4 7>;
  74. };
  75. shdwc@fffffd10 {
  76. compatible = "atmel,at91sam9rl-shdwc";
  77. reg = <0xfffffd10 0x10>;
  78. };
  79. tcb0: timer@fff7c000 {
  80. compatible = "atmel,at91rm9200-tcb";
  81. reg = <0xfff7c000 0x100>;
  82. interrupts = <18 4 0>;
  83. };
  84. tcb1: timer@fffd4000 {
  85. compatible = "atmel,at91rm9200-tcb";
  86. reg = <0xfffd4000 0x100>;
  87. interrupts = <18 4 0>;
  88. };
  89. dma: dma-controller@ffffec00 {
  90. compatible = "atmel,at91sam9g45-dma";
  91. reg = <0xffffec00 0x200>;
  92. interrupts = <21 4 0>;
  93. };
  94. pinctrl@fffff200 {
  95. #address-cells = <1>;
  96. #size-cells = <1>;
  97. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  98. ranges = <0xfffff200 0xfffff200 0xa00>;
  99. atmel,mux-mask = <
  100. /* A B */
  101. 0xffffffff 0xffc003ff /* pioA */
  102. 0xffffffff 0x800f8f00 /* pioB */
  103. 0xffffffff 0x00000e00 /* pioC */
  104. 0xffffffff 0xff0c1381 /* pioD */
  105. 0xffffffff 0x81ffff81 /* pioE */
  106. >;
  107. /* shared pinctrl settings */
  108. pioA: gpio@fffff200 {
  109. compatible = "atmel,at91rm9200-gpio";
  110. reg = <0xfffff200 0x200>;
  111. interrupts = <2 4 1>;
  112. #gpio-cells = <2>;
  113. gpio-controller;
  114. interrupt-controller;
  115. #interrupt-cells = <2>;
  116. };
  117. pioB: gpio@fffff400 {
  118. compatible = "atmel,at91rm9200-gpio";
  119. reg = <0xfffff400 0x200>;
  120. interrupts = <3 4 1>;
  121. #gpio-cells = <2>;
  122. gpio-controller;
  123. interrupt-controller;
  124. #interrupt-cells = <2>;
  125. };
  126. pioC: gpio@fffff600 {
  127. compatible = "atmel,at91rm9200-gpio";
  128. reg = <0xfffff600 0x200>;
  129. interrupts = <4 4 1>;
  130. #gpio-cells = <2>;
  131. gpio-controller;
  132. interrupt-controller;
  133. #interrupt-cells = <2>;
  134. };
  135. pioD: gpio@fffff800 {
  136. compatible = "atmel,at91rm9200-gpio";
  137. reg = <0xfffff800 0x200>;
  138. interrupts = <5 4 1>;
  139. #gpio-cells = <2>;
  140. gpio-controller;
  141. interrupt-controller;
  142. #interrupt-cells = <2>;
  143. };
  144. pioE: gpio@fffffa00 {
  145. compatible = "atmel,at91rm9200-gpio";
  146. reg = <0xfffffa00 0x200>;
  147. interrupts = <5 4 1>;
  148. #gpio-cells = <2>;
  149. gpio-controller;
  150. interrupt-controller;
  151. #interrupt-cells = <2>;
  152. };
  153. };
  154. dbgu: serial@ffffee00 {
  155. compatible = "atmel,at91sam9260-usart";
  156. reg = <0xffffee00 0x200>;
  157. interrupts = <1 4 7>;
  158. status = "disabled";
  159. };
  160. usart0: serial@fff8c000 {
  161. compatible = "atmel,at91sam9260-usart";
  162. reg = <0xfff8c000 0x200>;
  163. interrupts = <7 4 5>;
  164. atmel,use-dma-rx;
  165. atmel,use-dma-tx;
  166. status = "disabled";
  167. };
  168. usart1: serial@fff90000 {
  169. compatible = "atmel,at91sam9260-usart";
  170. reg = <0xfff90000 0x200>;
  171. interrupts = <8 4 5>;
  172. atmel,use-dma-rx;
  173. atmel,use-dma-tx;
  174. status = "disabled";
  175. };
  176. usart2: serial@fff94000 {
  177. compatible = "atmel,at91sam9260-usart";
  178. reg = <0xfff94000 0x200>;
  179. interrupts = <9 4 5>;
  180. atmel,use-dma-rx;
  181. atmel,use-dma-tx;
  182. status = "disabled";
  183. };
  184. usart3: serial@fff98000 {
  185. compatible = "atmel,at91sam9260-usart";
  186. reg = <0xfff98000 0x200>;
  187. interrupts = <10 4 5>;
  188. atmel,use-dma-rx;
  189. atmel,use-dma-tx;
  190. status = "disabled";
  191. };
  192. macb0: ethernet@fffbc000 {
  193. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  194. reg = <0xfffbc000 0x100>;
  195. interrupts = <25 4 3>;
  196. status = "disabled";
  197. };
  198. i2c0: i2c@fff84000 {
  199. compatible = "atmel,at91sam9g10-i2c";
  200. reg = <0xfff84000 0x100>;
  201. interrupts = <12 4 6>;
  202. #address-cells = <1>;
  203. #size-cells = <0>;
  204. status = "disabled";
  205. };
  206. i2c1: i2c@fff88000 {
  207. compatible = "atmel,at91sam9g10-i2c";
  208. reg = <0xfff88000 0x100>;
  209. interrupts = <13 4 6>;
  210. #address-cells = <1>;
  211. #size-cells = <0>;
  212. status = "disabled";
  213. };
  214. adc0: adc@fffb0000 {
  215. compatible = "atmel,at91sam9260-adc";
  216. reg = <0xfffb0000 0x100>;
  217. interrupts = <20 4 0>;
  218. atmel,adc-use-external-triggers;
  219. atmel,adc-channels-used = <0xff>;
  220. atmel,adc-vref = <3300>;
  221. atmel,adc-num-channels = <8>;
  222. atmel,adc-startup-time = <40>;
  223. atmel,adc-channel-base = <0x30>;
  224. atmel,adc-drdy-mask = <0x10000>;
  225. atmel,adc-status-register = <0x1c>;
  226. atmel,adc-trigger-register = <0x08>;
  227. trigger@0 {
  228. trigger-name = "external-rising";
  229. trigger-value = <0x1>;
  230. trigger-external;
  231. };
  232. trigger@1 {
  233. trigger-name = "external-falling";
  234. trigger-value = <0x2>;
  235. trigger-external;
  236. };
  237. trigger@2 {
  238. trigger-name = "external-any";
  239. trigger-value = <0x3>;
  240. trigger-external;
  241. };
  242. trigger@3 {
  243. trigger-name = "continuous";
  244. trigger-value = <0x6>;
  245. };
  246. };
  247. };
  248. nand0: nand@40000000 {
  249. compatible = "atmel,at91rm9200-nand";
  250. #address-cells = <1>;
  251. #size-cells = <1>;
  252. reg = <0x40000000 0x10000000
  253. 0xffffe200 0x200
  254. >;
  255. atmel,nand-addr-offset = <21>;
  256. atmel,nand-cmd-offset = <22>;
  257. gpios = <&pioC 8 0
  258. &pioC 14 0
  259. 0
  260. >;
  261. status = "disabled";
  262. };
  263. usb0: ohci@00700000 {
  264. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  265. reg = <0x00700000 0x100000>;
  266. interrupts = <22 4 2>;
  267. status = "disabled";
  268. };
  269. usb1: ehci@00800000 {
  270. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  271. reg = <0x00800000 0x100000>;
  272. interrupts = <22 4 2>;
  273. status = "disabled";
  274. };
  275. };
  276. i2c@0 {
  277. compatible = "i2c-gpio";
  278. gpios = <&pioA 20 0 /* sda */
  279. &pioA 21 0 /* scl */
  280. >;
  281. i2c-gpio,sda-open-drain;
  282. i2c-gpio,scl-open-drain;
  283. i2c-gpio,delay-us = <5>; /* ~100 kHz */
  284. #address-cells = <1>;
  285. #size-cells = <0>;
  286. status = "disabled";
  287. };
  288. };