mthca_cmd.c 57 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
  4. * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. *
  34. * $Id: mthca_cmd.c 1349 2004-12-16 21:09:43Z roland $
  35. */
  36. #include <linux/sched.h>
  37. #include <linux/pci.h>
  38. #include <linux/errno.h>
  39. #include <asm/io.h>
  40. #include <rdma/ib_mad.h>
  41. #include "mthca_dev.h"
  42. #include "mthca_config_reg.h"
  43. #include "mthca_cmd.h"
  44. #include "mthca_memfree.h"
  45. #define CMD_POLL_TOKEN 0xffff
  46. enum {
  47. HCR_IN_PARAM_OFFSET = 0x00,
  48. HCR_IN_MODIFIER_OFFSET = 0x08,
  49. HCR_OUT_PARAM_OFFSET = 0x0c,
  50. HCR_TOKEN_OFFSET = 0x14,
  51. HCR_STATUS_OFFSET = 0x18,
  52. HCR_OPMOD_SHIFT = 12,
  53. HCA_E_BIT = 22,
  54. HCR_GO_BIT = 23
  55. };
  56. enum {
  57. /* initialization and general commands */
  58. CMD_SYS_EN = 0x1,
  59. CMD_SYS_DIS = 0x2,
  60. CMD_MAP_FA = 0xfff,
  61. CMD_UNMAP_FA = 0xffe,
  62. CMD_RUN_FW = 0xff6,
  63. CMD_MOD_STAT_CFG = 0x34,
  64. CMD_QUERY_DEV_LIM = 0x3,
  65. CMD_QUERY_FW = 0x4,
  66. CMD_ENABLE_LAM = 0xff8,
  67. CMD_DISABLE_LAM = 0xff7,
  68. CMD_QUERY_DDR = 0x5,
  69. CMD_QUERY_ADAPTER = 0x6,
  70. CMD_INIT_HCA = 0x7,
  71. CMD_CLOSE_HCA = 0x8,
  72. CMD_INIT_IB = 0x9,
  73. CMD_CLOSE_IB = 0xa,
  74. CMD_QUERY_HCA = 0xb,
  75. CMD_SET_IB = 0xc,
  76. CMD_ACCESS_DDR = 0x2e,
  77. CMD_MAP_ICM = 0xffa,
  78. CMD_UNMAP_ICM = 0xff9,
  79. CMD_MAP_ICM_AUX = 0xffc,
  80. CMD_UNMAP_ICM_AUX = 0xffb,
  81. CMD_SET_ICM_SIZE = 0xffd,
  82. /* TPT commands */
  83. CMD_SW2HW_MPT = 0xd,
  84. CMD_QUERY_MPT = 0xe,
  85. CMD_HW2SW_MPT = 0xf,
  86. CMD_READ_MTT = 0x10,
  87. CMD_WRITE_MTT = 0x11,
  88. CMD_SYNC_TPT = 0x2f,
  89. /* EQ commands */
  90. CMD_MAP_EQ = 0x12,
  91. CMD_SW2HW_EQ = 0x13,
  92. CMD_HW2SW_EQ = 0x14,
  93. CMD_QUERY_EQ = 0x15,
  94. /* CQ commands */
  95. CMD_SW2HW_CQ = 0x16,
  96. CMD_HW2SW_CQ = 0x17,
  97. CMD_QUERY_CQ = 0x18,
  98. CMD_RESIZE_CQ = 0x2c,
  99. /* SRQ commands */
  100. CMD_SW2HW_SRQ = 0x35,
  101. CMD_HW2SW_SRQ = 0x36,
  102. CMD_QUERY_SRQ = 0x37,
  103. CMD_ARM_SRQ = 0x40,
  104. /* QP/EE commands */
  105. CMD_RST2INIT_QPEE = 0x19,
  106. CMD_INIT2RTR_QPEE = 0x1a,
  107. CMD_RTR2RTS_QPEE = 0x1b,
  108. CMD_RTS2RTS_QPEE = 0x1c,
  109. CMD_SQERR2RTS_QPEE = 0x1d,
  110. CMD_2ERR_QPEE = 0x1e,
  111. CMD_RTS2SQD_QPEE = 0x1f,
  112. CMD_SQD2SQD_QPEE = 0x38,
  113. CMD_SQD2RTS_QPEE = 0x20,
  114. CMD_ERR2RST_QPEE = 0x21,
  115. CMD_QUERY_QPEE = 0x22,
  116. CMD_INIT2INIT_QPEE = 0x2d,
  117. CMD_SUSPEND_QPEE = 0x32,
  118. CMD_UNSUSPEND_QPEE = 0x33,
  119. /* special QPs and management commands */
  120. CMD_CONF_SPECIAL_QP = 0x23,
  121. CMD_MAD_IFC = 0x24,
  122. /* multicast commands */
  123. CMD_READ_MGM = 0x25,
  124. CMD_WRITE_MGM = 0x26,
  125. CMD_MGID_HASH = 0x27,
  126. /* miscellaneous commands */
  127. CMD_DIAG_RPRT = 0x30,
  128. CMD_NOP = 0x31,
  129. /* debug commands */
  130. CMD_QUERY_DEBUG_MSG = 0x2a,
  131. CMD_SET_DEBUG_MSG = 0x2b,
  132. };
  133. /*
  134. * According to Mellanox code, FW may be starved and never complete
  135. * commands. So we can't use strict timeouts described in PRM -- we
  136. * just arbitrarily select 60 seconds for now.
  137. */
  138. #if 0
  139. /*
  140. * Round up and add 1 to make sure we get the full wait time (since we
  141. * will be starting in the middle of a jiffy)
  142. */
  143. enum {
  144. CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1,
  145. CMD_TIME_CLASS_B = (HZ + 99) / 100 + 1,
  146. CMD_TIME_CLASS_C = (HZ + 9) / 10 + 1
  147. };
  148. #else
  149. enum {
  150. CMD_TIME_CLASS_A = 60 * HZ,
  151. CMD_TIME_CLASS_B = 60 * HZ,
  152. CMD_TIME_CLASS_C = 60 * HZ
  153. };
  154. #endif
  155. enum {
  156. GO_BIT_TIMEOUT = HZ * 10
  157. };
  158. struct mthca_cmd_context {
  159. struct completion done;
  160. struct timer_list timer;
  161. int result;
  162. int next;
  163. u64 out_param;
  164. u16 token;
  165. u8 status;
  166. };
  167. static int fw_cmd_doorbell = 1;
  168. module_param(fw_cmd_doorbell, int, 0644);
  169. MODULE_PARM_DESC(fw_cmd_doorbell, "post FW commands through doorbell page if nonzero "
  170. "(and supported by FW)");
  171. static inline int go_bit(struct mthca_dev *dev)
  172. {
  173. return readl(dev->hcr + HCR_STATUS_OFFSET) &
  174. swab32(1 << HCR_GO_BIT);
  175. }
  176. static void mthca_cmd_post_dbell(struct mthca_dev *dev,
  177. u64 in_param,
  178. u64 out_param,
  179. u32 in_modifier,
  180. u8 op_modifier,
  181. u16 op,
  182. u16 token)
  183. {
  184. void __iomem *ptr = dev->cmd.dbell_map;
  185. u16 *offs = dev->cmd.dbell_offsets;
  186. __raw_writel((__force u32) cpu_to_be32(in_param >> 32), ptr + offs[0]);
  187. wmb();
  188. __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), ptr + offs[1]);
  189. wmb();
  190. __raw_writel((__force u32) cpu_to_be32(in_modifier), ptr + offs[2]);
  191. wmb();
  192. __raw_writel((__force u32) cpu_to_be32(out_param >> 32), ptr + offs[3]);
  193. wmb();
  194. __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), ptr + offs[4]);
  195. wmb();
  196. __raw_writel((__force u32) cpu_to_be32(token << 16), ptr + offs[5]);
  197. wmb();
  198. __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
  199. (1 << HCA_E_BIT) |
  200. (op_modifier << HCR_OPMOD_SHIFT) |
  201. op), ptr + offs[6]);
  202. wmb();
  203. __raw_writel((__force u32) 0, ptr + offs[7]);
  204. wmb();
  205. }
  206. static int mthca_cmd_post_hcr(struct mthca_dev *dev,
  207. u64 in_param,
  208. u64 out_param,
  209. u32 in_modifier,
  210. u8 op_modifier,
  211. u16 op,
  212. u16 token,
  213. int event)
  214. {
  215. if (event) {
  216. unsigned long end = jiffies + GO_BIT_TIMEOUT;
  217. while (go_bit(dev) && time_before(jiffies, end)) {
  218. set_current_state(TASK_RUNNING);
  219. schedule();
  220. }
  221. }
  222. if (go_bit(dev))
  223. return -EAGAIN;
  224. /*
  225. * We use writel (instead of something like memcpy_toio)
  226. * because writes of less than 32 bits to the HCR don't work
  227. * (and some architectures such as ia64 implement memcpy_toio
  228. * in terms of writeb).
  229. */
  230. __raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4);
  231. __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4);
  232. __raw_writel((__force u32) cpu_to_be32(in_modifier), dev->hcr + 2 * 4);
  233. __raw_writel((__force u32) cpu_to_be32(out_param >> 32), dev->hcr + 3 * 4);
  234. __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4);
  235. __raw_writel((__force u32) cpu_to_be32(token << 16), dev->hcr + 5 * 4);
  236. /* __raw_writel may not order writes. */
  237. wmb();
  238. __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
  239. (event ? (1 << HCA_E_BIT) : 0) |
  240. (op_modifier << HCR_OPMOD_SHIFT) |
  241. op), dev->hcr + 6 * 4);
  242. return 0;
  243. }
  244. static int mthca_cmd_post(struct mthca_dev *dev,
  245. u64 in_param,
  246. u64 out_param,
  247. u32 in_modifier,
  248. u8 op_modifier,
  249. u16 op,
  250. u16 token,
  251. int event)
  252. {
  253. int err = 0;
  254. mutex_lock(&dev->cmd.hcr_mutex);
  255. if (event && dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS && fw_cmd_doorbell)
  256. mthca_cmd_post_dbell(dev, in_param, out_param, in_modifier,
  257. op_modifier, op, token);
  258. else
  259. err = mthca_cmd_post_hcr(dev, in_param, out_param, in_modifier,
  260. op_modifier, op, token, event);
  261. mutex_unlock(&dev->cmd.hcr_mutex);
  262. return err;
  263. }
  264. static int mthca_cmd_poll(struct mthca_dev *dev,
  265. u64 in_param,
  266. u64 *out_param,
  267. int out_is_imm,
  268. u32 in_modifier,
  269. u8 op_modifier,
  270. u16 op,
  271. unsigned long timeout,
  272. u8 *status)
  273. {
  274. int err = 0;
  275. unsigned long end;
  276. down(&dev->cmd.poll_sem);
  277. err = mthca_cmd_post(dev, in_param,
  278. out_param ? *out_param : 0,
  279. in_modifier, op_modifier,
  280. op, CMD_POLL_TOKEN, 0);
  281. if (err)
  282. goto out;
  283. end = timeout + jiffies;
  284. while (go_bit(dev) && time_before(jiffies, end)) {
  285. set_current_state(TASK_RUNNING);
  286. schedule();
  287. }
  288. if (go_bit(dev)) {
  289. err = -EBUSY;
  290. goto out;
  291. }
  292. if (out_is_imm)
  293. *out_param =
  294. (u64) be32_to_cpu((__force __be32)
  295. __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
  296. (u64) be32_to_cpu((__force __be32)
  297. __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4));
  298. *status = be32_to_cpu((__force __be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24;
  299. out:
  300. up(&dev->cmd.poll_sem);
  301. return err;
  302. }
  303. void mthca_cmd_event(struct mthca_dev *dev,
  304. u16 token,
  305. u8 status,
  306. u64 out_param)
  307. {
  308. struct mthca_cmd_context *context =
  309. &dev->cmd.context[token & dev->cmd.token_mask];
  310. /* previously timed out command completing at long last */
  311. if (token != context->token)
  312. return;
  313. context->result = 0;
  314. context->status = status;
  315. context->out_param = out_param;
  316. context->token += dev->cmd.token_mask + 1;
  317. complete(&context->done);
  318. }
  319. static void event_timeout(unsigned long context_ptr)
  320. {
  321. struct mthca_cmd_context *context =
  322. (struct mthca_cmd_context *) context_ptr;
  323. context->result = -EBUSY;
  324. complete(&context->done);
  325. }
  326. static int mthca_cmd_wait(struct mthca_dev *dev,
  327. u64 in_param,
  328. u64 *out_param,
  329. int out_is_imm,
  330. u32 in_modifier,
  331. u8 op_modifier,
  332. u16 op,
  333. unsigned long timeout,
  334. u8 *status)
  335. {
  336. int err = 0;
  337. struct mthca_cmd_context *context;
  338. down(&dev->cmd.event_sem);
  339. spin_lock(&dev->cmd.context_lock);
  340. BUG_ON(dev->cmd.free_head < 0);
  341. context = &dev->cmd.context[dev->cmd.free_head];
  342. dev->cmd.free_head = context->next;
  343. spin_unlock(&dev->cmd.context_lock);
  344. init_completion(&context->done);
  345. err = mthca_cmd_post(dev, in_param,
  346. out_param ? *out_param : 0,
  347. in_modifier, op_modifier,
  348. op, context->token, 1);
  349. if (err)
  350. goto out;
  351. context->timer.expires = jiffies + timeout;
  352. add_timer(&context->timer);
  353. wait_for_completion(&context->done);
  354. del_timer_sync(&context->timer);
  355. err = context->result;
  356. if (err)
  357. goto out;
  358. *status = context->status;
  359. if (*status)
  360. mthca_dbg(dev, "Command %02x completed with status %02x\n",
  361. op, *status);
  362. if (out_is_imm)
  363. *out_param = context->out_param;
  364. out:
  365. spin_lock(&dev->cmd.context_lock);
  366. context->next = dev->cmd.free_head;
  367. dev->cmd.free_head = context - dev->cmd.context;
  368. spin_unlock(&dev->cmd.context_lock);
  369. up(&dev->cmd.event_sem);
  370. return err;
  371. }
  372. /* Invoke a command with an output mailbox */
  373. static int mthca_cmd_box(struct mthca_dev *dev,
  374. u64 in_param,
  375. u64 out_param,
  376. u32 in_modifier,
  377. u8 op_modifier,
  378. u16 op,
  379. unsigned long timeout,
  380. u8 *status)
  381. {
  382. if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS)
  383. return mthca_cmd_wait(dev, in_param, &out_param, 0,
  384. in_modifier, op_modifier, op,
  385. timeout, status);
  386. else
  387. return mthca_cmd_poll(dev, in_param, &out_param, 0,
  388. in_modifier, op_modifier, op,
  389. timeout, status);
  390. }
  391. /* Invoke a command with no output parameter */
  392. static int mthca_cmd(struct mthca_dev *dev,
  393. u64 in_param,
  394. u32 in_modifier,
  395. u8 op_modifier,
  396. u16 op,
  397. unsigned long timeout,
  398. u8 *status)
  399. {
  400. return mthca_cmd_box(dev, in_param, 0, in_modifier,
  401. op_modifier, op, timeout, status);
  402. }
  403. /*
  404. * Invoke a command with an immediate output parameter (and copy the
  405. * output into the caller's out_param pointer after the command
  406. * executes).
  407. */
  408. static int mthca_cmd_imm(struct mthca_dev *dev,
  409. u64 in_param,
  410. u64 *out_param,
  411. u32 in_modifier,
  412. u8 op_modifier,
  413. u16 op,
  414. unsigned long timeout,
  415. u8 *status)
  416. {
  417. if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS)
  418. return mthca_cmd_wait(dev, in_param, out_param, 1,
  419. in_modifier, op_modifier, op,
  420. timeout, status);
  421. else
  422. return mthca_cmd_poll(dev, in_param, out_param, 1,
  423. in_modifier, op_modifier, op,
  424. timeout, status);
  425. }
  426. int mthca_cmd_init(struct mthca_dev *dev)
  427. {
  428. mutex_init(&dev->cmd.hcr_mutex);
  429. sema_init(&dev->cmd.poll_sem, 1);
  430. dev->cmd.flags = 0;
  431. dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + MTHCA_HCR_BASE,
  432. MTHCA_HCR_SIZE);
  433. if (!dev->hcr) {
  434. mthca_err(dev, "Couldn't map command register.");
  435. return -ENOMEM;
  436. }
  437. dev->cmd.pool = pci_pool_create("mthca_cmd", dev->pdev,
  438. MTHCA_MAILBOX_SIZE,
  439. MTHCA_MAILBOX_SIZE, 0);
  440. if (!dev->cmd.pool) {
  441. iounmap(dev->hcr);
  442. return -ENOMEM;
  443. }
  444. return 0;
  445. }
  446. void mthca_cmd_cleanup(struct mthca_dev *dev)
  447. {
  448. pci_pool_destroy(dev->cmd.pool);
  449. iounmap(dev->hcr);
  450. if (dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS)
  451. iounmap(dev->cmd.dbell_map);
  452. }
  453. /*
  454. * Switch to using events to issue FW commands (should be called after
  455. * event queue to command events has been initialized).
  456. */
  457. int mthca_cmd_use_events(struct mthca_dev *dev)
  458. {
  459. int i;
  460. dev->cmd.context = kmalloc(dev->cmd.max_cmds *
  461. sizeof (struct mthca_cmd_context),
  462. GFP_KERNEL);
  463. if (!dev->cmd.context)
  464. return -ENOMEM;
  465. for (i = 0; i < dev->cmd.max_cmds; ++i) {
  466. dev->cmd.context[i].token = i;
  467. dev->cmd.context[i].next = i + 1;
  468. init_timer(&dev->cmd.context[i].timer);
  469. dev->cmd.context[i].timer.data =
  470. (unsigned long) &dev->cmd.context[i];
  471. dev->cmd.context[i].timer.function = event_timeout;
  472. }
  473. dev->cmd.context[dev->cmd.max_cmds - 1].next = -1;
  474. dev->cmd.free_head = 0;
  475. sema_init(&dev->cmd.event_sem, dev->cmd.max_cmds);
  476. spin_lock_init(&dev->cmd.context_lock);
  477. for (dev->cmd.token_mask = 1;
  478. dev->cmd.token_mask < dev->cmd.max_cmds;
  479. dev->cmd.token_mask <<= 1)
  480. ; /* nothing */
  481. --dev->cmd.token_mask;
  482. dev->cmd.flags |= MTHCA_CMD_USE_EVENTS;
  483. down(&dev->cmd.poll_sem);
  484. return 0;
  485. }
  486. /*
  487. * Switch back to polling (used when shutting down the device)
  488. */
  489. void mthca_cmd_use_polling(struct mthca_dev *dev)
  490. {
  491. int i;
  492. dev->cmd.flags &= ~MTHCA_CMD_USE_EVENTS;
  493. for (i = 0; i < dev->cmd.max_cmds; ++i)
  494. down(&dev->cmd.event_sem);
  495. kfree(dev->cmd.context);
  496. up(&dev->cmd.poll_sem);
  497. }
  498. struct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev,
  499. gfp_t gfp_mask)
  500. {
  501. struct mthca_mailbox *mailbox;
  502. mailbox = kmalloc(sizeof *mailbox, gfp_mask);
  503. if (!mailbox)
  504. return ERR_PTR(-ENOMEM);
  505. mailbox->buf = pci_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma);
  506. if (!mailbox->buf) {
  507. kfree(mailbox);
  508. return ERR_PTR(-ENOMEM);
  509. }
  510. return mailbox;
  511. }
  512. void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox)
  513. {
  514. if (!mailbox)
  515. return;
  516. pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
  517. kfree(mailbox);
  518. }
  519. int mthca_SYS_EN(struct mthca_dev *dev, u8 *status)
  520. {
  521. u64 out;
  522. int ret;
  523. ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, HZ, status);
  524. if (*status == MTHCA_CMD_STAT_DDR_MEM_ERR)
  525. mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, "
  526. "sladdr=%d, SPD source=%s\n",
  527. (int) (out >> 6) & 0xf, (int) (out >> 4) & 3,
  528. (int) (out >> 1) & 7, (int) out & 1 ? "NVMEM" : "DIMM");
  529. return ret;
  530. }
  531. int mthca_SYS_DIS(struct mthca_dev *dev, u8 *status)
  532. {
  533. return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, HZ, status);
  534. }
  535. static int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm,
  536. u64 virt, u8 *status)
  537. {
  538. struct mthca_mailbox *mailbox;
  539. struct mthca_icm_iter iter;
  540. __be64 *pages;
  541. int lg;
  542. int nent = 0;
  543. int i;
  544. int err = 0;
  545. int ts = 0, tc = 0;
  546. mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  547. if (IS_ERR(mailbox))
  548. return PTR_ERR(mailbox);
  549. memset(mailbox->buf, 0, MTHCA_MAILBOX_SIZE);
  550. pages = mailbox->buf;
  551. for (mthca_icm_first(icm, &iter);
  552. !mthca_icm_last(&iter);
  553. mthca_icm_next(&iter)) {
  554. /*
  555. * We have to pass pages that are aligned to their
  556. * size, so find the least significant 1 in the
  557. * address or size and use that as our log2 size.
  558. */
  559. lg = ffs(mthca_icm_addr(&iter) | mthca_icm_size(&iter)) - 1;
  560. if (lg < MTHCA_ICM_PAGE_SHIFT) {
  561. mthca_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
  562. MTHCA_ICM_PAGE_SIZE,
  563. (unsigned long long) mthca_icm_addr(&iter),
  564. mthca_icm_size(&iter));
  565. err = -EINVAL;
  566. goto out;
  567. }
  568. for (i = 0; i < mthca_icm_size(&iter) >> lg; ++i) {
  569. if (virt != -1) {
  570. pages[nent * 2] = cpu_to_be64(virt);
  571. virt += 1 << lg;
  572. }
  573. pages[nent * 2 + 1] =
  574. cpu_to_be64((mthca_icm_addr(&iter) + (i << lg)) |
  575. (lg - MTHCA_ICM_PAGE_SHIFT));
  576. ts += 1 << (lg - 10);
  577. ++tc;
  578. if (++nent == MTHCA_MAILBOX_SIZE / 16) {
  579. err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
  580. CMD_TIME_CLASS_B, status);
  581. if (err || *status)
  582. goto out;
  583. nent = 0;
  584. }
  585. }
  586. }
  587. if (nent)
  588. err = mthca_cmd(dev, mailbox->dma, nent, 0, op,
  589. CMD_TIME_CLASS_B, status);
  590. switch (op) {
  591. case CMD_MAP_FA:
  592. mthca_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
  593. break;
  594. case CMD_MAP_ICM_AUX:
  595. mthca_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
  596. break;
  597. case CMD_MAP_ICM:
  598. mthca_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
  599. tc, ts, (unsigned long long) virt - (ts << 10));
  600. break;
  601. }
  602. out:
  603. mthca_free_mailbox(dev, mailbox);
  604. return err;
  605. }
  606. int mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
  607. {
  608. return mthca_map_cmd(dev, CMD_MAP_FA, icm, -1, status);
  609. }
  610. int mthca_UNMAP_FA(struct mthca_dev *dev, u8 *status)
  611. {
  612. return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B, status);
  613. }
  614. int mthca_RUN_FW(struct mthca_dev *dev, u8 *status)
  615. {
  616. return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A, status);
  617. }
  618. static void mthca_setup_cmd_doorbells(struct mthca_dev *dev, u64 base)
  619. {
  620. unsigned long addr;
  621. u16 max_off = 0;
  622. int i;
  623. for (i = 0; i < 8; ++i)
  624. max_off = max(max_off, dev->cmd.dbell_offsets[i]);
  625. if ((base & PAGE_MASK) != ((base + max_off) & PAGE_MASK)) {
  626. mthca_warn(dev, "Firmware doorbell region at 0x%016llx, "
  627. "length 0x%x crosses a page boundary\n",
  628. (unsigned long long) base, max_off);
  629. return;
  630. }
  631. addr = pci_resource_start(dev->pdev, 2) +
  632. ((pci_resource_len(dev->pdev, 2) - 1) & base);
  633. dev->cmd.dbell_map = ioremap(addr, max_off + sizeof(u32));
  634. if (!dev->cmd.dbell_map)
  635. return;
  636. dev->cmd.flags |= MTHCA_CMD_POST_DOORBELLS;
  637. mthca_dbg(dev, "Mapped doorbell page for posting FW commands\n");
  638. }
  639. int mthca_QUERY_FW(struct mthca_dev *dev, u8 *status)
  640. {
  641. struct mthca_mailbox *mailbox;
  642. u32 *outbox;
  643. u64 base;
  644. u32 tmp;
  645. int err = 0;
  646. u8 lg;
  647. int i;
  648. #define QUERY_FW_OUT_SIZE 0x100
  649. #define QUERY_FW_VER_OFFSET 0x00
  650. #define QUERY_FW_MAX_CMD_OFFSET 0x0f
  651. #define QUERY_FW_ERR_START_OFFSET 0x30
  652. #define QUERY_FW_ERR_SIZE_OFFSET 0x38
  653. #define QUERY_FW_CMD_DB_EN_OFFSET 0x10
  654. #define QUERY_FW_CMD_DB_OFFSET 0x50
  655. #define QUERY_FW_CMD_DB_BASE 0x60
  656. #define QUERY_FW_START_OFFSET 0x20
  657. #define QUERY_FW_END_OFFSET 0x28
  658. #define QUERY_FW_SIZE_OFFSET 0x00
  659. #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
  660. #define QUERY_FW_EQ_ARM_BASE_OFFSET 0x40
  661. #define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48
  662. mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  663. if (IS_ERR(mailbox))
  664. return PTR_ERR(mailbox);
  665. outbox = mailbox->buf;
  666. err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_FW,
  667. CMD_TIME_CLASS_A, status);
  668. if (err)
  669. goto out;
  670. MTHCA_GET(dev->fw_ver, outbox, QUERY_FW_VER_OFFSET);
  671. /*
  672. * FW subminor version is at more signifant bits than minor
  673. * version, so swap here.
  674. */
  675. dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) |
  676. ((dev->fw_ver & 0xffff0000ull) >> 16) |
  677. ((dev->fw_ver & 0x0000ffffull) << 16);
  678. mthca_dbg(dev, "FW version %012llx, max commands %d\n",
  679. (unsigned long long) dev->fw_ver, dev->cmd.max_cmds);
  680. MTHCA_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
  681. dev->cmd.max_cmds = 1 << lg;
  682. MTHCA_GET(dev->catas_err.addr, outbox, QUERY_FW_ERR_START_OFFSET);
  683. MTHCA_GET(dev->catas_err.size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
  684. mthca_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x\n",
  685. (unsigned long long) dev->catas_err.addr, dev->catas_err.size);
  686. MTHCA_GET(tmp, outbox, QUERY_FW_CMD_DB_EN_OFFSET);
  687. if (tmp & 0x1) {
  688. mthca_dbg(dev, "FW supports commands through doorbells\n");
  689. MTHCA_GET(base, outbox, QUERY_FW_CMD_DB_BASE);
  690. for (i = 0; i < MTHCA_CMD_NUM_DBELL_DWORDS; ++i)
  691. MTHCA_GET(dev->cmd.dbell_offsets[i], outbox,
  692. QUERY_FW_CMD_DB_OFFSET + (i << 1));
  693. mthca_setup_cmd_doorbells(dev, base);
  694. }
  695. if (mthca_is_memfree(dev)) {
  696. MTHCA_GET(dev->fw.arbel.fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
  697. MTHCA_GET(dev->fw.arbel.clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
  698. MTHCA_GET(dev->fw.arbel.eq_arm_base, outbox, QUERY_FW_EQ_ARM_BASE_OFFSET);
  699. MTHCA_GET(dev->fw.arbel.eq_set_ci_base, outbox, QUERY_FW_EQ_SET_CI_BASE_OFFSET);
  700. mthca_dbg(dev, "FW size %d KB\n", dev->fw.arbel.fw_pages << 2);
  701. /*
  702. * Round up number of system pages needed in case
  703. * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
  704. */
  705. dev->fw.arbel.fw_pages =
  706. ALIGN(dev->fw.arbel.fw_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >>
  707. (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT);
  708. mthca_dbg(dev, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n",
  709. (unsigned long long) dev->fw.arbel.clr_int_base,
  710. (unsigned long long) dev->fw.arbel.eq_arm_base,
  711. (unsigned long long) dev->fw.arbel.eq_set_ci_base);
  712. } else {
  713. MTHCA_GET(dev->fw.tavor.fw_start, outbox, QUERY_FW_START_OFFSET);
  714. MTHCA_GET(dev->fw.tavor.fw_end, outbox, QUERY_FW_END_OFFSET);
  715. mthca_dbg(dev, "FW size %d KB (start %llx, end %llx)\n",
  716. (int) ((dev->fw.tavor.fw_end - dev->fw.tavor.fw_start) >> 10),
  717. (unsigned long long) dev->fw.tavor.fw_start,
  718. (unsigned long long) dev->fw.tavor.fw_end);
  719. }
  720. out:
  721. mthca_free_mailbox(dev, mailbox);
  722. return err;
  723. }
  724. int mthca_ENABLE_LAM(struct mthca_dev *dev, u8 *status)
  725. {
  726. struct mthca_mailbox *mailbox;
  727. u8 info;
  728. u32 *outbox;
  729. int err = 0;
  730. #define ENABLE_LAM_OUT_SIZE 0x100
  731. #define ENABLE_LAM_START_OFFSET 0x00
  732. #define ENABLE_LAM_END_OFFSET 0x08
  733. #define ENABLE_LAM_INFO_OFFSET 0x13
  734. #define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4)
  735. #define ENABLE_LAM_INFO_ECC_MASK 0x3
  736. mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  737. if (IS_ERR(mailbox))
  738. return PTR_ERR(mailbox);
  739. outbox = mailbox->buf;
  740. err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_ENABLE_LAM,
  741. CMD_TIME_CLASS_C, status);
  742. if (err)
  743. goto out;
  744. if (*status == MTHCA_CMD_STAT_LAM_NOT_PRE)
  745. goto out;
  746. MTHCA_GET(dev->ddr_start, outbox, ENABLE_LAM_START_OFFSET);
  747. MTHCA_GET(dev->ddr_end, outbox, ENABLE_LAM_END_OFFSET);
  748. MTHCA_GET(info, outbox, ENABLE_LAM_INFO_OFFSET);
  749. if (!!(info & ENABLE_LAM_INFO_HIDDEN_FLAG) !=
  750. !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
  751. mthca_info(dev, "FW reports that HCA-attached memory "
  752. "is %s hidden; does not match PCI config\n",
  753. (info & ENABLE_LAM_INFO_HIDDEN_FLAG) ?
  754. "" : "not");
  755. }
  756. if (info & ENABLE_LAM_INFO_HIDDEN_FLAG)
  757. mthca_dbg(dev, "HCA-attached memory is hidden.\n");
  758. mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
  759. (int) ((dev->ddr_end - dev->ddr_start) >> 10),
  760. (unsigned long long) dev->ddr_start,
  761. (unsigned long long) dev->ddr_end);
  762. out:
  763. mthca_free_mailbox(dev, mailbox);
  764. return err;
  765. }
  766. int mthca_DISABLE_LAM(struct mthca_dev *dev, u8 *status)
  767. {
  768. return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status);
  769. }
  770. int mthca_QUERY_DDR(struct mthca_dev *dev, u8 *status)
  771. {
  772. struct mthca_mailbox *mailbox;
  773. u8 info;
  774. u32 *outbox;
  775. int err = 0;
  776. #define QUERY_DDR_OUT_SIZE 0x100
  777. #define QUERY_DDR_START_OFFSET 0x00
  778. #define QUERY_DDR_END_OFFSET 0x08
  779. #define QUERY_DDR_INFO_OFFSET 0x13
  780. #define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4)
  781. #define QUERY_DDR_INFO_ECC_MASK 0x3
  782. mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  783. if (IS_ERR(mailbox))
  784. return PTR_ERR(mailbox);
  785. outbox = mailbox->buf;
  786. err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DDR,
  787. CMD_TIME_CLASS_A, status);
  788. if (err)
  789. goto out;
  790. MTHCA_GET(dev->ddr_start, outbox, QUERY_DDR_START_OFFSET);
  791. MTHCA_GET(dev->ddr_end, outbox, QUERY_DDR_END_OFFSET);
  792. MTHCA_GET(info, outbox, QUERY_DDR_INFO_OFFSET);
  793. if (!!(info & QUERY_DDR_INFO_HIDDEN_FLAG) !=
  794. !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) {
  795. mthca_info(dev, "FW reports that HCA-attached memory "
  796. "is %s hidden; does not match PCI config\n",
  797. (info & QUERY_DDR_INFO_HIDDEN_FLAG) ?
  798. "" : "not");
  799. }
  800. if (info & QUERY_DDR_INFO_HIDDEN_FLAG)
  801. mthca_dbg(dev, "HCA-attached memory is hidden.\n");
  802. mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n",
  803. (int) ((dev->ddr_end - dev->ddr_start) >> 10),
  804. (unsigned long long) dev->ddr_start,
  805. (unsigned long long) dev->ddr_end);
  806. out:
  807. mthca_free_mailbox(dev, mailbox);
  808. return err;
  809. }
  810. int mthca_QUERY_DEV_LIM(struct mthca_dev *dev,
  811. struct mthca_dev_lim *dev_lim, u8 *status)
  812. {
  813. struct mthca_mailbox *mailbox;
  814. u32 *outbox;
  815. u8 field;
  816. u16 size;
  817. int err;
  818. #define QUERY_DEV_LIM_OUT_SIZE 0x100
  819. #define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET 0x10
  820. #define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET 0x11
  821. #define QUERY_DEV_LIM_RSVD_QP_OFFSET 0x12
  822. #define QUERY_DEV_LIM_MAX_QP_OFFSET 0x13
  823. #define QUERY_DEV_LIM_RSVD_SRQ_OFFSET 0x14
  824. #define QUERY_DEV_LIM_MAX_SRQ_OFFSET 0x15
  825. #define QUERY_DEV_LIM_RSVD_EEC_OFFSET 0x16
  826. #define QUERY_DEV_LIM_MAX_EEC_OFFSET 0x17
  827. #define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET 0x19
  828. #define QUERY_DEV_LIM_RSVD_CQ_OFFSET 0x1a
  829. #define QUERY_DEV_LIM_MAX_CQ_OFFSET 0x1b
  830. #define QUERY_DEV_LIM_MAX_MPT_OFFSET 0x1d
  831. #define QUERY_DEV_LIM_RSVD_EQ_OFFSET 0x1e
  832. #define QUERY_DEV_LIM_MAX_EQ_OFFSET 0x1f
  833. #define QUERY_DEV_LIM_RSVD_MTT_OFFSET 0x20
  834. #define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET 0x21
  835. #define QUERY_DEV_LIM_RSVD_MRW_OFFSET 0x22
  836. #define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET 0x23
  837. #define QUERY_DEV_LIM_MAX_AV_OFFSET 0x27
  838. #define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET 0x29
  839. #define QUERY_DEV_LIM_MAX_RES_QP_OFFSET 0x2b
  840. #define QUERY_DEV_LIM_MAX_RDMA_OFFSET 0x2f
  841. #define QUERY_DEV_LIM_RSZ_SRQ_OFFSET 0x33
  842. #define QUERY_DEV_LIM_ACK_DELAY_OFFSET 0x35
  843. #define QUERY_DEV_LIM_MTU_WIDTH_OFFSET 0x36
  844. #define QUERY_DEV_LIM_VL_PORT_OFFSET 0x37
  845. #define QUERY_DEV_LIM_MAX_GID_OFFSET 0x3b
  846. #define QUERY_DEV_LIM_MAX_PKEY_OFFSET 0x3f
  847. #define QUERY_DEV_LIM_FLAGS_OFFSET 0x44
  848. #define QUERY_DEV_LIM_RSVD_UAR_OFFSET 0x48
  849. #define QUERY_DEV_LIM_UAR_SZ_OFFSET 0x49
  850. #define QUERY_DEV_LIM_PAGE_SZ_OFFSET 0x4b
  851. #define QUERY_DEV_LIM_MAX_SG_OFFSET 0x51
  852. #define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET 0x52
  853. #define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET 0x55
  854. #define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56
  855. #define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET 0x61
  856. #define QUERY_DEV_LIM_RSVD_MCG_OFFSET 0x62
  857. #define QUERY_DEV_LIM_MAX_MCG_OFFSET 0x63
  858. #define QUERY_DEV_LIM_RSVD_PD_OFFSET 0x64
  859. #define QUERY_DEV_LIM_MAX_PD_OFFSET 0x65
  860. #define QUERY_DEV_LIM_RSVD_RDD_OFFSET 0x66
  861. #define QUERY_DEV_LIM_MAX_RDD_OFFSET 0x67
  862. #define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET 0x80
  863. #define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET 0x82
  864. #define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET 0x84
  865. #define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET 0x86
  866. #define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET 0x88
  867. #define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET 0x8a
  868. #define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET 0x8c
  869. #define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET 0x8e
  870. #define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET 0x90
  871. #define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET 0x92
  872. #define QUERY_DEV_LIM_PBL_SZ_OFFSET 0x96
  873. #define QUERY_DEV_LIM_BMME_FLAGS_OFFSET 0x97
  874. #define QUERY_DEV_LIM_RSVD_LKEY_OFFSET 0x98
  875. #define QUERY_DEV_LIM_LAMR_OFFSET 0x9f
  876. #define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET 0xa0
  877. mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  878. if (IS_ERR(mailbox))
  879. return PTR_ERR(mailbox);
  880. outbox = mailbox->buf;
  881. err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM,
  882. CMD_TIME_CLASS_A, status);
  883. if (err)
  884. goto out;
  885. MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET);
  886. dev_lim->reserved_qps = 1 << (field & 0xf);
  887. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET);
  888. dev_lim->max_qps = 1 << (field & 0x1f);
  889. MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET);
  890. dev_lim->reserved_srqs = 1 << (field >> 4);
  891. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET);
  892. dev_lim->max_srqs = 1 << (field & 0x1f);
  893. MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET);
  894. dev_lim->reserved_eecs = 1 << (field & 0xf);
  895. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET);
  896. dev_lim->max_eecs = 1 << (field & 0x1f);
  897. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET);
  898. dev_lim->max_cq_sz = 1 << field;
  899. MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET);
  900. dev_lim->reserved_cqs = 1 << (field & 0xf);
  901. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET);
  902. dev_lim->max_cqs = 1 << (field & 0x1f);
  903. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET);
  904. dev_lim->max_mpts = 1 << (field & 0x3f);
  905. MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET);
  906. dev_lim->reserved_eqs = 1 << (field & 0xf);
  907. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET);
  908. dev_lim->max_eqs = 1 << (field & 0x7);
  909. MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET);
  910. dev_lim->reserved_mtts = 1 << (field >> 4);
  911. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET);
  912. dev_lim->max_mrw_sz = 1 << field;
  913. MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET);
  914. dev_lim->reserved_mrws = 1 << (field & 0xf);
  915. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET);
  916. dev_lim->max_mtt_seg = 1 << (field & 0x3f);
  917. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET);
  918. dev_lim->max_requester_per_qp = 1 << (field & 0x3f);
  919. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET);
  920. dev_lim->max_responder_per_qp = 1 << (field & 0x3f);
  921. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET);
  922. dev_lim->max_rdma_global = 1 << (field & 0x3f);
  923. MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET);
  924. dev_lim->local_ca_ack_delay = field & 0x1f;
  925. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET);
  926. dev_lim->max_mtu = field >> 4;
  927. dev_lim->max_port_width = field & 0xf;
  928. MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET);
  929. dev_lim->max_vl = field >> 4;
  930. dev_lim->num_ports = field & 0xf;
  931. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET);
  932. dev_lim->max_gids = 1 << (field & 0xf);
  933. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET);
  934. dev_lim->max_pkeys = 1 << (field & 0xf);
  935. MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET);
  936. MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET);
  937. dev_lim->reserved_uars = field >> 4;
  938. MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET);
  939. dev_lim->uar_size = 1 << ((field & 0x3f) + 20);
  940. MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET);
  941. dev_lim->min_page_sz = 1 << field;
  942. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET);
  943. dev_lim->max_sg = field;
  944. MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET);
  945. dev_lim->max_desc_sz = size;
  946. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET);
  947. dev_lim->max_qp_per_mcg = 1 << field;
  948. MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET);
  949. dev_lim->reserved_mgms = field & 0xf;
  950. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET);
  951. dev_lim->max_mcgs = 1 << field;
  952. MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET);
  953. dev_lim->reserved_pds = field >> 4;
  954. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET);
  955. dev_lim->max_pds = 1 << (field & 0x3f);
  956. MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET);
  957. dev_lim->reserved_rdds = field >> 4;
  958. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET);
  959. dev_lim->max_rdds = 1 << (field & 0x3f);
  960. MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET);
  961. dev_lim->eec_entry_sz = size;
  962. MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET);
  963. dev_lim->qpc_entry_sz = size;
  964. MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET);
  965. dev_lim->eeec_entry_sz = size;
  966. MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET);
  967. dev_lim->eqpc_entry_sz = size;
  968. MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET);
  969. dev_lim->eqc_entry_sz = size;
  970. MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET);
  971. dev_lim->cqc_entry_sz = size;
  972. MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET);
  973. dev_lim->srq_entry_sz = size;
  974. MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET);
  975. dev_lim->uar_scratch_entry_sz = size;
  976. if (mthca_is_memfree(dev)) {
  977. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
  978. dev_lim->max_srq_sz = 1 << field;
  979. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
  980. dev_lim->max_qp_sz = 1 << field;
  981. MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET);
  982. dev_lim->hca.arbel.resize_srq = field & 1;
  983. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET);
  984. dev_lim->max_sg = min_t(int, field, dev_lim->max_sg);
  985. MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET);
  986. dev_lim->max_desc_sz = min_t(int, size, dev_lim->max_desc_sz);
  987. MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET);
  988. dev_lim->mpt_entry_sz = size;
  989. MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET);
  990. dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f);
  991. MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox,
  992. QUERY_DEV_LIM_BMME_FLAGS_OFFSET);
  993. MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox,
  994. QUERY_DEV_LIM_RSVD_LKEY_OFFSET);
  995. MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET);
  996. dev_lim->hca.arbel.lam_required = field & 1;
  997. MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox,
  998. QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET);
  999. if (dev_lim->hca.arbel.bmme_flags & 1)
  1000. mthca_dbg(dev, "Base MM extensions: yes "
  1001. "(flags %d, max PBL %d, rsvd L_Key %08x)\n",
  1002. dev_lim->hca.arbel.bmme_flags,
  1003. dev_lim->hca.arbel.max_pbl_sz,
  1004. dev_lim->hca.arbel.reserved_lkey);
  1005. else
  1006. mthca_dbg(dev, "Base MM extensions: no\n");
  1007. mthca_dbg(dev, "Max ICM size %lld MB\n",
  1008. (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20);
  1009. } else {
  1010. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET);
  1011. dev_lim->max_srq_sz = (1 << field) - 1;
  1012. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET);
  1013. dev_lim->max_qp_sz = (1 << field) - 1;
  1014. MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET);
  1015. dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f);
  1016. dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE;
  1017. }
  1018. mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
  1019. dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz);
  1020. mthca_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
  1021. dev_lim->max_srqs, dev_lim->reserved_srqs, dev_lim->srq_entry_sz);
  1022. mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
  1023. dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz);
  1024. mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
  1025. dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz);
  1026. mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
  1027. dev_lim->reserved_mrws, dev_lim->reserved_mtts);
  1028. mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
  1029. dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars);
  1030. mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
  1031. dev_lim->max_pds, dev_lim->reserved_mgms);
  1032. mthca_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
  1033. dev_lim->max_cq_sz, dev_lim->max_qp_sz, dev_lim->max_srq_sz);
  1034. mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags);
  1035. out:
  1036. mthca_free_mailbox(dev, mailbox);
  1037. return err;
  1038. }
  1039. static void get_board_id(void *vsd, char *board_id)
  1040. {
  1041. int i;
  1042. #define VSD_OFFSET_SIG1 0x00
  1043. #define VSD_OFFSET_SIG2 0xde
  1044. #define VSD_OFFSET_MLX_BOARD_ID 0xd0
  1045. #define VSD_OFFSET_TS_BOARD_ID 0x20
  1046. #define VSD_SIGNATURE_TOPSPIN 0x5ad
  1047. memset(board_id, 0, MTHCA_BOARD_ID_LEN);
  1048. if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
  1049. be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
  1050. strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MTHCA_BOARD_ID_LEN);
  1051. } else {
  1052. /*
  1053. * The board ID is a string but the firmware byte
  1054. * swaps each 4-byte word before passing it back to
  1055. * us. Therefore we need to swab it before printing.
  1056. */
  1057. for (i = 0; i < 4; ++i)
  1058. ((u32 *) board_id)[i] =
  1059. swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
  1060. }
  1061. }
  1062. int mthca_QUERY_ADAPTER(struct mthca_dev *dev,
  1063. struct mthca_adapter *adapter, u8 *status)
  1064. {
  1065. struct mthca_mailbox *mailbox;
  1066. u32 *outbox;
  1067. int err;
  1068. #define QUERY_ADAPTER_OUT_SIZE 0x100
  1069. #define QUERY_ADAPTER_VENDOR_ID_OFFSET 0x00
  1070. #define QUERY_ADAPTER_DEVICE_ID_OFFSET 0x04
  1071. #define QUERY_ADAPTER_REVISION_ID_OFFSET 0x08
  1072. #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
  1073. #define QUERY_ADAPTER_VSD_OFFSET 0x20
  1074. mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  1075. if (IS_ERR(mailbox))
  1076. return PTR_ERR(mailbox);
  1077. outbox = mailbox->buf;
  1078. err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER,
  1079. CMD_TIME_CLASS_A, status);
  1080. if (err)
  1081. goto out;
  1082. MTHCA_GET(adapter->vendor_id, outbox, QUERY_ADAPTER_VENDOR_ID_OFFSET);
  1083. MTHCA_GET(adapter->device_id, outbox, QUERY_ADAPTER_DEVICE_ID_OFFSET);
  1084. MTHCA_GET(adapter->revision_id, outbox, QUERY_ADAPTER_REVISION_ID_OFFSET);
  1085. MTHCA_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
  1086. get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
  1087. adapter->board_id);
  1088. out:
  1089. mthca_free_mailbox(dev, mailbox);
  1090. return err;
  1091. }
  1092. int mthca_INIT_HCA(struct mthca_dev *dev,
  1093. struct mthca_init_hca_param *param,
  1094. u8 *status)
  1095. {
  1096. struct mthca_mailbox *mailbox;
  1097. __be32 *inbox;
  1098. int err;
  1099. #define INIT_HCA_IN_SIZE 0x200
  1100. #define INIT_HCA_FLAGS1_OFFSET 0x00c
  1101. #define INIT_HCA_FLAGS2_OFFSET 0x014
  1102. #define INIT_HCA_QPC_OFFSET 0x020
  1103. #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
  1104. #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
  1105. #define INIT_HCA_EEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x20)
  1106. #define INIT_HCA_LOG_EEC_OFFSET (INIT_HCA_QPC_OFFSET + 0x27)
  1107. #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
  1108. #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
  1109. #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
  1110. #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
  1111. #define INIT_HCA_EQPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
  1112. #define INIT_HCA_EEEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
  1113. #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
  1114. #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
  1115. #define INIT_HCA_RDB_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
  1116. #define INIT_HCA_UDAV_OFFSET 0x0b0
  1117. #define INIT_HCA_UDAV_LKEY_OFFSET (INIT_HCA_UDAV_OFFSET + 0x0)
  1118. #define INIT_HCA_UDAV_PD_OFFSET (INIT_HCA_UDAV_OFFSET + 0x4)
  1119. #define INIT_HCA_MCAST_OFFSET 0x0c0
  1120. #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
  1121. #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
  1122. #define INIT_HCA_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
  1123. #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
  1124. #define INIT_HCA_TPT_OFFSET 0x0f0
  1125. #define INIT_HCA_MPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
  1126. #define INIT_HCA_MTT_SEG_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x09)
  1127. #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
  1128. #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
  1129. #define INIT_HCA_UAR_OFFSET 0x120
  1130. #define INIT_HCA_UAR_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x00)
  1131. #define INIT_HCA_UARC_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x09)
  1132. #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
  1133. #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
  1134. #define INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10)
  1135. #define INIT_HCA_UAR_CTX_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x18)
  1136. mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  1137. if (IS_ERR(mailbox))
  1138. return PTR_ERR(mailbox);
  1139. inbox = mailbox->buf;
  1140. memset(inbox, 0, INIT_HCA_IN_SIZE);
  1141. if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
  1142. MTHCA_PUT(inbox, 0x1, INIT_HCA_FLAGS1_OFFSET);
  1143. #if defined(__LITTLE_ENDIAN)
  1144. *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
  1145. #elif defined(__BIG_ENDIAN)
  1146. *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1 << 1);
  1147. #else
  1148. #error Host endianness not defined
  1149. #endif
  1150. /* Check port for UD address vector: */
  1151. *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1);
  1152. /* We leave wqe_quota, responder_exu, etc as 0 (default) */
  1153. /* QPC/EEC/CQC/EQC/RDB attributes */
  1154. MTHCA_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
  1155. MTHCA_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
  1156. MTHCA_PUT(inbox, param->eec_base, INIT_HCA_EEC_BASE_OFFSET);
  1157. MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET);
  1158. MTHCA_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
  1159. MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
  1160. MTHCA_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
  1161. MTHCA_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
  1162. MTHCA_PUT(inbox, param->eqpc_base, INIT_HCA_EQPC_BASE_OFFSET);
  1163. MTHCA_PUT(inbox, param->eeec_base, INIT_HCA_EEEC_BASE_OFFSET);
  1164. MTHCA_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
  1165. MTHCA_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
  1166. MTHCA_PUT(inbox, param->rdb_base, INIT_HCA_RDB_BASE_OFFSET);
  1167. /* UD AV attributes */
  1168. /* multicast attributes */
  1169. MTHCA_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
  1170. MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
  1171. MTHCA_PUT(inbox, param->mc_hash_sz, INIT_HCA_MC_HASH_SZ_OFFSET);
  1172. MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
  1173. /* TPT attributes */
  1174. MTHCA_PUT(inbox, param->mpt_base, INIT_HCA_MPT_BASE_OFFSET);
  1175. if (!mthca_is_memfree(dev))
  1176. MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET);
  1177. MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
  1178. MTHCA_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
  1179. /* UAR attributes */
  1180. {
  1181. u8 uar_page_sz = PAGE_SHIFT - 12;
  1182. MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
  1183. }
  1184. MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET);
  1185. if (mthca_is_memfree(dev)) {
  1186. MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET);
  1187. MTHCA_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
  1188. MTHCA_PUT(inbox, param->uarc_base, INIT_HCA_UAR_CTX_BASE_OFFSET);
  1189. }
  1190. err = mthca_cmd(dev, mailbox->dma, 0, 0, CMD_INIT_HCA, HZ, status);
  1191. mthca_free_mailbox(dev, mailbox);
  1192. return err;
  1193. }
  1194. int mthca_INIT_IB(struct mthca_dev *dev,
  1195. struct mthca_init_ib_param *param,
  1196. int port, u8 *status)
  1197. {
  1198. struct mthca_mailbox *mailbox;
  1199. u32 *inbox;
  1200. int err;
  1201. u32 flags;
  1202. #define INIT_IB_IN_SIZE 56
  1203. #define INIT_IB_FLAGS_OFFSET 0x00
  1204. #define INIT_IB_FLAG_SIG (1 << 18)
  1205. #define INIT_IB_FLAG_NG (1 << 17)
  1206. #define INIT_IB_FLAG_G0 (1 << 16)
  1207. #define INIT_IB_VL_SHIFT 4
  1208. #define INIT_IB_PORT_WIDTH_SHIFT 8
  1209. #define INIT_IB_MTU_SHIFT 12
  1210. #define INIT_IB_MAX_GID_OFFSET 0x06
  1211. #define INIT_IB_MAX_PKEY_OFFSET 0x0a
  1212. #define INIT_IB_GUID0_OFFSET 0x10
  1213. #define INIT_IB_NODE_GUID_OFFSET 0x18
  1214. #define INIT_IB_SI_GUID_OFFSET 0x20
  1215. mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  1216. if (IS_ERR(mailbox))
  1217. return PTR_ERR(mailbox);
  1218. inbox = mailbox->buf;
  1219. memset(inbox, 0, INIT_IB_IN_SIZE);
  1220. flags = 0;
  1221. flags |= param->set_guid0 ? INIT_IB_FLAG_G0 : 0;
  1222. flags |= param->set_node_guid ? INIT_IB_FLAG_NG : 0;
  1223. flags |= param->set_si_guid ? INIT_IB_FLAG_SIG : 0;
  1224. flags |= param->vl_cap << INIT_IB_VL_SHIFT;
  1225. flags |= param->port_width << INIT_IB_PORT_WIDTH_SHIFT;
  1226. flags |= param->mtu_cap << INIT_IB_MTU_SHIFT;
  1227. MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET);
  1228. MTHCA_PUT(inbox, param->gid_cap, INIT_IB_MAX_GID_OFFSET);
  1229. MTHCA_PUT(inbox, param->pkey_cap, INIT_IB_MAX_PKEY_OFFSET);
  1230. MTHCA_PUT(inbox, param->guid0, INIT_IB_GUID0_OFFSET);
  1231. MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET);
  1232. MTHCA_PUT(inbox, param->si_guid, INIT_IB_SI_GUID_OFFSET);
  1233. err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB,
  1234. CMD_TIME_CLASS_A, status);
  1235. mthca_free_mailbox(dev, mailbox);
  1236. return err;
  1237. }
  1238. int mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status)
  1239. {
  1240. return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, HZ, status);
  1241. }
  1242. int mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status)
  1243. {
  1244. return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, HZ, status);
  1245. }
  1246. int mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param,
  1247. int port, u8 *status)
  1248. {
  1249. struct mthca_mailbox *mailbox;
  1250. u32 *inbox;
  1251. int err;
  1252. u32 flags = 0;
  1253. #define SET_IB_IN_SIZE 0x40
  1254. #define SET_IB_FLAGS_OFFSET 0x00
  1255. #define SET_IB_FLAG_SIG (1 << 18)
  1256. #define SET_IB_FLAG_RQK (1 << 0)
  1257. #define SET_IB_CAP_MASK_OFFSET 0x04
  1258. #define SET_IB_SI_GUID_OFFSET 0x08
  1259. mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  1260. if (IS_ERR(mailbox))
  1261. return PTR_ERR(mailbox);
  1262. inbox = mailbox->buf;
  1263. memset(inbox, 0, SET_IB_IN_SIZE);
  1264. flags |= param->set_si_guid ? SET_IB_FLAG_SIG : 0;
  1265. flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0;
  1266. MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET);
  1267. MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET);
  1268. MTHCA_PUT(inbox, param->si_guid, SET_IB_SI_GUID_OFFSET);
  1269. err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB,
  1270. CMD_TIME_CLASS_B, status);
  1271. mthca_free_mailbox(dev, mailbox);
  1272. return err;
  1273. }
  1274. int mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt, u8 *status)
  1275. {
  1276. return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt, status);
  1277. }
  1278. int mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt, u8 *status)
  1279. {
  1280. struct mthca_mailbox *mailbox;
  1281. __be64 *inbox;
  1282. int err;
  1283. mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  1284. if (IS_ERR(mailbox))
  1285. return PTR_ERR(mailbox);
  1286. inbox = mailbox->buf;
  1287. inbox[0] = cpu_to_be64(virt);
  1288. inbox[1] = cpu_to_be64(dma_addr);
  1289. err = mthca_cmd(dev, mailbox->dma, 1, 0, CMD_MAP_ICM,
  1290. CMD_TIME_CLASS_B, status);
  1291. mthca_free_mailbox(dev, mailbox);
  1292. if (!err)
  1293. mthca_dbg(dev, "Mapped page at %llx to %llx for ICM.\n",
  1294. (unsigned long long) dma_addr, (unsigned long long) virt);
  1295. return err;
  1296. }
  1297. int mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count, u8 *status)
  1298. {
  1299. mthca_dbg(dev, "Unmapping %d pages at %llx from ICM.\n",
  1300. page_count, (unsigned long long) virt);
  1301. return mthca_cmd(dev, virt, page_count, 0, CMD_UNMAP_ICM, CMD_TIME_CLASS_B, status);
  1302. }
  1303. int mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status)
  1304. {
  1305. return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, -1, status);
  1306. }
  1307. int mthca_UNMAP_ICM_AUX(struct mthca_dev *dev, u8 *status)
  1308. {
  1309. return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B, status);
  1310. }
  1311. int mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages,
  1312. u8 *status)
  1313. {
  1314. int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0, 0, CMD_SET_ICM_SIZE,
  1315. CMD_TIME_CLASS_A, status);
  1316. if (ret || status)
  1317. return ret;
  1318. /*
  1319. * Round up number of system pages needed in case
  1320. * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
  1321. */
  1322. *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >>
  1323. (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT);
  1324. return 0;
  1325. }
  1326. int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
  1327. int mpt_index, u8 *status)
  1328. {
  1329. return mthca_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT,
  1330. CMD_TIME_CLASS_B, status);
  1331. }
  1332. int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
  1333. int mpt_index, u8 *status)
  1334. {
  1335. return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
  1336. !mailbox, CMD_HW2SW_MPT,
  1337. CMD_TIME_CLASS_B, status);
  1338. }
  1339. int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
  1340. int num_mtt, u8 *status)
  1341. {
  1342. return mthca_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT,
  1343. CMD_TIME_CLASS_B, status);
  1344. }
  1345. int mthca_SYNC_TPT(struct mthca_dev *dev, u8 *status)
  1346. {
  1347. return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B, status);
  1348. }
  1349. int mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap,
  1350. int eq_num, u8 *status)
  1351. {
  1352. mthca_dbg(dev, "%s mask %016llx for eqn %d\n",
  1353. unmap ? "Clearing" : "Setting",
  1354. (unsigned long long) event_mask, eq_num);
  1355. return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num,
  1356. 0, CMD_MAP_EQ, CMD_TIME_CLASS_B, status);
  1357. }
  1358. int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
  1359. int eq_num, u8 *status)
  1360. {
  1361. return mthca_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ,
  1362. CMD_TIME_CLASS_A, status);
  1363. }
  1364. int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
  1365. int eq_num, u8 *status)
  1366. {
  1367. return mthca_cmd_box(dev, 0, mailbox->dma, eq_num, 0,
  1368. CMD_HW2SW_EQ,
  1369. CMD_TIME_CLASS_A, status);
  1370. }
  1371. int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
  1372. int cq_num, u8 *status)
  1373. {
  1374. return mthca_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ,
  1375. CMD_TIME_CLASS_A, status);
  1376. }
  1377. int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
  1378. int cq_num, u8 *status)
  1379. {
  1380. return mthca_cmd_box(dev, 0, mailbox->dma, cq_num, 0,
  1381. CMD_HW2SW_CQ,
  1382. CMD_TIME_CLASS_A, status);
  1383. }
  1384. int mthca_RESIZE_CQ(struct mthca_dev *dev, int cq_num, u32 lkey, u8 log_size,
  1385. u8 *status)
  1386. {
  1387. struct mthca_mailbox *mailbox;
  1388. __be32 *inbox;
  1389. int err;
  1390. #define RESIZE_CQ_IN_SIZE 0x40
  1391. #define RESIZE_CQ_LOG_SIZE_OFFSET 0x0c
  1392. #define RESIZE_CQ_LKEY_OFFSET 0x1c
  1393. mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  1394. if (IS_ERR(mailbox))
  1395. return PTR_ERR(mailbox);
  1396. inbox = mailbox->buf;
  1397. memset(inbox, 0, RESIZE_CQ_IN_SIZE);
  1398. /*
  1399. * Leave start address fields zeroed out -- mthca assumes that
  1400. * MRs for CQs always start at virtual address 0.
  1401. */
  1402. MTHCA_PUT(inbox, log_size, RESIZE_CQ_LOG_SIZE_OFFSET);
  1403. MTHCA_PUT(inbox, lkey, RESIZE_CQ_LKEY_OFFSET);
  1404. err = mthca_cmd(dev, mailbox->dma, cq_num, 1, CMD_RESIZE_CQ,
  1405. CMD_TIME_CLASS_B, status);
  1406. mthca_free_mailbox(dev, mailbox);
  1407. return err;
  1408. }
  1409. int mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
  1410. int srq_num, u8 *status)
  1411. {
  1412. return mthca_cmd(dev, mailbox->dma, srq_num, 0, CMD_SW2HW_SRQ,
  1413. CMD_TIME_CLASS_A, status);
  1414. }
  1415. int mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
  1416. int srq_num, u8 *status)
  1417. {
  1418. return mthca_cmd_box(dev, 0, mailbox->dma, srq_num, 0,
  1419. CMD_HW2SW_SRQ,
  1420. CMD_TIME_CLASS_A, status);
  1421. }
  1422. int mthca_QUERY_SRQ(struct mthca_dev *dev, u32 num,
  1423. struct mthca_mailbox *mailbox, u8 *status)
  1424. {
  1425. return mthca_cmd_box(dev, 0, mailbox->dma, num, 0,
  1426. CMD_QUERY_SRQ, CMD_TIME_CLASS_A, status);
  1427. }
  1428. int mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit, u8 *status)
  1429. {
  1430. return mthca_cmd(dev, limit, srq_num, 0, CMD_ARM_SRQ,
  1431. CMD_TIME_CLASS_B, status);
  1432. }
  1433. int mthca_MODIFY_QP(struct mthca_dev *dev, enum ib_qp_state cur,
  1434. enum ib_qp_state next, u32 num, int is_ee,
  1435. struct mthca_mailbox *mailbox, u32 optmask,
  1436. u8 *status)
  1437. {
  1438. static const u16 op[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
  1439. [IB_QPS_RESET] = {
  1440. [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
  1441. [IB_QPS_ERR] = CMD_2ERR_QPEE,
  1442. [IB_QPS_INIT] = CMD_RST2INIT_QPEE,
  1443. },
  1444. [IB_QPS_INIT] = {
  1445. [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
  1446. [IB_QPS_ERR] = CMD_2ERR_QPEE,
  1447. [IB_QPS_INIT] = CMD_INIT2INIT_QPEE,
  1448. [IB_QPS_RTR] = CMD_INIT2RTR_QPEE,
  1449. },
  1450. [IB_QPS_RTR] = {
  1451. [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
  1452. [IB_QPS_ERR] = CMD_2ERR_QPEE,
  1453. [IB_QPS_RTS] = CMD_RTR2RTS_QPEE,
  1454. },
  1455. [IB_QPS_RTS] = {
  1456. [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
  1457. [IB_QPS_ERR] = CMD_2ERR_QPEE,
  1458. [IB_QPS_RTS] = CMD_RTS2RTS_QPEE,
  1459. [IB_QPS_SQD] = CMD_RTS2SQD_QPEE,
  1460. },
  1461. [IB_QPS_SQD] = {
  1462. [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
  1463. [IB_QPS_ERR] = CMD_2ERR_QPEE,
  1464. [IB_QPS_RTS] = CMD_SQD2RTS_QPEE,
  1465. [IB_QPS_SQD] = CMD_SQD2SQD_QPEE,
  1466. },
  1467. [IB_QPS_SQE] = {
  1468. [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
  1469. [IB_QPS_ERR] = CMD_2ERR_QPEE,
  1470. [IB_QPS_RTS] = CMD_SQERR2RTS_QPEE,
  1471. },
  1472. [IB_QPS_ERR] = {
  1473. [IB_QPS_RESET] = CMD_ERR2RST_QPEE,
  1474. [IB_QPS_ERR] = CMD_2ERR_QPEE,
  1475. }
  1476. };
  1477. u8 op_mod = 0;
  1478. int my_mailbox = 0;
  1479. int err;
  1480. if (op[cur][next] == CMD_ERR2RST_QPEE) {
  1481. op_mod = 3; /* don't write outbox, any->reset */
  1482. /* For debugging */
  1483. if (!mailbox) {
  1484. mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  1485. if (!IS_ERR(mailbox)) {
  1486. my_mailbox = 1;
  1487. op_mod = 2; /* write outbox, any->reset */
  1488. } else
  1489. mailbox = NULL;
  1490. }
  1491. err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
  1492. (!!is_ee << 24) | num, op_mod,
  1493. op[cur][next], CMD_TIME_CLASS_C, status);
  1494. if (0 && mailbox) {
  1495. int i;
  1496. mthca_dbg(dev, "Dumping QP context:\n");
  1497. printk(" %08x\n", be32_to_cpup(mailbox->buf));
  1498. for (i = 0; i < 0x100 / 4; ++i) {
  1499. if (i % 8 == 0)
  1500. printk("[%02x] ", i * 4);
  1501. printk(" %08x",
  1502. be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
  1503. if ((i + 1) % 8 == 0)
  1504. printk("\n");
  1505. }
  1506. }
  1507. if (my_mailbox)
  1508. mthca_free_mailbox(dev, mailbox);
  1509. } else {
  1510. if (0) {
  1511. int i;
  1512. mthca_dbg(dev, "Dumping QP context:\n");
  1513. printk(" opt param mask: %08x\n", be32_to_cpup(mailbox->buf));
  1514. for (i = 0; i < 0x100 / 4; ++i) {
  1515. if (i % 8 == 0)
  1516. printk(" [%02x] ", i * 4);
  1517. printk(" %08x",
  1518. be32_to_cpu(((__be32 *) mailbox->buf)[i + 2]));
  1519. if ((i + 1) % 8 == 0)
  1520. printk("\n");
  1521. }
  1522. }
  1523. err = mthca_cmd(dev, mailbox->dma, optmask | (!!is_ee << 24) | num,
  1524. op_mod, op[cur][next], CMD_TIME_CLASS_C, status);
  1525. }
  1526. return err;
  1527. }
  1528. int mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee,
  1529. struct mthca_mailbox *mailbox, u8 *status)
  1530. {
  1531. return mthca_cmd_box(dev, 0, mailbox->dma, (!!is_ee << 24) | num, 0,
  1532. CMD_QUERY_QPEE, CMD_TIME_CLASS_A, status);
  1533. }
  1534. int mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn,
  1535. u8 *status)
  1536. {
  1537. u8 op_mod;
  1538. switch (type) {
  1539. case IB_QPT_SMI:
  1540. op_mod = 0;
  1541. break;
  1542. case IB_QPT_GSI:
  1543. op_mod = 1;
  1544. break;
  1545. case IB_QPT_RAW_IPV6:
  1546. op_mod = 2;
  1547. break;
  1548. case IB_QPT_RAW_ETY:
  1549. op_mod = 3;
  1550. break;
  1551. default:
  1552. return -EINVAL;
  1553. }
  1554. return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP,
  1555. CMD_TIME_CLASS_B, status);
  1556. }
  1557. int mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey,
  1558. int port, struct ib_wc *in_wc, struct ib_grh *in_grh,
  1559. void *in_mad, void *response_mad, u8 *status)
  1560. {
  1561. struct mthca_mailbox *inmailbox, *outmailbox;
  1562. void *inbox;
  1563. int err;
  1564. u32 in_modifier = port;
  1565. u8 op_modifier = 0;
  1566. #define MAD_IFC_BOX_SIZE 0x400
  1567. #define MAD_IFC_MY_QPN_OFFSET 0x100
  1568. #define MAD_IFC_RQPN_OFFSET 0x104
  1569. #define MAD_IFC_SL_OFFSET 0x108
  1570. #define MAD_IFC_G_PATH_OFFSET 0x109
  1571. #define MAD_IFC_RLID_OFFSET 0x10a
  1572. #define MAD_IFC_PKEY_OFFSET 0x10e
  1573. #define MAD_IFC_GRH_OFFSET 0x140
  1574. inmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  1575. if (IS_ERR(inmailbox))
  1576. return PTR_ERR(inmailbox);
  1577. inbox = inmailbox->buf;
  1578. outmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  1579. if (IS_ERR(outmailbox)) {
  1580. mthca_free_mailbox(dev, inmailbox);
  1581. return PTR_ERR(outmailbox);
  1582. }
  1583. memcpy(inbox, in_mad, 256);
  1584. /*
  1585. * Key check traps can't be generated unless we have in_wc to
  1586. * tell us where to send the trap.
  1587. */
  1588. if (ignore_mkey || !in_wc)
  1589. op_modifier |= 0x1;
  1590. if (ignore_bkey || !in_wc)
  1591. op_modifier |= 0x2;
  1592. if (in_wc) {
  1593. u8 val;
  1594. memset(inbox + 256, 0, 256);
  1595. MTHCA_PUT(inbox, in_wc->qp_num, MAD_IFC_MY_QPN_OFFSET);
  1596. MTHCA_PUT(inbox, in_wc->src_qp, MAD_IFC_RQPN_OFFSET);
  1597. val = in_wc->sl << 4;
  1598. MTHCA_PUT(inbox, val, MAD_IFC_SL_OFFSET);
  1599. val = in_wc->dlid_path_bits |
  1600. (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0);
  1601. MTHCA_PUT(inbox, val, MAD_IFC_GRH_OFFSET);
  1602. MTHCA_PUT(inbox, in_wc->slid, MAD_IFC_RLID_OFFSET);
  1603. MTHCA_PUT(inbox, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET);
  1604. if (in_grh)
  1605. memcpy(inbox + MAD_IFC_GRH_OFFSET, in_grh, 40);
  1606. op_modifier |= 0x10;
  1607. in_modifier |= in_wc->slid << 16;
  1608. }
  1609. err = mthca_cmd_box(dev, inmailbox->dma, outmailbox->dma,
  1610. in_modifier, op_modifier,
  1611. CMD_MAD_IFC, CMD_TIME_CLASS_C, status);
  1612. if (!err && !*status)
  1613. memcpy(response_mad, outmailbox->buf, 256);
  1614. mthca_free_mailbox(dev, inmailbox);
  1615. mthca_free_mailbox(dev, outmailbox);
  1616. return err;
  1617. }
  1618. int mthca_READ_MGM(struct mthca_dev *dev, int index,
  1619. struct mthca_mailbox *mailbox, u8 *status)
  1620. {
  1621. return mthca_cmd_box(dev, 0, mailbox->dma, index, 0,
  1622. CMD_READ_MGM, CMD_TIME_CLASS_A, status);
  1623. }
  1624. int mthca_WRITE_MGM(struct mthca_dev *dev, int index,
  1625. struct mthca_mailbox *mailbox, u8 *status)
  1626. {
  1627. return mthca_cmd(dev, mailbox->dma, index, 0, CMD_WRITE_MGM,
  1628. CMD_TIME_CLASS_A, status);
  1629. }
  1630. int mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
  1631. u16 *hash, u8 *status)
  1632. {
  1633. u64 imm;
  1634. int err;
  1635. err = mthca_cmd_imm(dev, mailbox->dma, &imm, 0, 0, CMD_MGID_HASH,
  1636. CMD_TIME_CLASS_A, status);
  1637. *hash = imm;
  1638. return err;
  1639. }
  1640. int mthca_NOP(struct mthca_dev *dev, u8 *status)
  1641. {
  1642. return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100), status);
  1643. }