atl1c_main.c 77 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774
  1. /*
  2. * Copyright(c) 2008 - 2009 Atheros Corporation. All rights reserved.
  3. *
  4. * Derived from Intel e1000 driver
  5. * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation; either version 2 of the License, or (at your option)
  10. * any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc., 59
  19. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20. */
  21. #include "atl1c.h"
  22. #define ATL1C_DRV_VERSION "1.0.1.0-NAPI"
  23. char atl1c_driver_name[] = "atl1c";
  24. char atl1c_driver_version[] = ATL1C_DRV_VERSION;
  25. #define PCI_DEVICE_ID_ATTANSIC_L2C 0x1062
  26. #define PCI_DEVICE_ID_ATTANSIC_L1C 0x1063
  27. #define PCI_DEVICE_ID_ATHEROS_L2C_B 0x2060 /* AR8152 v1.1 Fast 10/100 */
  28. #define PCI_DEVICE_ID_ATHEROS_L2C_B2 0x2062 /* AR8152 v2.0 Fast 10/100 */
  29. #define PCI_DEVICE_ID_ATHEROS_L1D 0x1073 /* AR8151 v1.0 Gigabit 1000 */
  30. #define PCI_DEVICE_ID_ATHEROS_L1D_2_0 0x1083 /* AR8151 v2.0 Gigabit 1000 */
  31. #define L2CB_V10 0xc0
  32. #define L2CB_V11 0xc1
  33. /*
  34. * atl1c_pci_tbl - PCI Device ID Table
  35. *
  36. * Wildcard entries (PCI_ANY_ID) should come last
  37. * Last entry must be all 0s
  38. *
  39. * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  40. * Class, Class Mask, private data (not used) }
  41. */
  42. static DEFINE_PCI_DEVICE_TABLE(atl1c_pci_tbl) = {
  43. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1C)},
  44. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2C)},
  45. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B)},
  46. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L2C_B2)},
  47. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D)},
  48. {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATHEROS_L1D_2_0)},
  49. /* required last entry */
  50. { 0 }
  51. };
  52. MODULE_DEVICE_TABLE(pci, atl1c_pci_tbl);
  53. MODULE_AUTHOR("Jie Yang");
  54. MODULE_AUTHOR("Qualcomm Atheros Inc., <nic-devel@qualcomm.com>");
  55. MODULE_DESCRIPTION("Qualcom Atheros 100/1000M Ethernet Network Driver");
  56. MODULE_LICENSE("GPL");
  57. MODULE_VERSION(ATL1C_DRV_VERSION);
  58. static int atl1c_stop_mac(struct atl1c_hw *hw);
  59. static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw);
  60. static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw);
  61. static void atl1c_disable_l0s_l1(struct atl1c_hw *hw);
  62. static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed);
  63. static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter);
  64. static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter,
  65. int *work_done, int work_to_do);
  66. static int atl1c_up(struct atl1c_adapter *adapter);
  67. static void atl1c_down(struct atl1c_adapter *adapter);
  68. static const u16 atl1c_pay_load_size[] = {
  69. 128, 256, 512, 1024, 2048, 4096,
  70. };
  71. static const u32 atl1c_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
  72. NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
  73. static void atl1c_pcie_patch(struct atl1c_hw *hw)
  74. {
  75. u32 mst_data, data;
  76. /* pclk sel could switch to 25M */
  77. AT_READ_REG(hw, REG_MASTER_CTRL, &mst_data);
  78. mst_data &= ~MASTER_CTRL_CLK_SEL_DIS;
  79. AT_WRITE_REG(hw, REG_MASTER_CTRL, mst_data);
  80. /* WoL/PCIE related settings */
  81. if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c) {
  82. AT_READ_REG(hw, REG_PCIE_PHYMISC, &data);
  83. data |= PCIE_PHYMISC_FORCE_RCV_DET;
  84. AT_WRITE_REG(hw, REG_PCIE_PHYMISC, data);
  85. } else { /* new dev set bit5 of MASTER */
  86. if (!(mst_data & MASTER_CTRL_WAKEN_25M))
  87. AT_WRITE_REG(hw, REG_MASTER_CTRL,
  88. mst_data | MASTER_CTRL_WAKEN_25M);
  89. }
  90. /* aspm/PCIE setting only for l2cb 1.0 */
  91. if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V10) {
  92. AT_READ_REG(hw, REG_PCIE_PHYMISC2, &data);
  93. data = FIELD_SETX(data, PCIE_PHYMISC2_CDR_BW,
  94. L2CB1_PCIE_PHYMISC2_CDR_BW);
  95. data = FIELD_SETX(data, PCIE_PHYMISC2_L0S_TH,
  96. L2CB1_PCIE_PHYMISC2_L0S_TH);
  97. AT_WRITE_REG(hw, REG_PCIE_PHYMISC2, data);
  98. /* extend L1 sync timer */
  99. AT_READ_REG(hw, REG_LINK_CTRL, &data);
  100. data |= LINK_CTRL_EXT_SYNC;
  101. AT_WRITE_REG(hw, REG_LINK_CTRL, data);
  102. }
  103. /* l2cb 1.x & l1d 1.x */
  104. if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d) {
  105. AT_READ_REG(hw, REG_PM_CTRL, &data);
  106. data |= PM_CTRL_L0S_BUFSRX_EN;
  107. AT_WRITE_REG(hw, REG_PM_CTRL, data);
  108. /* clear vendor msg */
  109. AT_READ_REG(hw, REG_DMA_DBG, &data);
  110. AT_WRITE_REG(hw, REG_DMA_DBG, data & ~DMA_DBG_VENDOR_MSG);
  111. }
  112. }
  113. /* FIXME: no need any more ? */
  114. /*
  115. * atl1c_init_pcie - init PCIE module
  116. */
  117. static void atl1c_reset_pcie(struct atl1c_hw *hw, u32 flag)
  118. {
  119. u32 data;
  120. u32 pci_cmd;
  121. struct pci_dev *pdev = hw->adapter->pdev;
  122. int pos;
  123. AT_READ_REG(hw, PCI_COMMAND, &pci_cmd);
  124. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  125. pci_cmd |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
  126. PCI_COMMAND_IO);
  127. AT_WRITE_REG(hw, PCI_COMMAND, pci_cmd);
  128. /*
  129. * Clear any PowerSaveing Settings
  130. */
  131. pci_enable_wake(pdev, PCI_D3hot, 0);
  132. pci_enable_wake(pdev, PCI_D3cold, 0);
  133. /*
  134. * Mask some pcie error bits
  135. */
  136. pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
  137. pci_read_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, &data);
  138. data &= ~(PCI_ERR_UNC_DLP | PCI_ERR_UNC_FCP);
  139. pci_write_config_dword(pdev, pos + PCI_ERR_UNCOR_SEVER, data);
  140. /* clear error status */
  141. pci_write_config_word(pdev, pci_pcie_cap(pdev) + PCI_EXP_DEVSTA,
  142. PCI_EXP_DEVSTA_NFED |
  143. PCI_EXP_DEVSTA_FED |
  144. PCI_EXP_DEVSTA_CED |
  145. PCI_EXP_DEVSTA_URD);
  146. AT_READ_REG(hw, REG_LTSSM_ID_CTRL, &data);
  147. data &= ~LTSSM_ID_EN_WRO;
  148. AT_WRITE_REG(hw, REG_LTSSM_ID_CTRL, data);
  149. atl1c_pcie_patch(hw);
  150. if (flag & ATL1C_PCIE_L0S_L1_DISABLE)
  151. atl1c_disable_l0s_l1(hw);
  152. msleep(5);
  153. }
  154. /*
  155. * atl1c_irq_enable - Enable default interrupt generation settings
  156. * @adapter: board private structure
  157. */
  158. static inline void atl1c_irq_enable(struct atl1c_adapter *adapter)
  159. {
  160. if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
  161. AT_WRITE_REG(&adapter->hw, REG_ISR, 0x7FFFFFFF);
  162. AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
  163. AT_WRITE_FLUSH(&adapter->hw);
  164. }
  165. }
  166. /*
  167. * atl1c_irq_disable - Mask off interrupt generation on the NIC
  168. * @adapter: board private structure
  169. */
  170. static inline void atl1c_irq_disable(struct atl1c_adapter *adapter)
  171. {
  172. atomic_inc(&adapter->irq_sem);
  173. AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
  174. AT_WRITE_REG(&adapter->hw, REG_ISR, ISR_DIS_INT);
  175. AT_WRITE_FLUSH(&adapter->hw);
  176. synchronize_irq(adapter->pdev->irq);
  177. }
  178. /*
  179. * atl1c_irq_reset - reset interrupt confiure on the NIC
  180. * @adapter: board private structure
  181. */
  182. static inline void atl1c_irq_reset(struct atl1c_adapter *adapter)
  183. {
  184. atomic_set(&adapter->irq_sem, 1);
  185. atl1c_irq_enable(adapter);
  186. }
  187. /*
  188. * atl1c_wait_until_idle - wait up to AT_HW_MAX_IDLE_DELAY reads
  189. * of the idle status register until the device is actually idle
  190. */
  191. static u32 atl1c_wait_until_idle(struct atl1c_hw *hw, u32 modu_ctrl)
  192. {
  193. int timeout;
  194. u32 data;
  195. for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
  196. AT_READ_REG(hw, REG_IDLE_STATUS, &data);
  197. if ((data & modu_ctrl) == 0)
  198. return 0;
  199. msleep(1);
  200. }
  201. return data;
  202. }
  203. /*
  204. * atl1c_phy_config - Timer Call-back
  205. * @data: pointer to netdev cast into an unsigned long
  206. */
  207. static void atl1c_phy_config(unsigned long data)
  208. {
  209. struct atl1c_adapter *adapter = (struct atl1c_adapter *) data;
  210. struct atl1c_hw *hw = &adapter->hw;
  211. unsigned long flags;
  212. spin_lock_irqsave(&adapter->mdio_lock, flags);
  213. atl1c_restart_autoneg(hw);
  214. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  215. }
  216. void atl1c_reinit_locked(struct atl1c_adapter *adapter)
  217. {
  218. WARN_ON(in_interrupt());
  219. atl1c_down(adapter);
  220. atl1c_up(adapter);
  221. clear_bit(__AT_RESETTING, &adapter->flags);
  222. }
  223. static void atl1c_check_link_status(struct atl1c_adapter *adapter)
  224. {
  225. struct atl1c_hw *hw = &adapter->hw;
  226. struct net_device *netdev = adapter->netdev;
  227. struct pci_dev *pdev = adapter->pdev;
  228. int err;
  229. unsigned long flags;
  230. u16 speed, duplex, phy_data;
  231. spin_lock_irqsave(&adapter->mdio_lock, flags);
  232. /* MII_BMSR must read twise */
  233. atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
  234. atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
  235. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  236. if ((phy_data & BMSR_LSTATUS) == 0) {
  237. /* link down */
  238. hw->hibernate = true;
  239. if (atl1c_stop_mac(hw) != 0)
  240. if (netif_msg_hw(adapter))
  241. dev_warn(&pdev->dev, "stop mac failed\n");
  242. atl1c_set_aspm(hw, SPEED_0);
  243. netif_carrier_off(netdev);
  244. netif_stop_queue(netdev);
  245. } else {
  246. /* Link Up */
  247. hw->hibernate = false;
  248. spin_lock_irqsave(&adapter->mdio_lock, flags);
  249. err = atl1c_get_speed_and_duplex(hw, &speed, &duplex);
  250. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  251. if (unlikely(err))
  252. return;
  253. /* link result is our setting */
  254. if (adapter->link_speed != speed ||
  255. adapter->link_duplex != duplex) {
  256. adapter->link_speed = speed;
  257. adapter->link_duplex = duplex;
  258. atl1c_set_aspm(hw, speed);
  259. atl1c_enable_tx_ctrl(hw);
  260. atl1c_enable_rx_ctrl(hw);
  261. atl1c_setup_mac_ctrl(adapter);
  262. if (netif_msg_link(adapter))
  263. dev_info(&pdev->dev,
  264. "%s: %s NIC Link is Up<%d Mbps %s>\n",
  265. atl1c_driver_name, netdev->name,
  266. adapter->link_speed,
  267. adapter->link_duplex == FULL_DUPLEX ?
  268. "Full Duplex" : "Half Duplex");
  269. }
  270. if (!netif_carrier_ok(netdev))
  271. netif_carrier_on(netdev);
  272. }
  273. }
  274. static void atl1c_link_chg_event(struct atl1c_adapter *adapter)
  275. {
  276. struct net_device *netdev = adapter->netdev;
  277. struct pci_dev *pdev = adapter->pdev;
  278. u16 phy_data;
  279. u16 link_up;
  280. spin_lock(&adapter->mdio_lock);
  281. atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
  282. atl1c_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
  283. spin_unlock(&adapter->mdio_lock);
  284. link_up = phy_data & BMSR_LSTATUS;
  285. /* notify upper layer link down ASAP */
  286. if (!link_up) {
  287. if (netif_carrier_ok(netdev)) {
  288. /* old link state: Up */
  289. netif_carrier_off(netdev);
  290. if (netif_msg_link(adapter))
  291. dev_info(&pdev->dev,
  292. "%s: %s NIC Link is Down\n",
  293. atl1c_driver_name, netdev->name);
  294. adapter->link_speed = SPEED_0;
  295. }
  296. }
  297. set_bit(ATL1C_WORK_EVENT_LINK_CHANGE, &adapter->work_event);
  298. schedule_work(&adapter->common_task);
  299. }
  300. static void atl1c_common_task(struct work_struct *work)
  301. {
  302. struct atl1c_adapter *adapter;
  303. struct net_device *netdev;
  304. adapter = container_of(work, struct atl1c_adapter, common_task);
  305. netdev = adapter->netdev;
  306. if (test_and_clear_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event)) {
  307. netif_device_detach(netdev);
  308. atl1c_down(adapter);
  309. atl1c_up(adapter);
  310. netif_device_attach(netdev);
  311. }
  312. if (test_and_clear_bit(ATL1C_WORK_EVENT_LINK_CHANGE,
  313. &adapter->work_event))
  314. atl1c_check_link_status(adapter);
  315. }
  316. static void atl1c_del_timer(struct atl1c_adapter *adapter)
  317. {
  318. del_timer_sync(&adapter->phy_config_timer);
  319. }
  320. /*
  321. * atl1c_tx_timeout - Respond to a Tx Hang
  322. * @netdev: network interface device structure
  323. */
  324. static void atl1c_tx_timeout(struct net_device *netdev)
  325. {
  326. struct atl1c_adapter *adapter = netdev_priv(netdev);
  327. /* Do the reset outside of interrupt context */
  328. set_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event);
  329. schedule_work(&adapter->common_task);
  330. }
  331. /*
  332. * atl1c_set_multi - Multicast and Promiscuous mode set
  333. * @netdev: network interface device structure
  334. *
  335. * The set_multi entry point is called whenever the multicast address
  336. * list or the network interface flags are updated. This routine is
  337. * responsible for configuring the hardware for proper multicast,
  338. * promiscuous mode, and all-multi behavior.
  339. */
  340. static void atl1c_set_multi(struct net_device *netdev)
  341. {
  342. struct atl1c_adapter *adapter = netdev_priv(netdev);
  343. struct atl1c_hw *hw = &adapter->hw;
  344. struct netdev_hw_addr *ha;
  345. u32 mac_ctrl_data;
  346. u32 hash_value;
  347. /* Check for Promiscuous and All Multicast modes */
  348. AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
  349. if (netdev->flags & IFF_PROMISC) {
  350. mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
  351. } else if (netdev->flags & IFF_ALLMULTI) {
  352. mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
  353. mac_ctrl_data &= ~MAC_CTRL_PROMIS_EN;
  354. } else {
  355. mac_ctrl_data &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
  356. }
  357. AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
  358. /* clear the old settings from the multicast hash table */
  359. AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
  360. AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
  361. /* comoute mc addresses' hash value ,and put it into hash table */
  362. netdev_for_each_mc_addr(ha, netdev) {
  363. hash_value = atl1c_hash_mc_addr(hw, ha->addr);
  364. atl1c_hash_set(hw, hash_value);
  365. }
  366. }
  367. static void __atl1c_vlan_mode(netdev_features_t features, u32 *mac_ctrl_data)
  368. {
  369. if (features & NETIF_F_HW_VLAN_RX) {
  370. /* enable VLAN tag insert/strip */
  371. *mac_ctrl_data |= MAC_CTRL_RMV_VLAN;
  372. } else {
  373. /* disable VLAN tag insert/strip */
  374. *mac_ctrl_data &= ~MAC_CTRL_RMV_VLAN;
  375. }
  376. }
  377. static void atl1c_vlan_mode(struct net_device *netdev,
  378. netdev_features_t features)
  379. {
  380. struct atl1c_adapter *adapter = netdev_priv(netdev);
  381. struct pci_dev *pdev = adapter->pdev;
  382. u32 mac_ctrl_data = 0;
  383. if (netif_msg_pktdata(adapter))
  384. dev_dbg(&pdev->dev, "atl1c_vlan_mode\n");
  385. atl1c_irq_disable(adapter);
  386. AT_READ_REG(&adapter->hw, REG_MAC_CTRL, &mac_ctrl_data);
  387. __atl1c_vlan_mode(features, &mac_ctrl_data);
  388. AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
  389. atl1c_irq_enable(adapter);
  390. }
  391. static void atl1c_restore_vlan(struct atl1c_adapter *adapter)
  392. {
  393. struct pci_dev *pdev = adapter->pdev;
  394. if (netif_msg_pktdata(adapter))
  395. dev_dbg(&pdev->dev, "atl1c_restore_vlan\n");
  396. atl1c_vlan_mode(adapter->netdev, adapter->netdev->features);
  397. }
  398. /*
  399. * atl1c_set_mac - Change the Ethernet Address of the NIC
  400. * @netdev: network interface device structure
  401. * @p: pointer to an address structure
  402. *
  403. * Returns 0 on success, negative on failure
  404. */
  405. static int atl1c_set_mac_addr(struct net_device *netdev, void *p)
  406. {
  407. struct atl1c_adapter *adapter = netdev_priv(netdev);
  408. struct sockaddr *addr = p;
  409. if (!is_valid_ether_addr(addr->sa_data))
  410. return -EADDRNOTAVAIL;
  411. if (netif_running(netdev))
  412. return -EBUSY;
  413. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  414. memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
  415. netdev->addr_assign_type &= ~NET_ADDR_RANDOM;
  416. atl1c_hw_set_mac_addr(&adapter->hw);
  417. return 0;
  418. }
  419. static void atl1c_set_rxbufsize(struct atl1c_adapter *adapter,
  420. struct net_device *dev)
  421. {
  422. int mtu = dev->mtu;
  423. adapter->rx_buffer_len = mtu > AT_RX_BUF_SIZE ?
  424. roundup(mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN, 8) : AT_RX_BUF_SIZE;
  425. }
  426. static netdev_features_t atl1c_fix_features(struct net_device *netdev,
  427. netdev_features_t features)
  428. {
  429. /*
  430. * Since there is no support for separate rx/tx vlan accel
  431. * enable/disable make sure tx flag is always in same state as rx.
  432. */
  433. if (features & NETIF_F_HW_VLAN_RX)
  434. features |= NETIF_F_HW_VLAN_TX;
  435. else
  436. features &= ~NETIF_F_HW_VLAN_TX;
  437. if (netdev->mtu > MAX_TSO_FRAME_SIZE)
  438. features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
  439. return features;
  440. }
  441. static int atl1c_set_features(struct net_device *netdev,
  442. netdev_features_t features)
  443. {
  444. netdev_features_t changed = netdev->features ^ features;
  445. if (changed & NETIF_F_HW_VLAN_RX)
  446. atl1c_vlan_mode(netdev, features);
  447. return 0;
  448. }
  449. /*
  450. * atl1c_change_mtu - Change the Maximum Transfer Unit
  451. * @netdev: network interface device structure
  452. * @new_mtu: new value for maximum frame size
  453. *
  454. * Returns 0 on success, negative on failure
  455. */
  456. static int atl1c_change_mtu(struct net_device *netdev, int new_mtu)
  457. {
  458. struct atl1c_adapter *adapter = netdev_priv(netdev);
  459. struct atl1c_hw *hw = &adapter->hw;
  460. int old_mtu = netdev->mtu;
  461. int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
  462. /* Fast Ethernet controller doesn't support jumbo packet */
  463. if (((hw->nic_type == athr_l2c ||
  464. hw->nic_type == athr_l2c_b ||
  465. hw->nic_type == athr_l2c_b2) && new_mtu > ETH_DATA_LEN) ||
  466. max_frame < ETH_ZLEN + ETH_FCS_LEN ||
  467. max_frame > MAX_JUMBO_FRAME_SIZE) {
  468. if (netif_msg_link(adapter))
  469. dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
  470. return -EINVAL;
  471. }
  472. /* set MTU */
  473. if (old_mtu != new_mtu && netif_running(netdev)) {
  474. while (test_and_set_bit(__AT_RESETTING, &adapter->flags))
  475. msleep(1);
  476. netdev->mtu = new_mtu;
  477. adapter->hw.max_frame_size = new_mtu;
  478. atl1c_set_rxbufsize(adapter, netdev);
  479. atl1c_down(adapter);
  480. netdev_update_features(netdev);
  481. atl1c_up(adapter);
  482. clear_bit(__AT_RESETTING, &adapter->flags);
  483. if (adapter->hw.ctrl_flags & ATL1C_FPGA_VERSION) {
  484. u32 phy_data;
  485. AT_READ_REG(&adapter->hw, 0x1414, &phy_data);
  486. phy_data |= 0x10000000;
  487. AT_WRITE_REG(&adapter->hw, 0x1414, phy_data);
  488. }
  489. }
  490. return 0;
  491. }
  492. /*
  493. * caller should hold mdio_lock
  494. */
  495. static int atl1c_mdio_read(struct net_device *netdev, int phy_id, int reg_num)
  496. {
  497. struct atl1c_adapter *adapter = netdev_priv(netdev);
  498. u16 result;
  499. atl1c_read_phy_reg(&adapter->hw, reg_num, &result);
  500. return result;
  501. }
  502. static void atl1c_mdio_write(struct net_device *netdev, int phy_id,
  503. int reg_num, int val)
  504. {
  505. struct atl1c_adapter *adapter = netdev_priv(netdev);
  506. atl1c_write_phy_reg(&adapter->hw, reg_num, val);
  507. }
  508. /*
  509. * atl1c_mii_ioctl -
  510. * @netdev:
  511. * @ifreq:
  512. * @cmd:
  513. */
  514. static int atl1c_mii_ioctl(struct net_device *netdev,
  515. struct ifreq *ifr, int cmd)
  516. {
  517. struct atl1c_adapter *adapter = netdev_priv(netdev);
  518. struct pci_dev *pdev = adapter->pdev;
  519. struct mii_ioctl_data *data = if_mii(ifr);
  520. unsigned long flags;
  521. int retval = 0;
  522. if (!netif_running(netdev))
  523. return -EINVAL;
  524. spin_lock_irqsave(&adapter->mdio_lock, flags);
  525. switch (cmd) {
  526. case SIOCGMIIPHY:
  527. data->phy_id = 0;
  528. break;
  529. case SIOCGMIIREG:
  530. if (atl1c_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
  531. &data->val_out)) {
  532. retval = -EIO;
  533. goto out;
  534. }
  535. break;
  536. case SIOCSMIIREG:
  537. if (data->reg_num & ~(0x1F)) {
  538. retval = -EFAULT;
  539. goto out;
  540. }
  541. dev_dbg(&pdev->dev, "<atl1c_mii_ioctl> write %x %x",
  542. data->reg_num, data->val_in);
  543. if (atl1c_write_phy_reg(&adapter->hw,
  544. data->reg_num, data->val_in)) {
  545. retval = -EIO;
  546. goto out;
  547. }
  548. break;
  549. default:
  550. retval = -EOPNOTSUPP;
  551. break;
  552. }
  553. out:
  554. spin_unlock_irqrestore(&adapter->mdio_lock, flags);
  555. return retval;
  556. }
  557. /*
  558. * atl1c_ioctl -
  559. * @netdev:
  560. * @ifreq:
  561. * @cmd:
  562. */
  563. static int atl1c_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
  564. {
  565. switch (cmd) {
  566. case SIOCGMIIPHY:
  567. case SIOCGMIIREG:
  568. case SIOCSMIIREG:
  569. return atl1c_mii_ioctl(netdev, ifr, cmd);
  570. default:
  571. return -EOPNOTSUPP;
  572. }
  573. }
  574. /*
  575. * atl1c_alloc_queues - Allocate memory for all rings
  576. * @adapter: board private structure to initialize
  577. *
  578. */
  579. static int __devinit atl1c_alloc_queues(struct atl1c_adapter *adapter)
  580. {
  581. return 0;
  582. }
  583. static void atl1c_set_mac_type(struct atl1c_hw *hw)
  584. {
  585. switch (hw->device_id) {
  586. case PCI_DEVICE_ID_ATTANSIC_L2C:
  587. hw->nic_type = athr_l2c;
  588. break;
  589. case PCI_DEVICE_ID_ATTANSIC_L1C:
  590. hw->nic_type = athr_l1c;
  591. break;
  592. case PCI_DEVICE_ID_ATHEROS_L2C_B:
  593. hw->nic_type = athr_l2c_b;
  594. break;
  595. case PCI_DEVICE_ID_ATHEROS_L2C_B2:
  596. hw->nic_type = athr_l2c_b2;
  597. break;
  598. case PCI_DEVICE_ID_ATHEROS_L1D:
  599. hw->nic_type = athr_l1d;
  600. break;
  601. case PCI_DEVICE_ID_ATHEROS_L1D_2_0:
  602. hw->nic_type = athr_l1d_2;
  603. break;
  604. default:
  605. break;
  606. }
  607. }
  608. static int atl1c_setup_mac_funcs(struct atl1c_hw *hw)
  609. {
  610. u32 link_ctrl_data;
  611. atl1c_set_mac_type(hw);
  612. AT_READ_REG(hw, REG_LINK_CTRL, &link_ctrl_data);
  613. hw->ctrl_flags = ATL1C_INTR_MODRT_ENABLE |
  614. ATL1C_TXQ_MODE_ENHANCE;
  615. hw->ctrl_flags |= ATL1C_ASPM_L0S_SUPPORT |
  616. ATL1C_ASPM_L1_SUPPORT;
  617. hw->ctrl_flags |= ATL1C_ASPM_CTRL_MON;
  618. if (hw->nic_type == athr_l1c ||
  619. hw->nic_type == athr_l1d ||
  620. hw->nic_type == athr_l1d_2)
  621. hw->link_cap_flags |= ATL1C_LINK_CAP_1000M;
  622. return 0;
  623. }
  624. /*
  625. * atl1c_sw_init - Initialize general software structures (struct atl1c_adapter)
  626. * @adapter: board private structure to initialize
  627. *
  628. * atl1c_sw_init initializes the Adapter private data structure.
  629. * Fields are initialized based on PCI device information and
  630. * OS network device settings (MTU size).
  631. */
  632. static int __devinit atl1c_sw_init(struct atl1c_adapter *adapter)
  633. {
  634. struct atl1c_hw *hw = &adapter->hw;
  635. struct pci_dev *pdev = adapter->pdev;
  636. u32 revision;
  637. adapter->wol = 0;
  638. device_set_wakeup_enable(&pdev->dev, false);
  639. adapter->link_speed = SPEED_0;
  640. adapter->link_duplex = FULL_DUPLEX;
  641. adapter->tpd_ring[0].count = 1024;
  642. adapter->rfd_ring.count = 512;
  643. hw->vendor_id = pdev->vendor;
  644. hw->device_id = pdev->device;
  645. hw->subsystem_vendor_id = pdev->subsystem_vendor;
  646. hw->subsystem_id = pdev->subsystem_device;
  647. AT_READ_REG(hw, PCI_CLASS_REVISION, &revision);
  648. hw->revision_id = revision & 0xFF;
  649. /* before link up, we assume hibernate is true */
  650. hw->hibernate = true;
  651. hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
  652. if (atl1c_setup_mac_funcs(hw) != 0) {
  653. dev_err(&pdev->dev, "set mac function pointers failed\n");
  654. return -1;
  655. }
  656. hw->intr_mask = IMR_NORMAL_MASK;
  657. hw->phy_configured = false;
  658. hw->preamble_len = 7;
  659. hw->max_frame_size = adapter->netdev->mtu;
  660. hw->autoneg_advertised = ADVERTISED_Autoneg;
  661. hw->indirect_tab = 0xE4E4E4E4;
  662. hw->base_cpu = 0;
  663. hw->ict = 50000; /* 100ms */
  664. hw->smb_timer = 200000; /* 400ms */
  665. hw->rx_imt = 200;
  666. hw->tx_imt = 1000;
  667. hw->tpd_burst = 5;
  668. hw->rfd_burst = 8;
  669. hw->dma_order = atl1c_dma_ord_out;
  670. hw->dmar_block = atl1c_dma_req_1024;
  671. if (atl1c_alloc_queues(adapter)) {
  672. dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
  673. return -ENOMEM;
  674. }
  675. /* TODO */
  676. atl1c_set_rxbufsize(adapter, adapter->netdev);
  677. atomic_set(&adapter->irq_sem, 1);
  678. spin_lock_init(&adapter->mdio_lock);
  679. spin_lock_init(&adapter->tx_lock);
  680. set_bit(__AT_DOWN, &adapter->flags);
  681. return 0;
  682. }
  683. static inline void atl1c_clean_buffer(struct pci_dev *pdev,
  684. struct atl1c_buffer *buffer_info, int in_irq)
  685. {
  686. u16 pci_driection;
  687. if (buffer_info->flags & ATL1C_BUFFER_FREE)
  688. return;
  689. if (buffer_info->dma) {
  690. if (buffer_info->flags & ATL1C_PCIMAP_FROMDEVICE)
  691. pci_driection = PCI_DMA_FROMDEVICE;
  692. else
  693. pci_driection = PCI_DMA_TODEVICE;
  694. if (buffer_info->flags & ATL1C_PCIMAP_SINGLE)
  695. pci_unmap_single(pdev, buffer_info->dma,
  696. buffer_info->length, pci_driection);
  697. else if (buffer_info->flags & ATL1C_PCIMAP_PAGE)
  698. pci_unmap_page(pdev, buffer_info->dma,
  699. buffer_info->length, pci_driection);
  700. }
  701. if (buffer_info->skb) {
  702. if (in_irq)
  703. dev_kfree_skb_irq(buffer_info->skb);
  704. else
  705. dev_kfree_skb(buffer_info->skb);
  706. }
  707. buffer_info->dma = 0;
  708. buffer_info->skb = NULL;
  709. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
  710. }
  711. /*
  712. * atl1c_clean_tx_ring - Free Tx-skb
  713. * @adapter: board private structure
  714. */
  715. static void atl1c_clean_tx_ring(struct atl1c_adapter *adapter,
  716. enum atl1c_trans_queue type)
  717. {
  718. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  719. struct atl1c_buffer *buffer_info;
  720. struct pci_dev *pdev = adapter->pdev;
  721. u16 index, ring_count;
  722. ring_count = tpd_ring->count;
  723. for (index = 0; index < ring_count; index++) {
  724. buffer_info = &tpd_ring->buffer_info[index];
  725. atl1c_clean_buffer(pdev, buffer_info, 0);
  726. }
  727. /* Zero out Tx-buffers */
  728. memset(tpd_ring->desc, 0, sizeof(struct atl1c_tpd_desc) *
  729. ring_count);
  730. atomic_set(&tpd_ring->next_to_clean, 0);
  731. tpd_ring->next_to_use = 0;
  732. }
  733. /*
  734. * atl1c_clean_rx_ring - Free rx-reservation skbs
  735. * @adapter: board private structure
  736. */
  737. static void atl1c_clean_rx_ring(struct atl1c_adapter *adapter)
  738. {
  739. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  740. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  741. struct atl1c_buffer *buffer_info;
  742. struct pci_dev *pdev = adapter->pdev;
  743. int j;
  744. for (j = 0; j < rfd_ring->count; j++) {
  745. buffer_info = &rfd_ring->buffer_info[j];
  746. atl1c_clean_buffer(pdev, buffer_info, 0);
  747. }
  748. /* zero out the descriptor ring */
  749. memset(rfd_ring->desc, 0, rfd_ring->size);
  750. rfd_ring->next_to_clean = 0;
  751. rfd_ring->next_to_use = 0;
  752. rrd_ring->next_to_use = 0;
  753. rrd_ring->next_to_clean = 0;
  754. }
  755. /*
  756. * Read / Write Ptr Initialize:
  757. */
  758. static void atl1c_init_ring_ptrs(struct atl1c_adapter *adapter)
  759. {
  760. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  761. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  762. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  763. struct atl1c_buffer *buffer_info;
  764. int i, j;
  765. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  766. tpd_ring[i].next_to_use = 0;
  767. atomic_set(&tpd_ring[i].next_to_clean, 0);
  768. buffer_info = tpd_ring[i].buffer_info;
  769. for (j = 0; j < tpd_ring->count; j++)
  770. ATL1C_SET_BUFFER_STATE(&buffer_info[i],
  771. ATL1C_BUFFER_FREE);
  772. }
  773. rfd_ring->next_to_use = 0;
  774. rfd_ring->next_to_clean = 0;
  775. rrd_ring->next_to_use = 0;
  776. rrd_ring->next_to_clean = 0;
  777. for (j = 0; j < rfd_ring->count; j++) {
  778. buffer_info = &rfd_ring->buffer_info[j];
  779. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_FREE);
  780. }
  781. }
  782. /*
  783. * atl1c_free_ring_resources - Free Tx / RX descriptor Resources
  784. * @adapter: board private structure
  785. *
  786. * Free all transmit software resources
  787. */
  788. static void atl1c_free_ring_resources(struct atl1c_adapter *adapter)
  789. {
  790. struct pci_dev *pdev = adapter->pdev;
  791. pci_free_consistent(pdev, adapter->ring_header.size,
  792. adapter->ring_header.desc,
  793. adapter->ring_header.dma);
  794. adapter->ring_header.desc = NULL;
  795. /* Note: just free tdp_ring.buffer_info,
  796. * it contain rfd_ring.buffer_info, do not double free */
  797. if (adapter->tpd_ring[0].buffer_info) {
  798. kfree(adapter->tpd_ring[0].buffer_info);
  799. adapter->tpd_ring[0].buffer_info = NULL;
  800. }
  801. }
  802. /*
  803. * atl1c_setup_mem_resources - allocate Tx / RX descriptor resources
  804. * @adapter: board private structure
  805. *
  806. * Return 0 on success, negative on failure
  807. */
  808. static int atl1c_setup_ring_resources(struct atl1c_adapter *adapter)
  809. {
  810. struct pci_dev *pdev = adapter->pdev;
  811. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  812. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  813. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  814. struct atl1c_ring_header *ring_header = &adapter->ring_header;
  815. int size;
  816. int i;
  817. int count = 0;
  818. int rx_desc_count = 0;
  819. u32 offset = 0;
  820. rrd_ring->count = rfd_ring->count;
  821. for (i = 1; i < AT_MAX_TRANSMIT_QUEUE; i++)
  822. tpd_ring[i].count = tpd_ring[0].count;
  823. /* 2 tpd queue, one high priority queue,
  824. * another normal priority queue */
  825. size = sizeof(struct atl1c_buffer) * (tpd_ring->count * 2 +
  826. rfd_ring->count);
  827. tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
  828. if (unlikely(!tpd_ring->buffer_info)) {
  829. dev_err(&pdev->dev, "kzalloc failed, size = %d\n",
  830. size);
  831. goto err_nomem;
  832. }
  833. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  834. tpd_ring[i].buffer_info =
  835. (struct atl1c_buffer *) (tpd_ring->buffer_info + count);
  836. count += tpd_ring[i].count;
  837. }
  838. rfd_ring->buffer_info =
  839. (struct atl1c_buffer *) (tpd_ring->buffer_info + count);
  840. count += rfd_ring->count;
  841. rx_desc_count += rfd_ring->count;
  842. /*
  843. * real ring DMA buffer
  844. * each ring/block may need up to 8 bytes for alignment, hence the
  845. * additional bytes tacked onto the end.
  846. */
  847. ring_header->size = size =
  848. sizeof(struct atl1c_tpd_desc) * tpd_ring->count * 2 +
  849. sizeof(struct atl1c_rx_free_desc) * rx_desc_count +
  850. sizeof(struct atl1c_recv_ret_status) * rx_desc_count +
  851. 8 * 4;
  852. ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
  853. &ring_header->dma);
  854. if (unlikely(!ring_header->desc)) {
  855. dev_err(&pdev->dev, "pci_alloc_consistend failed\n");
  856. goto err_nomem;
  857. }
  858. memset(ring_header->desc, 0, ring_header->size);
  859. /* init TPD ring */
  860. tpd_ring[0].dma = roundup(ring_header->dma, 8);
  861. offset = tpd_ring[0].dma - ring_header->dma;
  862. for (i = 0; i < AT_MAX_TRANSMIT_QUEUE; i++) {
  863. tpd_ring[i].dma = ring_header->dma + offset;
  864. tpd_ring[i].desc = (u8 *) ring_header->desc + offset;
  865. tpd_ring[i].size =
  866. sizeof(struct atl1c_tpd_desc) * tpd_ring[i].count;
  867. offset += roundup(tpd_ring[i].size, 8);
  868. }
  869. /* init RFD ring */
  870. rfd_ring->dma = ring_header->dma + offset;
  871. rfd_ring->desc = (u8 *) ring_header->desc + offset;
  872. rfd_ring->size = sizeof(struct atl1c_rx_free_desc) * rfd_ring->count;
  873. offset += roundup(rfd_ring->size, 8);
  874. /* init RRD ring */
  875. rrd_ring->dma = ring_header->dma + offset;
  876. rrd_ring->desc = (u8 *) ring_header->desc + offset;
  877. rrd_ring->size = sizeof(struct atl1c_recv_ret_status) *
  878. rrd_ring->count;
  879. offset += roundup(rrd_ring->size, 8);
  880. return 0;
  881. err_nomem:
  882. kfree(tpd_ring->buffer_info);
  883. return -ENOMEM;
  884. }
  885. static void atl1c_configure_des_ring(struct atl1c_adapter *adapter)
  886. {
  887. struct atl1c_hw *hw = &adapter->hw;
  888. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  889. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  890. struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
  891. adapter->tpd_ring;
  892. /* TPD */
  893. AT_WRITE_REG(hw, REG_TX_BASE_ADDR_HI,
  894. (u32)((tpd_ring[atl1c_trans_normal].dma &
  895. AT_DMA_HI_ADDR_MASK) >> 32));
  896. /* just enable normal priority TX queue */
  897. AT_WRITE_REG(hw, REG_TPD_PRI0_ADDR_LO,
  898. (u32)(tpd_ring[atl1c_trans_normal].dma &
  899. AT_DMA_LO_ADDR_MASK));
  900. AT_WRITE_REG(hw, REG_TPD_PRI1_ADDR_LO,
  901. (u32)(tpd_ring[atl1c_trans_high].dma &
  902. AT_DMA_LO_ADDR_MASK));
  903. AT_WRITE_REG(hw, REG_TPD_RING_SIZE,
  904. (u32)(tpd_ring[0].count & TPD_RING_SIZE_MASK));
  905. /* RFD */
  906. AT_WRITE_REG(hw, REG_RX_BASE_ADDR_HI,
  907. (u32)((rfd_ring->dma & AT_DMA_HI_ADDR_MASK) >> 32));
  908. AT_WRITE_REG(hw, REG_RFD0_HEAD_ADDR_LO,
  909. (u32)(rfd_ring->dma & AT_DMA_LO_ADDR_MASK));
  910. AT_WRITE_REG(hw, REG_RFD_RING_SIZE,
  911. rfd_ring->count & RFD_RING_SIZE_MASK);
  912. AT_WRITE_REG(hw, REG_RX_BUF_SIZE,
  913. adapter->rx_buffer_len & RX_BUF_SIZE_MASK);
  914. /* RRD */
  915. AT_WRITE_REG(hw, REG_RRD0_HEAD_ADDR_LO,
  916. (u32)(rrd_ring->dma & AT_DMA_LO_ADDR_MASK));
  917. AT_WRITE_REG(hw, REG_RRD_RING_SIZE,
  918. (rrd_ring->count & RRD_RING_SIZE_MASK));
  919. if (hw->nic_type == athr_l2c_b) {
  920. AT_WRITE_REG(hw, REG_SRAM_RXF_LEN, 0x02a0L);
  921. AT_WRITE_REG(hw, REG_SRAM_TXF_LEN, 0x0100L);
  922. AT_WRITE_REG(hw, REG_SRAM_RXF_ADDR, 0x029f0000L);
  923. AT_WRITE_REG(hw, REG_SRAM_RFD0_INFO, 0x02bf02a0L);
  924. AT_WRITE_REG(hw, REG_SRAM_TXF_ADDR, 0x03bf02c0L);
  925. AT_WRITE_REG(hw, REG_SRAM_TRD_ADDR, 0x03df03c0L);
  926. AT_WRITE_REG(hw, REG_TXF_WATER_MARK, 0); /* TX watermark, to enter l1 state.*/
  927. AT_WRITE_REG(hw, REG_RXD_DMA_CTRL, 0); /* RXD threshold.*/
  928. }
  929. /* Load all of base address above */
  930. AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
  931. }
  932. static void atl1c_configure_tx(struct atl1c_adapter *adapter)
  933. {
  934. struct atl1c_hw *hw = &adapter->hw;
  935. int max_pay_load;
  936. u16 tx_offload_thresh;
  937. u32 txq_ctrl_data;
  938. tx_offload_thresh = MAX_TSO_FRAME_SIZE;
  939. AT_WRITE_REG(hw, REG_TX_TSO_OFFLOAD_THRESH,
  940. (tx_offload_thresh >> 3) & TX_TSO_OFFLOAD_THRESH_MASK);
  941. max_pay_load = pcie_get_readrq(adapter->pdev) >> 8;
  942. hw->dmar_block = min_t(u32, max_pay_load, hw->dmar_block);
  943. /*
  944. * if BIOS had changed the dam-read-max-length to an invalid value,
  945. * restore it to default value
  946. */
  947. if (hw->dmar_block < DEVICE_CTRL_MAXRRS_MIN) {
  948. pcie_set_readrq(adapter->pdev, 128 << DEVICE_CTRL_MAXRRS_MIN);
  949. hw->dmar_block = DEVICE_CTRL_MAXRRS_MIN;
  950. }
  951. txq_ctrl_data =
  952. hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2 ?
  953. L2CB_TXQ_CFGV : L1C_TXQ_CFGV;
  954. AT_WRITE_REG(hw, REG_TXQ_CTRL, txq_ctrl_data);
  955. }
  956. static void atl1c_configure_rx(struct atl1c_adapter *adapter)
  957. {
  958. struct atl1c_hw *hw = &adapter->hw;
  959. u32 rxq_ctrl_data;
  960. rxq_ctrl_data = (hw->rfd_burst & RXQ_RFD_BURST_NUM_MASK) <<
  961. RXQ_RFD_BURST_NUM_SHIFT;
  962. if (hw->ctrl_flags & ATL1C_RX_IPV6_CHKSUM)
  963. rxq_ctrl_data |= IPV6_CHKSUM_CTRL_EN;
  964. /* aspm for gigabit */
  965. if (hw->nic_type != athr_l1d_2 && (hw->device_id & 1) != 0)
  966. rxq_ctrl_data = FIELD_SETX(rxq_ctrl_data, ASPM_THRUPUT_LIMIT,
  967. ASPM_THRUPUT_LIMIT_100M);
  968. AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
  969. }
  970. static void atl1c_configure_dma(struct atl1c_adapter *adapter)
  971. {
  972. struct atl1c_hw *hw = &adapter->hw;
  973. u32 dma_ctrl_data;
  974. dma_ctrl_data = FIELDX(DMA_CTRL_RORDER_MODE, DMA_CTRL_RORDER_MODE_OUT) |
  975. DMA_CTRL_RREQ_PRI_DATA |
  976. FIELDX(DMA_CTRL_RREQ_BLEN, hw->dmar_block) |
  977. FIELDX(DMA_CTRL_WDLY_CNT, DMA_CTRL_WDLY_CNT_DEF) |
  978. FIELDX(DMA_CTRL_RDLY_CNT, DMA_CTRL_RDLY_CNT_DEF);
  979. AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
  980. }
  981. /*
  982. * Stop the mac, transmit and receive units
  983. * hw - Struct containing variables accessed by shared code
  984. * return : 0 or idle status (if error)
  985. */
  986. static int atl1c_stop_mac(struct atl1c_hw *hw)
  987. {
  988. u32 data;
  989. AT_READ_REG(hw, REG_RXQ_CTRL, &data);
  990. data &= ~RXQ_CTRL_EN;
  991. AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
  992. AT_READ_REG(hw, REG_TXQ_CTRL, &data);
  993. data &= ~TXQ_CTRL_EN;
  994. AT_WRITE_REG(hw, REG_TXQ_CTRL, data);
  995. atl1c_wait_until_idle(hw, IDLE_STATUS_RXQ_BUSY | IDLE_STATUS_TXQ_BUSY);
  996. AT_READ_REG(hw, REG_MAC_CTRL, &data);
  997. data &= ~(MAC_CTRL_TX_EN | MAC_CTRL_RX_EN);
  998. AT_WRITE_REG(hw, REG_MAC_CTRL, data);
  999. return (int)atl1c_wait_until_idle(hw,
  1000. IDLE_STATUS_TXMAC_BUSY | IDLE_STATUS_RXMAC_BUSY);
  1001. }
  1002. static void atl1c_enable_rx_ctrl(struct atl1c_hw *hw)
  1003. {
  1004. u32 data;
  1005. AT_READ_REG(hw, REG_RXQ_CTRL, &data);
  1006. data |= RXQ_CTRL_EN;
  1007. AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
  1008. }
  1009. static void atl1c_enable_tx_ctrl(struct atl1c_hw *hw)
  1010. {
  1011. u32 data;
  1012. AT_READ_REG(hw, REG_TXQ_CTRL, &data);
  1013. data |= TXQ_CTRL_EN;
  1014. AT_WRITE_REG(hw, REG_TXQ_CTRL, data);
  1015. }
  1016. /*
  1017. * Reset the transmit and receive units; mask and clear all interrupts.
  1018. * hw - Struct containing variables accessed by shared code
  1019. * return : 0 or idle status (if error)
  1020. */
  1021. static int atl1c_reset_mac(struct atl1c_hw *hw)
  1022. {
  1023. struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
  1024. struct pci_dev *pdev = adapter->pdev;
  1025. u32 ctrl_data = 0;
  1026. AT_WRITE_REG(hw, REG_IMR, 0);
  1027. AT_WRITE_REG(hw, REG_ISR, ISR_DIS_INT);
  1028. atl1c_stop_mac(hw);
  1029. /*
  1030. * Issue Soft Reset to the MAC. This will reset the chip's
  1031. * transmit, receive, DMA. It will not effect
  1032. * the current PCI configuration. The global reset bit is self-
  1033. * clearing, and should clear within a microsecond.
  1034. */
  1035. AT_READ_REG(hw, REG_MASTER_CTRL, &ctrl_data);
  1036. ctrl_data |= MASTER_CTRL_OOB_DIS;
  1037. AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data | MASTER_CTRL_SOFT_RST);
  1038. AT_WRITE_FLUSH(hw);
  1039. msleep(10);
  1040. /* Wait at least 10ms for All module to be Idle */
  1041. if (atl1c_wait_until_idle(hw, IDLE_STATUS_MASK)) {
  1042. dev_err(&pdev->dev,
  1043. "MAC state machine can't be idle since"
  1044. " disabled for 10ms second\n");
  1045. return -1;
  1046. }
  1047. AT_WRITE_REG(hw, REG_MASTER_CTRL, ctrl_data);
  1048. /* driver control speed/duplex */
  1049. AT_READ_REG(hw, REG_MAC_CTRL, &ctrl_data);
  1050. AT_WRITE_REG(hw, REG_MAC_CTRL, ctrl_data | MAC_CTRL_SPEED_MODE_SW);
  1051. /* clk switch setting */
  1052. AT_READ_REG(hw, REG_SERDES, &ctrl_data);
  1053. switch (hw->nic_type) {
  1054. case athr_l2c_b:
  1055. ctrl_data &= ~(SERDES_PHY_CLK_SLOWDOWN |
  1056. SERDES_MAC_CLK_SLOWDOWN);
  1057. AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
  1058. break;
  1059. case athr_l2c_b2:
  1060. case athr_l1d_2:
  1061. ctrl_data |= SERDES_PHY_CLK_SLOWDOWN | SERDES_MAC_CLK_SLOWDOWN;
  1062. AT_WRITE_REG(hw, REG_SERDES, ctrl_data);
  1063. break;
  1064. default:
  1065. break;
  1066. }
  1067. return 0;
  1068. }
  1069. static void atl1c_disable_l0s_l1(struct atl1c_hw *hw)
  1070. {
  1071. u16 ctrl_flags = hw->ctrl_flags;
  1072. hw->ctrl_flags &= ~(ATL1C_ASPM_L0S_SUPPORT | ATL1C_ASPM_L1_SUPPORT);
  1073. atl1c_set_aspm(hw, SPEED_0);
  1074. hw->ctrl_flags = ctrl_flags;
  1075. }
  1076. /*
  1077. * Set ASPM state.
  1078. * Enable/disable L0s/L1 depend on link state.
  1079. */
  1080. static void atl1c_set_aspm(struct atl1c_hw *hw, u16 link_speed)
  1081. {
  1082. u32 pm_ctrl_data;
  1083. u32 link_l1_timer;
  1084. AT_READ_REG(hw, REG_PM_CTRL, &pm_ctrl_data);
  1085. pm_ctrl_data &= ~(PM_CTRL_ASPM_L1_EN |
  1086. PM_CTRL_ASPM_L0S_EN |
  1087. PM_CTRL_MAC_ASPM_CHK);
  1088. /* L1 timer */
  1089. if (hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
  1090. pm_ctrl_data &= ~PMCTRL_TXL1_AFTER_L0S;
  1091. link_l1_timer =
  1092. link_speed == SPEED_1000 || link_speed == SPEED_100 ?
  1093. L1D_PMCTRL_L1_ENTRY_TM_16US : 1;
  1094. pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
  1095. L1D_PMCTRL_L1_ENTRY_TM, link_l1_timer);
  1096. } else {
  1097. link_l1_timer = hw->nic_type == athr_l2c_b ?
  1098. L2CB1_PM_CTRL_L1_ENTRY_TM : L1C_PM_CTRL_L1_ENTRY_TM;
  1099. if (link_speed != SPEED_1000 && link_speed != SPEED_100)
  1100. link_l1_timer = 1;
  1101. pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
  1102. PM_CTRL_L1_ENTRY_TIMER, link_l1_timer);
  1103. }
  1104. /* L0S/L1 enable */
  1105. if (hw->ctrl_flags & ATL1C_ASPM_L0S_SUPPORT)
  1106. pm_ctrl_data |= PM_CTRL_ASPM_L0S_EN | PM_CTRL_MAC_ASPM_CHK;
  1107. if (hw->ctrl_flags & ATL1C_ASPM_L1_SUPPORT)
  1108. pm_ctrl_data |= PM_CTRL_ASPM_L1_EN | PM_CTRL_MAC_ASPM_CHK;
  1109. /* l2cb & l1d & l2cb2 & l1d2 */
  1110. if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l1d ||
  1111. hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) {
  1112. pm_ctrl_data = FIELD_SETX(pm_ctrl_data,
  1113. PM_CTRL_PM_REQ_TIMER, PM_CTRL_PM_REQ_TO_DEF);
  1114. pm_ctrl_data |= PM_CTRL_RCVR_WT_TIMER |
  1115. PM_CTRL_SERDES_PD_EX_L1 |
  1116. PM_CTRL_CLK_SWH_L1;
  1117. pm_ctrl_data &= ~(PM_CTRL_SERDES_L1_EN |
  1118. PM_CTRL_SERDES_PLL_L1_EN |
  1119. PM_CTRL_SERDES_BUFS_RX_L1_EN |
  1120. PM_CTRL_SA_DLY_EN |
  1121. PM_CTRL_HOTRST);
  1122. /* disable l0s if link down or l2cb */
  1123. if (link_speed == SPEED_0 || hw->nic_type == athr_l2c_b)
  1124. pm_ctrl_data &= ~PM_CTRL_ASPM_L0S_EN;
  1125. } else { /* l1c */
  1126. pm_ctrl_data =
  1127. FIELD_SETX(pm_ctrl_data, PM_CTRL_L1_ENTRY_TIMER, 0);
  1128. if (link_speed != SPEED_0) {
  1129. pm_ctrl_data |= PM_CTRL_SERDES_L1_EN |
  1130. PM_CTRL_SERDES_PLL_L1_EN |
  1131. PM_CTRL_SERDES_BUFS_RX_L1_EN;
  1132. pm_ctrl_data &= ~(PM_CTRL_SERDES_PD_EX_L1 |
  1133. PM_CTRL_CLK_SWH_L1 |
  1134. PM_CTRL_ASPM_L0S_EN |
  1135. PM_CTRL_ASPM_L1_EN);
  1136. } else { /* link down */
  1137. pm_ctrl_data |= PM_CTRL_CLK_SWH_L1;
  1138. pm_ctrl_data &= ~(PM_CTRL_SERDES_L1_EN |
  1139. PM_CTRL_SERDES_PLL_L1_EN |
  1140. PM_CTRL_SERDES_BUFS_RX_L1_EN |
  1141. PM_CTRL_ASPM_L0S_EN);
  1142. }
  1143. }
  1144. AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
  1145. return;
  1146. }
  1147. static void atl1c_setup_mac_ctrl(struct atl1c_adapter *adapter)
  1148. {
  1149. struct atl1c_hw *hw = &adapter->hw;
  1150. struct net_device *netdev = adapter->netdev;
  1151. u32 mac_ctrl_data;
  1152. mac_ctrl_data = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
  1153. mac_ctrl_data |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
  1154. if (adapter->link_duplex == FULL_DUPLEX) {
  1155. hw->mac_duplex = true;
  1156. mac_ctrl_data |= MAC_CTRL_DUPLX;
  1157. }
  1158. if (adapter->link_speed == SPEED_1000)
  1159. hw->mac_speed = atl1c_mac_speed_1000;
  1160. else
  1161. hw->mac_speed = atl1c_mac_speed_10_100;
  1162. mac_ctrl_data |= (hw->mac_speed & MAC_CTRL_SPEED_MASK) <<
  1163. MAC_CTRL_SPEED_SHIFT;
  1164. mac_ctrl_data |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
  1165. mac_ctrl_data |= ((hw->preamble_len & MAC_CTRL_PRMLEN_MASK) <<
  1166. MAC_CTRL_PRMLEN_SHIFT);
  1167. __atl1c_vlan_mode(netdev->features, &mac_ctrl_data);
  1168. mac_ctrl_data |= MAC_CTRL_BC_EN;
  1169. if (netdev->flags & IFF_PROMISC)
  1170. mac_ctrl_data |= MAC_CTRL_PROMIS_EN;
  1171. if (netdev->flags & IFF_ALLMULTI)
  1172. mac_ctrl_data |= MAC_CTRL_MC_ALL_EN;
  1173. mac_ctrl_data |= MAC_CTRL_SINGLE_PAUSE_EN;
  1174. if (hw->nic_type == athr_l1d || hw->nic_type == athr_l2c_b2 ||
  1175. hw->nic_type == athr_l1d_2) {
  1176. mac_ctrl_data |= MAC_CTRL_SPEED_MODE_SW;
  1177. mac_ctrl_data |= MAC_CTRL_HASH_ALG_CRC32;
  1178. }
  1179. AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
  1180. }
  1181. /*
  1182. * atl1c_configure - Configure Transmit&Receive Unit after Reset
  1183. * @adapter: board private structure
  1184. *
  1185. * Configure the Tx /Rx unit of the MAC after a reset.
  1186. */
  1187. static int atl1c_configure(struct atl1c_adapter *adapter)
  1188. {
  1189. struct atl1c_hw *hw = &adapter->hw;
  1190. u32 master_ctrl_data = 0;
  1191. u32 intr_modrt_data;
  1192. u32 data;
  1193. AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
  1194. master_ctrl_data &= ~(MASTER_CTRL_TX_ITIMER_EN |
  1195. MASTER_CTRL_RX_ITIMER_EN |
  1196. MASTER_CTRL_INT_RDCLR);
  1197. /* clear interrupt status */
  1198. AT_WRITE_REG(hw, REG_ISR, 0xFFFFFFFF);
  1199. /* Clear any WOL status */
  1200. AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
  1201. /* set Interrupt Clear Timer
  1202. * HW will enable self to assert interrupt event to system after
  1203. * waiting x-time for software to notify it accept interrupt.
  1204. */
  1205. data = CLK_GATING_EN_ALL;
  1206. if (hw->ctrl_flags & ATL1C_CLK_GATING_EN) {
  1207. if (hw->nic_type == athr_l2c_b)
  1208. data &= ~CLK_GATING_RXMAC_EN;
  1209. } else
  1210. data = 0;
  1211. AT_WRITE_REG(hw, REG_CLK_GATING_CTRL, data);
  1212. AT_WRITE_REG(hw, REG_INT_RETRIG_TIMER,
  1213. hw->ict & INT_RETRIG_TIMER_MASK);
  1214. atl1c_configure_des_ring(adapter);
  1215. if (hw->ctrl_flags & ATL1C_INTR_MODRT_ENABLE) {
  1216. intr_modrt_data = (hw->tx_imt & IRQ_MODRT_TIMER_MASK) <<
  1217. IRQ_MODRT_TX_TIMER_SHIFT;
  1218. intr_modrt_data |= (hw->rx_imt & IRQ_MODRT_TIMER_MASK) <<
  1219. IRQ_MODRT_RX_TIMER_SHIFT;
  1220. AT_WRITE_REG(hw, REG_IRQ_MODRT_TIMER_INIT, intr_modrt_data);
  1221. master_ctrl_data |=
  1222. MASTER_CTRL_TX_ITIMER_EN | MASTER_CTRL_RX_ITIMER_EN;
  1223. }
  1224. if (hw->ctrl_flags & ATL1C_INTR_CLEAR_ON_READ)
  1225. master_ctrl_data |= MASTER_CTRL_INT_RDCLR;
  1226. master_ctrl_data |= MASTER_CTRL_SA_TIMER_EN;
  1227. AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
  1228. AT_WRITE_REG(hw, REG_SMB_STAT_TIMER,
  1229. hw->smb_timer & SMB_STAT_TIMER_MASK);
  1230. /* set MTU */
  1231. AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
  1232. VLAN_HLEN + ETH_FCS_LEN);
  1233. atl1c_configure_tx(adapter);
  1234. atl1c_configure_rx(adapter);
  1235. atl1c_configure_dma(adapter);
  1236. return 0;
  1237. }
  1238. static void atl1c_update_hw_stats(struct atl1c_adapter *adapter)
  1239. {
  1240. u16 hw_reg_addr = 0;
  1241. unsigned long *stats_item = NULL;
  1242. u32 data;
  1243. /* update rx status */
  1244. hw_reg_addr = REG_MAC_RX_STATUS_BIN;
  1245. stats_item = &adapter->hw_stats.rx_ok;
  1246. while (hw_reg_addr <= REG_MAC_RX_STATUS_END) {
  1247. AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
  1248. *stats_item += data;
  1249. stats_item++;
  1250. hw_reg_addr += 4;
  1251. }
  1252. /* update tx status */
  1253. hw_reg_addr = REG_MAC_TX_STATUS_BIN;
  1254. stats_item = &adapter->hw_stats.tx_ok;
  1255. while (hw_reg_addr <= REG_MAC_TX_STATUS_END) {
  1256. AT_READ_REG(&adapter->hw, hw_reg_addr, &data);
  1257. *stats_item += data;
  1258. stats_item++;
  1259. hw_reg_addr += 4;
  1260. }
  1261. }
  1262. /*
  1263. * atl1c_get_stats - Get System Network Statistics
  1264. * @netdev: network interface device structure
  1265. *
  1266. * Returns the address of the device statistics structure.
  1267. * The statistics are actually updated from the timer callback.
  1268. */
  1269. static struct net_device_stats *atl1c_get_stats(struct net_device *netdev)
  1270. {
  1271. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1272. struct atl1c_hw_stats *hw_stats = &adapter->hw_stats;
  1273. struct net_device_stats *net_stats = &netdev->stats;
  1274. atl1c_update_hw_stats(adapter);
  1275. net_stats->rx_packets = hw_stats->rx_ok;
  1276. net_stats->tx_packets = hw_stats->tx_ok;
  1277. net_stats->rx_bytes = hw_stats->rx_byte_cnt;
  1278. net_stats->tx_bytes = hw_stats->tx_byte_cnt;
  1279. net_stats->multicast = hw_stats->rx_mcast;
  1280. net_stats->collisions = hw_stats->tx_1_col +
  1281. hw_stats->tx_2_col * 2 +
  1282. hw_stats->tx_late_col + hw_stats->tx_abort_col;
  1283. net_stats->rx_errors = hw_stats->rx_frag + hw_stats->rx_fcs_err +
  1284. hw_stats->rx_len_err + hw_stats->rx_sz_ov +
  1285. hw_stats->rx_rrd_ov + hw_stats->rx_align_err;
  1286. net_stats->rx_fifo_errors = hw_stats->rx_rxf_ov;
  1287. net_stats->rx_length_errors = hw_stats->rx_len_err;
  1288. net_stats->rx_crc_errors = hw_stats->rx_fcs_err;
  1289. net_stats->rx_frame_errors = hw_stats->rx_align_err;
  1290. net_stats->rx_over_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
  1291. net_stats->rx_missed_errors = hw_stats->rx_rrd_ov + hw_stats->rx_rxf_ov;
  1292. net_stats->tx_errors = hw_stats->tx_late_col + hw_stats->tx_abort_col +
  1293. hw_stats->tx_underrun + hw_stats->tx_trunc;
  1294. net_stats->tx_fifo_errors = hw_stats->tx_underrun;
  1295. net_stats->tx_aborted_errors = hw_stats->tx_abort_col;
  1296. net_stats->tx_window_errors = hw_stats->tx_late_col;
  1297. return net_stats;
  1298. }
  1299. static inline void atl1c_clear_phy_int(struct atl1c_adapter *adapter)
  1300. {
  1301. u16 phy_data;
  1302. spin_lock(&adapter->mdio_lock);
  1303. atl1c_read_phy_reg(&adapter->hw, MII_ISR, &phy_data);
  1304. spin_unlock(&adapter->mdio_lock);
  1305. }
  1306. static bool atl1c_clean_tx_irq(struct atl1c_adapter *adapter,
  1307. enum atl1c_trans_queue type)
  1308. {
  1309. struct atl1c_tpd_ring *tpd_ring = (struct atl1c_tpd_ring *)
  1310. &adapter->tpd_ring[type];
  1311. struct atl1c_buffer *buffer_info;
  1312. struct pci_dev *pdev = adapter->pdev;
  1313. u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
  1314. u16 hw_next_to_clean;
  1315. u16 reg;
  1316. reg = type == atl1c_trans_high ? REG_TPD_PRI1_CIDX : REG_TPD_PRI0_CIDX;
  1317. AT_READ_REGW(&adapter->hw, reg, &hw_next_to_clean);
  1318. while (next_to_clean != hw_next_to_clean) {
  1319. buffer_info = &tpd_ring->buffer_info[next_to_clean];
  1320. atl1c_clean_buffer(pdev, buffer_info, 1);
  1321. if (++next_to_clean == tpd_ring->count)
  1322. next_to_clean = 0;
  1323. atomic_set(&tpd_ring->next_to_clean, next_to_clean);
  1324. }
  1325. if (netif_queue_stopped(adapter->netdev) &&
  1326. netif_carrier_ok(adapter->netdev)) {
  1327. netif_wake_queue(adapter->netdev);
  1328. }
  1329. return true;
  1330. }
  1331. /*
  1332. * atl1c_intr - Interrupt Handler
  1333. * @irq: interrupt number
  1334. * @data: pointer to a network interface device structure
  1335. * @pt_regs: CPU registers structure
  1336. */
  1337. static irqreturn_t atl1c_intr(int irq, void *data)
  1338. {
  1339. struct net_device *netdev = data;
  1340. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1341. struct pci_dev *pdev = adapter->pdev;
  1342. struct atl1c_hw *hw = &adapter->hw;
  1343. int max_ints = AT_MAX_INT_WORK;
  1344. int handled = IRQ_NONE;
  1345. u32 status;
  1346. u32 reg_data;
  1347. do {
  1348. AT_READ_REG(hw, REG_ISR, &reg_data);
  1349. status = reg_data & hw->intr_mask;
  1350. if (status == 0 || (status & ISR_DIS_INT) != 0) {
  1351. if (max_ints != AT_MAX_INT_WORK)
  1352. handled = IRQ_HANDLED;
  1353. break;
  1354. }
  1355. /* link event */
  1356. if (status & ISR_GPHY)
  1357. atl1c_clear_phy_int(adapter);
  1358. /* Ack ISR */
  1359. AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
  1360. if (status & ISR_RX_PKT) {
  1361. if (likely(napi_schedule_prep(&adapter->napi))) {
  1362. hw->intr_mask &= ~ISR_RX_PKT;
  1363. AT_WRITE_REG(hw, REG_IMR, hw->intr_mask);
  1364. __napi_schedule(&adapter->napi);
  1365. }
  1366. }
  1367. if (status & ISR_TX_PKT)
  1368. atl1c_clean_tx_irq(adapter, atl1c_trans_normal);
  1369. handled = IRQ_HANDLED;
  1370. /* check if PCIE PHY Link down */
  1371. if (status & ISR_ERROR) {
  1372. if (netif_msg_hw(adapter))
  1373. dev_err(&pdev->dev,
  1374. "atl1c hardware error (status = 0x%x)\n",
  1375. status & ISR_ERROR);
  1376. /* reset MAC */
  1377. set_bit(ATL1C_WORK_EVENT_RESET, &adapter->work_event);
  1378. schedule_work(&adapter->common_task);
  1379. return IRQ_HANDLED;
  1380. }
  1381. if (status & ISR_OVER)
  1382. if (netif_msg_intr(adapter))
  1383. dev_warn(&pdev->dev,
  1384. "TX/RX overflow (status = 0x%x)\n",
  1385. status & ISR_OVER);
  1386. /* link event */
  1387. if (status & (ISR_GPHY | ISR_MANUAL)) {
  1388. netdev->stats.tx_carrier_errors++;
  1389. atl1c_link_chg_event(adapter);
  1390. break;
  1391. }
  1392. } while (--max_ints > 0);
  1393. /* re-enable Interrupt*/
  1394. AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
  1395. return handled;
  1396. }
  1397. static inline void atl1c_rx_checksum(struct atl1c_adapter *adapter,
  1398. struct sk_buff *skb, struct atl1c_recv_ret_status *prrs)
  1399. {
  1400. /*
  1401. * The pid field in RRS in not correct sometimes, so we
  1402. * cannot figure out if the packet is fragmented or not,
  1403. * so we tell the KERNEL CHECKSUM_NONE
  1404. */
  1405. skb_checksum_none_assert(skb);
  1406. }
  1407. static int atl1c_alloc_rx_buffer(struct atl1c_adapter *adapter)
  1408. {
  1409. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  1410. struct pci_dev *pdev = adapter->pdev;
  1411. struct atl1c_buffer *buffer_info, *next_info;
  1412. struct sk_buff *skb;
  1413. void *vir_addr = NULL;
  1414. u16 num_alloc = 0;
  1415. u16 rfd_next_to_use, next_next;
  1416. struct atl1c_rx_free_desc *rfd_desc;
  1417. next_next = rfd_next_to_use = rfd_ring->next_to_use;
  1418. if (++next_next == rfd_ring->count)
  1419. next_next = 0;
  1420. buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
  1421. next_info = &rfd_ring->buffer_info[next_next];
  1422. while (next_info->flags & ATL1C_BUFFER_FREE) {
  1423. rfd_desc = ATL1C_RFD_DESC(rfd_ring, rfd_next_to_use);
  1424. skb = netdev_alloc_skb(adapter->netdev, adapter->rx_buffer_len);
  1425. if (unlikely(!skb)) {
  1426. if (netif_msg_rx_err(adapter))
  1427. dev_warn(&pdev->dev, "alloc rx buffer failed\n");
  1428. break;
  1429. }
  1430. /*
  1431. * Make buffer alignment 2 beyond a 16 byte boundary
  1432. * this will result in a 16 byte aligned IP header after
  1433. * the 14 byte MAC header is removed
  1434. */
  1435. vir_addr = skb->data;
  1436. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1437. buffer_info->skb = skb;
  1438. buffer_info->length = adapter->rx_buffer_len;
  1439. buffer_info->dma = pci_map_single(pdev, vir_addr,
  1440. buffer_info->length,
  1441. PCI_DMA_FROMDEVICE);
  1442. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1443. ATL1C_PCIMAP_FROMDEVICE);
  1444. rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
  1445. rfd_next_to_use = next_next;
  1446. if (++next_next == rfd_ring->count)
  1447. next_next = 0;
  1448. buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
  1449. next_info = &rfd_ring->buffer_info[next_next];
  1450. num_alloc++;
  1451. }
  1452. if (num_alloc) {
  1453. /* TODO: update mailbox here */
  1454. wmb();
  1455. rfd_ring->next_to_use = rfd_next_to_use;
  1456. AT_WRITE_REG(&adapter->hw, REG_MB_RFD0_PROD_IDX,
  1457. rfd_ring->next_to_use & MB_RFDX_PROD_IDX_MASK);
  1458. }
  1459. return num_alloc;
  1460. }
  1461. static void atl1c_clean_rrd(struct atl1c_rrd_ring *rrd_ring,
  1462. struct atl1c_recv_ret_status *rrs, u16 num)
  1463. {
  1464. u16 i;
  1465. /* the relationship between rrd and rfd is one map one */
  1466. for (i = 0; i < num; i++, rrs = ATL1C_RRD_DESC(rrd_ring,
  1467. rrd_ring->next_to_clean)) {
  1468. rrs->word3 &= ~RRS_RXD_UPDATED;
  1469. if (++rrd_ring->next_to_clean == rrd_ring->count)
  1470. rrd_ring->next_to_clean = 0;
  1471. }
  1472. }
  1473. static void atl1c_clean_rfd(struct atl1c_rfd_ring *rfd_ring,
  1474. struct atl1c_recv_ret_status *rrs, u16 num)
  1475. {
  1476. u16 i;
  1477. u16 rfd_index;
  1478. struct atl1c_buffer *buffer_info = rfd_ring->buffer_info;
  1479. rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
  1480. RRS_RX_RFD_INDEX_MASK;
  1481. for (i = 0; i < num; i++) {
  1482. buffer_info[rfd_index].skb = NULL;
  1483. ATL1C_SET_BUFFER_STATE(&buffer_info[rfd_index],
  1484. ATL1C_BUFFER_FREE);
  1485. if (++rfd_index == rfd_ring->count)
  1486. rfd_index = 0;
  1487. }
  1488. rfd_ring->next_to_clean = rfd_index;
  1489. }
  1490. static void atl1c_clean_rx_irq(struct atl1c_adapter *adapter,
  1491. int *work_done, int work_to_do)
  1492. {
  1493. u16 rfd_num, rfd_index;
  1494. u16 count = 0;
  1495. u16 length;
  1496. struct pci_dev *pdev = adapter->pdev;
  1497. struct net_device *netdev = adapter->netdev;
  1498. struct atl1c_rfd_ring *rfd_ring = &adapter->rfd_ring;
  1499. struct atl1c_rrd_ring *rrd_ring = &adapter->rrd_ring;
  1500. struct sk_buff *skb;
  1501. struct atl1c_recv_ret_status *rrs;
  1502. struct atl1c_buffer *buffer_info;
  1503. while (1) {
  1504. if (*work_done >= work_to_do)
  1505. break;
  1506. rrs = ATL1C_RRD_DESC(rrd_ring, rrd_ring->next_to_clean);
  1507. if (likely(RRS_RXD_IS_VALID(rrs->word3))) {
  1508. rfd_num = (rrs->word0 >> RRS_RX_RFD_CNT_SHIFT) &
  1509. RRS_RX_RFD_CNT_MASK;
  1510. if (unlikely(rfd_num != 1))
  1511. /* TODO support mul rfd*/
  1512. if (netif_msg_rx_err(adapter))
  1513. dev_warn(&pdev->dev,
  1514. "Multi rfd not support yet!\n");
  1515. goto rrs_checked;
  1516. } else {
  1517. break;
  1518. }
  1519. rrs_checked:
  1520. atl1c_clean_rrd(rrd_ring, rrs, rfd_num);
  1521. if (rrs->word3 & (RRS_RX_ERR_SUM | RRS_802_3_LEN_ERR)) {
  1522. atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
  1523. if (netif_msg_rx_err(adapter))
  1524. dev_warn(&pdev->dev,
  1525. "wrong packet! rrs word3 is %x\n",
  1526. rrs->word3);
  1527. continue;
  1528. }
  1529. length = le16_to_cpu((rrs->word3 >> RRS_PKT_SIZE_SHIFT) &
  1530. RRS_PKT_SIZE_MASK);
  1531. /* Good Receive */
  1532. if (likely(rfd_num == 1)) {
  1533. rfd_index = (rrs->word0 >> RRS_RX_RFD_INDEX_SHIFT) &
  1534. RRS_RX_RFD_INDEX_MASK;
  1535. buffer_info = &rfd_ring->buffer_info[rfd_index];
  1536. pci_unmap_single(pdev, buffer_info->dma,
  1537. buffer_info->length, PCI_DMA_FROMDEVICE);
  1538. skb = buffer_info->skb;
  1539. } else {
  1540. /* TODO */
  1541. if (netif_msg_rx_err(adapter))
  1542. dev_warn(&pdev->dev,
  1543. "Multi rfd not support yet!\n");
  1544. break;
  1545. }
  1546. atl1c_clean_rfd(rfd_ring, rrs, rfd_num);
  1547. skb_put(skb, length - ETH_FCS_LEN);
  1548. skb->protocol = eth_type_trans(skb, netdev);
  1549. atl1c_rx_checksum(adapter, skb, rrs);
  1550. if (rrs->word3 & RRS_VLAN_INS) {
  1551. u16 vlan;
  1552. AT_TAG_TO_VLAN(rrs->vlan_tag, vlan);
  1553. vlan = le16_to_cpu(vlan);
  1554. __vlan_hwaccel_put_tag(skb, vlan);
  1555. }
  1556. netif_receive_skb(skb);
  1557. (*work_done)++;
  1558. count++;
  1559. }
  1560. if (count)
  1561. atl1c_alloc_rx_buffer(adapter);
  1562. }
  1563. /*
  1564. * atl1c_clean - NAPI Rx polling callback
  1565. * @adapter: board private structure
  1566. */
  1567. static int atl1c_clean(struct napi_struct *napi, int budget)
  1568. {
  1569. struct atl1c_adapter *adapter =
  1570. container_of(napi, struct atl1c_adapter, napi);
  1571. int work_done = 0;
  1572. /* Keep link state information with original netdev */
  1573. if (!netif_carrier_ok(adapter->netdev))
  1574. goto quit_polling;
  1575. /* just enable one RXQ */
  1576. atl1c_clean_rx_irq(adapter, &work_done, budget);
  1577. if (work_done < budget) {
  1578. quit_polling:
  1579. napi_complete(napi);
  1580. adapter->hw.intr_mask |= ISR_RX_PKT;
  1581. AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
  1582. }
  1583. return work_done;
  1584. }
  1585. #ifdef CONFIG_NET_POLL_CONTROLLER
  1586. /*
  1587. * Polling 'interrupt' - used by things like netconsole to send skbs
  1588. * without having to re-enable interrupts. It's not called while
  1589. * the interrupt routine is executing.
  1590. */
  1591. static void atl1c_netpoll(struct net_device *netdev)
  1592. {
  1593. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1594. disable_irq(adapter->pdev->irq);
  1595. atl1c_intr(adapter->pdev->irq, netdev);
  1596. enable_irq(adapter->pdev->irq);
  1597. }
  1598. #endif
  1599. static inline u16 atl1c_tpd_avail(struct atl1c_adapter *adapter, enum atl1c_trans_queue type)
  1600. {
  1601. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1602. u16 next_to_use = 0;
  1603. u16 next_to_clean = 0;
  1604. next_to_clean = atomic_read(&tpd_ring->next_to_clean);
  1605. next_to_use = tpd_ring->next_to_use;
  1606. return (u16)(next_to_clean > next_to_use) ?
  1607. (next_to_clean - next_to_use - 1) :
  1608. (tpd_ring->count + next_to_clean - next_to_use - 1);
  1609. }
  1610. /*
  1611. * get next usable tpd
  1612. * Note: should call atl1c_tdp_avail to make sure
  1613. * there is enough tpd to use
  1614. */
  1615. static struct atl1c_tpd_desc *atl1c_get_tpd(struct atl1c_adapter *adapter,
  1616. enum atl1c_trans_queue type)
  1617. {
  1618. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1619. struct atl1c_tpd_desc *tpd_desc;
  1620. u16 next_to_use = 0;
  1621. next_to_use = tpd_ring->next_to_use;
  1622. if (++tpd_ring->next_to_use == tpd_ring->count)
  1623. tpd_ring->next_to_use = 0;
  1624. tpd_desc = ATL1C_TPD_DESC(tpd_ring, next_to_use);
  1625. memset(tpd_desc, 0, sizeof(struct atl1c_tpd_desc));
  1626. return tpd_desc;
  1627. }
  1628. static struct atl1c_buffer *
  1629. atl1c_get_tx_buffer(struct atl1c_adapter *adapter, struct atl1c_tpd_desc *tpd)
  1630. {
  1631. struct atl1c_tpd_ring *tpd_ring = adapter->tpd_ring;
  1632. return &tpd_ring->buffer_info[tpd -
  1633. (struct atl1c_tpd_desc *)tpd_ring->desc];
  1634. }
  1635. /* Calculate the transmit packet descript needed*/
  1636. static u16 atl1c_cal_tpd_req(const struct sk_buff *skb)
  1637. {
  1638. u16 tpd_req;
  1639. u16 proto_hdr_len = 0;
  1640. tpd_req = skb_shinfo(skb)->nr_frags + 1;
  1641. if (skb_is_gso(skb)) {
  1642. proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  1643. if (proto_hdr_len < skb_headlen(skb))
  1644. tpd_req++;
  1645. if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
  1646. tpd_req++;
  1647. }
  1648. return tpd_req;
  1649. }
  1650. static int atl1c_tso_csum(struct atl1c_adapter *adapter,
  1651. struct sk_buff *skb,
  1652. struct atl1c_tpd_desc **tpd,
  1653. enum atl1c_trans_queue type)
  1654. {
  1655. struct pci_dev *pdev = adapter->pdev;
  1656. u8 hdr_len;
  1657. u32 real_len;
  1658. unsigned short offload_type;
  1659. int err;
  1660. if (skb_is_gso(skb)) {
  1661. if (skb_header_cloned(skb)) {
  1662. err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
  1663. if (unlikely(err))
  1664. return -1;
  1665. }
  1666. offload_type = skb_shinfo(skb)->gso_type;
  1667. if (offload_type & SKB_GSO_TCPV4) {
  1668. real_len = (((unsigned char *)ip_hdr(skb) - skb->data)
  1669. + ntohs(ip_hdr(skb)->tot_len));
  1670. if (real_len < skb->len)
  1671. pskb_trim(skb, real_len);
  1672. hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
  1673. if (unlikely(skb->len == hdr_len)) {
  1674. /* only xsum need */
  1675. if (netif_msg_tx_queued(adapter))
  1676. dev_warn(&pdev->dev,
  1677. "IPV4 tso with zero data??\n");
  1678. goto check_sum;
  1679. } else {
  1680. ip_hdr(skb)->check = 0;
  1681. tcp_hdr(skb)->check = ~csum_tcpudp_magic(
  1682. ip_hdr(skb)->saddr,
  1683. ip_hdr(skb)->daddr,
  1684. 0, IPPROTO_TCP, 0);
  1685. (*tpd)->word1 |= 1 << TPD_IPV4_PACKET_SHIFT;
  1686. }
  1687. }
  1688. if (offload_type & SKB_GSO_TCPV6) {
  1689. struct atl1c_tpd_ext_desc *etpd =
  1690. *(struct atl1c_tpd_ext_desc **)(tpd);
  1691. memset(etpd, 0, sizeof(struct atl1c_tpd_ext_desc));
  1692. *tpd = atl1c_get_tpd(adapter, type);
  1693. ipv6_hdr(skb)->payload_len = 0;
  1694. /* check payload == 0 byte ? */
  1695. hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
  1696. if (unlikely(skb->len == hdr_len)) {
  1697. /* only xsum need */
  1698. if (netif_msg_tx_queued(adapter))
  1699. dev_warn(&pdev->dev,
  1700. "IPV6 tso with zero data??\n");
  1701. goto check_sum;
  1702. } else
  1703. tcp_hdr(skb)->check = ~csum_ipv6_magic(
  1704. &ipv6_hdr(skb)->saddr,
  1705. &ipv6_hdr(skb)->daddr,
  1706. 0, IPPROTO_TCP, 0);
  1707. etpd->word1 |= 1 << TPD_LSO_EN_SHIFT;
  1708. etpd->word1 |= 1 << TPD_LSO_VER_SHIFT;
  1709. etpd->pkt_len = cpu_to_le32(skb->len);
  1710. (*tpd)->word1 |= 1 << TPD_LSO_VER_SHIFT;
  1711. }
  1712. (*tpd)->word1 |= 1 << TPD_LSO_EN_SHIFT;
  1713. (*tpd)->word1 |= (skb_transport_offset(skb) & TPD_TCPHDR_OFFSET_MASK) <<
  1714. TPD_TCPHDR_OFFSET_SHIFT;
  1715. (*tpd)->word1 |= (skb_shinfo(skb)->gso_size & TPD_MSS_MASK) <<
  1716. TPD_MSS_SHIFT;
  1717. return 0;
  1718. }
  1719. check_sum:
  1720. if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
  1721. u8 css, cso;
  1722. cso = skb_checksum_start_offset(skb);
  1723. if (unlikely(cso & 0x1)) {
  1724. if (netif_msg_tx_err(adapter))
  1725. dev_err(&adapter->pdev->dev,
  1726. "payload offset should not an event number\n");
  1727. return -1;
  1728. } else {
  1729. css = cso + skb->csum_offset;
  1730. (*tpd)->word1 |= ((cso >> 1) & TPD_PLOADOFFSET_MASK) <<
  1731. TPD_PLOADOFFSET_SHIFT;
  1732. (*tpd)->word1 |= ((css >> 1) & TPD_CCSUM_OFFSET_MASK) <<
  1733. TPD_CCSUM_OFFSET_SHIFT;
  1734. (*tpd)->word1 |= 1 << TPD_CCSUM_EN_SHIFT;
  1735. }
  1736. }
  1737. return 0;
  1738. }
  1739. static void atl1c_tx_map(struct atl1c_adapter *adapter,
  1740. struct sk_buff *skb, struct atl1c_tpd_desc *tpd,
  1741. enum atl1c_trans_queue type)
  1742. {
  1743. struct atl1c_tpd_desc *use_tpd = NULL;
  1744. struct atl1c_buffer *buffer_info = NULL;
  1745. u16 buf_len = skb_headlen(skb);
  1746. u16 map_len = 0;
  1747. u16 mapped_len = 0;
  1748. u16 hdr_len = 0;
  1749. u16 nr_frags;
  1750. u16 f;
  1751. int tso;
  1752. nr_frags = skb_shinfo(skb)->nr_frags;
  1753. tso = (tpd->word1 >> TPD_LSO_EN_SHIFT) & TPD_LSO_EN_MASK;
  1754. if (tso) {
  1755. /* TSO */
  1756. map_len = hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
  1757. use_tpd = tpd;
  1758. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1759. buffer_info->length = map_len;
  1760. buffer_info->dma = pci_map_single(adapter->pdev,
  1761. skb->data, hdr_len, PCI_DMA_TODEVICE);
  1762. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1763. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1764. ATL1C_PCIMAP_TODEVICE);
  1765. mapped_len += map_len;
  1766. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1767. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1768. }
  1769. if (mapped_len < buf_len) {
  1770. /* mapped_len == 0, means we should use the first tpd,
  1771. which is given by caller */
  1772. if (mapped_len == 0)
  1773. use_tpd = tpd;
  1774. else {
  1775. use_tpd = atl1c_get_tpd(adapter, type);
  1776. memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
  1777. }
  1778. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1779. buffer_info->length = buf_len - mapped_len;
  1780. buffer_info->dma =
  1781. pci_map_single(adapter->pdev, skb->data + mapped_len,
  1782. buffer_info->length, PCI_DMA_TODEVICE);
  1783. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1784. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_SINGLE,
  1785. ATL1C_PCIMAP_TODEVICE);
  1786. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1787. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1788. }
  1789. for (f = 0; f < nr_frags; f++) {
  1790. struct skb_frag_struct *frag;
  1791. frag = &skb_shinfo(skb)->frags[f];
  1792. use_tpd = atl1c_get_tpd(adapter, type);
  1793. memcpy(use_tpd, tpd, sizeof(struct atl1c_tpd_desc));
  1794. buffer_info = atl1c_get_tx_buffer(adapter, use_tpd);
  1795. buffer_info->length = skb_frag_size(frag);
  1796. buffer_info->dma = skb_frag_dma_map(&adapter->pdev->dev,
  1797. frag, 0,
  1798. buffer_info->length,
  1799. DMA_TO_DEVICE);
  1800. ATL1C_SET_BUFFER_STATE(buffer_info, ATL1C_BUFFER_BUSY);
  1801. ATL1C_SET_PCIMAP_TYPE(buffer_info, ATL1C_PCIMAP_PAGE,
  1802. ATL1C_PCIMAP_TODEVICE);
  1803. use_tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
  1804. use_tpd->buffer_len = cpu_to_le16(buffer_info->length);
  1805. }
  1806. /* The last tpd */
  1807. use_tpd->word1 |= 1 << TPD_EOP_SHIFT;
  1808. /* The last buffer info contain the skb address,
  1809. so it will be free after unmap */
  1810. buffer_info->skb = skb;
  1811. }
  1812. static void atl1c_tx_queue(struct atl1c_adapter *adapter, struct sk_buff *skb,
  1813. struct atl1c_tpd_desc *tpd, enum atl1c_trans_queue type)
  1814. {
  1815. struct atl1c_tpd_ring *tpd_ring = &adapter->tpd_ring[type];
  1816. u16 reg;
  1817. reg = type == atl1c_trans_high ? REG_TPD_PRI1_PIDX : REG_TPD_PRI0_PIDX;
  1818. AT_WRITE_REGW(&adapter->hw, reg, tpd_ring->next_to_use);
  1819. }
  1820. static netdev_tx_t atl1c_xmit_frame(struct sk_buff *skb,
  1821. struct net_device *netdev)
  1822. {
  1823. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1824. unsigned long flags;
  1825. u16 tpd_req = 1;
  1826. struct atl1c_tpd_desc *tpd;
  1827. enum atl1c_trans_queue type = atl1c_trans_normal;
  1828. if (test_bit(__AT_DOWN, &adapter->flags)) {
  1829. dev_kfree_skb_any(skb);
  1830. return NETDEV_TX_OK;
  1831. }
  1832. tpd_req = atl1c_cal_tpd_req(skb);
  1833. if (!spin_trylock_irqsave(&adapter->tx_lock, flags)) {
  1834. if (netif_msg_pktdata(adapter))
  1835. dev_info(&adapter->pdev->dev, "tx locked\n");
  1836. return NETDEV_TX_LOCKED;
  1837. }
  1838. if (atl1c_tpd_avail(adapter, type) < tpd_req) {
  1839. /* no enough descriptor, just stop queue */
  1840. netif_stop_queue(netdev);
  1841. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1842. return NETDEV_TX_BUSY;
  1843. }
  1844. tpd = atl1c_get_tpd(adapter, type);
  1845. /* do TSO and check sum */
  1846. if (atl1c_tso_csum(adapter, skb, &tpd, type) != 0) {
  1847. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1848. dev_kfree_skb_any(skb);
  1849. return NETDEV_TX_OK;
  1850. }
  1851. if (unlikely(vlan_tx_tag_present(skb))) {
  1852. u16 vlan = vlan_tx_tag_get(skb);
  1853. __le16 tag;
  1854. vlan = cpu_to_le16(vlan);
  1855. AT_VLAN_TO_TAG(vlan, tag);
  1856. tpd->word1 |= 1 << TPD_INS_VTAG_SHIFT;
  1857. tpd->vlan_tag = tag;
  1858. }
  1859. if (skb_network_offset(skb) != ETH_HLEN)
  1860. tpd->word1 |= 1 << TPD_ETH_TYPE_SHIFT; /* Ethernet frame */
  1861. atl1c_tx_map(adapter, skb, tpd, type);
  1862. atl1c_tx_queue(adapter, skb, tpd, type);
  1863. spin_unlock_irqrestore(&adapter->tx_lock, flags);
  1864. return NETDEV_TX_OK;
  1865. }
  1866. static void atl1c_free_irq(struct atl1c_adapter *adapter)
  1867. {
  1868. struct net_device *netdev = adapter->netdev;
  1869. free_irq(adapter->pdev->irq, netdev);
  1870. if (adapter->have_msi)
  1871. pci_disable_msi(adapter->pdev);
  1872. }
  1873. static int atl1c_request_irq(struct atl1c_adapter *adapter)
  1874. {
  1875. struct pci_dev *pdev = adapter->pdev;
  1876. struct net_device *netdev = adapter->netdev;
  1877. int flags = 0;
  1878. int err = 0;
  1879. adapter->have_msi = true;
  1880. err = pci_enable_msi(adapter->pdev);
  1881. if (err) {
  1882. if (netif_msg_ifup(adapter))
  1883. dev_err(&pdev->dev,
  1884. "Unable to allocate MSI interrupt Error: %d\n",
  1885. err);
  1886. adapter->have_msi = false;
  1887. }
  1888. if (!adapter->have_msi)
  1889. flags |= IRQF_SHARED;
  1890. err = request_irq(adapter->pdev->irq, atl1c_intr, flags,
  1891. netdev->name, netdev);
  1892. if (err) {
  1893. if (netif_msg_ifup(adapter))
  1894. dev_err(&pdev->dev,
  1895. "Unable to allocate interrupt Error: %d\n",
  1896. err);
  1897. if (adapter->have_msi)
  1898. pci_disable_msi(adapter->pdev);
  1899. return err;
  1900. }
  1901. if (netif_msg_ifup(adapter))
  1902. dev_dbg(&pdev->dev, "atl1c_request_irq OK\n");
  1903. return err;
  1904. }
  1905. static int atl1c_up(struct atl1c_adapter *adapter)
  1906. {
  1907. struct net_device *netdev = adapter->netdev;
  1908. int num;
  1909. int err;
  1910. netif_carrier_off(netdev);
  1911. atl1c_init_ring_ptrs(adapter);
  1912. atl1c_set_multi(netdev);
  1913. atl1c_restore_vlan(adapter);
  1914. num = atl1c_alloc_rx_buffer(adapter);
  1915. if (unlikely(num == 0)) {
  1916. err = -ENOMEM;
  1917. goto err_alloc_rx;
  1918. }
  1919. if (atl1c_configure(adapter)) {
  1920. err = -EIO;
  1921. goto err_up;
  1922. }
  1923. err = atl1c_request_irq(adapter);
  1924. if (unlikely(err))
  1925. goto err_up;
  1926. clear_bit(__AT_DOWN, &adapter->flags);
  1927. napi_enable(&adapter->napi);
  1928. atl1c_irq_enable(adapter);
  1929. atl1c_check_link_status(adapter);
  1930. netif_start_queue(netdev);
  1931. return err;
  1932. err_up:
  1933. err_alloc_rx:
  1934. atl1c_clean_rx_ring(adapter);
  1935. return err;
  1936. }
  1937. static void atl1c_down(struct atl1c_adapter *adapter)
  1938. {
  1939. struct net_device *netdev = adapter->netdev;
  1940. atl1c_del_timer(adapter);
  1941. adapter->work_event = 0; /* clear all event */
  1942. /* signal that we're down so the interrupt handler does not
  1943. * reschedule our watchdog timer */
  1944. set_bit(__AT_DOWN, &adapter->flags);
  1945. netif_carrier_off(netdev);
  1946. napi_disable(&adapter->napi);
  1947. atl1c_irq_disable(adapter);
  1948. atl1c_free_irq(adapter);
  1949. /* disable ASPM if device inactive */
  1950. atl1c_disable_l0s_l1(&adapter->hw);
  1951. /* reset MAC to disable all RX/TX */
  1952. atl1c_reset_mac(&adapter->hw);
  1953. msleep(1);
  1954. adapter->link_speed = SPEED_0;
  1955. adapter->link_duplex = -1;
  1956. atl1c_clean_tx_ring(adapter, atl1c_trans_normal);
  1957. atl1c_clean_tx_ring(adapter, atl1c_trans_high);
  1958. atl1c_clean_rx_ring(adapter);
  1959. }
  1960. /*
  1961. * atl1c_open - Called when a network interface is made active
  1962. * @netdev: network interface device structure
  1963. *
  1964. * Returns 0 on success, negative value on failure
  1965. *
  1966. * The open entry point is called when a network interface is made
  1967. * active by the system (IFF_UP). At this point all resources needed
  1968. * for transmit and receive operations are allocated, the interrupt
  1969. * handler is registered with the OS, the watchdog timer is started,
  1970. * and the stack is notified that the interface is ready.
  1971. */
  1972. static int atl1c_open(struct net_device *netdev)
  1973. {
  1974. struct atl1c_adapter *adapter = netdev_priv(netdev);
  1975. int err;
  1976. /* disallow open during test */
  1977. if (test_bit(__AT_TESTING, &adapter->flags))
  1978. return -EBUSY;
  1979. /* allocate rx/tx dma buffer & descriptors */
  1980. err = atl1c_setup_ring_resources(adapter);
  1981. if (unlikely(err))
  1982. return err;
  1983. err = atl1c_up(adapter);
  1984. if (unlikely(err))
  1985. goto err_up;
  1986. return 0;
  1987. err_up:
  1988. atl1c_free_irq(adapter);
  1989. atl1c_free_ring_resources(adapter);
  1990. atl1c_reset_mac(&adapter->hw);
  1991. return err;
  1992. }
  1993. /*
  1994. * atl1c_close - Disables a network interface
  1995. * @netdev: network interface device structure
  1996. *
  1997. * Returns 0, this is not allowed to fail
  1998. *
  1999. * The close entry point is called when an interface is de-activated
  2000. * by the OS. The hardware is still under the drivers control, but
  2001. * needs to be disabled. A global MAC reset is issued to stop the
  2002. * hardware, and all transmit and receive resources are freed.
  2003. */
  2004. static int atl1c_close(struct net_device *netdev)
  2005. {
  2006. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2007. WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
  2008. atl1c_down(adapter);
  2009. atl1c_free_ring_resources(adapter);
  2010. return 0;
  2011. }
  2012. static int atl1c_suspend(struct device *dev)
  2013. {
  2014. struct pci_dev *pdev = to_pci_dev(dev);
  2015. struct net_device *netdev = pci_get_drvdata(pdev);
  2016. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2017. struct atl1c_hw *hw = &adapter->hw;
  2018. u32 mac_ctrl_data = 0;
  2019. u32 master_ctrl_data = 0;
  2020. u32 wol_ctrl_data = 0;
  2021. u16 mii_intr_status_data = 0;
  2022. u32 wufc = adapter->wol;
  2023. u32 phy_ctrl_data;
  2024. atl1c_disable_l0s_l1(hw);
  2025. if (netif_running(netdev)) {
  2026. WARN_ON(test_bit(__AT_RESETTING, &adapter->flags));
  2027. atl1c_down(adapter);
  2028. }
  2029. netif_device_detach(netdev);
  2030. if (wufc)
  2031. if (atl1c_phy_power_saving(hw) != 0)
  2032. dev_dbg(&pdev->dev, "phy power saving failed");
  2033. AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl_data);
  2034. AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl_data);
  2035. AT_READ_REG(hw, REG_GPHY_CTRL, &phy_ctrl_data);
  2036. master_ctrl_data &= ~MASTER_CTRL_CLK_SEL_DIS;
  2037. mac_ctrl_data &= ~(MAC_CTRL_PRMLEN_MASK << MAC_CTRL_PRMLEN_SHIFT);
  2038. mac_ctrl_data |= (((u32)adapter->hw.preamble_len &
  2039. MAC_CTRL_PRMLEN_MASK) <<
  2040. MAC_CTRL_PRMLEN_SHIFT);
  2041. mac_ctrl_data &= ~(MAC_CTRL_SPEED_MASK << MAC_CTRL_SPEED_SHIFT);
  2042. mac_ctrl_data &= ~MAC_CTRL_DUPLX;
  2043. phy_ctrl_data &= ~(GPHY_CTRL_EXT_RESET | GPHY_CTRL_CLS);
  2044. phy_ctrl_data |= GPHY_CTRL_SEL_ANA_RST | GPHY_CTRL_HIB_PULSE |
  2045. GPHY_CTRL_HIB_EN;
  2046. if (wufc) {
  2047. mac_ctrl_data |= MAC_CTRL_RX_EN;
  2048. phy_ctrl_data |= GPHY_CTRL_EXT_RESET;
  2049. if (adapter->link_speed == SPEED_1000 ||
  2050. adapter->link_speed == SPEED_0) {
  2051. mac_ctrl_data |= atl1c_mac_speed_1000 <<
  2052. MAC_CTRL_SPEED_SHIFT;
  2053. mac_ctrl_data |= MAC_CTRL_DUPLX;
  2054. } else
  2055. mac_ctrl_data |= atl1c_mac_speed_10_100 <<
  2056. MAC_CTRL_SPEED_SHIFT;
  2057. if (adapter->link_duplex == DUPLEX_FULL)
  2058. mac_ctrl_data |= MAC_CTRL_DUPLX;
  2059. /* turn on magic packet wol */
  2060. if (wufc & AT_WUFC_MAG) {
  2061. wol_ctrl_data |= WOL_MAGIC_EN | WOL_MAGIC_PME_EN;
  2062. if (hw->nic_type == athr_l2c_b &&
  2063. hw->revision_id == L2CB_V11) {
  2064. wol_ctrl_data |=
  2065. WOL_PATTERN_EN | WOL_PATTERN_PME_EN;
  2066. }
  2067. }
  2068. if (wufc & AT_WUFC_LNKC) {
  2069. wol_ctrl_data |= WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN;
  2070. /* only link up can wake up */
  2071. if (atl1c_write_phy_reg(hw, MII_IER, IER_LINK_UP) != 0) {
  2072. dev_dbg(&pdev->dev, "%s: read write phy "
  2073. "register failed.\n",
  2074. atl1c_driver_name);
  2075. }
  2076. }
  2077. /* clear phy interrupt */
  2078. atl1c_read_phy_reg(hw, MII_ISR, &mii_intr_status_data);
  2079. /* Config MAC Ctrl register */
  2080. __atl1c_vlan_mode(netdev->features, &mac_ctrl_data);
  2081. /* magic packet maybe Broadcast&multicast&Unicast frame */
  2082. if (wufc & AT_WUFC_MAG)
  2083. mac_ctrl_data |= MAC_CTRL_BC_EN;
  2084. dev_dbg(&pdev->dev,
  2085. "%s: suspend MAC=0x%x\n",
  2086. atl1c_driver_name, mac_ctrl_data);
  2087. } else {
  2088. master_ctrl_data |= MASTER_CTRL_CLK_SEL_DIS;
  2089. mac_ctrl_data |= atl1c_mac_speed_10_100 << MAC_CTRL_SPEED_SHIFT;
  2090. mac_ctrl_data |= MAC_CTRL_DUPLX;
  2091. phy_ctrl_data |= GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PWDOWN_HW;
  2092. wol_ctrl_data = 0;
  2093. hw->phy_configured = false; /* re-init PHY when resume */
  2094. }
  2095. AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
  2096. AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
  2097. AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data);
  2098. AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
  2099. return 0;
  2100. }
  2101. #ifdef CONFIG_PM_SLEEP
  2102. static int atl1c_resume(struct device *dev)
  2103. {
  2104. struct pci_dev *pdev = to_pci_dev(dev);
  2105. struct net_device *netdev = pci_get_drvdata(pdev);
  2106. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2107. AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
  2108. atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE);
  2109. atl1c_phy_reset(&adapter->hw);
  2110. atl1c_reset_mac(&adapter->hw);
  2111. atl1c_phy_init(&adapter->hw);
  2112. #if 0
  2113. AT_READ_REG(&adapter->hw, REG_PM_CTRLSTAT, &pm_data);
  2114. pm_data &= ~PM_CTRLSTAT_PME_EN;
  2115. AT_WRITE_REG(&adapter->hw, REG_PM_CTRLSTAT, pm_data);
  2116. #endif
  2117. netif_device_attach(netdev);
  2118. if (netif_running(netdev))
  2119. atl1c_up(adapter);
  2120. return 0;
  2121. }
  2122. #endif
  2123. static void atl1c_shutdown(struct pci_dev *pdev)
  2124. {
  2125. struct net_device *netdev = pci_get_drvdata(pdev);
  2126. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2127. atl1c_suspend(&pdev->dev);
  2128. pci_wake_from_d3(pdev, adapter->wol);
  2129. pci_set_power_state(pdev, PCI_D3hot);
  2130. }
  2131. static const struct net_device_ops atl1c_netdev_ops = {
  2132. .ndo_open = atl1c_open,
  2133. .ndo_stop = atl1c_close,
  2134. .ndo_validate_addr = eth_validate_addr,
  2135. .ndo_start_xmit = atl1c_xmit_frame,
  2136. .ndo_set_mac_address = atl1c_set_mac_addr,
  2137. .ndo_set_rx_mode = atl1c_set_multi,
  2138. .ndo_change_mtu = atl1c_change_mtu,
  2139. .ndo_fix_features = atl1c_fix_features,
  2140. .ndo_set_features = atl1c_set_features,
  2141. .ndo_do_ioctl = atl1c_ioctl,
  2142. .ndo_tx_timeout = atl1c_tx_timeout,
  2143. .ndo_get_stats = atl1c_get_stats,
  2144. #ifdef CONFIG_NET_POLL_CONTROLLER
  2145. .ndo_poll_controller = atl1c_netpoll,
  2146. #endif
  2147. };
  2148. static int atl1c_init_netdev(struct net_device *netdev, struct pci_dev *pdev)
  2149. {
  2150. SET_NETDEV_DEV(netdev, &pdev->dev);
  2151. pci_set_drvdata(pdev, netdev);
  2152. netdev->netdev_ops = &atl1c_netdev_ops;
  2153. netdev->watchdog_timeo = AT_TX_WATCHDOG;
  2154. atl1c_set_ethtool_ops(netdev);
  2155. /* TODO: add when ready */
  2156. netdev->hw_features = NETIF_F_SG |
  2157. NETIF_F_HW_CSUM |
  2158. NETIF_F_HW_VLAN_RX |
  2159. NETIF_F_TSO |
  2160. NETIF_F_TSO6;
  2161. netdev->features = netdev->hw_features |
  2162. NETIF_F_HW_VLAN_TX;
  2163. return 0;
  2164. }
  2165. /*
  2166. * atl1c_probe - Device Initialization Routine
  2167. * @pdev: PCI device information struct
  2168. * @ent: entry in atl1c_pci_tbl
  2169. *
  2170. * Returns 0 on success, negative on failure
  2171. *
  2172. * atl1c_probe initializes an adapter identified by a pci_dev structure.
  2173. * The OS initialization, configuring of the adapter private structure,
  2174. * and a hardware reset occur.
  2175. */
  2176. static int __devinit atl1c_probe(struct pci_dev *pdev,
  2177. const struct pci_device_id *ent)
  2178. {
  2179. struct net_device *netdev;
  2180. struct atl1c_adapter *adapter;
  2181. static int cards_found;
  2182. int err = 0;
  2183. /* enable device (incl. PCI PM wakeup and hotplug setup) */
  2184. err = pci_enable_device_mem(pdev);
  2185. if (err) {
  2186. dev_err(&pdev->dev, "cannot enable PCI device\n");
  2187. return err;
  2188. }
  2189. /*
  2190. * The atl1c chip can DMA to 64-bit addresses, but it uses a single
  2191. * shared register for the high 32 bits, so only a single, aligned,
  2192. * 4 GB physical address range can be used at a time.
  2193. *
  2194. * Supporting 64-bit DMA on this hardware is more trouble than it's
  2195. * worth. It is far easier to limit to 32-bit DMA than update
  2196. * various kernel subsystems to support the mechanics required by a
  2197. * fixed-high-32-bit system.
  2198. */
  2199. if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
  2200. (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
  2201. dev_err(&pdev->dev, "No usable DMA configuration,aborting\n");
  2202. goto err_dma;
  2203. }
  2204. err = pci_request_regions(pdev, atl1c_driver_name);
  2205. if (err) {
  2206. dev_err(&pdev->dev, "cannot obtain PCI resources\n");
  2207. goto err_pci_reg;
  2208. }
  2209. pci_set_master(pdev);
  2210. netdev = alloc_etherdev(sizeof(struct atl1c_adapter));
  2211. if (netdev == NULL) {
  2212. err = -ENOMEM;
  2213. goto err_alloc_etherdev;
  2214. }
  2215. err = atl1c_init_netdev(netdev, pdev);
  2216. if (err) {
  2217. dev_err(&pdev->dev, "init netdevice failed\n");
  2218. goto err_init_netdev;
  2219. }
  2220. adapter = netdev_priv(netdev);
  2221. adapter->bd_number = cards_found;
  2222. adapter->netdev = netdev;
  2223. adapter->pdev = pdev;
  2224. adapter->hw.adapter = adapter;
  2225. adapter->msg_enable = netif_msg_init(-1, atl1c_default_msg);
  2226. adapter->hw.hw_addr = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
  2227. if (!adapter->hw.hw_addr) {
  2228. err = -EIO;
  2229. dev_err(&pdev->dev, "cannot map device registers\n");
  2230. goto err_ioremap;
  2231. }
  2232. /* init mii data */
  2233. adapter->mii.dev = netdev;
  2234. adapter->mii.mdio_read = atl1c_mdio_read;
  2235. adapter->mii.mdio_write = atl1c_mdio_write;
  2236. adapter->mii.phy_id_mask = 0x1f;
  2237. adapter->mii.reg_num_mask = MDIO_CTRL_REG_MASK;
  2238. netif_napi_add(netdev, &adapter->napi, atl1c_clean, 64);
  2239. setup_timer(&adapter->phy_config_timer, atl1c_phy_config,
  2240. (unsigned long)adapter);
  2241. /* setup the private structure */
  2242. err = atl1c_sw_init(adapter);
  2243. if (err) {
  2244. dev_err(&pdev->dev, "net device private data init failed\n");
  2245. goto err_sw_init;
  2246. }
  2247. atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE);
  2248. /* Init GPHY as early as possible due to power saving issue */
  2249. atl1c_phy_reset(&adapter->hw);
  2250. err = atl1c_reset_mac(&adapter->hw);
  2251. if (err) {
  2252. err = -EIO;
  2253. goto err_reset;
  2254. }
  2255. /* reset the controller to
  2256. * put the device in a known good starting state */
  2257. err = atl1c_phy_init(&adapter->hw);
  2258. if (err) {
  2259. err = -EIO;
  2260. goto err_reset;
  2261. }
  2262. if (atl1c_read_mac_addr(&adapter->hw)) {
  2263. /* got a random MAC address, set NET_ADDR_RANDOM to netdev */
  2264. netdev->addr_assign_type |= NET_ADDR_RANDOM;
  2265. }
  2266. memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
  2267. memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
  2268. if (netif_msg_probe(adapter))
  2269. dev_dbg(&pdev->dev, "mac address : %pM\n",
  2270. adapter->hw.mac_addr);
  2271. atl1c_hw_set_mac_addr(&adapter->hw);
  2272. INIT_WORK(&adapter->common_task, atl1c_common_task);
  2273. adapter->work_event = 0;
  2274. err = register_netdev(netdev);
  2275. if (err) {
  2276. dev_err(&pdev->dev, "register netdevice failed\n");
  2277. goto err_register;
  2278. }
  2279. if (netif_msg_probe(adapter))
  2280. dev_info(&pdev->dev, "version %s\n", ATL1C_DRV_VERSION);
  2281. cards_found++;
  2282. return 0;
  2283. err_reset:
  2284. err_register:
  2285. err_sw_init:
  2286. iounmap(adapter->hw.hw_addr);
  2287. err_init_netdev:
  2288. err_ioremap:
  2289. free_netdev(netdev);
  2290. err_alloc_etherdev:
  2291. pci_release_regions(pdev);
  2292. err_pci_reg:
  2293. err_dma:
  2294. pci_disable_device(pdev);
  2295. return err;
  2296. }
  2297. /*
  2298. * atl1c_remove - Device Removal Routine
  2299. * @pdev: PCI device information struct
  2300. *
  2301. * atl1c_remove is called by the PCI subsystem to alert the driver
  2302. * that it should release a PCI device. The could be caused by a
  2303. * Hot-Plug event, or because the driver is going to be removed from
  2304. * memory.
  2305. */
  2306. static void __devexit atl1c_remove(struct pci_dev *pdev)
  2307. {
  2308. struct net_device *netdev = pci_get_drvdata(pdev);
  2309. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2310. unregister_netdev(netdev);
  2311. atl1c_phy_disable(&adapter->hw);
  2312. iounmap(adapter->hw.hw_addr);
  2313. pci_release_regions(pdev);
  2314. pci_disable_device(pdev);
  2315. free_netdev(netdev);
  2316. }
  2317. /*
  2318. * atl1c_io_error_detected - called when PCI error is detected
  2319. * @pdev: Pointer to PCI device
  2320. * @state: The current pci connection state
  2321. *
  2322. * This function is called after a PCI bus error affecting
  2323. * this device has been detected.
  2324. */
  2325. static pci_ers_result_t atl1c_io_error_detected(struct pci_dev *pdev,
  2326. pci_channel_state_t state)
  2327. {
  2328. struct net_device *netdev = pci_get_drvdata(pdev);
  2329. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2330. netif_device_detach(netdev);
  2331. if (state == pci_channel_io_perm_failure)
  2332. return PCI_ERS_RESULT_DISCONNECT;
  2333. if (netif_running(netdev))
  2334. atl1c_down(adapter);
  2335. pci_disable_device(pdev);
  2336. /* Request a slot slot reset. */
  2337. return PCI_ERS_RESULT_NEED_RESET;
  2338. }
  2339. /*
  2340. * atl1c_io_slot_reset - called after the pci bus has been reset.
  2341. * @pdev: Pointer to PCI device
  2342. *
  2343. * Restart the card from scratch, as if from a cold-boot. Implementation
  2344. * resembles the first-half of the e1000_resume routine.
  2345. */
  2346. static pci_ers_result_t atl1c_io_slot_reset(struct pci_dev *pdev)
  2347. {
  2348. struct net_device *netdev = pci_get_drvdata(pdev);
  2349. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2350. if (pci_enable_device(pdev)) {
  2351. if (netif_msg_hw(adapter))
  2352. dev_err(&pdev->dev,
  2353. "Cannot re-enable PCI device after reset\n");
  2354. return PCI_ERS_RESULT_DISCONNECT;
  2355. }
  2356. pci_set_master(pdev);
  2357. pci_enable_wake(pdev, PCI_D3hot, 0);
  2358. pci_enable_wake(pdev, PCI_D3cold, 0);
  2359. atl1c_reset_mac(&adapter->hw);
  2360. return PCI_ERS_RESULT_RECOVERED;
  2361. }
  2362. /*
  2363. * atl1c_io_resume - called when traffic can start flowing again.
  2364. * @pdev: Pointer to PCI device
  2365. *
  2366. * This callback is called when the error recovery driver tells us that
  2367. * its OK to resume normal operation. Implementation resembles the
  2368. * second-half of the atl1c_resume routine.
  2369. */
  2370. static void atl1c_io_resume(struct pci_dev *pdev)
  2371. {
  2372. struct net_device *netdev = pci_get_drvdata(pdev);
  2373. struct atl1c_adapter *adapter = netdev_priv(netdev);
  2374. if (netif_running(netdev)) {
  2375. if (atl1c_up(adapter)) {
  2376. if (netif_msg_hw(adapter))
  2377. dev_err(&pdev->dev,
  2378. "Cannot bring device back up after reset\n");
  2379. return;
  2380. }
  2381. }
  2382. netif_device_attach(netdev);
  2383. }
  2384. static struct pci_error_handlers atl1c_err_handler = {
  2385. .error_detected = atl1c_io_error_detected,
  2386. .slot_reset = atl1c_io_slot_reset,
  2387. .resume = atl1c_io_resume,
  2388. };
  2389. static SIMPLE_DEV_PM_OPS(atl1c_pm_ops, atl1c_suspend, atl1c_resume);
  2390. static struct pci_driver atl1c_driver = {
  2391. .name = atl1c_driver_name,
  2392. .id_table = atl1c_pci_tbl,
  2393. .probe = atl1c_probe,
  2394. .remove = __devexit_p(atl1c_remove),
  2395. .shutdown = atl1c_shutdown,
  2396. .err_handler = &atl1c_err_handler,
  2397. .driver.pm = &atl1c_pm_ops,
  2398. };
  2399. /*
  2400. * atl1c_init_module - Driver Registration Routine
  2401. *
  2402. * atl1c_init_module is the first routine called when the driver is
  2403. * loaded. All it does is register with the PCI subsystem.
  2404. */
  2405. static int __init atl1c_init_module(void)
  2406. {
  2407. return pci_register_driver(&atl1c_driver);
  2408. }
  2409. /*
  2410. * atl1c_exit_module - Driver Exit Cleanup Routine
  2411. *
  2412. * atl1c_exit_module is called just before the driver is removed
  2413. * from memory.
  2414. */
  2415. static void __exit atl1c_exit_module(void)
  2416. {
  2417. pci_unregister_driver(&atl1c_driver);
  2418. }
  2419. module_init(atl1c_init_module);
  2420. module_exit(atl1c_exit_module);