gdth.c 182 KB

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  1. /************************************************************************
  2. * Linux driver for *
  3. * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
  4. * Intel Corporation: Storage RAID Controllers *
  5. * *
  6. * gdth.c *
  7. * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
  8. * Copyright (C) 2002-04 Intel Corporation *
  9. * Copyright (C) 2003-06 Adaptec Inc. *
  10. * <achim_leubner@adaptec.com> *
  11. * *
  12. * Additions/Fixes: *
  13. * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
  14. * Johannes Dinner <johannes_dinner@adaptec.com> *
  15. * *
  16. * This program is free software; you can redistribute it and/or modify *
  17. * it under the terms of the GNU General Public License as published *
  18. * by the Free Software Foundation; either version 2 of the License, *
  19. * or (at your option) any later version. *
  20. * *
  21. * This program is distributed in the hope that it will be useful, *
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  24. * GNU General Public License for more details. *
  25. * *
  26. * You should have received a copy of the GNU General Public License *
  27. * along with this kernel; if not, write to the Free Software *
  28. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  29. * *
  30. * Linux kernel 2.6.x supported *
  31. * *
  32. ************************************************************************/
  33. /* All GDT Disk Array Controllers are fully supported by this driver.
  34. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
  35. * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
  36. * list of all controller types.
  37. *
  38. * If you have one or more GDT3000/3020 EISA controllers with
  39. * controller BIOS disabled, you have to set the IRQ values with the
  40. * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
  41. * the IRQ values for the EISA controllers.
  42. *
  43. * After the optional list of IRQ values, other possible
  44. * command line options are:
  45. * disable:Y disable driver
  46. * disable:N enable driver
  47. * reserve_mode:0 reserve no drives for the raw service
  48. * reserve_mode:1 reserve all not init., removable drives
  49. * reserve_mode:2 reserve all not init. drives
  50. * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
  51. * h- controller no., b- channel no.,
  52. * t- target ID, l- LUN
  53. * reverse_scan:Y reverse scan order for PCI controllers
  54. * reverse_scan:N scan PCI controllers like BIOS
  55. * max_ids:x x - target ID count per channel (1..MAXID)
  56. * rescan:Y rescan all channels/IDs
  57. * rescan:N use all devices found until now
  58. * hdr_channel:x x - number of virtual bus for host drives
  59. * shared_access:Y disable driver reserve/release protocol to
  60. * access a shared resource from several nodes,
  61. * appropriate controller firmware required
  62. * shared_access:N enable driver reserve/release protocol
  63. * probe_eisa_isa:Y scan for EISA/ISA controllers
  64. * probe_eisa_isa:N do not scan for EISA/ISA controllers
  65. * force_dma32:Y use only 32 bit DMA mode
  66. * force_dma32:N use 64 bit DMA mode, if supported
  67. *
  68. * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
  69. * max_ids:127,rescan:N,hdr_channel:0,
  70. * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
  71. * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
  72. *
  73. * When loading the gdth driver as a module, the same options are available.
  74. * You can set the IRQs with "IRQ=...". However, the syntax to specify the
  75. * options changes slightly. You must replace all ',' between options
  76. * with ' ' and all ':' with '=' and you must use
  77. * '1' in place of 'Y' and '0' in place of 'N'.
  78. *
  79. * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
  80. * max_ids=127 rescan=0 hdr_channel=0 shared_access=0
  81. * probe_eisa_isa=0 force_dma32=0"
  82. * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
  83. */
  84. /* The meaning of the Scsi_Pointer members in this driver is as follows:
  85. * ptr: Chaining
  86. * this_residual: Command priority
  87. * buffer: phys. DMA sense buffer
  88. * dma_handle: phys. DMA buffer (kernel >= 2.4.0)
  89. * buffers_residual: Timeout value
  90. * Status: Command status (gdth_do_cmd()), DMA mem. mappings
  91. * Message: Additional info (gdth_do_cmd()), DMA direction
  92. * have_data_in: Flag for gdth_wait_completion()
  93. * sent_command: Opcode special command
  94. * phase: Service/parameter/return code special command
  95. */
  96. /* interrupt coalescing */
  97. /* #define INT_COAL */
  98. /* statistics */
  99. #define GDTH_STATISTICS
  100. #include <linux/module.h>
  101. #include <linux/version.h>
  102. #include <linux/kernel.h>
  103. #include <linux/types.h>
  104. #include <linux/pci.h>
  105. #include <linux/string.h>
  106. #include <linux/ctype.h>
  107. #include <linux/ioport.h>
  108. #include <linux/delay.h>
  109. #include <linux/interrupt.h>
  110. #include <linux/in.h>
  111. #include <linux/proc_fs.h>
  112. #include <linux/time.h>
  113. #include <linux/timer.h>
  114. #include <linux/dma-mapping.h>
  115. #ifdef GDTH_RTC
  116. #include <linux/mc146818rtc.h>
  117. #endif
  118. #include <linux/reboot.h>
  119. #include <asm/dma.h>
  120. #include <asm/system.h>
  121. #include <asm/io.h>
  122. #include <asm/uaccess.h>
  123. #include <linux/spinlock.h>
  124. #include <linux/blkdev.h>
  125. #include "scsi.h"
  126. #include <scsi/scsi_host.h>
  127. #include "gdth.h"
  128. static void gdth_delay(int milliseconds);
  129. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
  130. static irqreturn_t gdth_interrupt(int irq, void *dev_id);
  131. static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp);
  132. static int gdth_async_event(int hanum);
  133. static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
  134. static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority);
  135. static void gdth_next(int hanum);
  136. static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b);
  137. static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp);
  138. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  139. ushort idx, gdth_evt_data *evt);
  140. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
  141. static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
  142. gdth_evt_str *estr);
  143. static void gdth_clear_events(void);
  144. static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
  145. char *buffer,ushort count);
  146. static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp);
  147. static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive);
  148. static void gdth_enable_int(int hanum);
  149. static int gdth_get_status(unchar *pIStatus,int irq);
  150. static int gdth_test_busy(int hanum);
  151. static int gdth_get_cmd_index(int hanum);
  152. static void gdth_release_event(int hanum);
  153. static int gdth_wait(int hanum,int index,ulong32 time);
  154. static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
  155. ulong64 p2,ulong64 p3);
  156. static int gdth_search_drives(int hanum);
  157. static int gdth_analyse_hdrive(int hanum, ushort hdrive);
  158. static const char *gdth_ctr_name(int hanum);
  159. static int gdth_open(struct inode *inode, struct file *filep);
  160. static int gdth_close(struct inode *inode, struct file *filep);
  161. static int gdth_ioctl(struct inode *inode, struct file *filep,
  162. unsigned int cmd, unsigned long arg);
  163. static void gdth_flush(int hanum);
  164. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
  165. static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
  166. static void gdth_scsi_done(struct scsi_cmnd *scp);
  167. #ifdef CONFIG_ISA
  168. static int gdth_isa_probe_one(struct scsi_host_template *, ulong32);
  169. #endif
  170. #ifdef CONFIG_EISA
  171. static int gdth_eisa_probe_one(struct scsi_host_template *, ushort);
  172. #endif
  173. #ifdef CONFIG_PCI
  174. static int gdth_pci_probe_one(struct scsi_host_template *, gdth_pci_str *, int);
  175. #endif
  176. #ifdef DEBUG_GDTH
  177. static unchar DebugState = DEBUG_GDTH;
  178. #ifdef __SERIAL__
  179. #define MAX_SERBUF 160
  180. static void ser_init(void);
  181. static void ser_puts(char *str);
  182. static void ser_putc(char c);
  183. static int ser_printk(const char *fmt, ...);
  184. static char strbuf[MAX_SERBUF+1];
  185. #ifdef __COM2__
  186. #define COM_BASE 0x2f8
  187. #else
  188. #define COM_BASE 0x3f8
  189. #endif
  190. static void ser_init()
  191. {
  192. unsigned port=COM_BASE;
  193. outb(0x80,port+3);
  194. outb(0,port+1);
  195. /* 19200 Baud, if 9600: outb(12,port) */
  196. outb(6, port);
  197. outb(3,port+3);
  198. outb(0,port+1);
  199. /*
  200. ser_putc('I');
  201. ser_putc(' ');
  202. */
  203. }
  204. static void ser_puts(char *str)
  205. {
  206. char *ptr;
  207. ser_init();
  208. for (ptr=str;*ptr;++ptr)
  209. ser_putc(*ptr);
  210. }
  211. static void ser_putc(char c)
  212. {
  213. unsigned port=COM_BASE;
  214. while ((inb(port+5) & 0x20)==0);
  215. outb(c,port);
  216. if (c==0x0a)
  217. {
  218. while ((inb(port+5) & 0x20)==0);
  219. outb(0x0d,port);
  220. }
  221. }
  222. static int ser_printk(const char *fmt, ...)
  223. {
  224. va_list args;
  225. int i;
  226. va_start(args,fmt);
  227. i = vsprintf(strbuf,fmt,args);
  228. ser_puts(strbuf);
  229. va_end(args);
  230. return i;
  231. }
  232. #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
  233. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
  234. #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
  235. #else /* !__SERIAL__ */
  236. #define TRACE(a) {if (DebugState==1) {printk a;}}
  237. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
  238. #define TRACE3(a) {if (DebugState!=0) {printk a;}}
  239. #endif
  240. #else /* !DEBUG */
  241. #define TRACE(a)
  242. #define TRACE2(a)
  243. #define TRACE3(a)
  244. #endif
  245. #ifdef GDTH_STATISTICS
  246. static ulong32 max_rq=0, max_index=0, max_sg=0;
  247. #ifdef INT_COAL
  248. static ulong32 max_int_coal=0;
  249. #endif
  250. static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
  251. static struct timer_list gdth_timer;
  252. #endif
  253. #define PTR2USHORT(a) (ushort)(ulong)(a)
  254. #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
  255. #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
  256. #define NUMDATA(a) ( (gdth_num_str *)((a)->hostdata))
  257. #define HADATA(a) (&((gdth_ext_str *)((a)->hostdata))->haext)
  258. #define CMDDATA(a) (&((gdth_ext_str *)((a)->hostdata))->cmdext)
  259. #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
  260. #ifdef CONFIG_ISA
  261. static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
  262. #endif
  263. #ifdef CONFIG_EISA
  264. static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
  265. #endif
  266. static unchar gdth_polling; /* polling if TRUE */
  267. static unchar gdth_from_wait = FALSE; /* gdth_wait() */
  268. static int wait_index,wait_hanum; /* gdth_wait() */
  269. static int gdth_ctr_count = 0; /* controller count */
  270. static int gdth_ctr_released = 0; /* gdth_release() */
  271. static struct Scsi_Host *gdth_ctr_tab[MAXHA]; /* controller table */
  272. static unchar gdth_write_through = FALSE; /* write through */
  273. static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
  274. static int elastidx;
  275. static int eoldidx;
  276. static int major;
  277. #define DIN 1 /* IN data direction */
  278. #define DOU 2 /* OUT data direction */
  279. #define DNO DIN /* no data transfer */
  280. #define DUN DIN /* unknown data direction */
  281. static unchar gdth_direction_tab[0x100] = {
  282. DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
  283. DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
  284. DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
  285. DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
  286. DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
  287. DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
  288. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  289. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  290. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  291. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
  292. DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
  293. DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  294. DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  295. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  296. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  297. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
  298. };
  299. /* LILO and modprobe/insmod parameters */
  300. /* IRQ list for GDT3000/3020 EISA controllers */
  301. static int irq[MAXHA] __initdata =
  302. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  303. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  304. /* disable driver flag */
  305. static int disable __initdata = 0;
  306. /* reserve flag */
  307. static int reserve_mode = 1;
  308. /* reserve list */
  309. static int reserve_list[MAX_RES_ARGS] =
  310. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  311. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  312. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  313. /* scan order for PCI controllers */
  314. static int reverse_scan = 0;
  315. /* virtual channel for the host drives */
  316. static int hdr_channel = 0;
  317. /* max. IDs per channel */
  318. static int max_ids = MAXID;
  319. /* rescan all IDs */
  320. static int rescan = 0;
  321. /* shared access */
  322. static int shared_access = 1;
  323. /* enable support for EISA and ISA controllers */
  324. static int probe_eisa_isa = 0;
  325. /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
  326. static int force_dma32 = 0;
  327. /* parameters for modprobe/insmod */
  328. module_param_array(irq, int, NULL, 0);
  329. module_param(disable, int, 0);
  330. module_param(reserve_mode, int, 0);
  331. module_param_array(reserve_list, int, NULL, 0);
  332. module_param(reverse_scan, int, 0);
  333. module_param(hdr_channel, int, 0);
  334. module_param(max_ids, int, 0);
  335. module_param(rescan, int, 0);
  336. module_param(shared_access, int, 0);
  337. module_param(probe_eisa_isa, int, 0);
  338. module_param(force_dma32, int, 0);
  339. MODULE_AUTHOR("Achim Leubner");
  340. MODULE_LICENSE("GPL");
  341. /* ioctl interface */
  342. static const struct file_operations gdth_fops = {
  343. .ioctl = gdth_ioctl,
  344. .open = gdth_open,
  345. .release = gdth_close,
  346. };
  347. #define GDTH_MAGIC 0xc2e7c389 /* I got it from /dev/urandom */
  348. #define IS_GDTH_INTERNAL_CMD(scp) (scp->underflow == GDTH_MAGIC)
  349. #include "gdth_proc.h"
  350. #include "gdth_proc.c"
  351. /* notifier block to get a notify on system shutdown/halt/reboot */
  352. static struct notifier_block gdth_notifier = {
  353. gdth_halt, NULL, 0
  354. };
  355. static int notifier_disabled = 0;
  356. static void gdth_delay(int milliseconds)
  357. {
  358. if (milliseconds == 0) {
  359. udelay(1);
  360. } else {
  361. mdelay(milliseconds);
  362. }
  363. }
  364. static void gdth_scsi_done(struct scsi_cmnd *scp)
  365. {
  366. TRACE2(("gdth_scsi_done()\n"));
  367. if (IS_GDTH_INTERNAL_CMD(scp))
  368. complete((struct completion *)scp->request);
  369. else
  370. scp->scsi_done(scp);
  371. }
  372. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  373. int timeout, u32 *info)
  374. {
  375. Scsi_Cmnd *scp;
  376. DECLARE_COMPLETION_ONSTACK(wait);
  377. int rval;
  378. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  379. if (!scp)
  380. return -ENOMEM;
  381. scp->device = sdev;
  382. /* use request field to save the ptr. to completion struct. */
  383. scp->request = (struct request *)&wait;
  384. scp->timeout_per_command = timeout*HZ;
  385. scp->request_buffer = gdtcmd;
  386. scp->cmd_len = 12;
  387. memcpy(scp->cmnd, cmnd, 12);
  388. scp->SCp.this_residual = IOCTL_PRI; /* priority */
  389. scp->underflow = GDTH_MAGIC;
  390. gdth_queuecommand(scp, NULL);
  391. wait_for_completion(&wait);
  392. rval = scp->SCp.Status;
  393. if (info)
  394. *info = scp->SCp.Message;
  395. kfree(scp);
  396. return rval;
  397. }
  398. int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
  399. int timeout, u32 *info)
  400. {
  401. struct scsi_device *sdev = scsi_get_host_dev(shost);
  402. int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
  403. scsi_free_host_dev(sdev);
  404. return rval;
  405. }
  406. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
  407. {
  408. *cyls = size /HEADS/SECS;
  409. if (*cyls <= MAXCYLS) {
  410. *heads = HEADS;
  411. *secs = SECS;
  412. } else { /* too high for 64*32 */
  413. *cyls = size /MEDHEADS/MEDSECS;
  414. if (*cyls <= MAXCYLS) {
  415. *heads = MEDHEADS;
  416. *secs = MEDSECS;
  417. } else { /* too high for 127*63 */
  418. *cyls = size /BIGHEADS/BIGSECS;
  419. *heads = BIGHEADS;
  420. *secs = BIGSECS;
  421. }
  422. }
  423. }
  424. /* controller search and initialization functions */
  425. #ifdef CONFIG_EISA
  426. static int __init gdth_search_eisa(ushort eisa_adr)
  427. {
  428. ulong32 id;
  429. TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
  430. id = inl(eisa_adr+ID0REG);
  431. if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
  432. if ((inb(eisa_adr+EISAREG) & 8) == 0)
  433. return 0; /* not EISA configured */
  434. return 1;
  435. }
  436. if (id == GDT3_ID) /* GDT3000 */
  437. return 1;
  438. return 0;
  439. }
  440. #endif /* CONFIG_EISA */
  441. #ifdef CONFIG_ISA
  442. static int __init gdth_search_isa(ulong32 bios_adr)
  443. {
  444. void __iomem *addr;
  445. ulong32 id;
  446. TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
  447. if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
  448. id = readl(addr);
  449. iounmap(addr);
  450. if (id == GDT2_ID) /* GDT2000 */
  451. return 1;
  452. }
  453. return 0;
  454. }
  455. #endif /* CONFIG_ISA */
  456. #ifdef CONFIG_PCI
  457. static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  458. ushort vendor, ushort dev);
  459. static int __init gdth_search_pci(gdth_pci_str *pcistr)
  460. {
  461. ushort device, cnt;
  462. TRACE(("gdth_search_pci()\n"));
  463. cnt = 0;
  464. for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
  465. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  466. for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
  467. device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
  468. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  469. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  470. PCI_DEVICE_ID_VORTEX_GDTNEWRX);
  471. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  472. PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
  473. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  474. PCI_DEVICE_ID_INTEL_SRC);
  475. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  476. PCI_DEVICE_ID_INTEL_SRC_XSCALE);
  477. return cnt;
  478. }
  479. /* Vortex only makes RAID controllers.
  480. * We do not really want to specify all 550 ids here, so wildcard match.
  481. */
  482. static struct pci_device_id gdthtable[] __maybe_unused = {
  483. {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
  484. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
  485. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
  486. {0}
  487. };
  488. MODULE_DEVICE_TABLE(pci,gdthtable);
  489. static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  490. ushort vendor, ushort device)
  491. {
  492. ulong base0, base1, base2;
  493. struct pci_dev *pdev;
  494. TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
  495. *cnt, vendor, device));
  496. pdev = NULL;
  497. while ((pdev = pci_find_device(vendor, device, pdev))
  498. != NULL) {
  499. if (pci_enable_device(pdev))
  500. continue;
  501. if (*cnt >= MAXHA)
  502. return;
  503. /* GDT PCI controller found, resources are already in pdev */
  504. pcistr[*cnt].pdev = pdev;
  505. pcistr[*cnt].irq = pdev->irq;
  506. base0 = pci_resource_flags(pdev, 0);
  507. base1 = pci_resource_flags(pdev, 1);
  508. base2 = pci_resource_flags(pdev, 2);
  509. if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
  510. device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
  511. if (!(base0 & IORESOURCE_MEM))
  512. continue;
  513. pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
  514. } else { /* GDT6110, GDT6120, .. */
  515. if (!(base0 & IORESOURCE_MEM) ||
  516. !(base2 & IORESOURCE_MEM) ||
  517. !(base1 & IORESOURCE_IO))
  518. continue;
  519. pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
  520. pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
  521. pcistr[*cnt].io = pci_resource_start(pdev, 1);
  522. }
  523. TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
  524. pcistr[*cnt].pdev->bus->number,
  525. PCI_SLOT(pcistr[*cnt].pdev->devfn),
  526. pcistr[*cnt].irq, pcistr[*cnt].dpmem));
  527. (*cnt)++;
  528. }
  529. }
  530. static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
  531. {
  532. gdth_pci_str temp;
  533. int i, changed;
  534. TRACE(("gdth_sort_pci() cnt %d\n",cnt));
  535. if (cnt == 0)
  536. return;
  537. do {
  538. changed = FALSE;
  539. for (i = 0; i < cnt-1; ++i) {
  540. if (!reverse_scan) {
  541. if ((pcistr[i].pdev->bus->number > pcistr[i+1].pdev->bus->number) ||
  542. (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
  543. PCI_SLOT(pcistr[i].pdev->devfn) >
  544. PCI_SLOT(pcistr[i+1].pdev->devfn))) {
  545. temp = pcistr[i];
  546. pcistr[i] = pcistr[i+1];
  547. pcistr[i+1] = temp;
  548. changed = TRUE;
  549. }
  550. } else {
  551. if ((pcistr[i].pdev->bus->number < pcistr[i+1].pdev->bus->number) ||
  552. (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
  553. PCI_SLOT(pcistr[i].pdev->devfn) <
  554. PCI_SLOT(pcistr[i+1].pdev->devfn))) {
  555. temp = pcistr[i];
  556. pcistr[i] = pcistr[i+1];
  557. pcistr[i+1] = temp;
  558. changed = TRUE;
  559. }
  560. }
  561. }
  562. } while (changed);
  563. }
  564. #endif /* CONFIG_PCI */
  565. #ifdef CONFIG_EISA
  566. static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
  567. {
  568. ulong32 retries,id;
  569. unchar prot_ver,eisacf,i,irq_found;
  570. TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
  571. /* disable board interrupts, deinitialize services */
  572. outb(0xff,eisa_adr+EDOORREG);
  573. outb(0x00,eisa_adr+EDENABREG);
  574. outb(0x00,eisa_adr+EINTENABREG);
  575. outb(0xff,eisa_adr+LDOORREG);
  576. retries = INIT_RETRIES;
  577. gdth_delay(20);
  578. while (inb(eisa_adr+EDOORREG) != 0xff) {
  579. if (--retries == 0) {
  580. printk("GDT-EISA: Initialization error (DEINIT failed)\n");
  581. return 0;
  582. }
  583. gdth_delay(1);
  584. TRACE2(("wait for DEINIT: retries=%d\n",retries));
  585. }
  586. prot_ver = inb(eisa_adr+MAILBOXREG);
  587. outb(0xff,eisa_adr+EDOORREG);
  588. if (prot_ver != PROTOCOL_VERSION) {
  589. printk("GDT-EISA: Illegal protocol version\n");
  590. return 0;
  591. }
  592. ha->bmic = eisa_adr;
  593. ha->brd_phys = (ulong32)eisa_adr >> 12;
  594. outl(0,eisa_adr+MAILBOXREG);
  595. outl(0,eisa_adr+MAILBOXREG+4);
  596. outl(0,eisa_adr+MAILBOXREG+8);
  597. outl(0,eisa_adr+MAILBOXREG+12);
  598. /* detect IRQ */
  599. if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
  600. ha->oem_id = OEM_ID_ICP;
  601. ha->type = GDT_EISA;
  602. ha->stype = id;
  603. outl(1,eisa_adr+MAILBOXREG+8);
  604. outb(0xfe,eisa_adr+LDOORREG);
  605. retries = INIT_RETRIES;
  606. gdth_delay(20);
  607. while (inb(eisa_adr+EDOORREG) != 0xfe) {
  608. if (--retries == 0) {
  609. printk("GDT-EISA: Initialization error (get IRQ failed)\n");
  610. return 0;
  611. }
  612. gdth_delay(1);
  613. }
  614. ha->irq = inb(eisa_adr+MAILBOXREG);
  615. outb(0xff,eisa_adr+EDOORREG);
  616. TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
  617. /* check the result */
  618. if (ha->irq == 0) {
  619. TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
  620. for (i = 0, irq_found = FALSE;
  621. i < MAXHA && irq[i] != 0xff; ++i) {
  622. if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
  623. irq_found = TRUE;
  624. break;
  625. }
  626. }
  627. if (irq_found) {
  628. ha->irq = irq[i];
  629. irq[i] = 0;
  630. printk("GDT-EISA: Can not detect controller IRQ,\n");
  631. printk("Use IRQ setting from command line (IRQ = %d)\n",
  632. ha->irq);
  633. } else {
  634. printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
  635. printk("the controller BIOS or use command line parameters\n");
  636. return 0;
  637. }
  638. }
  639. } else {
  640. eisacf = inb(eisa_adr+EISAREG) & 7;
  641. if (eisacf > 4) /* level triggered */
  642. eisacf -= 4;
  643. ha->irq = gdth_irq_tab[eisacf];
  644. ha->oem_id = OEM_ID_ICP;
  645. ha->type = GDT_EISA;
  646. ha->stype = id;
  647. }
  648. ha->dma64_support = 0;
  649. return 1;
  650. }
  651. #endif /* CONFIG_EISA */
  652. #ifdef CONFIG_ISA
  653. static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
  654. {
  655. register gdt2_dpram_str __iomem *dp2_ptr;
  656. int i;
  657. unchar irq_drq,prot_ver;
  658. ulong32 retries;
  659. TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
  660. ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
  661. if (ha->brd == NULL) {
  662. printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
  663. return 0;
  664. }
  665. dp2_ptr = ha->brd;
  666. writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
  667. /* reset interface area */
  668. memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
  669. if (readl(&dp2_ptr->u) != 0) {
  670. printk("GDT-ISA: Initialization error (DPMEM write error)\n");
  671. iounmap(ha->brd);
  672. return 0;
  673. }
  674. /* disable board interrupts, read DRQ and IRQ */
  675. writeb(0xff, &dp2_ptr->io.irqdel);
  676. writeb(0x00, &dp2_ptr->io.irqen);
  677. writeb(0x00, &dp2_ptr->u.ic.S_Status);
  678. writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
  679. irq_drq = readb(&dp2_ptr->io.rq);
  680. for (i=0; i<3; ++i) {
  681. if ((irq_drq & 1)==0)
  682. break;
  683. irq_drq >>= 1;
  684. }
  685. ha->drq = gdth_drq_tab[i];
  686. irq_drq = readb(&dp2_ptr->io.rq) >> 3;
  687. for (i=1; i<5; ++i) {
  688. if ((irq_drq & 1)==0)
  689. break;
  690. irq_drq >>= 1;
  691. }
  692. ha->irq = gdth_irq_tab[i];
  693. /* deinitialize services */
  694. writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
  695. writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
  696. writeb(0, &dp2_ptr->io.event);
  697. retries = INIT_RETRIES;
  698. gdth_delay(20);
  699. while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
  700. if (--retries == 0) {
  701. printk("GDT-ISA: Initialization error (DEINIT failed)\n");
  702. iounmap(ha->brd);
  703. return 0;
  704. }
  705. gdth_delay(1);
  706. }
  707. prot_ver = (unchar)readl(&dp2_ptr->u.ic.S_Info[0]);
  708. writeb(0, &dp2_ptr->u.ic.Status);
  709. writeb(0xff, &dp2_ptr->io.irqdel);
  710. if (prot_ver != PROTOCOL_VERSION) {
  711. printk("GDT-ISA: Illegal protocol version\n");
  712. iounmap(ha->brd);
  713. return 0;
  714. }
  715. ha->oem_id = OEM_ID_ICP;
  716. ha->type = GDT_ISA;
  717. ha->ic_all_size = sizeof(dp2_ptr->u);
  718. ha->stype= GDT2_ID;
  719. ha->brd_phys = bios_adr >> 4;
  720. /* special request to controller BIOS */
  721. writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
  722. writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
  723. writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
  724. writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
  725. writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
  726. writeb(0, &dp2_ptr->io.event);
  727. retries = INIT_RETRIES;
  728. gdth_delay(20);
  729. while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
  730. if (--retries == 0) {
  731. printk("GDT-ISA: Initialization error\n");
  732. iounmap(ha->brd);
  733. return 0;
  734. }
  735. gdth_delay(1);
  736. }
  737. writeb(0, &dp2_ptr->u.ic.Status);
  738. writeb(0xff, &dp2_ptr->io.irqdel);
  739. ha->dma64_support = 0;
  740. return 1;
  741. }
  742. #endif /* CONFIG_ISA */
  743. #ifdef CONFIG_PCI
  744. static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
  745. {
  746. register gdt6_dpram_str __iomem *dp6_ptr;
  747. register gdt6c_dpram_str __iomem *dp6c_ptr;
  748. register gdt6m_dpram_str __iomem *dp6m_ptr;
  749. ulong32 retries;
  750. unchar prot_ver;
  751. ushort command;
  752. int i, found = FALSE;
  753. TRACE(("gdth_init_pci()\n"));
  754. if (pcistr->pdev->vendor == PCI_VENDOR_ID_INTEL)
  755. ha->oem_id = OEM_ID_INTEL;
  756. else
  757. ha->oem_id = OEM_ID_ICP;
  758. ha->brd_phys = (pcistr->pdev->bus->number << 8) | (pcistr->pdev->devfn & 0xf8);
  759. ha->stype = (ulong32)pcistr->pdev->device;
  760. ha->irq = pcistr->irq;
  761. ha->pdev = pcistr->pdev;
  762. if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
  763. TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  764. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
  765. if (ha->brd == NULL) {
  766. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  767. return 0;
  768. }
  769. /* check and reset interface area */
  770. dp6_ptr = ha->brd;
  771. writel(DPMEM_MAGIC, &dp6_ptr->u);
  772. if (readl(&dp6_ptr->u) != DPMEM_MAGIC) {
  773. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  774. pcistr->dpmem);
  775. found = FALSE;
  776. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  777. iounmap(ha->brd);
  778. ha->brd = ioremap(i, sizeof(ushort));
  779. if (ha->brd == NULL) {
  780. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  781. return 0;
  782. }
  783. if (readw(ha->brd) != 0xffff) {
  784. TRACE2(("init_pci_old() address 0x%x busy\n", i));
  785. continue;
  786. }
  787. iounmap(ha->brd);
  788. pci_write_config_dword(pcistr->pdev,
  789. PCI_BASE_ADDRESS_0, i);
  790. ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
  791. if (ha->brd == NULL) {
  792. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  793. return 0;
  794. }
  795. dp6_ptr = ha->brd;
  796. writel(DPMEM_MAGIC, &dp6_ptr->u);
  797. if (readl(&dp6_ptr->u) == DPMEM_MAGIC) {
  798. printk("GDT-PCI: Use free address at 0x%x\n", i);
  799. found = TRUE;
  800. break;
  801. }
  802. }
  803. if (!found) {
  804. printk("GDT-PCI: No free address found!\n");
  805. iounmap(ha->brd);
  806. return 0;
  807. }
  808. }
  809. memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
  810. if (readl(&dp6_ptr->u) != 0) {
  811. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  812. iounmap(ha->brd);
  813. return 0;
  814. }
  815. /* disable board interrupts, deinit services */
  816. writeb(0xff, &dp6_ptr->io.irqdel);
  817. writeb(0x00, &dp6_ptr->io.irqen);
  818. writeb(0x00, &dp6_ptr->u.ic.S_Status);
  819. writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
  820. writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
  821. writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
  822. writeb(0, &dp6_ptr->io.event);
  823. retries = INIT_RETRIES;
  824. gdth_delay(20);
  825. while (readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  826. if (--retries == 0) {
  827. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  828. iounmap(ha->brd);
  829. return 0;
  830. }
  831. gdth_delay(1);
  832. }
  833. prot_ver = (unchar)readl(&dp6_ptr->u.ic.S_Info[0]);
  834. writeb(0, &dp6_ptr->u.ic.S_Status);
  835. writeb(0xff, &dp6_ptr->io.irqdel);
  836. if (prot_ver != PROTOCOL_VERSION) {
  837. printk("GDT-PCI: Illegal protocol version\n");
  838. iounmap(ha->brd);
  839. return 0;
  840. }
  841. ha->type = GDT_PCI;
  842. ha->ic_all_size = sizeof(dp6_ptr->u);
  843. /* special command to controller BIOS */
  844. writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
  845. writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
  846. writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
  847. writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
  848. writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
  849. writeb(0, &dp6_ptr->io.event);
  850. retries = INIT_RETRIES;
  851. gdth_delay(20);
  852. while (readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  853. if (--retries == 0) {
  854. printk("GDT-PCI: Initialization error\n");
  855. iounmap(ha->brd);
  856. return 0;
  857. }
  858. gdth_delay(1);
  859. }
  860. writeb(0, &dp6_ptr->u.ic.S_Status);
  861. writeb(0xff, &dp6_ptr->io.irqdel);
  862. ha->dma64_support = 0;
  863. } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
  864. ha->plx = (gdt6c_plx_regs *)pcistr->io;
  865. TRACE2(("init_pci_new() dpmem %lx irq %d\n",
  866. pcistr->dpmem,ha->irq));
  867. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
  868. if (ha->brd == NULL) {
  869. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  870. iounmap(ha->brd);
  871. return 0;
  872. }
  873. /* check and reset interface area */
  874. dp6c_ptr = ha->brd;
  875. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  876. if (readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
  877. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  878. pcistr->dpmem);
  879. found = FALSE;
  880. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  881. iounmap(ha->brd);
  882. ha->brd = ioremap(i, sizeof(ushort));
  883. if (ha->brd == NULL) {
  884. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  885. return 0;
  886. }
  887. if (readw(ha->brd) != 0xffff) {
  888. TRACE2(("init_pci_plx() address 0x%x busy\n", i));
  889. continue;
  890. }
  891. iounmap(ha->brd);
  892. pci_write_config_dword(pcistr->pdev,
  893. PCI_BASE_ADDRESS_2, i);
  894. ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
  895. if (ha->brd == NULL) {
  896. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  897. return 0;
  898. }
  899. dp6c_ptr = ha->brd;
  900. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  901. if (readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
  902. printk("GDT-PCI: Use free address at 0x%x\n", i);
  903. found = TRUE;
  904. break;
  905. }
  906. }
  907. if (!found) {
  908. printk("GDT-PCI: No free address found!\n");
  909. iounmap(ha->brd);
  910. return 0;
  911. }
  912. }
  913. memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
  914. if (readl(&dp6c_ptr->u) != 0) {
  915. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  916. iounmap(ha->brd);
  917. return 0;
  918. }
  919. /* disable board interrupts, deinit services */
  920. outb(0x00,PTR2USHORT(&ha->plx->control1));
  921. outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
  922. writeb(0x00, &dp6c_ptr->u.ic.S_Status);
  923. writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
  924. writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
  925. writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
  926. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  927. retries = INIT_RETRIES;
  928. gdth_delay(20);
  929. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  930. if (--retries == 0) {
  931. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  932. iounmap(ha->brd);
  933. return 0;
  934. }
  935. gdth_delay(1);
  936. }
  937. prot_ver = (unchar)readl(&dp6c_ptr->u.ic.S_Info[0]);
  938. writeb(0, &dp6c_ptr->u.ic.Status);
  939. if (prot_ver != PROTOCOL_VERSION) {
  940. printk("GDT-PCI: Illegal protocol version\n");
  941. iounmap(ha->brd);
  942. return 0;
  943. }
  944. ha->type = GDT_PCINEW;
  945. ha->ic_all_size = sizeof(dp6c_ptr->u);
  946. /* special command to controller BIOS */
  947. writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
  948. writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
  949. writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
  950. writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
  951. writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
  952. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  953. retries = INIT_RETRIES;
  954. gdth_delay(20);
  955. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  956. if (--retries == 0) {
  957. printk("GDT-PCI: Initialization error\n");
  958. iounmap(ha->brd);
  959. return 0;
  960. }
  961. gdth_delay(1);
  962. }
  963. writeb(0, &dp6c_ptr->u.ic.S_Status);
  964. ha->dma64_support = 0;
  965. } else { /* MPR */
  966. TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  967. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
  968. if (ha->brd == NULL) {
  969. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  970. return 0;
  971. }
  972. /* manipulate config. space to enable DPMEM, start RP controller */
  973. pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
  974. command |= 6;
  975. pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
  976. if (pci_resource_start(pcistr->pdev, 8) == 1UL)
  977. pci_resource_start(pcistr->pdev, 8) = 0UL;
  978. i = 0xFEFF0001UL;
  979. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
  980. gdth_delay(1);
  981. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
  982. pci_resource_start(pcistr->pdev, 8));
  983. dp6m_ptr = ha->brd;
  984. /* Ensure that it is safe to access the non HW portions of DPMEM.
  985. * Aditional check needed for Xscale based RAID controllers */
  986. while( ((int)readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
  987. gdth_delay(1);
  988. /* check and reset interface area */
  989. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  990. if (readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
  991. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  992. pcistr->dpmem);
  993. found = FALSE;
  994. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  995. iounmap(ha->brd);
  996. ha->brd = ioremap(i, sizeof(ushort));
  997. if (ha->brd == NULL) {
  998. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  999. return 0;
  1000. }
  1001. if (readw(ha->brd) != 0xffff) {
  1002. TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
  1003. continue;
  1004. }
  1005. iounmap(ha->brd);
  1006. pci_write_config_dword(pcistr->pdev,
  1007. PCI_BASE_ADDRESS_0, i);
  1008. ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
  1009. if (ha->brd == NULL) {
  1010. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1011. return 0;
  1012. }
  1013. dp6m_ptr = ha->brd;
  1014. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1015. if (readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
  1016. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1017. found = TRUE;
  1018. break;
  1019. }
  1020. }
  1021. if (!found) {
  1022. printk("GDT-PCI: No free address found!\n");
  1023. iounmap(ha->brd);
  1024. return 0;
  1025. }
  1026. }
  1027. memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
  1028. /* disable board interrupts, deinit services */
  1029. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
  1030. &dp6m_ptr->i960r.edoor_en_reg);
  1031. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1032. writeb(0x00, &dp6m_ptr->u.ic.S_Status);
  1033. writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
  1034. writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
  1035. writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1036. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1037. retries = INIT_RETRIES;
  1038. gdth_delay(20);
  1039. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
  1040. if (--retries == 0) {
  1041. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1042. iounmap(ha->brd);
  1043. return 0;
  1044. }
  1045. gdth_delay(1);
  1046. }
  1047. prot_ver = (unchar)readl(&dp6m_ptr->u.ic.S_Info[0]);
  1048. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1049. if (prot_ver != PROTOCOL_VERSION) {
  1050. printk("GDT-PCI: Illegal protocol version\n");
  1051. iounmap(ha->brd);
  1052. return 0;
  1053. }
  1054. ha->type = GDT_PCIMPR;
  1055. ha->ic_all_size = sizeof(dp6m_ptr->u);
  1056. /* special command to controller BIOS */
  1057. writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
  1058. writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
  1059. writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
  1060. writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
  1061. writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1062. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1063. retries = INIT_RETRIES;
  1064. gdth_delay(20);
  1065. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
  1066. if (--retries == 0) {
  1067. printk("GDT-PCI: Initialization error\n");
  1068. iounmap(ha->brd);
  1069. return 0;
  1070. }
  1071. gdth_delay(1);
  1072. }
  1073. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1074. /* read FW version to detect 64-bit DMA support */
  1075. writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1076. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1077. retries = INIT_RETRIES;
  1078. gdth_delay(20);
  1079. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
  1080. if (--retries == 0) {
  1081. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1082. iounmap(ha->brd);
  1083. return 0;
  1084. }
  1085. gdth_delay(1);
  1086. }
  1087. prot_ver = (unchar)(readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
  1088. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1089. if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
  1090. ha->dma64_support = 0;
  1091. else
  1092. ha->dma64_support = 1;
  1093. }
  1094. return 1;
  1095. }
  1096. #endif /* CONFIG_PCI */
  1097. /* controller protocol functions */
  1098. static void __init gdth_enable_int(int hanum)
  1099. {
  1100. gdth_ha_str *ha;
  1101. ulong flags;
  1102. gdt2_dpram_str __iomem *dp2_ptr;
  1103. gdt6_dpram_str __iomem *dp6_ptr;
  1104. gdt6m_dpram_str __iomem *dp6m_ptr;
  1105. TRACE(("gdth_enable_int() hanum %d\n",hanum));
  1106. ha = HADATA(gdth_ctr_tab[hanum]);
  1107. spin_lock_irqsave(&ha->smp_lock, flags);
  1108. if (ha->type == GDT_EISA) {
  1109. outb(0xff, ha->bmic + EDOORREG);
  1110. outb(0xff, ha->bmic + EDENABREG);
  1111. outb(0x01, ha->bmic + EINTENABREG);
  1112. } else if (ha->type == GDT_ISA) {
  1113. dp2_ptr = ha->brd;
  1114. writeb(1, &dp2_ptr->io.irqdel);
  1115. writeb(0, &dp2_ptr->u.ic.Cmd_Index);
  1116. writeb(1, &dp2_ptr->io.irqen);
  1117. } else if (ha->type == GDT_PCI) {
  1118. dp6_ptr = ha->brd;
  1119. writeb(1, &dp6_ptr->io.irqdel);
  1120. writeb(0, &dp6_ptr->u.ic.Cmd_Index);
  1121. writeb(1, &dp6_ptr->io.irqen);
  1122. } else if (ha->type == GDT_PCINEW) {
  1123. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  1124. outb(0x03, PTR2USHORT(&ha->plx->control1));
  1125. } else if (ha->type == GDT_PCIMPR) {
  1126. dp6m_ptr = ha->brd;
  1127. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1128. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
  1129. &dp6m_ptr->i960r.edoor_en_reg);
  1130. }
  1131. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1132. }
  1133. static int gdth_get_status(unchar *pIStatus,int irq)
  1134. {
  1135. register gdth_ha_str *ha;
  1136. int i;
  1137. TRACE(("gdth_get_status() irq %d ctr_count %d\n",
  1138. irq,gdth_ctr_count));
  1139. *pIStatus = 0;
  1140. for (i=0; i<gdth_ctr_count; ++i) {
  1141. ha = HADATA(gdth_ctr_tab[i]);
  1142. if (ha->irq != (unchar)irq) /* check IRQ */
  1143. continue;
  1144. if (ha->type == GDT_EISA)
  1145. *pIStatus = inb((ushort)ha->bmic + EDOORREG);
  1146. else if (ha->type == GDT_ISA)
  1147. *pIStatus =
  1148. readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1149. else if (ha->type == GDT_PCI)
  1150. *pIStatus =
  1151. readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1152. else if (ha->type == GDT_PCINEW)
  1153. *pIStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
  1154. else if (ha->type == GDT_PCIMPR)
  1155. *pIStatus =
  1156. readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
  1157. if (*pIStatus)
  1158. return i; /* board found */
  1159. }
  1160. return -1;
  1161. }
  1162. static int gdth_test_busy(int hanum)
  1163. {
  1164. register gdth_ha_str *ha;
  1165. register int gdtsema0 = 0;
  1166. TRACE(("gdth_test_busy() hanum %d\n",hanum));
  1167. ha = HADATA(gdth_ctr_tab[hanum]);
  1168. if (ha->type == GDT_EISA)
  1169. gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
  1170. else if (ha->type == GDT_ISA)
  1171. gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1172. else if (ha->type == GDT_PCI)
  1173. gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1174. else if (ha->type == GDT_PCINEW)
  1175. gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
  1176. else if (ha->type == GDT_PCIMPR)
  1177. gdtsema0 =
  1178. (int)readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1179. return (gdtsema0 & 1);
  1180. }
  1181. static int gdth_get_cmd_index(int hanum)
  1182. {
  1183. register gdth_ha_str *ha;
  1184. int i;
  1185. TRACE(("gdth_get_cmd_index() hanum %d\n",hanum));
  1186. ha = HADATA(gdth_ctr_tab[hanum]);
  1187. for (i=0; i<GDTH_MAXCMDS; ++i) {
  1188. if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
  1189. ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
  1190. ha->cmd_tab[i].service = ha->pccb->Service;
  1191. ha->pccb->CommandIndex = (ulong32)i+2;
  1192. return (i+2);
  1193. }
  1194. }
  1195. return 0;
  1196. }
  1197. static void gdth_set_sema0(int hanum)
  1198. {
  1199. register gdth_ha_str *ha;
  1200. TRACE(("gdth_set_sema0() hanum %d\n",hanum));
  1201. ha = HADATA(gdth_ctr_tab[hanum]);
  1202. if (ha->type == GDT_EISA) {
  1203. outb(1, ha->bmic + SEMA0REG);
  1204. } else if (ha->type == GDT_ISA) {
  1205. writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1206. } else if (ha->type == GDT_PCI) {
  1207. writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1208. } else if (ha->type == GDT_PCINEW) {
  1209. outb(1, PTR2USHORT(&ha->plx->sema0_reg));
  1210. } else if (ha->type == GDT_PCIMPR) {
  1211. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1212. }
  1213. }
  1214. static void gdth_copy_command(int hanum)
  1215. {
  1216. register gdth_ha_str *ha;
  1217. register gdth_cmd_str *cmd_ptr;
  1218. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1219. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1220. gdt6_dpram_str __iomem *dp6_ptr;
  1221. gdt2_dpram_str __iomem *dp2_ptr;
  1222. ushort cp_count,dp_offset,cmd_no;
  1223. TRACE(("gdth_copy_command() hanum %d\n",hanum));
  1224. ha = HADATA(gdth_ctr_tab[hanum]);
  1225. cp_count = ha->cmd_len;
  1226. dp_offset= ha->cmd_offs_dpmem;
  1227. cmd_no = ha->cmd_cnt;
  1228. cmd_ptr = ha->pccb;
  1229. ++ha->cmd_cnt;
  1230. if (ha->type == GDT_EISA)
  1231. return; /* no DPMEM, no copy */
  1232. /* set cpcount dword aligned */
  1233. if (cp_count & 3)
  1234. cp_count += (4 - (cp_count & 3));
  1235. ha->cmd_offs_dpmem += cp_count;
  1236. /* set offset and service, copy command to DPMEM */
  1237. if (ha->type == GDT_ISA) {
  1238. dp2_ptr = ha->brd;
  1239. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1240. &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
  1241. writew((ushort)cmd_ptr->Service,
  1242. &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1243. memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1244. } else if (ha->type == GDT_PCI) {
  1245. dp6_ptr = ha->brd;
  1246. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1247. &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
  1248. writew((ushort)cmd_ptr->Service,
  1249. &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1250. memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1251. } else if (ha->type == GDT_PCINEW) {
  1252. dp6c_ptr = ha->brd;
  1253. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1254. &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
  1255. writew((ushort)cmd_ptr->Service,
  1256. &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1257. memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1258. } else if (ha->type == GDT_PCIMPR) {
  1259. dp6m_ptr = ha->brd;
  1260. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1261. &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
  1262. writew((ushort)cmd_ptr->Service,
  1263. &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1264. memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1265. }
  1266. }
  1267. static void gdth_release_event(int hanum)
  1268. {
  1269. register gdth_ha_str *ha;
  1270. TRACE(("gdth_release_event() hanum %d\n",hanum));
  1271. ha = HADATA(gdth_ctr_tab[hanum]);
  1272. #ifdef GDTH_STATISTICS
  1273. {
  1274. ulong32 i,j;
  1275. for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
  1276. if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
  1277. ++i;
  1278. }
  1279. if (max_index < i) {
  1280. max_index = i;
  1281. TRACE3(("GDT: max_index = %d\n",(ushort)i));
  1282. }
  1283. }
  1284. #endif
  1285. if (ha->pccb->OpCode == GDT_INIT)
  1286. ha->pccb->Service |= 0x80;
  1287. if (ha->type == GDT_EISA) {
  1288. if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
  1289. outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
  1290. outb(ha->pccb->Service, ha->bmic + LDOORREG);
  1291. } else if (ha->type == GDT_ISA) {
  1292. writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
  1293. } else if (ha->type == GDT_PCI) {
  1294. writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
  1295. } else if (ha->type == GDT_PCINEW) {
  1296. outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
  1297. } else if (ha->type == GDT_PCIMPR) {
  1298. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
  1299. }
  1300. }
  1301. static int gdth_wait(int hanum,int index,ulong32 time)
  1302. {
  1303. gdth_ha_str *ha;
  1304. int answer_found = FALSE;
  1305. TRACE(("gdth_wait() hanum %d index %d time %d\n",hanum,index,time));
  1306. ha = HADATA(gdth_ctr_tab[hanum]);
  1307. if (index == 0)
  1308. return 1; /* no wait required */
  1309. gdth_from_wait = TRUE;
  1310. do {
  1311. gdth_interrupt((int)ha->irq,ha);
  1312. if (wait_hanum==hanum && wait_index==index) {
  1313. answer_found = TRUE;
  1314. break;
  1315. }
  1316. gdth_delay(1);
  1317. } while (--time);
  1318. gdth_from_wait = FALSE;
  1319. while (gdth_test_busy(hanum))
  1320. gdth_delay(0);
  1321. return (answer_found);
  1322. }
  1323. static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
  1324. ulong64 p2,ulong64 p3)
  1325. {
  1326. register gdth_ha_str *ha;
  1327. register gdth_cmd_str *cmd_ptr;
  1328. int retries,index;
  1329. TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
  1330. ha = HADATA(gdth_ctr_tab[hanum]);
  1331. cmd_ptr = ha->pccb;
  1332. memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
  1333. /* make command */
  1334. for (retries = INIT_RETRIES;;) {
  1335. cmd_ptr->Service = service;
  1336. cmd_ptr->RequestBuffer = INTERNAL_CMND;
  1337. if (!(index=gdth_get_cmd_index(hanum))) {
  1338. TRACE(("GDT: No free command index found\n"));
  1339. return 0;
  1340. }
  1341. gdth_set_sema0(hanum);
  1342. cmd_ptr->OpCode = opcode;
  1343. cmd_ptr->BoardNode = LOCALBOARD;
  1344. if (service == CACHESERVICE) {
  1345. if (opcode == GDT_IOCTL) {
  1346. cmd_ptr->u.ioctl.subfunc = p1;
  1347. cmd_ptr->u.ioctl.channel = (ulong32)p2;
  1348. cmd_ptr->u.ioctl.param_size = (ushort)p3;
  1349. cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
  1350. } else {
  1351. if (ha->cache_feat & GDT_64BIT) {
  1352. cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
  1353. cmd_ptr->u.cache64.BlockNo = p2;
  1354. } else {
  1355. cmd_ptr->u.cache.DeviceNo = (ushort)p1;
  1356. cmd_ptr->u.cache.BlockNo = (ulong32)p2;
  1357. }
  1358. }
  1359. } else if (service == SCSIRAWSERVICE) {
  1360. if (ha->raw_feat & GDT_64BIT) {
  1361. cmd_ptr->u.raw64.direction = p1;
  1362. cmd_ptr->u.raw64.bus = (unchar)p2;
  1363. cmd_ptr->u.raw64.target = (unchar)p3;
  1364. cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
  1365. } else {
  1366. cmd_ptr->u.raw.direction = p1;
  1367. cmd_ptr->u.raw.bus = (unchar)p2;
  1368. cmd_ptr->u.raw.target = (unchar)p3;
  1369. cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
  1370. }
  1371. } else if (service == SCREENSERVICE) {
  1372. if (opcode == GDT_REALTIME) {
  1373. *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
  1374. *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
  1375. *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
  1376. }
  1377. }
  1378. ha->cmd_len = sizeof(gdth_cmd_str);
  1379. ha->cmd_offs_dpmem = 0;
  1380. ha->cmd_cnt = 0;
  1381. gdth_copy_command(hanum);
  1382. gdth_release_event(hanum);
  1383. gdth_delay(20);
  1384. if (!gdth_wait(hanum,index,INIT_TIMEOUT)) {
  1385. printk("GDT: Initialization error (timeout service %d)\n",service);
  1386. return 0;
  1387. }
  1388. if (ha->status != S_BSY || --retries == 0)
  1389. break;
  1390. gdth_delay(1);
  1391. }
  1392. return (ha->status != S_OK ? 0:1);
  1393. }
  1394. /* search for devices */
  1395. static int __init gdth_search_drives(int hanum)
  1396. {
  1397. register gdth_ha_str *ha;
  1398. ushort cdev_cnt, i;
  1399. int ok;
  1400. ulong32 bus_no, drv_cnt, drv_no, j;
  1401. gdth_getch_str *chn;
  1402. gdth_drlist_str *drl;
  1403. gdth_iochan_str *ioc;
  1404. gdth_raw_iochan_str *iocr;
  1405. gdth_arcdl_str *alst;
  1406. gdth_alist_str *alst2;
  1407. gdth_oem_str_ioctl *oemstr;
  1408. #ifdef INT_COAL
  1409. gdth_perf_modes *pmod;
  1410. #endif
  1411. #ifdef GDTH_RTC
  1412. unchar rtc[12];
  1413. ulong flags;
  1414. #endif
  1415. TRACE(("gdth_search_drives() hanum %d\n",hanum));
  1416. ha = HADATA(gdth_ctr_tab[hanum]);
  1417. ok = 0;
  1418. /* initialize controller services, at first: screen service */
  1419. ha->screen_feat = 0;
  1420. if (!force_dma32) {
  1421. ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_X_INIT_SCR,0,0,0);
  1422. if (ok)
  1423. ha->screen_feat = GDT_64BIT;
  1424. }
  1425. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1426. ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_INIT,0,0,0);
  1427. if (!ok) {
  1428. printk("GDT-HA %d: Initialization error screen service (code %d)\n",
  1429. hanum, ha->status);
  1430. return 0;
  1431. }
  1432. TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
  1433. #ifdef GDTH_RTC
  1434. /* read realtime clock info, send to controller */
  1435. /* 1. wait for the falling edge of update flag */
  1436. spin_lock_irqsave(&rtc_lock, flags);
  1437. for (j = 0; j < 1000000; ++j)
  1438. if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
  1439. break;
  1440. for (j = 0; j < 1000000; ++j)
  1441. if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
  1442. break;
  1443. /* 2. read info */
  1444. do {
  1445. for (j = 0; j < 12; ++j)
  1446. rtc[j] = CMOS_READ(j);
  1447. } while (rtc[0] != CMOS_READ(0));
  1448. spin_unlock_irqrestore(&rtc_lock, flags);
  1449. TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
  1450. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
  1451. /* 3. send to controller firmware */
  1452. gdth_internal_cmd(hanum,SCREENSERVICE,GDT_REALTIME, *(ulong32 *)&rtc[0],
  1453. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
  1454. #endif
  1455. /* unfreeze all IOs */
  1456. gdth_internal_cmd(hanum,CACHESERVICE,GDT_UNFREEZE_IO,0,0,0);
  1457. /* initialize cache service */
  1458. ha->cache_feat = 0;
  1459. if (!force_dma32) {
  1460. ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INIT_HOST,LINUX_OS,0,0);
  1461. if (ok)
  1462. ha->cache_feat = GDT_64BIT;
  1463. }
  1464. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1465. ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_INIT,LINUX_OS,0,0);
  1466. if (!ok) {
  1467. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1468. hanum, ha->status);
  1469. return 0;
  1470. }
  1471. TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
  1472. cdev_cnt = (ushort)ha->info;
  1473. ha->fw_vers = ha->service;
  1474. #ifdef INT_COAL
  1475. if (ha->type == GDT_PCIMPR) {
  1476. /* set perf. modes */
  1477. pmod = (gdth_perf_modes *)ha->pscratch;
  1478. pmod->version = 1;
  1479. pmod->st_mode = 1; /* enable one status buffer */
  1480. *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
  1481. pmod->st_buff_indx1 = COALINDEX;
  1482. pmod->st_buff_addr2 = 0;
  1483. pmod->st_buff_u_addr2 = 0;
  1484. pmod->st_buff_indx2 = 0;
  1485. pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
  1486. pmod->cmd_mode = 0; // disable all cmd buffers
  1487. pmod->cmd_buff_addr1 = 0;
  1488. pmod->cmd_buff_u_addr1 = 0;
  1489. pmod->cmd_buff_indx1 = 0;
  1490. pmod->cmd_buff_addr2 = 0;
  1491. pmod->cmd_buff_u_addr2 = 0;
  1492. pmod->cmd_buff_indx2 = 0;
  1493. pmod->cmd_buff_size = 0;
  1494. pmod->reserved1 = 0;
  1495. pmod->reserved2 = 0;
  1496. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,SET_PERF_MODES,
  1497. INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
  1498. printk("GDT-HA %d: Interrupt coalescing activated\n", hanum);
  1499. }
  1500. }
  1501. #endif
  1502. /* detect number of buses - try new IOCTL */
  1503. iocr = (gdth_raw_iochan_str *)ha->pscratch;
  1504. iocr->hdr.version = 0xffffffff;
  1505. iocr->hdr.list_entries = MAXBUS;
  1506. iocr->hdr.first_chan = 0;
  1507. iocr->hdr.last_chan = MAXBUS-1;
  1508. iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
  1509. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_RAW_DESC,
  1510. INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
  1511. TRACE2(("IOCHAN_RAW_DESC supported!\n"));
  1512. ha->bus_cnt = iocr->hdr.chan_count;
  1513. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1514. if (iocr->list[bus_no].proc_id < MAXID)
  1515. ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
  1516. else
  1517. ha->bus_id[bus_no] = 0xff;
  1518. }
  1519. } else {
  1520. /* old method */
  1521. chn = (gdth_getch_str *)ha->pscratch;
  1522. for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
  1523. chn->channel_no = bus_no;
  1524. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1525. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1526. IO_CHANNEL | INVALID_CHANNEL,
  1527. sizeof(gdth_getch_str))) {
  1528. if (bus_no == 0) {
  1529. printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
  1530. hanum, ha->status);
  1531. return 0;
  1532. }
  1533. break;
  1534. }
  1535. if (chn->siop_id < MAXID)
  1536. ha->bus_id[bus_no] = chn->siop_id;
  1537. else
  1538. ha->bus_id[bus_no] = 0xff;
  1539. }
  1540. ha->bus_cnt = (unchar)bus_no;
  1541. }
  1542. TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
  1543. /* read cache configuration */
  1544. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_INFO,
  1545. INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
  1546. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1547. hanum, ha->status);
  1548. return 0;
  1549. }
  1550. ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
  1551. TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
  1552. ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
  1553. ha->cpar.write_back,ha->cpar.block_size));
  1554. /* read board info and features */
  1555. ha->more_proc = FALSE;
  1556. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_INFO,
  1557. INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
  1558. memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
  1559. sizeof(gdth_binfo_str));
  1560. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_FEATURES,
  1561. INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
  1562. TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
  1563. ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
  1564. ha->more_proc = TRUE;
  1565. }
  1566. } else {
  1567. TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
  1568. strcpy(ha->binfo.type_string, gdth_ctr_name(hanum));
  1569. }
  1570. TRACE2(("Controller name: %s\n",ha->binfo.type_string));
  1571. /* read more informations */
  1572. if (ha->more_proc) {
  1573. /* physical drives, channel addresses */
  1574. ioc = (gdth_iochan_str *)ha->pscratch;
  1575. ioc->hdr.version = 0xffffffff;
  1576. ioc->hdr.list_entries = MAXBUS;
  1577. ioc->hdr.first_chan = 0;
  1578. ioc->hdr.last_chan = MAXBUS-1;
  1579. ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
  1580. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_DESC,
  1581. INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
  1582. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1583. ha->raw[bus_no].address = ioc->list[bus_no].address;
  1584. ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
  1585. }
  1586. } else {
  1587. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1588. ha->raw[bus_no].address = IO_CHANNEL;
  1589. ha->raw[bus_no].local_no = bus_no;
  1590. }
  1591. }
  1592. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1593. chn = (gdth_getch_str *)ha->pscratch;
  1594. chn->channel_no = ha->raw[bus_no].local_no;
  1595. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1596. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1597. ha->raw[bus_no].address | INVALID_CHANNEL,
  1598. sizeof(gdth_getch_str))) {
  1599. ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
  1600. TRACE2(("Channel %d: %d phys. drives\n",
  1601. bus_no,chn->drive_cnt));
  1602. }
  1603. if (ha->raw[bus_no].pdev_cnt > 0) {
  1604. drl = (gdth_drlist_str *)ha->pscratch;
  1605. drl->sc_no = ha->raw[bus_no].local_no;
  1606. drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
  1607. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1608. SCSI_DR_LIST | L_CTRL_PATTERN,
  1609. ha->raw[bus_no].address | INVALID_CHANNEL,
  1610. sizeof(gdth_drlist_str))) {
  1611. for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
  1612. ha->raw[bus_no].id_list[j] = drl->sc_list[j];
  1613. } else {
  1614. ha->raw[bus_no].pdev_cnt = 0;
  1615. }
  1616. }
  1617. }
  1618. /* logical drives */
  1619. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_CNT,
  1620. INVALID_CHANNEL,sizeof(ulong32))) {
  1621. drv_cnt = *(ulong32 *)ha->pscratch;
  1622. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_LIST,
  1623. INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
  1624. for (j = 0; j < drv_cnt; ++j) {
  1625. drv_no = ((ulong32 *)ha->pscratch)[j];
  1626. if (drv_no < MAX_LDRIVES) {
  1627. ha->hdr[drv_no].is_logdrv = TRUE;
  1628. TRACE2(("Drive %d is log. drive\n",drv_no));
  1629. }
  1630. }
  1631. }
  1632. alst = (gdth_arcdl_str *)ha->pscratch;
  1633. alst->entries_avail = MAX_LDRIVES;
  1634. alst->first_entry = 0;
  1635. alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
  1636. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1637. ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
  1638. INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
  1639. (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
  1640. for (j = 0; j < alst->entries_init; ++j) {
  1641. ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
  1642. ha->hdr[j].is_master = alst->list[j].is_master;
  1643. ha->hdr[j].is_parity = alst->list[j].is_parity;
  1644. ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
  1645. ha->hdr[j].master_no = alst->list[j].cd_handle;
  1646. }
  1647. } else if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1648. ARRAY_DRV_LIST | LA_CTRL_PATTERN,
  1649. 0, 35 * sizeof(gdth_alist_str))) {
  1650. for (j = 0; j < 35; ++j) {
  1651. alst2 = &((gdth_alist_str *)ha->pscratch)[j];
  1652. ha->hdr[j].is_arraydrv = alst2->is_arrayd;
  1653. ha->hdr[j].is_master = alst2->is_master;
  1654. ha->hdr[j].is_parity = alst2->is_parity;
  1655. ha->hdr[j].is_hotfix = alst2->is_hotfix;
  1656. ha->hdr[j].master_no = alst2->cd_handle;
  1657. }
  1658. }
  1659. }
  1660. }
  1661. /* initialize raw service */
  1662. ha->raw_feat = 0;
  1663. if (!force_dma32) {
  1664. ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_X_INIT_RAW,0,0,0);
  1665. if (ok)
  1666. ha->raw_feat = GDT_64BIT;
  1667. }
  1668. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1669. ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_INIT,0,0,0);
  1670. if (!ok) {
  1671. printk("GDT-HA %d: Initialization error raw service (code %d)\n",
  1672. hanum, ha->status);
  1673. return 0;
  1674. }
  1675. TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
  1676. /* set/get features raw service (scatter/gather) */
  1677. if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_SET_FEAT,SCATTER_GATHER,
  1678. 0,0)) {
  1679. TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
  1680. if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_GET_FEAT,0,0,0)) {
  1681. TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
  1682. ha->info));
  1683. ha->raw_feat |= (ushort)ha->info;
  1684. }
  1685. }
  1686. /* set/get features cache service (equal to raw service) */
  1687. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_SET_FEAT,0,
  1688. SCATTER_GATHER,0)) {
  1689. TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
  1690. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_GET_FEAT,0,0,0)) {
  1691. TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
  1692. ha->info));
  1693. ha->cache_feat |= (ushort)ha->info;
  1694. }
  1695. }
  1696. /* reserve drives for raw service */
  1697. if (reserve_mode != 0) {
  1698. gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE_ALL,
  1699. reserve_mode == 1 ? 1 : 3, 0, 0);
  1700. TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
  1701. ha->status));
  1702. }
  1703. for (i = 0; i < MAX_RES_ARGS; i += 4) {
  1704. if (reserve_list[i] == hanum && reserve_list[i+1] < ha->bus_cnt &&
  1705. reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
  1706. TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
  1707. reserve_list[i], reserve_list[i+1],
  1708. reserve_list[i+2], reserve_list[i+3]));
  1709. if (!gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE,0,
  1710. reserve_list[i+1], reserve_list[i+2] |
  1711. (reserve_list[i+3] << 8))) {
  1712. printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
  1713. hanum, ha->status);
  1714. }
  1715. }
  1716. }
  1717. /* Determine OEM string using IOCTL */
  1718. oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
  1719. oemstr->params.ctl_version = 0x01;
  1720. oemstr->params.buffer_size = sizeof(oemstr->text);
  1721. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1722. CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
  1723. sizeof(gdth_oem_str_ioctl))) {
  1724. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
  1725. printk("GDT-HA %d: Vendor: %s Name: %s\n",
  1726. hanum,oemstr->text.oem_company_name,ha->binfo.type_string);
  1727. /* Save the Host Drive inquiry data */
  1728. strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
  1729. sizeof(ha->oem_name));
  1730. } else {
  1731. /* Old method, based on PCI ID */
  1732. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
  1733. printk("GDT-HA %d: Name: %s\n",
  1734. hanum,ha->binfo.type_string);
  1735. if (ha->oem_id == OEM_ID_INTEL)
  1736. strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
  1737. else
  1738. strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
  1739. }
  1740. /* scanning for host drives */
  1741. for (i = 0; i < cdev_cnt; ++i)
  1742. gdth_analyse_hdrive(hanum,i);
  1743. TRACE(("gdth_search_drives() OK\n"));
  1744. return 1;
  1745. }
  1746. static int gdth_analyse_hdrive(int hanum,ushort hdrive)
  1747. {
  1748. register gdth_ha_str *ha;
  1749. ulong32 drv_cyls;
  1750. int drv_hds, drv_secs;
  1751. TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n",hanum,hdrive));
  1752. if (hdrive >= MAX_HDRIVES)
  1753. return 0;
  1754. ha = HADATA(gdth_ctr_tab[hanum]);
  1755. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_INFO,hdrive,0,0))
  1756. return 0;
  1757. ha->hdr[hdrive].present = TRUE;
  1758. ha->hdr[hdrive].size = ha->info;
  1759. /* evaluate mapping (sectors per head, heads per cylinder) */
  1760. ha->hdr[hdrive].size &= ~SECS32;
  1761. if (ha->info2 == 0) {
  1762. gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
  1763. } else {
  1764. drv_hds = ha->info2 & 0xff;
  1765. drv_secs = (ha->info2 >> 8) & 0xff;
  1766. drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
  1767. }
  1768. ha->hdr[hdrive].heads = (unchar)drv_hds;
  1769. ha->hdr[hdrive].secs = (unchar)drv_secs;
  1770. /* round size */
  1771. ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
  1772. if (ha->cache_feat & GDT_64BIT) {
  1773. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INFO,hdrive,0,0)
  1774. && ha->info2 != 0) {
  1775. ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
  1776. }
  1777. }
  1778. TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
  1779. hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
  1780. /* get informations about device */
  1781. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_DEVTYPE,hdrive,0,0)) {
  1782. TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
  1783. hdrive,ha->info));
  1784. ha->hdr[hdrive].devtype = (ushort)ha->info;
  1785. }
  1786. /* cluster info */
  1787. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_CLUST_INFO,hdrive,0,0)) {
  1788. TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
  1789. hdrive,ha->info));
  1790. if (!shared_access)
  1791. ha->hdr[hdrive].cluster_type = (unchar)ha->info;
  1792. }
  1793. /* R/W attributes */
  1794. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_RW_ATTRIBS,hdrive,0,0)) {
  1795. TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
  1796. hdrive,ha->info));
  1797. ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
  1798. }
  1799. return 1;
  1800. }
  1801. /* command queueing/sending functions */
  1802. static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority)
  1803. {
  1804. register gdth_ha_str *ha;
  1805. register Scsi_Cmnd *pscp;
  1806. register Scsi_Cmnd *nscp;
  1807. ulong flags;
  1808. unchar b, t;
  1809. TRACE(("gdth_putq() priority %d\n",priority));
  1810. ha = HADATA(gdth_ctr_tab[hanum]);
  1811. spin_lock_irqsave(&ha->smp_lock, flags);
  1812. if (!IS_GDTH_INTERNAL_CMD(scp)) {
  1813. scp->SCp.this_residual = (int)priority;
  1814. b = scp->device->channel;
  1815. t = scp->device->id;
  1816. if (priority >= DEFAULT_PRI) {
  1817. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1818. (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
  1819. TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
  1820. scp->SCp.buffers_residual = gdth_update_timeout(hanum, scp, 0);
  1821. }
  1822. }
  1823. }
  1824. if (ha->req_first==NULL) {
  1825. ha->req_first = scp; /* queue was empty */
  1826. scp->SCp.ptr = NULL;
  1827. } else { /* queue not empty */
  1828. pscp = ha->req_first;
  1829. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1830. /* priority: 0-highest,..,0xff-lowest */
  1831. while (nscp && (unchar)nscp->SCp.this_residual <= priority) {
  1832. pscp = nscp;
  1833. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1834. }
  1835. pscp->SCp.ptr = (char *)scp;
  1836. scp->SCp.ptr = (char *)nscp;
  1837. }
  1838. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1839. #ifdef GDTH_STATISTICS
  1840. flags = 0;
  1841. for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  1842. ++flags;
  1843. if (max_rq < flags) {
  1844. max_rq = flags;
  1845. TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
  1846. }
  1847. #endif
  1848. }
  1849. static void gdth_next(int hanum)
  1850. {
  1851. register gdth_ha_str *ha;
  1852. register Scsi_Cmnd *pscp;
  1853. register Scsi_Cmnd *nscp;
  1854. unchar b, t, l, firsttime;
  1855. unchar this_cmd, next_cmd;
  1856. ulong flags = 0;
  1857. int cmd_index;
  1858. TRACE(("gdth_next() hanum %d\n",hanum));
  1859. ha = HADATA(gdth_ctr_tab[hanum]);
  1860. if (!gdth_polling)
  1861. spin_lock_irqsave(&ha->smp_lock, flags);
  1862. ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
  1863. this_cmd = firsttime = TRUE;
  1864. next_cmd = gdth_polling ? FALSE:TRUE;
  1865. cmd_index = 0;
  1866. for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
  1867. if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
  1868. pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1869. if (!IS_GDTH_INTERNAL_CMD(nscp)) {
  1870. b = nscp->device->channel;
  1871. t = nscp->device->id;
  1872. l = nscp->device->lun;
  1873. if (nscp->SCp.this_residual >= DEFAULT_PRI) {
  1874. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1875. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
  1876. continue;
  1877. }
  1878. } else
  1879. b = t = l = 0;
  1880. if (firsttime) {
  1881. if (gdth_test_busy(hanum)) { /* controller busy ? */
  1882. TRACE(("gdth_next() controller %d busy !\n",hanum));
  1883. if (!gdth_polling) {
  1884. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1885. return;
  1886. }
  1887. while (gdth_test_busy(hanum))
  1888. gdth_delay(1);
  1889. }
  1890. firsttime = FALSE;
  1891. }
  1892. if (!IS_GDTH_INTERNAL_CMD(nscp)) {
  1893. if (nscp->SCp.phase == -1) {
  1894. nscp->SCp.phase = CACHESERVICE; /* default: cache svc. */
  1895. if (nscp->cmnd[0] == TEST_UNIT_READY) {
  1896. TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
  1897. b, t, l));
  1898. /* TEST_UNIT_READY -> set scan mode */
  1899. if ((ha->scan_mode & 0x0f) == 0) {
  1900. if (b == 0 && t == 0 && l == 0) {
  1901. ha->scan_mode |= 1;
  1902. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1903. }
  1904. } else if ((ha->scan_mode & 0x0f) == 1) {
  1905. if (b == 0 && ((t == 0 && l == 1) ||
  1906. (t == 1 && l == 0))) {
  1907. nscp->SCp.sent_command = GDT_SCAN_START;
  1908. nscp->SCp.phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
  1909. | SCSIRAWSERVICE;
  1910. ha->scan_mode = 0x12;
  1911. TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
  1912. ha->scan_mode));
  1913. } else {
  1914. ha->scan_mode &= 0x10;
  1915. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1916. }
  1917. } else if (ha->scan_mode == 0x12) {
  1918. if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
  1919. nscp->SCp.phase = SCSIRAWSERVICE;
  1920. nscp->SCp.sent_command = GDT_SCAN_END;
  1921. ha->scan_mode &= 0x10;
  1922. TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
  1923. ha->scan_mode));
  1924. }
  1925. }
  1926. }
  1927. if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
  1928. nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
  1929. (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
  1930. /* always GDT_CLUST_INFO! */
  1931. nscp->SCp.sent_command = GDT_CLUST_INFO;
  1932. }
  1933. }
  1934. }
  1935. if (nscp->SCp.sent_command != -1) {
  1936. if ((nscp->SCp.phase & 0xff) == CACHESERVICE) {
  1937. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  1938. this_cmd = FALSE;
  1939. next_cmd = FALSE;
  1940. } else if ((nscp->SCp.phase & 0xff) == SCSIRAWSERVICE) {
  1941. if (!(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
  1942. this_cmd = FALSE;
  1943. next_cmd = FALSE;
  1944. } else {
  1945. memset((char*)nscp->sense_buffer,0,16);
  1946. nscp->sense_buffer[0] = 0x70;
  1947. nscp->sense_buffer[2] = NOT_READY;
  1948. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1949. if (!nscp->SCp.have_data_in)
  1950. nscp->SCp.have_data_in++;
  1951. else
  1952. gdth_scsi_done(nscp);
  1953. }
  1954. } else if (IS_GDTH_INTERNAL_CMD(nscp)) {
  1955. if (!(cmd_index=gdth_special_cmd(hanum,nscp)))
  1956. this_cmd = FALSE;
  1957. next_cmd = FALSE;
  1958. } else if (b != ha->virt_bus) {
  1959. if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
  1960. !(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
  1961. this_cmd = FALSE;
  1962. else
  1963. ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
  1964. } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
  1965. TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
  1966. nscp->cmnd[0], b, t, l));
  1967. nscp->result = DID_BAD_TARGET << 16;
  1968. if (!nscp->SCp.have_data_in)
  1969. nscp->SCp.have_data_in++;
  1970. else
  1971. gdth_scsi_done(nscp);
  1972. } else {
  1973. switch (nscp->cmnd[0]) {
  1974. case TEST_UNIT_READY:
  1975. case INQUIRY:
  1976. case REQUEST_SENSE:
  1977. case READ_CAPACITY:
  1978. case VERIFY:
  1979. case START_STOP:
  1980. case MODE_SENSE:
  1981. case SERVICE_ACTION_IN:
  1982. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  1983. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  1984. nscp->cmnd[4],nscp->cmnd[5]));
  1985. if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
  1986. /* return UNIT_ATTENTION */
  1987. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  1988. nscp->cmnd[0], t));
  1989. ha->hdr[t].media_changed = FALSE;
  1990. memset((char*)nscp->sense_buffer,0,16);
  1991. nscp->sense_buffer[0] = 0x70;
  1992. nscp->sense_buffer[2] = UNIT_ATTENTION;
  1993. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1994. if (!nscp->SCp.have_data_in)
  1995. nscp->SCp.have_data_in++;
  1996. else
  1997. gdth_scsi_done(nscp);
  1998. } else if (gdth_internal_cache_cmd(hanum, nscp))
  1999. gdth_scsi_done(nscp);
  2000. break;
  2001. case ALLOW_MEDIUM_REMOVAL:
  2002. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2003. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2004. nscp->cmnd[4],nscp->cmnd[5]));
  2005. if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
  2006. TRACE(("Prevent r. nonremov. drive->do nothing\n"));
  2007. nscp->result = DID_OK << 16;
  2008. nscp->sense_buffer[0] = 0;
  2009. if (!nscp->SCp.have_data_in)
  2010. nscp->SCp.have_data_in++;
  2011. else
  2012. gdth_scsi_done(nscp);
  2013. } else {
  2014. nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
  2015. TRACE(("Prevent/allow r. %d rem. drive %d\n",
  2016. nscp->cmnd[4],nscp->cmnd[3]));
  2017. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2018. this_cmd = FALSE;
  2019. }
  2020. break;
  2021. case RESERVE:
  2022. case RELEASE:
  2023. TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
  2024. "RESERVE" : "RELEASE"));
  2025. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2026. this_cmd = FALSE;
  2027. break;
  2028. case READ_6:
  2029. case WRITE_6:
  2030. case READ_10:
  2031. case WRITE_10:
  2032. case READ_16:
  2033. case WRITE_16:
  2034. if (ha->hdr[t].media_changed) {
  2035. /* return UNIT_ATTENTION */
  2036. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2037. nscp->cmnd[0], t));
  2038. ha->hdr[t].media_changed = FALSE;
  2039. memset((char*)nscp->sense_buffer,0,16);
  2040. nscp->sense_buffer[0] = 0x70;
  2041. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2042. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2043. if (!nscp->SCp.have_data_in)
  2044. nscp->SCp.have_data_in++;
  2045. else
  2046. gdth_scsi_done(nscp);
  2047. } else if (!(cmd_index=gdth_fill_cache_cmd(hanum, nscp, t)))
  2048. this_cmd = FALSE;
  2049. break;
  2050. default:
  2051. TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
  2052. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2053. nscp->cmnd[4],nscp->cmnd[5]));
  2054. printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
  2055. hanum, nscp->cmnd[0]);
  2056. nscp->result = DID_ABORT << 16;
  2057. if (!nscp->SCp.have_data_in)
  2058. nscp->SCp.have_data_in++;
  2059. else
  2060. gdth_scsi_done(nscp);
  2061. break;
  2062. }
  2063. }
  2064. if (!this_cmd)
  2065. break;
  2066. if (nscp == ha->req_first)
  2067. ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
  2068. else
  2069. pscp->SCp.ptr = nscp->SCp.ptr;
  2070. if (!next_cmd)
  2071. break;
  2072. }
  2073. if (ha->cmd_cnt > 0) {
  2074. gdth_release_event(hanum);
  2075. }
  2076. if (!gdth_polling)
  2077. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2078. if (gdth_polling && ha->cmd_cnt > 0) {
  2079. if (!gdth_wait(hanum,cmd_index,POLL_TIMEOUT))
  2080. printk("GDT-HA %d: Command %d timed out !\n",
  2081. hanum,cmd_index);
  2082. }
  2083. }
  2084. static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
  2085. char *buffer,ushort count)
  2086. {
  2087. ushort cpcount,i;
  2088. ushort cpsum,cpnow;
  2089. struct scatterlist *sl;
  2090. gdth_ha_str *ha;
  2091. char *address;
  2092. cpcount = count<=(ushort)scp->request_bufflen ? count:(ushort)scp->request_bufflen;
  2093. ha = HADATA(gdth_ctr_tab[hanum]);
  2094. if (scp->use_sg) {
  2095. sl = (struct scatterlist *)scp->request_buffer;
  2096. for (i=0,cpsum=0; i<scp->use_sg; ++i,++sl) {
  2097. unsigned long flags;
  2098. cpnow = (ushort)sl->length;
  2099. TRACE(("copy_internal() now %d sum %d count %d %d\n",
  2100. cpnow,cpsum,cpcount,(ushort)scp->bufflen));
  2101. if (cpsum+cpnow > cpcount)
  2102. cpnow = cpcount - cpsum;
  2103. cpsum += cpnow;
  2104. if (!sl->page) {
  2105. printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
  2106. hanum);
  2107. return;
  2108. }
  2109. local_irq_save(flags);
  2110. address = kmap_atomic(sl->page, KM_BIO_SRC_IRQ) + sl->offset;
  2111. memcpy(address,buffer,cpnow);
  2112. flush_dcache_page(sl->page);
  2113. kunmap_atomic(address, KM_BIO_SRC_IRQ);
  2114. local_irq_restore(flags);
  2115. if (cpsum == cpcount)
  2116. break;
  2117. buffer += cpnow;
  2118. }
  2119. } else {
  2120. TRACE(("copy_internal() count %d\n",cpcount));
  2121. memcpy((char*)scp->request_buffer,buffer,cpcount);
  2122. }
  2123. }
  2124. static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp)
  2125. {
  2126. register gdth_ha_str *ha;
  2127. unchar t;
  2128. gdth_inq_data inq;
  2129. gdth_rdcap_data rdc;
  2130. gdth_sense_data sd;
  2131. gdth_modep_data mpd;
  2132. ha = HADATA(gdth_ctr_tab[hanum]);
  2133. t = scp->device->id;
  2134. TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
  2135. scp->cmnd[0],t));
  2136. scp->result = DID_OK << 16;
  2137. scp->sense_buffer[0] = 0;
  2138. switch (scp->cmnd[0]) {
  2139. case TEST_UNIT_READY:
  2140. case VERIFY:
  2141. case START_STOP:
  2142. TRACE2(("Test/Verify/Start hdrive %d\n",t));
  2143. break;
  2144. case INQUIRY:
  2145. TRACE2(("Inquiry hdrive %d devtype %d\n",
  2146. t,ha->hdr[t].devtype));
  2147. inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
  2148. /* you can here set all disks to removable, if you want to do
  2149. a flush using the ALLOW_MEDIUM_REMOVAL command */
  2150. inq.modif_rmb = 0x00;
  2151. if ((ha->hdr[t].devtype & 1) ||
  2152. (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
  2153. inq.modif_rmb = 0x80;
  2154. inq.version = 2;
  2155. inq.resp_aenc = 2;
  2156. inq.add_length= 32;
  2157. strcpy(inq.vendor,ha->oem_name);
  2158. sprintf(inq.product,"Host Drive #%02d",t);
  2159. strcpy(inq.revision," ");
  2160. gdth_copy_internal_data(hanum,scp,(char*)&inq,sizeof(gdth_inq_data));
  2161. break;
  2162. case REQUEST_SENSE:
  2163. TRACE2(("Request sense hdrive %d\n",t));
  2164. sd.errorcode = 0x70;
  2165. sd.segno = 0x00;
  2166. sd.key = NO_SENSE;
  2167. sd.info = 0;
  2168. sd.add_length= 0;
  2169. gdth_copy_internal_data(hanum,scp,(char*)&sd,sizeof(gdth_sense_data));
  2170. break;
  2171. case MODE_SENSE:
  2172. TRACE2(("Mode sense hdrive %d\n",t));
  2173. memset((char*)&mpd,0,sizeof(gdth_modep_data));
  2174. mpd.hd.data_length = sizeof(gdth_modep_data);
  2175. mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
  2176. mpd.hd.bd_length = sizeof(mpd.bd);
  2177. mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
  2178. mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
  2179. mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
  2180. gdth_copy_internal_data(hanum,scp,(char*)&mpd,sizeof(gdth_modep_data));
  2181. break;
  2182. case READ_CAPACITY:
  2183. TRACE2(("Read capacity hdrive %d\n",t));
  2184. if (ha->hdr[t].size > (ulong64)0xffffffff)
  2185. rdc.last_block_no = 0xffffffff;
  2186. else
  2187. rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
  2188. rdc.block_length = cpu_to_be32(SECTOR_SIZE);
  2189. gdth_copy_internal_data(hanum,scp,(char*)&rdc,sizeof(gdth_rdcap_data));
  2190. break;
  2191. case SERVICE_ACTION_IN:
  2192. if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
  2193. (ha->cache_feat & GDT_64BIT)) {
  2194. gdth_rdcap16_data rdc16;
  2195. TRACE2(("Read capacity (16) hdrive %d\n",t));
  2196. rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
  2197. rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
  2198. gdth_copy_internal_data(hanum,scp,(char*)&rdc16,sizeof(gdth_rdcap16_data));
  2199. } else {
  2200. scp->result = DID_ABORT << 16;
  2201. }
  2202. break;
  2203. default:
  2204. TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
  2205. break;
  2206. }
  2207. if (!scp->SCp.have_data_in)
  2208. scp->SCp.have_data_in++;
  2209. else
  2210. return 1;
  2211. return 0;
  2212. }
  2213. static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive)
  2214. {
  2215. register gdth_ha_str *ha;
  2216. register gdth_cmd_str *cmdp;
  2217. struct scatterlist *sl;
  2218. ulong32 cnt, blockcnt;
  2219. ulong64 no, blockno;
  2220. dma_addr_t phys_addr;
  2221. int i, cmd_index, read_write, sgcnt, mode64;
  2222. struct page *page;
  2223. ulong offset;
  2224. ha = HADATA(gdth_ctr_tab[hanum]);
  2225. cmdp = ha->pccb;
  2226. TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
  2227. scp->cmnd[0],scp->cmd_len,hdrive));
  2228. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2229. return 0;
  2230. mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
  2231. /* test for READ_16, WRITE_16 if !mode64 ? ---
  2232. not required, should not occur due to error return on
  2233. READ_CAPACITY_16 */
  2234. cmdp->Service = CACHESERVICE;
  2235. cmdp->RequestBuffer = scp;
  2236. /* search free command index */
  2237. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2238. TRACE(("GDT: No free command index found\n"));
  2239. return 0;
  2240. }
  2241. /* if it's the first command, set command semaphore */
  2242. if (ha->cmd_cnt == 0)
  2243. gdth_set_sema0(hanum);
  2244. /* fill command */
  2245. read_write = 0;
  2246. if (scp->SCp.sent_command != -1)
  2247. cmdp->OpCode = scp->SCp.sent_command; /* special cache cmd. */
  2248. else if (scp->cmnd[0] == RESERVE)
  2249. cmdp->OpCode = GDT_RESERVE_DRV;
  2250. else if (scp->cmnd[0] == RELEASE)
  2251. cmdp->OpCode = GDT_RELEASE_DRV;
  2252. else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
  2253. if (scp->cmnd[4] & 1) /* prevent ? */
  2254. cmdp->OpCode = GDT_MOUNT;
  2255. else if (scp->cmnd[3] & 1) /* removable drive ? */
  2256. cmdp->OpCode = GDT_UNMOUNT;
  2257. else
  2258. cmdp->OpCode = GDT_FLUSH;
  2259. } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
  2260. scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
  2261. ) {
  2262. read_write = 1;
  2263. if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
  2264. (ha->cache_feat & GDT_WR_THROUGH)))
  2265. cmdp->OpCode = GDT_WRITE_THR;
  2266. else
  2267. cmdp->OpCode = GDT_WRITE;
  2268. } else {
  2269. read_write = 2;
  2270. cmdp->OpCode = GDT_READ;
  2271. }
  2272. cmdp->BoardNode = LOCALBOARD;
  2273. if (mode64) {
  2274. cmdp->u.cache64.DeviceNo = hdrive;
  2275. cmdp->u.cache64.BlockNo = 1;
  2276. cmdp->u.cache64.sg_canz = 0;
  2277. } else {
  2278. cmdp->u.cache.DeviceNo = hdrive;
  2279. cmdp->u.cache.BlockNo = 1;
  2280. cmdp->u.cache.sg_canz = 0;
  2281. }
  2282. if (read_write) {
  2283. if (scp->cmd_len == 16) {
  2284. memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
  2285. blockno = be64_to_cpu(no);
  2286. memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
  2287. blockcnt = be32_to_cpu(cnt);
  2288. } else if (scp->cmd_len == 10) {
  2289. memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
  2290. blockno = be32_to_cpu(no);
  2291. memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
  2292. blockcnt = be16_to_cpu(cnt);
  2293. } else {
  2294. memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
  2295. blockno = be32_to_cpu(no) & 0x001fffffUL;
  2296. blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
  2297. }
  2298. if (mode64) {
  2299. cmdp->u.cache64.BlockNo = blockno;
  2300. cmdp->u.cache64.BlockCnt = blockcnt;
  2301. } else {
  2302. cmdp->u.cache.BlockNo = (ulong32)blockno;
  2303. cmdp->u.cache.BlockCnt = blockcnt;
  2304. }
  2305. if (scp->use_sg) {
  2306. sl = (struct scatterlist *)scp->request_buffer;
  2307. sgcnt = scp->use_sg;
  2308. scp->SCp.Status = GDTH_MAP_SG;
  2309. scp->SCp.Message = (read_write == 1 ?
  2310. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2311. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2312. if (mode64) {
  2313. cmdp->u.cache64.DestAddr= (ulong64)-1;
  2314. cmdp->u.cache64.sg_canz = sgcnt;
  2315. for (i=0; i<sgcnt; ++i,++sl) {
  2316. cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2317. #ifdef GDTH_DMA_STATISTICS
  2318. if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2319. ha->dma64_cnt++;
  2320. else
  2321. ha->dma32_cnt++;
  2322. #endif
  2323. cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
  2324. }
  2325. } else {
  2326. cmdp->u.cache.DestAddr= 0xffffffff;
  2327. cmdp->u.cache.sg_canz = sgcnt;
  2328. for (i=0; i<sgcnt; ++i,++sl) {
  2329. cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2330. #ifdef GDTH_DMA_STATISTICS
  2331. ha->dma32_cnt++;
  2332. #endif
  2333. cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
  2334. }
  2335. }
  2336. #ifdef GDTH_STATISTICS
  2337. if (max_sg < (ulong32)sgcnt) {
  2338. max_sg = (ulong32)sgcnt;
  2339. TRACE3(("GDT: max_sg = %d\n",max_sg));
  2340. }
  2341. #endif
  2342. } else if (scp->request_bufflen) {
  2343. scp->SCp.Status = GDTH_MAP_SINGLE;
  2344. scp->SCp.Message = (read_write == 1 ?
  2345. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2346. page = virt_to_page(scp->request_buffer);
  2347. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2348. phys_addr = pci_map_page(ha->pdev,page,offset,
  2349. scp->request_bufflen,scp->SCp.Message);
  2350. scp->SCp.dma_handle = phys_addr;
  2351. if (mode64) {
  2352. if (ha->cache_feat & SCATTER_GATHER) {
  2353. cmdp->u.cache64.DestAddr = (ulong64)-1;
  2354. cmdp->u.cache64.sg_canz = 1;
  2355. cmdp->u.cache64.sg_lst[0].sg_ptr = phys_addr;
  2356. cmdp->u.cache64.sg_lst[0].sg_len = scp->request_bufflen;
  2357. cmdp->u.cache64.sg_lst[1].sg_len = 0;
  2358. } else {
  2359. cmdp->u.cache64.DestAddr = phys_addr;
  2360. cmdp->u.cache64.sg_canz= 0;
  2361. }
  2362. } else {
  2363. if (ha->cache_feat & SCATTER_GATHER) {
  2364. cmdp->u.cache.DestAddr = 0xffffffff;
  2365. cmdp->u.cache.sg_canz = 1;
  2366. cmdp->u.cache.sg_lst[0].sg_ptr = phys_addr;
  2367. cmdp->u.cache.sg_lst[0].sg_len = scp->request_bufflen;
  2368. cmdp->u.cache.sg_lst[1].sg_len = 0;
  2369. } else {
  2370. cmdp->u.cache.DestAddr = phys_addr;
  2371. cmdp->u.cache.sg_canz= 0;
  2372. }
  2373. }
  2374. }
  2375. }
  2376. /* evaluate command size, check space */
  2377. if (mode64) {
  2378. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2379. cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
  2380. cmdp->u.cache64.sg_lst[0].sg_ptr,
  2381. cmdp->u.cache64.sg_lst[0].sg_len));
  2382. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2383. cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
  2384. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
  2385. (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
  2386. } else {
  2387. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2388. cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
  2389. cmdp->u.cache.sg_lst[0].sg_ptr,
  2390. cmdp->u.cache.sg_lst[0].sg_len));
  2391. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2392. cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
  2393. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
  2394. (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
  2395. }
  2396. if (ha->cmd_len & 3)
  2397. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2398. if (ha->cmd_cnt > 0) {
  2399. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2400. ha->ic_all_size) {
  2401. TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
  2402. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2403. return 0;
  2404. }
  2405. }
  2406. /* copy command */
  2407. gdth_copy_command(hanum);
  2408. return cmd_index;
  2409. }
  2410. static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b)
  2411. {
  2412. register gdth_ha_str *ha;
  2413. register gdth_cmd_str *cmdp;
  2414. struct scatterlist *sl;
  2415. ushort i;
  2416. dma_addr_t phys_addr, sense_paddr;
  2417. int cmd_index, sgcnt, mode64;
  2418. unchar t,l;
  2419. struct page *page;
  2420. ulong offset;
  2421. ha = HADATA(gdth_ctr_tab[hanum]);
  2422. t = scp->device->id;
  2423. l = scp->device->lun;
  2424. cmdp = ha->pccb;
  2425. TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
  2426. scp->cmnd[0],b,t,l));
  2427. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2428. return 0;
  2429. mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
  2430. cmdp->Service = SCSIRAWSERVICE;
  2431. cmdp->RequestBuffer = scp;
  2432. /* search free command index */
  2433. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2434. TRACE(("GDT: No free command index found\n"));
  2435. return 0;
  2436. }
  2437. /* if it's the first command, set command semaphore */
  2438. if (ha->cmd_cnt == 0)
  2439. gdth_set_sema0(hanum);
  2440. /* fill command */
  2441. if (scp->SCp.sent_command != -1) {
  2442. cmdp->OpCode = scp->SCp.sent_command; /* special raw cmd. */
  2443. cmdp->BoardNode = LOCALBOARD;
  2444. if (mode64) {
  2445. cmdp->u.raw64.direction = (scp->SCp.phase >> 8);
  2446. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2447. cmdp->OpCode, cmdp->u.raw64.direction));
  2448. /* evaluate command size */
  2449. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
  2450. } else {
  2451. cmdp->u.raw.direction = (scp->SCp.phase >> 8);
  2452. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2453. cmdp->OpCode, cmdp->u.raw.direction));
  2454. /* evaluate command size */
  2455. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
  2456. }
  2457. } else {
  2458. page = virt_to_page(scp->sense_buffer);
  2459. offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
  2460. sense_paddr = pci_map_page(ha->pdev,page,offset,
  2461. 16,PCI_DMA_FROMDEVICE);
  2462. *(ulong32 *)&scp->SCp.buffer = (ulong32)sense_paddr;
  2463. /* high part, if 64bit */
  2464. *(ulong32 *)&scp->host_scribble = (ulong32)((ulong64)sense_paddr >> 32);
  2465. cmdp->OpCode = GDT_WRITE; /* always */
  2466. cmdp->BoardNode = LOCALBOARD;
  2467. if (mode64) {
  2468. cmdp->u.raw64.reserved = 0;
  2469. cmdp->u.raw64.mdisc_time = 0;
  2470. cmdp->u.raw64.mcon_time = 0;
  2471. cmdp->u.raw64.clen = scp->cmd_len;
  2472. cmdp->u.raw64.target = t;
  2473. cmdp->u.raw64.lun = l;
  2474. cmdp->u.raw64.bus = b;
  2475. cmdp->u.raw64.priority = 0;
  2476. cmdp->u.raw64.sdlen = scp->request_bufflen;
  2477. cmdp->u.raw64.sense_len = 16;
  2478. cmdp->u.raw64.sense_data = sense_paddr;
  2479. cmdp->u.raw64.direction =
  2480. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2481. memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
  2482. cmdp->u.raw64.sg_ranz = 0;
  2483. } else {
  2484. cmdp->u.raw.reserved = 0;
  2485. cmdp->u.raw.mdisc_time = 0;
  2486. cmdp->u.raw.mcon_time = 0;
  2487. cmdp->u.raw.clen = scp->cmd_len;
  2488. cmdp->u.raw.target = t;
  2489. cmdp->u.raw.lun = l;
  2490. cmdp->u.raw.bus = b;
  2491. cmdp->u.raw.priority = 0;
  2492. cmdp->u.raw.link_p = 0;
  2493. cmdp->u.raw.sdlen = scp->request_bufflen;
  2494. cmdp->u.raw.sense_len = 16;
  2495. cmdp->u.raw.sense_data = sense_paddr;
  2496. cmdp->u.raw.direction =
  2497. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2498. memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
  2499. cmdp->u.raw.sg_ranz = 0;
  2500. }
  2501. if (scp->use_sg) {
  2502. sl = (struct scatterlist *)scp->request_buffer;
  2503. sgcnt = scp->use_sg;
  2504. scp->SCp.Status = GDTH_MAP_SG;
  2505. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2506. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2507. if (mode64) {
  2508. cmdp->u.raw64.sdata = (ulong64)-1;
  2509. cmdp->u.raw64.sg_ranz = sgcnt;
  2510. for (i=0; i<sgcnt; ++i,++sl) {
  2511. cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2512. #ifdef GDTH_DMA_STATISTICS
  2513. if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2514. ha->dma64_cnt++;
  2515. else
  2516. ha->dma32_cnt++;
  2517. #endif
  2518. cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
  2519. }
  2520. } else {
  2521. cmdp->u.raw.sdata = 0xffffffff;
  2522. cmdp->u.raw.sg_ranz = sgcnt;
  2523. for (i=0; i<sgcnt; ++i,++sl) {
  2524. cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2525. #ifdef GDTH_DMA_STATISTICS
  2526. ha->dma32_cnt++;
  2527. #endif
  2528. cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
  2529. }
  2530. }
  2531. #ifdef GDTH_STATISTICS
  2532. if (max_sg < sgcnt) {
  2533. max_sg = sgcnt;
  2534. TRACE3(("GDT: max_sg = %d\n",sgcnt));
  2535. }
  2536. #endif
  2537. } else if (scp->request_bufflen) {
  2538. scp->SCp.Status = GDTH_MAP_SINGLE;
  2539. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2540. page = virt_to_page(scp->request_buffer);
  2541. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2542. phys_addr = pci_map_page(ha->pdev,page,offset,
  2543. scp->request_bufflen,scp->SCp.Message);
  2544. scp->SCp.dma_handle = phys_addr;
  2545. if (mode64) {
  2546. if (ha->raw_feat & SCATTER_GATHER) {
  2547. cmdp->u.raw64.sdata = (ulong64)-1;
  2548. cmdp->u.raw64.sg_ranz= 1;
  2549. cmdp->u.raw64.sg_lst[0].sg_ptr = phys_addr;
  2550. cmdp->u.raw64.sg_lst[0].sg_len = scp->request_bufflen;
  2551. cmdp->u.raw64.sg_lst[1].sg_len = 0;
  2552. } else {
  2553. cmdp->u.raw64.sdata = phys_addr;
  2554. cmdp->u.raw64.sg_ranz= 0;
  2555. }
  2556. } else {
  2557. if (ha->raw_feat & SCATTER_GATHER) {
  2558. cmdp->u.raw.sdata = 0xffffffff;
  2559. cmdp->u.raw.sg_ranz= 1;
  2560. cmdp->u.raw.sg_lst[0].sg_ptr = phys_addr;
  2561. cmdp->u.raw.sg_lst[0].sg_len = scp->request_bufflen;
  2562. cmdp->u.raw.sg_lst[1].sg_len = 0;
  2563. } else {
  2564. cmdp->u.raw.sdata = phys_addr;
  2565. cmdp->u.raw.sg_ranz= 0;
  2566. }
  2567. }
  2568. }
  2569. if (mode64) {
  2570. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2571. cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
  2572. cmdp->u.raw64.sg_lst[0].sg_ptr,
  2573. cmdp->u.raw64.sg_lst[0].sg_len));
  2574. /* evaluate command size */
  2575. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
  2576. (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
  2577. } else {
  2578. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2579. cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
  2580. cmdp->u.raw.sg_lst[0].sg_ptr,
  2581. cmdp->u.raw.sg_lst[0].sg_len));
  2582. /* evaluate command size */
  2583. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
  2584. (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
  2585. }
  2586. }
  2587. /* check space */
  2588. if (ha->cmd_len & 3)
  2589. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2590. if (ha->cmd_cnt > 0) {
  2591. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2592. ha->ic_all_size) {
  2593. TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
  2594. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2595. return 0;
  2596. }
  2597. }
  2598. /* copy command */
  2599. gdth_copy_command(hanum);
  2600. return cmd_index;
  2601. }
  2602. static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp)
  2603. {
  2604. register gdth_ha_str *ha;
  2605. register gdth_cmd_str *cmdp;
  2606. int cmd_index;
  2607. ha = HADATA(gdth_ctr_tab[hanum]);
  2608. cmdp= ha->pccb;
  2609. TRACE2(("gdth_special_cmd(): "));
  2610. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2611. return 0;
  2612. memcpy( cmdp, scp->request_buffer, sizeof(gdth_cmd_str));
  2613. cmdp->RequestBuffer = scp;
  2614. /* search free command index */
  2615. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2616. TRACE(("GDT: No free command index found\n"));
  2617. return 0;
  2618. }
  2619. /* if it's the first command, set command semaphore */
  2620. if (ha->cmd_cnt == 0)
  2621. gdth_set_sema0(hanum);
  2622. /* evaluate command size, check space */
  2623. if (cmdp->OpCode == GDT_IOCTL) {
  2624. TRACE2(("IOCTL\n"));
  2625. ha->cmd_len =
  2626. GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
  2627. } else if (cmdp->Service == CACHESERVICE) {
  2628. TRACE2(("cache command %d\n",cmdp->OpCode));
  2629. if (ha->cache_feat & GDT_64BIT)
  2630. ha->cmd_len =
  2631. GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
  2632. else
  2633. ha->cmd_len =
  2634. GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
  2635. } else if (cmdp->Service == SCSIRAWSERVICE) {
  2636. TRACE2(("raw command %d\n",cmdp->OpCode));
  2637. if (ha->raw_feat & GDT_64BIT)
  2638. ha->cmd_len =
  2639. GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
  2640. else
  2641. ha->cmd_len =
  2642. GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
  2643. }
  2644. if (ha->cmd_len & 3)
  2645. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2646. if (ha->cmd_cnt > 0) {
  2647. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2648. ha->ic_all_size) {
  2649. TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
  2650. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2651. return 0;
  2652. }
  2653. }
  2654. /* copy command */
  2655. gdth_copy_command(hanum);
  2656. return cmd_index;
  2657. }
  2658. /* Controller event handling functions */
  2659. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  2660. ushort idx, gdth_evt_data *evt)
  2661. {
  2662. gdth_evt_str *e;
  2663. struct timeval tv;
  2664. /* no GDTH_LOCK_HA() ! */
  2665. TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
  2666. if (source == 0) /* no source -> no event */
  2667. return NULL;
  2668. if (ebuffer[elastidx].event_source == source &&
  2669. ebuffer[elastidx].event_idx == idx &&
  2670. ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
  2671. !memcmp((char *)&ebuffer[elastidx].event_data.eu,
  2672. (char *)&evt->eu, evt->size)) ||
  2673. (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
  2674. !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
  2675. (char *)&evt->event_string)))) {
  2676. e = &ebuffer[elastidx];
  2677. do_gettimeofday(&tv);
  2678. e->last_stamp = tv.tv_sec;
  2679. ++e->same_count;
  2680. } else {
  2681. if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
  2682. ++elastidx;
  2683. if (elastidx == MAX_EVENTS)
  2684. elastidx = 0;
  2685. if (elastidx == eoldidx) { /* reached mark ? */
  2686. ++eoldidx;
  2687. if (eoldidx == MAX_EVENTS)
  2688. eoldidx = 0;
  2689. }
  2690. }
  2691. e = &ebuffer[elastidx];
  2692. e->event_source = source;
  2693. e->event_idx = idx;
  2694. do_gettimeofday(&tv);
  2695. e->first_stamp = e->last_stamp = tv.tv_sec;
  2696. e->same_count = 1;
  2697. e->event_data = *evt;
  2698. e->application = 0;
  2699. }
  2700. return e;
  2701. }
  2702. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
  2703. {
  2704. gdth_evt_str *e;
  2705. int eindex;
  2706. ulong flags;
  2707. TRACE2(("gdth_read_event() handle %d\n", handle));
  2708. spin_lock_irqsave(&ha->smp_lock, flags);
  2709. if (handle == -1)
  2710. eindex = eoldidx;
  2711. else
  2712. eindex = handle;
  2713. estr->event_source = 0;
  2714. if (eindex >= MAX_EVENTS) {
  2715. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2716. return eindex;
  2717. }
  2718. e = &ebuffer[eindex];
  2719. if (e->event_source != 0) {
  2720. if (eindex != elastidx) {
  2721. if (++eindex == MAX_EVENTS)
  2722. eindex = 0;
  2723. } else {
  2724. eindex = -1;
  2725. }
  2726. memcpy(estr, e, sizeof(gdth_evt_str));
  2727. }
  2728. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2729. return eindex;
  2730. }
  2731. static void gdth_readapp_event(gdth_ha_str *ha,
  2732. unchar application, gdth_evt_str *estr)
  2733. {
  2734. gdth_evt_str *e;
  2735. int eindex;
  2736. ulong flags;
  2737. unchar found = FALSE;
  2738. TRACE2(("gdth_readapp_event() app. %d\n", application));
  2739. spin_lock_irqsave(&ha->smp_lock, flags);
  2740. eindex = eoldidx;
  2741. for (;;) {
  2742. e = &ebuffer[eindex];
  2743. if (e->event_source == 0)
  2744. break;
  2745. if ((e->application & application) == 0) {
  2746. e->application |= application;
  2747. found = TRUE;
  2748. break;
  2749. }
  2750. if (eindex == elastidx)
  2751. break;
  2752. if (++eindex == MAX_EVENTS)
  2753. eindex = 0;
  2754. }
  2755. if (found)
  2756. memcpy(estr, e, sizeof(gdth_evt_str));
  2757. else
  2758. estr->event_source = 0;
  2759. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2760. }
  2761. static void gdth_clear_events(void)
  2762. {
  2763. TRACE(("gdth_clear_events()"));
  2764. eoldidx = elastidx = 0;
  2765. ebuffer[0].event_source = 0;
  2766. }
  2767. /* SCSI interface functions */
  2768. static irqreturn_t gdth_interrupt(int irq,void *dev_id)
  2769. {
  2770. gdth_ha_str *ha2 = (gdth_ha_str *)dev_id;
  2771. register gdth_ha_str *ha;
  2772. gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
  2773. gdt6_dpram_str __iomem *dp6_ptr;
  2774. gdt2_dpram_str __iomem *dp2_ptr;
  2775. Scsi_Cmnd *scp;
  2776. int hanum, rval, i;
  2777. unchar IStatus;
  2778. ushort Service;
  2779. ulong flags = 0;
  2780. #ifdef INT_COAL
  2781. int coalesced = FALSE;
  2782. int next = FALSE;
  2783. gdth_coal_status *pcs = NULL;
  2784. int act_int_coal = 0;
  2785. #endif
  2786. TRACE(("gdth_interrupt() IRQ %d\n",irq));
  2787. /* if polling and not from gdth_wait() -> return */
  2788. if (gdth_polling) {
  2789. if (!gdth_from_wait) {
  2790. return IRQ_HANDLED;
  2791. }
  2792. }
  2793. if (!gdth_polling)
  2794. spin_lock_irqsave(&ha2->smp_lock, flags);
  2795. wait_index = 0;
  2796. /* search controller */
  2797. if ((hanum = gdth_get_status(&IStatus,irq)) == -1) {
  2798. /* spurious interrupt */
  2799. if (!gdth_polling)
  2800. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  2801. return IRQ_HANDLED;
  2802. }
  2803. ha = HADATA(gdth_ctr_tab[hanum]);
  2804. #ifdef GDTH_STATISTICS
  2805. ++act_ints;
  2806. #endif
  2807. #ifdef INT_COAL
  2808. /* See if the fw is returning coalesced status */
  2809. if (IStatus == COALINDEX) {
  2810. /* Coalesced status. Setup the initial status
  2811. buffer pointer and flags */
  2812. pcs = ha->coal_stat;
  2813. coalesced = TRUE;
  2814. next = TRUE;
  2815. }
  2816. do {
  2817. if (coalesced) {
  2818. /* For coalesced requests all status
  2819. information is found in the status buffer */
  2820. IStatus = (unchar)(pcs->status & 0xff);
  2821. }
  2822. #endif
  2823. if (ha->type == GDT_EISA) {
  2824. if (IStatus & 0x80) { /* error flag */
  2825. IStatus &= ~0x80;
  2826. ha->status = inw(ha->bmic + MAILBOXREG+8);
  2827. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2828. } else /* no error */
  2829. ha->status = S_OK;
  2830. ha->info = inl(ha->bmic + MAILBOXREG+12);
  2831. ha->service = inw(ha->bmic + MAILBOXREG+10);
  2832. ha->info2 = inl(ha->bmic + MAILBOXREG+4);
  2833. outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
  2834. outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
  2835. } else if (ha->type == GDT_ISA) {
  2836. dp2_ptr = ha->brd;
  2837. if (IStatus & 0x80) { /* error flag */
  2838. IStatus &= ~0x80;
  2839. ha->status = readw(&dp2_ptr->u.ic.Status);
  2840. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2841. } else /* no error */
  2842. ha->status = S_OK;
  2843. ha->info = readl(&dp2_ptr->u.ic.Info[0]);
  2844. ha->service = readw(&dp2_ptr->u.ic.Service);
  2845. ha->info2 = readl(&dp2_ptr->u.ic.Info[1]);
  2846. writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
  2847. writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
  2848. writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
  2849. } else if (ha->type == GDT_PCI) {
  2850. dp6_ptr = ha->brd;
  2851. if (IStatus & 0x80) { /* error flag */
  2852. IStatus &= ~0x80;
  2853. ha->status = readw(&dp6_ptr->u.ic.Status);
  2854. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2855. } else /* no error */
  2856. ha->status = S_OK;
  2857. ha->info = readl(&dp6_ptr->u.ic.Info[0]);
  2858. ha->service = readw(&dp6_ptr->u.ic.Service);
  2859. ha->info2 = readl(&dp6_ptr->u.ic.Info[1]);
  2860. writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
  2861. writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
  2862. writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
  2863. } else if (ha->type == GDT_PCINEW) {
  2864. if (IStatus & 0x80) { /* error flag */
  2865. IStatus &= ~0x80;
  2866. ha->status = inw(PTR2USHORT(&ha->plx->status));
  2867. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2868. } else
  2869. ha->status = S_OK;
  2870. ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
  2871. ha->service = inw(PTR2USHORT(&ha->plx->service));
  2872. ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
  2873. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  2874. outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
  2875. } else if (ha->type == GDT_PCIMPR) {
  2876. dp6m_ptr = ha->brd;
  2877. if (IStatus & 0x80) { /* error flag */
  2878. IStatus &= ~0x80;
  2879. #ifdef INT_COAL
  2880. if (coalesced)
  2881. ha->status = pcs->ext_status & 0xffff;
  2882. else
  2883. #endif
  2884. ha->status = readw(&dp6m_ptr->i960r.status);
  2885. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2886. } else /* no error */
  2887. ha->status = S_OK;
  2888. #ifdef INT_COAL
  2889. /* get information */
  2890. if (coalesced) {
  2891. ha->info = pcs->info0;
  2892. ha->info2 = pcs->info1;
  2893. ha->service = (pcs->ext_status >> 16) & 0xffff;
  2894. } else
  2895. #endif
  2896. {
  2897. ha->info = readl(&dp6m_ptr->i960r.info[0]);
  2898. ha->service = readw(&dp6m_ptr->i960r.service);
  2899. ha->info2 = readl(&dp6m_ptr->i960r.info[1]);
  2900. }
  2901. /* event string */
  2902. if (IStatus == ASYNCINDEX) {
  2903. if (ha->service != SCREENSERVICE &&
  2904. (ha->fw_vers & 0xff) >= 0x1a) {
  2905. ha->dvr.severity = readb
  2906. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
  2907. for (i = 0; i < 256; ++i) {
  2908. ha->dvr.event_string[i] = readb
  2909. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
  2910. if (ha->dvr.event_string[i] == 0)
  2911. break;
  2912. }
  2913. }
  2914. }
  2915. #ifdef INT_COAL
  2916. /* Make sure that non coalesced interrupts get cleared
  2917. before being handled by gdth_async_event/gdth_sync_event */
  2918. if (!coalesced)
  2919. #endif
  2920. {
  2921. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2922. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2923. }
  2924. } else {
  2925. TRACE2(("gdth_interrupt() unknown controller type\n"));
  2926. if (!gdth_polling)
  2927. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  2928. return IRQ_HANDLED;
  2929. }
  2930. TRACE(("gdth_interrupt() index %d stat %d info %d\n",
  2931. IStatus,ha->status,ha->info));
  2932. if (gdth_from_wait) {
  2933. wait_hanum = hanum;
  2934. wait_index = (int)IStatus;
  2935. }
  2936. if (IStatus == ASYNCINDEX) {
  2937. TRACE2(("gdth_interrupt() async. event\n"));
  2938. gdth_async_event(hanum);
  2939. if (!gdth_polling)
  2940. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  2941. gdth_next(hanum);
  2942. return IRQ_HANDLED;
  2943. }
  2944. if (IStatus == SPEZINDEX) {
  2945. TRACE2(("Service unknown or not initialized !\n"));
  2946. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2947. ha->dvr.eu.driver.ionode = hanum;
  2948. gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
  2949. if (!gdth_polling)
  2950. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  2951. return IRQ_HANDLED;
  2952. }
  2953. scp = ha->cmd_tab[IStatus-2].cmnd;
  2954. Service = ha->cmd_tab[IStatus-2].service;
  2955. ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
  2956. if (scp == UNUSED_CMND) {
  2957. TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
  2958. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2959. ha->dvr.eu.driver.ionode = hanum;
  2960. ha->dvr.eu.driver.index = IStatus;
  2961. gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
  2962. if (!gdth_polling)
  2963. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  2964. return IRQ_HANDLED;
  2965. }
  2966. if (scp == INTERNAL_CMND) {
  2967. TRACE(("gdth_interrupt() answer to internal command\n"));
  2968. if (!gdth_polling)
  2969. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  2970. return IRQ_HANDLED;
  2971. }
  2972. TRACE(("gdth_interrupt() sync. status\n"));
  2973. rval = gdth_sync_event(hanum,Service,IStatus,scp);
  2974. if (!gdth_polling)
  2975. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  2976. if (rval == 2) {
  2977. gdth_putq(hanum,scp,scp->SCp.this_residual);
  2978. } else if (rval == 1) {
  2979. gdth_scsi_done(scp);
  2980. }
  2981. #ifdef INT_COAL
  2982. if (coalesced) {
  2983. /* go to the next status in the status buffer */
  2984. ++pcs;
  2985. #ifdef GDTH_STATISTICS
  2986. ++act_int_coal;
  2987. if (act_int_coal > max_int_coal) {
  2988. max_int_coal = act_int_coal;
  2989. printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
  2990. }
  2991. #endif
  2992. /* see if there is another status */
  2993. if (pcs->status == 0)
  2994. /* Stop the coalesce loop */
  2995. next = FALSE;
  2996. }
  2997. } while (next);
  2998. /* coalescing only for new GDT_PCIMPR controllers available */
  2999. if (ha->type == GDT_PCIMPR && coalesced) {
  3000. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  3001. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  3002. }
  3003. #endif
  3004. gdth_next(hanum);
  3005. return IRQ_HANDLED;
  3006. }
  3007. static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp)
  3008. {
  3009. register gdth_ha_str *ha;
  3010. gdth_msg_str *msg;
  3011. gdth_cmd_str *cmdp;
  3012. unchar b, t;
  3013. ha = HADATA(gdth_ctr_tab[hanum]);
  3014. cmdp = ha->pccb;
  3015. TRACE(("gdth_sync_event() serv %d status %d\n",
  3016. service,ha->status));
  3017. if (service == SCREENSERVICE) {
  3018. msg = ha->pmsg;
  3019. TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
  3020. msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
  3021. if (msg->msg_len > MSGLEN+1)
  3022. msg->msg_len = MSGLEN+1;
  3023. if (msg->msg_len)
  3024. if (!(msg->msg_answer && msg->msg_ext)) {
  3025. msg->msg_text[msg->msg_len] = '\0';
  3026. printk("%s",msg->msg_text);
  3027. }
  3028. if (msg->msg_ext && !msg->msg_answer) {
  3029. while (gdth_test_busy(hanum))
  3030. gdth_delay(0);
  3031. cmdp->Service = SCREENSERVICE;
  3032. cmdp->RequestBuffer = SCREEN_CMND;
  3033. gdth_get_cmd_index(hanum);
  3034. gdth_set_sema0(hanum);
  3035. cmdp->OpCode = GDT_READ;
  3036. cmdp->BoardNode = LOCALBOARD;
  3037. cmdp->u.screen.reserved = 0;
  3038. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3039. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3040. ha->cmd_offs_dpmem = 0;
  3041. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3042. + sizeof(ulong64);
  3043. ha->cmd_cnt = 0;
  3044. gdth_copy_command(hanum);
  3045. gdth_release_event(hanum);
  3046. return 0;
  3047. }
  3048. if (msg->msg_answer && msg->msg_alen) {
  3049. /* default answers (getchar() not possible) */
  3050. if (msg->msg_alen == 1) {
  3051. msg->msg_alen = 0;
  3052. msg->msg_len = 1;
  3053. msg->msg_text[0] = 0;
  3054. } else {
  3055. msg->msg_alen -= 2;
  3056. msg->msg_len = 2;
  3057. msg->msg_text[0] = 1;
  3058. msg->msg_text[1] = 0;
  3059. }
  3060. msg->msg_ext = 0;
  3061. msg->msg_answer = 0;
  3062. while (gdth_test_busy(hanum))
  3063. gdth_delay(0);
  3064. cmdp->Service = SCREENSERVICE;
  3065. cmdp->RequestBuffer = SCREEN_CMND;
  3066. gdth_get_cmd_index(hanum);
  3067. gdth_set_sema0(hanum);
  3068. cmdp->OpCode = GDT_WRITE;
  3069. cmdp->BoardNode = LOCALBOARD;
  3070. cmdp->u.screen.reserved = 0;
  3071. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3072. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3073. ha->cmd_offs_dpmem = 0;
  3074. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3075. + sizeof(ulong64);
  3076. ha->cmd_cnt = 0;
  3077. gdth_copy_command(hanum);
  3078. gdth_release_event(hanum);
  3079. return 0;
  3080. }
  3081. printk("\n");
  3082. } else {
  3083. b = scp->device->channel;
  3084. t = scp->device->id;
  3085. if (scp->SCp.sent_command == -1 && b != ha->virt_bus) {
  3086. ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
  3087. }
  3088. /* cache or raw service */
  3089. if (ha->status == S_BSY) {
  3090. TRACE2(("Controller busy -> retry !\n"));
  3091. if (scp->SCp.sent_command == GDT_MOUNT)
  3092. scp->SCp.sent_command = GDT_CLUST_INFO;
  3093. /* retry */
  3094. return 2;
  3095. }
  3096. if (scp->SCp.Status == GDTH_MAP_SG)
  3097. pci_unmap_sg(ha->pdev,scp->request_buffer,
  3098. scp->use_sg,scp->SCp.Message);
  3099. else if (scp->SCp.Status == GDTH_MAP_SINGLE)
  3100. pci_unmap_page(ha->pdev,scp->SCp.dma_handle,
  3101. scp->request_bufflen,scp->SCp.Message);
  3102. if (scp->SCp.buffer) {
  3103. dma_addr_t addr;
  3104. addr = (dma_addr_t)*(ulong32 *)&scp->SCp.buffer;
  3105. if (scp->host_scribble)
  3106. addr += (dma_addr_t)
  3107. ((ulong64)(*(ulong32 *)&scp->host_scribble) << 32);
  3108. pci_unmap_page(ha->pdev,addr,16,PCI_DMA_FROMDEVICE);
  3109. }
  3110. if (ha->status == S_OK) {
  3111. scp->SCp.Status = S_OK;
  3112. scp->SCp.Message = ha->info;
  3113. if (scp->SCp.sent_command != -1) {
  3114. TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
  3115. scp->SCp.sent_command));
  3116. /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
  3117. if (scp->SCp.sent_command == GDT_CLUST_INFO) {
  3118. ha->hdr[t].cluster_type = (unchar)ha->info;
  3119. if (!(ha->hdr[t].cluster_type &
  3120. CLUSTER_MOUNTED)) {
  3121. /* NOT MOUNTED -> MOUNT */
  3122. scp->SCp.sent_command = GDT_MOUNT;
  3123. if (ha->hdr[t].cluster_type &
  3124. CLUSTER_RESERVED) {
  3125. /* cluster drive RESERVED (on the other node) */
  3126. scp->SCp.phase = -2; /* reservation conflict */
  3127. }
  3128. } else {
  3129. scp->SCp.sent_command = -1;
  3130. }
  3131. } else {
  3132. if (scp->SCp.sent_command == GDT_MOUNT) {
  3133. ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
  3134. ha->hdr[t].media_changed = TRUE;
  3135. } else if (scp->SCp.sent_command == GDT_UNMOUNT) {
  3136. ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
  3137. ha->hdr[t].media_changed = TRUE;
  3138. }
  3139. scp->SCp.sent_command = -1;
  3140. }
  3141. /* retry */
  3142. scp->SCp.this_residual = HIGH_PRI;
  3143. return 2;
  3144. } else {
  3145. /* RESERVE/RELEASE ? */
  3146. if (scp->cmnd[0] == RESERVE) {
  3147. ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
  3148. } else if (scp->cmnd[0] == RELEASE) {
  3149. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3150. }
  3151. scp->result = DID_OK << 16;
  3152. scp->sense_buffer[0] = 0;
  3153. }
  3154. } else {
  3155. scp->SCp.Status = ha->status;
  3156. scp->SCp.Message = ha->info;
  3157. if (scp->SCp.sent_command != -1) {
  3158. TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
  3159. scp->SCp.sent_command, ha->status));
  3160. if (scp->SCp.sent_command == GDT_SCAN_START ||
  3161. scp->SCp.sent_command == GDT_SCAN_END) {
  3162. scp->SCp.sent_command = -1;
  3163. /* retry */
  3164. scp->SCp.this_residual = HIGH_PRI;
  3165. return 2;
  3166. }
  3167. memset((char*)scp->sense_buffer,0,16);
  3168. scp->sense_buffer[0] = 0x70;
  3169. scp->sense_buffer[2] = NOT_READY;
  3170. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3171. } else if (service == CACHESERVICE) {
  3172. if (ha->status == S_CACHE_UNKNOWN &&
  3173. (ha->hdr[t].cluster_type &
  3174. CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
  3175. /* bus reset -> force GDT_CLUST_INFO */
  3176. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3177. }
  3178. memset((char*)scp->sense_buffer,0,16);
  3179. if (ha->status == (ushort)S_CACHE_RESERV) {
  3180. scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
  3181. } else {
  3182. scp->sense_buffer[0] = 0x70;
  3183. scp->sense_buffer[2] = NOT_READY;
  3184. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3185. }
  3186. if (!IS_GDTH_INTERNAL_CMD(scp)) {
  3187. ha->dvr.size = sizeof(ha->dvr.eu.sync);
  3188. ha->dvr.eu.sync.ionode = hanum;
  3189. ha->dvr.eu.sync.service = service;
  3190. ha->dvr.eu.sync.status = ha->status;
  3191. ha->dvr.eu.sync.info = ha->info;
  3192. ha->dvr.eu.sync.hostdrive = t;
  3193. if (ha->status >= 0x8000)
  3194. gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
  3195. else
  3196. gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
  3197. }
  3198. } else {
  3199. /* sense buffer filled from controller firmware (DMA) */
  3200. if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
  3201. scp->result = DID_BAD_TARGET << 16;
  3202. } else {
  3203. scp->result = (DID_OK << 16) | ha->info;
  3204. }
  3205. }
  3206. }
  3207. if (!scp->SCp.have_data_in)
  3208. scp->SCp.have_data_in++;
  3209. else
  3210. return 1;
  3211. }
  3212. return 0;
  3213. }
  3214. static char *async_cache_tab[] = {
  3215. /* 0*/ "\011\000\002\002\002\004\002\006\004"
  3216. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3217. /* 1*/ "\011\000\002\002\002\004\002\006\004"
  3218. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3219. /* 2*/ "\005\000\002\006\004"
  3220. "GDT HA %u, Host Drive %lu not ready",
  3221. /* 3*/ "\005\000\002\006\004"
  3222. "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3223. /* 4*/ "\005\000\002\006\004"
  3224. "GDT HA %u, mirror update on Host Drive %lu failed",
  3225. /* 5*/ "\005\000\002\006\004"
  3226. "GDT HA %u, Mirror Drive %lu failed",
  3227. /* 6*/ "\005\000\002\006\004"
  3228. "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3229. /* 7*/ "\005\000\002\006\004"
  3230. "GDT HA %u, Host Drive %lu write protected",
  3231. /* 8*/ "\005\000\002\006\004"
  3232. "GDT HA %u, media changed in Host Drive %lu",
  3233. /* 9*/ "\005\000\002\006\004"
  3234. "GDT HA %u, Host Drive %lu is offline",
  3235. /*10*/ "\005\000\002\006\004"
  3236. "GDT HA %u, media change of Mirror Drive %lu",
  3237. /*11*/ "\005\000\002\006\004"
  3238. "GDT HA %u, Mirror Drive %lu is write protected",
  3239. /*12*/ "\005\000\002\006\004"
  3240. "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
  3241. /*13*/ "\007\000\002\006\002\010\002"
  3242. "GDT HA %u, Array Drive %u: Cache Drive %u failed",
  3243. /*14*/ "\005\000\002\006\002"
  3244. "GDT HA %u, Array Drive %u: FAIL state entered",
  3245. /*15*/ "\005\000\002\006\002"
  3246. "GDT HA %u, Array Drive %u: error",
  3247. /*16*/ "\007\000\002\006\002\010\002"
  3248. "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
  3249. /*17*/ "\005\000\002\006\002"
  3250. "GDT HA %u, Array Drive %u: parity build failed",
  3251. /*18*/ "\005\000\002\006\002"
  3252. "GDT HA %u, Array Drive %u: drive rebuild failed",
  3253. /*19*/ "\005\000\002\010\002"
  3254. "GDT HA %u, Test of Hot Fix %u failed",
  3255. /*20*/ "\005\000\002\006\002"
  3256. "GDT HA %u, Array Drive %u: drive build finished successfully",
  3257. /*21*/ "\005\000\002\006\002"
  3258. "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
  3259. /*22*/ "\007\000\002\006\002\010\002"
  3260. "GDT HA %u, Array Drive %u: Hot Fix %u activated",
  3261. /*23*/ "\005\000\002\006\002"
  3262. "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
  3263. /*24*/ "\005\000\002\010\002"
  3264. "GDT HA %u, mirror update on Cache Drive %u completed",
  3265. /*25*/ "\005\000\002\010\002"
  3266. "GDT HA %u, mirror update on Cache Drive %lu failed",
  3267. /*26*/ "\005\000\002\006\002"
  3268. "GDT HA %u, Array Drive %u: drive rebuild started",
  3269. /*27*/ "\005\000\002\012\001"
  3270. "GDT HA %u, Fault bus %u: SHELF OK detected",
  3271. /*28*/ "\005\000\002\012\001"
  3272. "GDT HA %u, Fault bus %u: SHELF not OK detected",
  3273. /*29*/ "\007\000\002\012\001\013\001"
  3274. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
  3275. /*30*/ "\007\000\002\012\001\013\001"
  3276. "GDT HA %u, Fault bus %u, ID %u: new disk detected",
  3277. /*31*/ "\007\000\002\012\001\013\001"
  3278. "GDT HA %u, Fault bus %u, ID %u: old disk detected",
  3279. /*32*/ "\007\000\002\012\001\013\001"
  3280. "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
  3281. /*33*/ "\007\000\002\012\001\013\001"
  3282. "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
  3283. /*34*/ "\011\000\002\012\001\013\001\006\004"
  3284. "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
  3285. /*35*/ "\007\000\002\012\001\013\001"
  3286. "GDT HA %u, Fault bus %u, ID %u: disk write protected",
  3287. /*36*/ "\007\000\002\012\001\013\001"
  3288. "GDT HA %u, Fault bus %u, ID %u: disk not available",
  3289. /*37*/ "\007\000\002\012\001\006\004"
  3290. "GDT HA %u, Fault bus %u: swap detected (%lu)",
  3291. /*38*/ "\007\000\002\012\001\013\001"
  3292. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
  3293. /*39*/ "\007\000\002\012\001\013\001"
  3294. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
  3295. /*40*/ "\007\000\002\012\001\013\001"
  3296. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
  3297. /*41*/ "\007\000\002\012\001\013\001"
  3298. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
  3299. /*42*/ "\005\000\002\006\002"
  3300. "GDT HA %u, Array Drive %u: drive build started",
  3301. /*43*/ "\003\000\002"
  3302. "GDT HA %u, DRAM parity error detected",
  3303. /*44*/ "\005\000\002\006\002"
  3304. "GDT HA %u, Mirror Drive %u: update started",
  3305. /*45*/ "\007\000\002\006\002\010\002"
  3306. "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
  3307. /*46*/ "\005\000\002\006\002"
  3308. "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
  3309. /*47*/ "\005\000\002\006\002"
  3310. "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
  3311. /*48*/ "\005\000\002\006\002"
  3312. "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
  3313. /*49*/ "\005\000\002\006\002"
  3314. "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
  3315. /*50*/ "\007\000\002\012\001\013\001"
  3316. "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
  3317. /*51*/ "\005\000\002\006\002"
  3318. "GDT HA %u, Array Drive %u: expand started",
  3319. /*52*/ "\005\000\002\006\002"
  3320. "GDT HA %u, Array Drive %u: expand finished successfully",
  3321. /*53*/ "\005\000\002\006\002"
  3322. "GDT HA %u, Array Drive %u: expand failed",
  3323. /*54*/ "\003\000\002"
  3324. "GDT HA %u, CPU temperature critical",
  3325. /*55*/ "\003\000\002"
  3326. "GDT HA %u, CPU temperature OK",
  3327. /*56*/ "\005\000\002\006\004"
  3328. "GDT HA %u, Host drive %lu created",
  3329. /*57*/ "\005\000\002\006\002"
  3330. "GDT HA %u, Array Drive %u: expand restarted",
  3331. /*58*/ "\005\000\002\006\002"
  3332. "GDT HA %u, Array Drive %u: expand stopped",
  3333. /*59*/ "\005\000\002\010\002"
  3334. "GDT HA %u, Mirror Drive %u: drive build quited",
  3335. /*60*/ "\005\000\002\006\002"
  3336. "GDT HA %u, Array Drive %u: parity build quited",
  3337. /*61*/ "\005\000\002\006\002"
  3338. "GDT HA %u, Array Drive %u: drive rebuild quited",
  3339. /*62*/ "\005\000\002\006\002"
  3340. "GDT HA %u, Array Drive %u: parity verify started",
  3341. /*63*/ "\005\000\002\006\002"
  3342. "GDT HA %u, Array Drive %u: parity verify done",
  3343. /*64*/ "\005\000\002\006\002"
  3344. "GDT HA %u, Array Drive %u: parity verify failed",
  3345. /*65*/ "\005\000\002\006\002"
  3346. "GDT HA %u, Array Drive %u: parity error detected",
  3347. /*66*/ "\005\000\002\006\002"
  3348. "GDT HA %u, Array Drive %u: parity verify quited",
  3349. /*67*/ "\005\000\002\006\002"
  3350. "GDT HA %u, Host Drive %u reserved",
  3351. /*68*/ "\005\000\002\006\002"
  3352. "GDT HA %u, Host Drive %u mounted and released",
  3353. /*69*/ "\005\000\002\006\002"
  3354. "GDT HA %u, Host Drive %u released",
  3355. /*70*/ "\003\000\002"
  3356. "GDT HA %u, DRAM error detected and corrected with ECC",
  3357. /*71*/ "\003\000\002"
  3358. "GDT HA %u, Uncorrectable DRAM error detected with ECC",
  3359. /*72*/ "\011\000\002\012\001\013\001\014\001"
  3360. "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
  3361. /*73*/ "\005\000\002\006\002"
  3362. "GDT HA %u, Host drive %u resetted locally",
  3363. /*74*/ "\005\000\002\006\002"
  3364. "GDT HA %u, Host drive %u resetted remotely",
  3365. /*75*/ "\003\000\002"
  3366. "GDT HA %u, async. status 75 unknown",
  3367. };
  3368. static int gdth_async_event(int hanum)
  3369. {
  3370. gdth_ha_str *ha;
  3371. gdth_cmd_str *cmdp;
  3372. int cmd_index;
  3373. ha = HADATA(gdth_ctr_tab[hanum]);
  3374. cmdp= ha->pccb;
  3375. TRACE2(("gdth_async_event() ha %d serv %d\n",
  3376. hanum,ha->service));
  3377. if (ha->service == SCREENSERVICE) {
  3378. if (ha->status == MSG_REQUEST) {
  3379. while (gdth_test_busy(hanum))
  3380. gdth_delay(0);
  3381. cmdp->Service = SCREENSERVICE;
  3382. cmdp->RequestBuffer = SCREEN_CMND;
  3383. cmd_index = gdth_get_cmd_index(hanum);
  3384. gdth_set_sema0(hanum);
  3385. cmdp->OpCode = GDT_READ;
  3386. cmdp->BoardNode = LOCALBOARD;
  3387. cmdp->u.screen.reserved = 0;
  3388. cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
  3389. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3390. ha->cmd_offs_dpmem = 0;
  3391. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3392. + sizeof(ulong64);
  3393. ha->cmd_cnt = 0;
  3394. gdth_copy_command(hanum);
  3395. if (ha->type == GDT_EISA)
  3396. printk("[EISA slot %d] ",(ushort)ha->brd_phys);
  3397. else if (ha->type == GDT_ISA)
  3398. printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
  3399. else
  3400. printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
  3401. (ushort)((ha->brd_phys>>3)&0x1f));
  3402. gdth_release_event(hanum);
  3403. }
  3404. } else {
  3405. if (ha->type == GDT_PCIMPR &&
  3406. (ha->fw_vers & 0xff) >= 0x1a) {
  3407. ha->dvr.size = 0;
  3408. ha->dvr.eu.async.ionode = hanum;
  3409. ha->dvr.eu.async.status = ha->status;
  3410. /* severity and event_string already set! */
  3411. } else {
  3412. ha->dvr.size = sizeof(ha->dvr.eu.async);
  3413. ha->dvr.eu.async.ionode = hanum;
  3414. ha->dvr.eu.async.service = ha->service;
  3415. ha->dvr.eu.async.status = ha->status;
  3416. ha->dvr.eu.async.info = ha->info;
  3417. *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
  3418. }
  3419. gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
  3420. gdth_log_event( &ha->dvr, NULL );
  3421. /* new host drive from expand? */
  3422. if (ha->service == CACHESERVICE && ha->status == 56) {
  3423. TRACE2(("gdth_async_event(): new host drive %d created\n",
  3424. (ushort)ha->info));
  3425. /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
  3426. }
  3427. }
  3428. return 1;
  3429. }
  3430. static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
  3431. {
  3432. gdth_stackframe stack;
  3433. char *f = NULL;
  3434. int i,j;
  3435. TRACE2(("gdth_log_event()\n"));
  3436. if (dvr->size == 0) {
  3437. if (buffer == NULL) {
  3438. printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
  3439. } else {
  3440. sprintf(buffer,"Adapter %d: %s\n",
  3441. dvr->eu.async.ionode,dvr->event_string);
  3442. }
  3443. } else if (dvr->eu.async.service == CACHESERVICE &&
  3444. INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
  3445. TRACE2(("GDT: Async. event cache service, event no.: %d\n",
  3446. dvr->eu.async.status));
  3447. f = async_cache_tab[dvr->eu.async.status];
  3448. /* i: parameter to push, j: stack element to fill */
  3449. for (j=0,i=1; i < f[0]; i+=2) {
  3450. switch (f[i+1]) {
  3451. case 4:
  3452. stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
  3453. break;
  3454. case 2:
  3455. stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
  3456. break;
  3457. case 1:
  3458. stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
  3459. break;
  3460. default:
  3461. break;
  3462. }
  3463. }
  3464. if (buffer == NULL) {
  3465. printk(&f[(int)f[0]],stack);
  3466. printk("\n");
  3467. } else {
  3468. sprintf(buffer,&f[(int)f[0]],stack);
  3469. }
  3470. } else {
  3471. if (buffer == NULL) {
  3472. printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
  3473. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3474. } else {
  3475. sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
  3476. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3477. }
  3478. }
  3479. }
  3480. #ifdef GDTH_STATISTICS
  3481. static void gdth_timeout(ulong data)
  3482. {
  3483. ulong32 i;
  3484. Scsi_Cmnd *nscp;
  3485. gdth_ha_str *ha;
  3486. ulong flags;
  3487. int hanum = 0;
  3488. ha = HADATA(gdth_ctr_tab[hanum]);
  3489. spin_lock_irqsave(&ha->smp_lock, flags);
  3490. for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
  3491. if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
  3492. ++act_stats;
  3493. for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  3494. ++act_rq;
  3495. TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
  3496. act_ints, act_ios, act_stats, act_rq));
  3497. act_ints = act_ios = 0;
  3498. gdth_timer.expires = jiffies + 30 * HZ;
  3499. add_timer(&gdth_timer);
  3500. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3501. }
  3502. #endif
  3503. static void __init internal_setup(char *str,int *ints)
  3504. {
  3505. int i, argc;
  3506. char *cur_str, *argv;
  3507. TRACE2(("internal_setup() str %s ints[0] %d\n",
  3508. str ? str:"NULL", ints ? ints[0]:0));
  3509. /* read irq[] from ints[] */
  3510. if (ints) {
  3511. argc = ints[0];
  3512. if (argc > 0) {
  3513. if (argc > MAXHA)
  3514. argc = MAXHA;
  3515. for (i = 0; i < argc; ++i)
  3516. irq[i] = ints[i+1];
  3517. }
  3518. }
  3519. /* analyse string */
  3520. argv = str;
  3521. while (argv && (cur_str = strchr(argv, ':'))) {
  3522. int val = 0, c = *++cur_str;
  3523. if (c == 'n' || c == 'N')
  3524. val = 0;
  3525. else if (c == 'y' || c == 'Y')
  3526. val = 1;
  3527. else
  3528. val = (int)simple_strtoul(cur_str, NULL, 0);
  3529. if (!strncmp(argv, "disable:", 8))
  3530. disable = val;
  3531. else if (!strncmp(argv, "reserve_mode:", 13))
  3532. reserve_mode = val;
  3533. else if (!strncmp(argv, "reverse_scan:", 13))
  3534. reverse_scan = val;
  3535. else if (!strncmp(argv, "hdr_channel:", 12))
  3536. hdr_channel = val;
  3537. else if (!strncmp(argv, "max_ids:", 8))
  3538. max_ids = val;
  3539. else if (!strncmp(argv, "rescan:", 7))
  3540. rescan = val;
  3541. else if (!strncmp(argv, "shared_access:", 14))
  3542. shared_access = val;
  3543. else if (!strncmp(argv, "probe_eisa_isa:", 15))
  3544. probe_eisa_isa = val;
  3545. else if (!strncmp(argv, "reserve_list:", 13)) {
  3546. reserve_list[0] = val;
  3547. for (i = 1; i < MAX_RES_ARGS; i++) {
  3548. cur_str = strchr(cur_str, ',');
  3549. if (!cur_str)
  3550. break;
  3551. if (!isdigit((int)*++cur_str)) {
  3552. --cur_str;
  3553. break;
  3554. }
  3555. reserve_list[i] =
  3556. (int)simple_strtoul(cur_str, NULL, 0);
  3557. }
  3558. if (!cur_str)
  3559. break;
  3560. argv = ++cur_str;
  3561. continue;
  3562. }
  3563. if ((argv = strchr(argv, ',')))
  3564. ++argv;
  3565. }
  3566. }
  3567. int __init option_setup(char *str)
  3568. {
  3569. int ints[MAXHA];
  3570. char *cur = str;
  3571. int i = 1;
  3572. TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
  3573. while (cur && isdigit(*cur) && i <= MAXHA) {
  3574. ints[i++] = simple_strtoul(cur, NULL, 0);
  3575. if ((cur = strchr(cur, ',')) != NULL) cur++;
  3576. }
  3577. ints[0] = i - 1;
  3578. internal_setup(cur, ints);
  3579. return 1;
  3580. }
  3581. static int __init gdth_detect(struct scsi_host_template *shtp)
  3582. {
  3583. #ifdef DEBUG_GDTH
  3584. printk("GDT: This driver contains debugging information !! Trace level = %d\n",
  3585. DebugState);
  3586. printk(" Destination of debugging information: ");
  3587. #ifdef __SERIAL__
  3588. #ifdef __COM2__
  3589. printk("Serial port COM2\n");
  3590. #else
  3591. printk("Serial port COM1\n");
  3592. #endif
  3593. #else
  3594. printk("Console\n");
  3595. #endif
  3596. gdth_delay(3000);
  3597. #endif
  3598. TRACE(("gdth_detect()\n"));
  3599. if (disable) {
  3600. printk("GDT-HA: Controller driver disabled from command line !\n");
  3601. return 0;
  3602. }
  3603. printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",GDTH_VERSION_STR);
  3604. /* initializations */
  3605. gdth_polling = TRUE;
  3606. gdth_clear_events();
  3607. /* As default we do not probe for EISA or ISA controllers */
  3608. if (probe_eisa_isa) {
  3609. /* scanning for controllers, at first: ISA controller */
  3610. #ifdef CONFIG_ISA
  3611. ulong32 isa_bios;
  3612. for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
  3613. isa_bios += 0x8000UL) {
  3614. if (gdth_ctr_count >= MAXHA)
  3615. break;
  3616. gdth_isa_probe_one(shtp, isa_bios);
  3617. }
  3618. #endif
  3619. #ifdef CONFIG_EISA
  3620. {
  3621. ushort eisa_slot;
  3622. for (eisa_slot = 0x1000; eisa_slot <= 0x8000; eisa_slot += 0x1000) {
  3623. if (gdth_ctr_count >= MAXHA)
  3624. break;
  3625. gdth_eisa_probe_one(shtp, eisa_slot);
  3626. }
  3627. }
  3628. #endif
  3629. }
  3630. #ifdef CONFIG_PCI
  3631. /* scanning for PCI controllers */
  3632. {
  3633. gdth_pci_str pcistr[MAXHA];
  3634. int cnt,ctr;
  3635. cnt = gdth_search_pci(pcistr);
  3636. printk("GDT-HA: Found %d PCI Storage RAID Controllers\n",cnt);
  3637. gdth_sort_pci(pcistr,cnt);
  3638. for (ctr = 0; ctr < cnt; ++ctr) {
  3639. if (gdth_ctr_count >= MAXHA)
  3640. break;
  3641. gdth_pci_probe_one(shtp, pcistr, ctr);
  3642. }
  3643. }
  3644. #endif /* CONFIG_PCI */
  3645. TRACE2(("gdth_detect() %d controller detected\n",gdth_ctr_count));
  3646. if (gdth_ctr_count > 0) {
  3647. #ifdef GDTH_STATISTICS
  3648. TRACE2(("gdth_detect(): Initializing timer !\n"));
  3649. init_timer(&gdth_timer);
  3650. gdth_timer.expires = jiffies + HZ;
  3651. gdth_timer.data = 0L;
  3652. gdth_timer.function = gdth_timeout;
  3653. add_timer(&gdth_timer);
  3654. #endif
  3655. major = register_chrdev(0,"gdth",&gdth_fops);
  3656. notifier_disabled = 0;
  3657. register_reboot_notifier(&gdth_notifier);
  3658. }
  3659. gdth_polling = FALSE;
  3660. return gdth_ctr_count;
  3661. }
  3662. static int gdth_release(struct Scsi_Host *shp)
  3663. {
  3664. int hanum;
  3665. gdth_ha_str *ha;
  3666. TRACE2(("gdth_release()\n"));
  3667. hanum = NUMDATA(shp)->hanum;
  3668. ha = HADATA(gdth_ctr_tab[hanum]);
  3669. if (ha->sdev) {
  3670. scsi_free_host_dev(ha->sdev);
  3671. ha->sdev = NULL;
  3672. }
  3673. gdth_flush(hanum);
  3674. if (shp->irq) {
  3675. free_irq(shp->irq,ha);
  3676. }
  3677. #ifdef CONFIG_ISA
  3678. if (shp->dma_channel != 0xff) {
  3679. free_dma(shp->dma_channel);
  3680. }
  3681. #endif
  3682. #ifdef INT_COAL
  3683. if (ha->coal_stat)
  3684. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  3685. MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
  3686. #endif
  3687. if (ha->pscratch)
  3688. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  3689. ha->pscratch, ha->scratch_phys);
  3690. if (ha->pmsg)
  3691. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  3692. ha->pmsg, ha->msg_phys);
  3693. if (ha->ccb_phys)
  3694. pci_unmap_single(ha->pdev,ha->ccb_phys,
  3695. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  3696. gdth_ctr_released++;
  3697. TRACE2(("gdth_release(): HA %d of %d\n",
  3698. gdth_ctr_released, gdth_ctr_count));
  3699. if (gdth_ctr_released == gdth_ctr_count) {
  3700. #ifdef GDTH_STATISTICS
  3701. del_timer(&gdth_timer);
  3702. #endif
  3703. unregister_chrdev(major,"gdth");
  3704. unregister_reboot_notifier(&gdth_notifier);
  3705. }
  3706. scsi_unregister(shp);
  3707. return 0;
  3708. }
  3709. static const char *gdth_ctr_name(int hanum)
  3710. {
  3711. gdth_ha_str *ha;
  3712. TRACE2(("gdth_ctr_name()\n"));
  3713. ha = HADATA(gdth_ctr_tab[hanum]);
  3714. if (ha->type == GDT_EISA) {
  3715. switch (ha->stype) {
  3716. case GDT3_ID:
  3717. return("GDT3000/3020");
  3718. case GDT3A_ID:
  3719. return("GDT3000A/3020A/3050A");
  3720. case GDT3B_ID:
  3721. return("GDT3000B/3010A");
  3722. }
  3723. } else if (ha->type == GDT_ISA) {
  3724. return("GDT2000/2020");
  3725. } else if (ha->type == GDT_PCI) {
  3726. switch (ha->pdev->device) {
  3727. case PCI_DEVICE_ID_VORTEX_GDT60x0:
  3728. return("GDT6000/6020/6050");
  3729. case PCI_DEVICE_ID_VORTEX_GDT6000B:
  3730. return("GDT6000B/6010");
  3731. }
  3732. }
  3733. /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
  3734. return("");
  3735. }
  3736. static const char *gdth_info(struct Scsi_Host *shp)
  3737. {
  3738. int hanum;
  3739. gdth_ha_str *ha;
  3740. TRACE2(("gdth_info()\n"));
  3741. hanum = NUMDATA(shp)->hanum;
  3742. ha = HADATA(gdth_ctr_tab[hanum]);
  3743. return ((const char *)ha->binfo.type_string);
  3744. }
  3745. static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
  3746. {
  3747. int i, hanum;
  3748. gdth_ha_str *ha;
  3749. ulong flags;
  3750. Scsi_Cmnd *cmnd;
  3751. unchar b;
  3752. TRACE2(("gdth_eh_bus_reset()\n"));
  3753. hanum = NUMDATA(scp->device->host)->hanum;
  3754. b = scp->device->channel;
  3755. ha = HADATA(gdth_ctr_tab[hanum]);
  3756. /* clear command tab */
  3757. spin_lock_irqsave(&ha->smp_lock, flags);
  3758. for (i = 0; i < GDTH_MAXCMDS; ++i) {
  3759. cmnd = ha->cmd_tab[i].cmnd;
  3760. if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
  3761. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  3762. }
  3763. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3764. if (b == ha->virt_bus) {
  3765. /* host drives */
  3766. for (i = 0; i < MAX_HDRIVES; ++i) {
  3767. if (ha->hdr[i].present) {
  3768. spin_lock_irqsave(&ha->smp_lock, flags);
  3769. gdth_polling = TRUE;
  3770. while (gdth_test_busy(hanum))
  3771. gdth_delay(0);
  3772. if (gdth_internal_cmd(hanum, CACHESERVICE,
  3773. GDT_CLUST_RESET, i, 0, 0))
  3774. ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
  3775. gdth_polling = FALSE;
  3776. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3777. }
  3778. }
  3779. } else {
  3780. /* raw devices */
  3781. spin_lock_irqsave(&ha->smp_lock, flags);
  3782. for (i = 0; i < MAXID; ++i)
  3783. ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
  3784. gdth_polling = TRUE;
  3785. while (gdth_test_busy(hanum))
  3786. gdth_delay(0);
  3787. gdth_internal_cmd(hanum, SCSIRAWSERVICE, GDT_RESET_BUS,
  3788. BUS_L2P(ha,b), 0, 0);
  3789. gdth_polling = FALSE;
  3790. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3791. }
  3792. return SUCCESS;
  3793. }
  3794. static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
  3795. {
  3796. unchar b, t;
  3797. int hanum;
  3798. gdth_ha_str *ha;
  3799. struct scsi_device *sd;
  3800. unsigned capacity;
  3801. sd = sdev;
  3802. capacity = cap;
  3803. hanum = NUMDATA(sd->host)->hanum;
  3804. b = sd->channel;
  3805. t = sd->id;
  3806. TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", hanum, b, t));
  3807. ha = HADATA(gdth_ctr_tab[hanum]);
  3808. if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
  3809. /* raw device or host drive without mapping information */
  3810. TRACE2(("Evaluate mapping\n"));
  3811. gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
  3812. } else {
  3813. ip[0] = ha->hdr[t].heads;
  3814. ip[1] = ha->hdr[t].secs;
  3815. ip[2] = capacity / ip[0] / ip[1];
  3816. }
  3817. TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
  3818. ip[0],ip[1],ip[2]));
  3819. return 0;
  3820. }
  3821. static int gdth_queuecommand(struct scsi_cmnd *scp,
  3822. void (*done)(struct scsi_cmnd *))
  3823. {
  3824. int hanum;
  3825. int priority;
  3826. TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
  3827. scp->scsi_done = done;
  3828. scp->SCp.have_data_in = 1;
  3829. scp->SCp.phase = -1;
  3830. scp->SCp.sent_command = -1;
  3831. scp->SCp.Status = GDTH_MAP_NONE;
  3832. scp->SCp.buffer = (struct scatterlist *)NULL;
  3833. hanum = NUMDATA(scp->device->host)->hanum;
  3834. #ifdef GDTH_STATISTICS
  3835. ++act_ios;
  3836. #endif
  3837. priority = DEFAULT_PRI;
  3838. if (IS_GDTH_INTERNAL_CMD(scp))
  3839. priority = scp->SCp.this_residual;
  3840. else
  3841. gdth_update_timeout(hanum, scp, scp->timeout_per_command * 6);
  3842. gdth_putq( hanum, scp, priority );
  3843. gdth_next( hanum );
  3844. return 0;
  3845. }
  3846. static int gdth_open(struct inode *inode, struct file *filep)
  3847. {
  3848. gdth_ha_str *ha;
  3849. int i;
  3850. for (i = 0; i < gdth_ctr_count; i++) {
  3851. ha = HADATA(gdth_ctr_tab[i]);
  3852. if (!ha->sdev)
  3853. ha->sdev = scsi_get_host_dev(gdth_ctr_tab[i]);
  3854. }
  3855. TRACE(("gdth_open()\n"));
  3856. return 0;
  3857. }
  3858. static int gdth_close(struct inode *inode, struct file *filep)
  3859. {
  3860. TRACE(("gdth_close()\n"));
  3861. return 0;
  3862. }
  3863. static int ioc_event(void __user *arg)
  3864. {
  3865. gdth_ioctl_event evt;
  3866. gdth_ha_str *ha;
  3867. ulong flags;
  3868. if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)) ||
  3869. evt.ionode >= gdth_ctr_count)
  3870. return -EFAULT;
  3871. ha = HADATA(gdth_ctr_tab[evt.ionode]);
  3872. if (evt.erase == 0xff) {
  3873. if (evt.event.event_source == ES_TEST)
  3874. evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
  3875. else if (evt.event.event_source == ES_DRIVER)
  3876. evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
  3877. else if (evt.event.event_source == ES_SYNC)
  3878. evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
  3879. else
  3880. evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
  3881. spin_lock_irqsave(&ha->smp_lock, flags);
  3882. gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
  3883. &evt.event.event_data);
  3884. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3885. } else if (evt.erase == 0xfe) {
  3886. gdth_clear_events();
  3887. } else if (evt.erase == 0) {
  3888. evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
  3889. } else {
  3890. gdth_readapp_event(ha, evt.erase, &evt.event);
  3891. }
  3892. if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
  3893. return -EFAULT;
  3894. return 0;
  3895. }
  3896. static int ioc_lockdrv(void __user *arg)
  3897. {
  3898. gdth_ioctl_lockdrv ldrv;
  3899. unchar i, j;
  3900. ulong flags;
  3901. gdth_ha_str *ha;
  3902. if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)) ||
  3903. ldrv.ionode >= gdth_ctr_count)
  3904. return -EFAULT;
  3905. ha = HADATA(gdth_ctr_tab[ldrv.ionode]);
  3906. for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
  3907. j = ldrv.drives[i];
  3908. if (j >= MAX_HDRIVES || !ha->hdr[j].present)
  3909. continue;
  3910. if (ldrv.lock) {
  3911. spin_lock_irqsave(&ha->smp_lock, flags);
  3912. ha->hdr[j].lock = 1;
  3913. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3914. gdth_wait_completion(ldrv.ionode, ha->bus_cnt, j);
  3915. gdth_stop_timeout(ldrv.ionode, ha->bus_cnt, j);
  3916. } else {
  3917. spin_lock_irqsave(&ha->smp_lock, flags);
  3918. ha->hdr[j].lock = 0;
  3919. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3920. gdth_start_timeout(ldrv.ionode, ha->bus_cnt, j);
  3921. gdth_next(ldrv.ionode);
  3922. }
  3923. }
  3924. return 0;
  3925. }
  3926. static int ioc_resetdrv(void __user *arg, char *cmnd)
  3927. {
  3928. gdth_ioctl_reset res;
  3929. gdth_cmd_str cmd;
  3930. int hanum;
  3931. gdth_ha_str *ha;
  3932. int rval;
  3933. if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
  3934. res.ionode >= gdth_ctr_count || res.number >= MAX_HDRIVES)
  3935. return -EFAULT;
  3936. hanum = res.ionode;
  3937. ha = HADATA(gdth_ctr_tab[hanum]);
  3938. if (!ha->hdr[res.number].present)
  3939. return 0;
  3940. memset(&cmd, 0, sizeof(gdth_cmd_str));
  3941. cmd.Service = CACHESERVICE;
  3942. cmd.OpCode = GDT_CLUST_RESET;
  3943. if (ha->cache_feat & GDT_64BIT)
  3944. cmd.u.cache64.DeviceNo = res.number;
  3945. else
  3946. cmd.u.cache.DeviceNo = res.number;
  3947. rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
  3948. if (rval < 0)
  3949. return rval;
  3950. res.status = rval;
  3951. if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
  3952. return -EFAULT;
  3953. return 0;
  3954. }
  3955. static int ioc_general(void __user *arg, char *cmnd)
  3956. {
  3957. gdth_ioctl_general gen;
  3958. char *buf = NULL;
  3959. ulong64 paddr;
  3960. int hanum;
  3961. gdth_ha_str *ha;
  3962. int rval;
  3963. if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)) ||
  3964. gen.ionode >= gdth_ctr_count)
  3965. return -EFAULT;
  3966. hanum = gen.ionode;
  3967. ha = HADATA(gdth_ctr_tab[hanum]);
  3968. if (gen.data_len + gen.sense_len != 0) {
  3969. if (!(buf = gdth_ioctl_alloc(hanum, gen.data_len + gen.sense_len,
  3970. FALSE, &paddr)))
  3971. return -EFAULT;
  3972. if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
  3973. gen.data_len + gen.sense_len)) {
  3974. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  3975. return -EFAULT;
  3976. }
  3977. if (gen.command.OpCode == GDT_IOCTL) {
  3978. gen.command.u.ioctl.p_param = paddr;
  3979. } else if (gen.command.Service == CACHESERVICE) {
  3980. if (ha->cache_feat & GDT_64BIT) {
  3981. /* copy elements from 32-bit IOCTL structure */
  3982. gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
  3983. gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
  3984. gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
  3985. /* addresses */
  3986. if (ha->cache_feat & SCATTER_GATHER) {
  3987. gen.command.u.cache64.DestAddr = (ulong64)-1;
  3988. gen.command.u.cache64.sg_canz = 1;
  3989. gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
  3990. gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
  3991. gen.command.u.cache64.sg_lst[1].sg_len = 0;
  3992. } else {
  3993. gen.command.u.cache64.DestAddr = paddr;
  3994. gen.command.u.cache64.sg_canz = 0;
  3995. }
  3996. } else {
  3997. if (ha->cache_feat & SCATTER_GATHER) {
  3998. gen.command.u.cache.DestAddr = 0xffffffff;
  3999. gen.command.u.cache.sg_canz = 1;
  4000. gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
  4001. gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
  4002. gen.command.u.cache.sg_lst[1].sg_len = 0;
  4003. } else {
  4004. gen.command.u.cache.DestAddr = paddr;
  4005. gen.command.u.cache.sg_canz = 0;
  4006. }
  4007. }
  4008. } else if (gen.command.Service == SCSIRAWSERVICE) {
  4009. if (ha->raw_feat & GDT_64BIT) {
  4010. /* copy elements from 32-bit IOCTL structure */
  4011. char cmd[16];
  4012. gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
  4013. gen.command.u.raw64.bus = gen.command.u.raw.bus;
  4014. gen.command.u.raw64.lun = gen.command.u.raw.lun;
  4015. gen.command.u.raw64.target = gen.command.u.raw.target;
  4016. memcpy(cmd, gen.command.u.raw.cmd, 16);
  4017. memcpy(gen.command.u.raw64.cmd, cmd, 16);
  4018. gen.command.u.raw64.clen = gen.command.u.raw.clen;
  4019. gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
  4020. gen.command.u.raw64.direction = gen.command.u.raw.direction;
  4021. /* addresses */
  4022. if (ha->raw_feat & SCATTER_GATHER) {
  4023. gen.command.u.raw64.sdata = (ulong64)-1;
  4024. gen.command.u.raw64.sg_ranz = 1;
  4025. gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
  4026. gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
  4027. gen.command.u.raw64.sg_lst[1].sg_len = 0;
  4028. } else {
  4029. gen.command.u.raw64.sdata = paddr;
  4030. gen.command.u.raw64.sg_ranz = 0;
  4031. }
  4032. gen.command.u.raw64.sense_data = paddr + gen.data_len;
  4033. } else {
  4034. if (ha->raw_feat & SCATTER_GATHER) {
  4035. gen.command.u.raw.sdata = 0xffffffff;
  4036. gen.command.u.raw.sg_ranz = 1;
  4037. gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
  4038. gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
  4039. gen.command.u.raw.sg_lst[1].sg_len = 0;
  4040. } else {
  4041. gen.command.u.raw.sdata = paddr;
  4042. gen.command.u.raw.sg_ranz = 0;
  4043. }
  4044. gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
  4045. }
  4046. } else {
  4047. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4048. return -EFAULT;
  4049. }
  4050. }
  4051. rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
  4052. if (rval < 0)
  4053. return rval;
  4054. gen.status = rval;
  4055. if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
  4056. gen.data_len + gen.sense_len)) {
  4057. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4058. return -EFAULT;
  4059. }
  4060. if (copy_to_user(arg, &gen,
  4061. sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
  4062. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4063. return -EFAULT;
  4064. }
  4065. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4066. return 0;
  4067. }
  4068. static int ioc_hdrlist(void __user *arg, char *cmnd)
  4069. {
  4070. gdth_ioctl_rescan *rsc;
  4071. gdth_cmd_str *cmd;
  4072. gdth_ha_str *ha;
  4073. unchar i;
  4074. int hanum, rc = -ENOMEM;
  4075. u32 cluster_type = 0;
  4076. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  4077. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  4078. if (!rsc || !cmd)
  4079. goto free_fail;
  4080. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  4081. rsc->ionode >= gdth_ctr_count) {
  4082. rc = -EFAULT;
  4083. goto free_fail;
  4084. }
  4085. hanum = rsc->ionode;
  4086. ha = HADATA(gdth_ctr_tab[hanum]);
  4087. memset(cmd, 0, sizeof(gdth_cmd_str));
  4088. for (i = 0; i < MAX_HDRIVES; ++i) {
  4089. if (!ha->hdr[i].present) {
  4090. rsc->hdr_list[i].bus = 0xff;
  4091. continue;
  4092. }
  4093. rsc->hdr_list[i].bus = ha->virt_bus;
  4094. rsc->hdr_list[i].target = i;
  4095. rsc->hdr_list[i].lun = 0;
  4096. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4097. if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
  4098. cmd->Service = CACHESERVICE;
  4099. cmd->OpCode = GDT_CLUST_INFO;
  4100. if (ha->cache_feat & GDT_64BIT)
  4101. cmd->u.cache64.DeviceNo = i;
  4102. else
  4103. cmd->u.cache.DeviceNo = i;
  4104. if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
  4105. rsc->hdr_list[i].cluster_type = cluster_type;
  4106. }
  4107. }
  4108. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4109. rc = -EFAULT;
  4110. else
  4111. rc = 0;
  4112. free_fail:
  4113. kfree(rsc);
  4114. kfree(cmd);
  4115. return rc;
  4116. }
  4117. static int ioc_rescan(void __user *arg, char *cmnd)
  4118. {
  4119. gdth_ioctl_rescan *rsc;
  4120. gdth_cmd_str *cmd;
  4121. ushort i, status, hdr_cnt;
  4122. ulong32 info;
  4123. int hanum, cyls, hds, secs;
  4124. int rc = -ENOMEM;
  4125. ulong flags;
  4126. gdth_ha_str *ha;
  4127. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  4128. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  4129. if (!cmd || !rsc)
  4130. goto free_fail;
  4131. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  4132. rsc->ionode >= gdth_ctr_count) {
  4133. rc = -EFAULT;
  4134. goto free_fail;
  4135. }
  4136. hanum = rsc->ionode;
  4137. ha = HADATA(gdth_ctr_tab[hanum]);
  4138. memset(cmd, 0, sizeof(gdth_cmd_str));
  4139. if (rsc->flag == 0) {
  4140. /* old method: re-init. cache service */
  4141. cmd->Service = CACHESERVICE;
  4142. if (ha->cache_feat & GDT_64BIT) {
  4143. cmd->OpCode = GDT_X_INIT_HOST;
  4144. cmd->u.cache64.DeviceNo = LINUX_OS;
  4145. } else {
  4146. cmd->OpCode = GDT_INIT;
  4147. cmd->u.cache.DeviceNo = LINUX_OS;
  4148. }
  4149. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4150. i = 0;
  4151. hdr_cnt = (status == S_OK ? (ushort)info : 0);
  4152. } else {
  4153. i = rsc->hdr_no;
  4154. hdr_cnt = i + 1;
  4155. }
  4156. for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
  4157. cmd->Service = CACHESERVICE;
  4158. cmd->OpCode = GDT_INFO;
  4159. if (ha->cache_feat & GDT_64BIT)
  4160. cmd->u.cache64.DeviceNo = i;
  4161. else
  4162. cmd->u.cache.DeviceNo = i;
  4163. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4164. spin_lock_irqsave(&ha->smp_lock, flags);
  4165. rsc->hdr_list[i].bus = ha->virt_bus;
  4166. rsc->hdr_list[i].target = i;
  4167. rsc->hdr_list[i].lun = 0;
  4168. if (status != S_OK) {
  4169. ha->hdr[i].present = FALSE;
  4170. } else {
  4171. ha->hdr[i].present = TRUE;
  4172. ha->hdr[i].size = info;
  4173. /* evaluate mapping */
  4174. ha->hdr[i].size &= ~SECS32;
  4175. gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
  4176. ha->hdr[i].heads = hds;
  4177. ha->hdr[i].secs = secs;
  4178. /* round size */
  4179. ha->hdr[i].size = cyls * hds * secs;
  4180. }
  4181. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4182. if (status != S_OK)
  4183. continue;
  4184. /* extended info, if GDT_64BIT, for drives > 2 TB */
  4185. /* but we need ha->info2, not yet stored in scp->SCp */
  4186. /* devtype, cluster info, R/W attribs */
  4187. cmd->Service = CACHESERVICE;
  4188. cmd->OpCode = GDT_DEVTYPE;
  4189. if (ha->cache_feat & GDT_64BIT)
  4190. cmd->u.cache64.DeviceNo = i;
  4191. else
  4192. cmd->u.cache.DeviceNo = i;
  4193. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4194. spin_lock_irqsave(&ha->smp_lock, flags);
  4195. ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
  4196. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4197. cmd->Service = CACHESERVICE;
  4198. cmd->OpCode = GDT_CLUST_INFO;
  4199. if (ha->cache_feat & GDT_64BIT)
  4200. cmd->u.cache64.DeviceNo = i;
  4201. else
  4202. cmd->u.cache.DeviceNo = i;
  4203. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4204. spin_lock_irqsave(&ha->smp_lock, flags);
  4205. ha->hdr[i].cluster_type =
  4206. ((status == S_OK && !shared_access) ? (ushort)info : 0);
  4207. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4208. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4209. cmd->Service = CACHESERVICE;
  4210. cmd->OpCode = GDT_RW_ATTRIBS;
  4211. if (ha->cache_feat & GDT_64BIT)
  4212. cmd->u.cache64.DeviceNo = i;
  4213. else
  4214. cmd->u.cache.DeviceNo = i;
  4215. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4216. spin_lock_irqsave(&ha->smp_lock, flags);
  4217. ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
  4218. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4219. }
  4220. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4221. rc = -EFAULT;
  4222. else
  4223. rc = 0;
  4224. free_fail:
  4225. kfree(rsc);
  4226. kfree(cmd);
  4227. return rc;
  4228. }
  4229. static int gdth_ioctl(struct inode *inode, struct file *filep,
  4230. unsigned int cmd, unsigned long arg)
  4231. {
  4232. gdth_ha_str *ha;
  4233. Scsi_Cmnd *scp;
  4234. ulong flags;
  4235. char cmnd[MAX_COMMAND_SIZE];
  4236. void __user *argp = (void __user *)arg;
  4237. memset(cmnd, 0xff, 12);
  4238. TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
  4239. switch (cmd) {
  4240. case GDTIOCTL_CTRCNT:
  4241. {
  4242. int cnt = gdth_ctr_count;
  4243. if (put_user(cnt, (int __user *)argp))
  4244. return -EFAULT;
  4245. break;
  4246. }
  4247. case GDTIOCTL_DRVERS:
  4248. {
  4249. int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
  4250. if (put_user(ver, (int __user *)argp))
  4251. return -EFAULT;
  4252. break;
  4253. }
  4254. case GDTIOCTL_OSVERS:
  4255. {
  4256. gdth_ioctl_osvers osv;
  4257. osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
  4258. osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
  4259. osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
  4260. if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
  4261. return -EFAULT;
  4262. break;
  4263. }
  4264. case GDTIOCTL_CTRTYPE:
  4265. {
  4266. gdth_ioctl_ctrtype ctrt;
  4267. if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
  4268. ctrt.ionode >= gdth_ctr_count)
  4269. return -EFAULT;
  4270. ha = HADATA(gdth_ctr_tab[ctrt.ionode]);
  4271. if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
  4272. ctrt.type = (unchar)((ha->stype>>20) - 0x10);
  4273. } else {
  4274. if (ha->type != GDT_PCIMPR) {
  4275. ctrt.type = (unchar)((ha->stype<<4) + 6);
  4276. } else {
  4277. ctrt.type =
  4278. (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
  4279. if (ha->stype >= 0x300)
  4280. ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
  4281. else
  4282. ctrt.ext_type = 0x6000 | ha->stype;
  4283. }
  4284. ctrt.device_id = ha->pdev->device;
  4285. ctrt.sub_device_id = ha->pdev->subsystem_device;
  4286. }
  4287. ctrt.info = ha->brd_phys;
  4288. ctrt.oem_id = ha->oem_id;
  4289. if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
  4290. return -EFAULT;
  4291. break;
  4292. }
  4293. case GDTIOCTL_GENERAL:
  4294. return ioc_general(argp, cmnd);
  4295. case GDTIOCTL_EVENT:
  4296. return ioc_event(argp);
  4297. case GDTIOCTL_LOCKDRV:
  4298. return ioc_lockdrv(argp);
  4299. case GDTIOCTL_LOCKCHN:
  4300. {
  4301. gdth_ioctl_lockchn lchn;
  4302. unchar i, j;
  4303. if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
  4304. lchn.ionode >= gdth_ctr_count)
  4305. return -EFAULT;
  4306. ha = HADATA(gdth_ctr_tab[lchn.ionode]);
  4307. i = lchn.channel;
  4308. if (i < ha->bus_cnt) {
  4309. if (lchn.lock) {
  4310. spin_lock_irqsave(&ha->smp_lock, flags);
  4311. ha->raw[i].lock = 1;
  4312. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4313. for (j = 0; j < ha->tid_cnt; ++j) {
  4314. gdth_wait_completion(lchn.ionode, i, j);
  4315. gdth_stop_timeout(lchn.ionode, i, j);
  4316. }
  4317. } else {
  4318. spin_lock_irqsave(&ha->smp_lock, flags);
  4319. ha->raw[i].lock = 0;
  4320. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4321. for (j = 0; j < ha->tid_cnt; ++j) {
  4322. gdth_start_timeout(lchn.ionode, i, j);
  4323. gdth_next(lchn.ionode);
  4324. }
  4325. }
  4326. }
  4327. break;
  4328. }
  4329. case GDTIOCTL_RESCAN:
  4330. return ioc_rescan(argp, cmnd);
  4331. case GDTIOCTL_HDRLIST:
  4332. return ioc_hdrlist(argp, cmnd);
  4333. case GDTIOCTL_RESET_BUS:
  4334. {
  4335. gdth_ioctl_reset res;
  4336. int hanum, rval;
  4337. if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
  4338. res.ionode >= gdth_ctr_count)
  4339. return -EFAULT;
  4340. hanum = res.ionode;
  4341. ha = HADATA(gdth_ctr_tab[hanum]);
  4342. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  4343. if (!scp)
  4344. return -ENOMEM;
  4345. scp->device = ha->sdev;
  4346. scp->cmd_len = 12;
  4347. scp->use_sg = 0;
  4348. scp->device->channel = res.number;
  4349. rval = gdth_eh_bus_reset(scp);
  4350. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  4351. kfree(scp);
  4352. if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
  4353. return -EFAULT;
  4354. break;
  4355. }
  4356. case GDTIOCTL_RESET_DRV:
  4357. return ioc_resetdrv(argp, cmnd);
  4358. default:
  4359. break;
  4360. }
  4361. return 0;
  4362. }
  4363. /* flush routine */
  4364. static void gdth_flush(int hanum)
  4365. {
  4366. int i;
  4367. gdth_ha_str *ha;
  4368. gdth_cmd_str gdtcmd;
  4369. char cmnd[MAX_COMMAND_SIZE];
  4370. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4371. TRACE2(("gdth_flush() hanum %d\n",hanum));
  4372. ha = HADATA(gdth_ctr_tab[hanum]);
  4373. for (i = 0; i < MAX_HDRIVES; ++i) {
  4374. if (ha->hdr[i].present) {
  4375. gdtcmd.BoardNode = LOCALBOARD;
  4376. gdtcmd.Service = CACHESERVICE;
  4377. gdtcmd.OpCode = GDT_FLUSH;
  4378. if (ha->cache_feat & GDT_64BIT) {
  4379. gdtcmd.u.cache64.DeviceNo = i;
  4380. gdtcmd.u.cache64.BlockNo = 1;
  4381. gdtcmd.u.cache64.sg_canz = 0;
  4382. } else {
  4383. gdtcmd.u.cache.DeviceNo = i;
  4384. gdtcmd.u.cache.BlockNo = 1;
  4385. gdtcmd.u.cache.sg_canz = 0;
  4386. }
  4387. TRACE2(("gdth_flush(): flush ha %d drive %d\n", hanum, i));
  4388. gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 30, NULL);
  4389. }
  4390. }
  4391. }
  4392. /* shutdown routine */
  4393. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
  4394. {
  4395. int hanum;
  4396. #ifndef __alpha__
  4397. gdth_cmd_str gdtcmd;
  4398. char cmnd[MAX_COMMAND_SIZE];
  4399. #endif
  4400. if (notifier_disabled)
  4401. return NOTIFY_OK;
  4402. TRACE2(("gdth_halt() event %d\n",(int)event));
  4403. if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
  4404. return NOTIFY_DONE;
  4405. notifier_disabled = 1;
  4406. printk("GDT-HA: Flushing all host drives .. ");
  4407. for (hanum = 0; hanum < gdth_ctr_count; ++hanum) {
  4408. gdth_flush(hanum);
  4409. #ifndef __alpha__
  4410. /* controller reset */
  4411. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4412. gdtcmd.BoardNode = LOCALBOARD;
  4413. gdtcmd.Service = CACHESERVICE;
  4414. gdtcmd.OpCode = GDT_RESET;
  4415. TRACE2(("gdth_halt(): reset controller %d\n", hanum));
  4416. gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 10, NULL);
  4417. #endif
  4418. }
  4419. printk("Done.\n");
  4420. #ifdef GDTH_STATISTICS
  4421. del_timer(&gdth_timer);
  4422. #endif
  4423. return NOTIFY_OK;
  4424. }
  4425. /* configure lun */
  4426. static int gdth_slave_configure(struct scsi_device *sdev)
  4427. {
  4428. scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
  4429. sdev->skip_ms_page_3f = 1;
  4430. sdev->skip_ms_page_8 = 1;
  4431. return 0;
  4432. }
  4433. static struct scsi_host_template driver_template = {
  4434. .name = "GDT SCSI Disk Array Controller",
  4435. .detect = gdth_detect,
  4436. .release = gdth_release,
  4437. .info = gdth_info,
  4438. .queuecommand = gdth_queuecommand,
  4439. .eh_bus_reset_handler = gdth_eh_bus_reset,
  4440. .slave_configure = gdth_slave_configure,
  4441. .bios_param = gdth_bios_param,
  4442. .proc_info = gdth_proc_info,
  4443. .proc_name = "gdth",
  4444. .can_queue = GDTH_MAXCMDS,
  4445. .this_id = -1,
  4446. .sg_tablesize = GDTH_MAXSG,
  4447. .cmd_per_lun = GDTH_MAXC_P_L,
  4448. .unchecked_isa_dma = 1,
  4449. .use_clustering = ENABLE_CLUSTERING,
  4450. };
  4451. #ifdef CONFIG_ISA
  4452. static int gdth_isa_probe_one(struct scsi_host_template *shtp, ulong32 isa_bios)
  4453. {
  4454. struct Scsi_Host *shp;
  4455. gdth_ha_str *ha;
  4456. dma_addr_t scratch_dma_handle = 0;
  4457. int error, hanum, i;
  4458. if (!gdth_search_isa(isa_bios))
  4459. return -ENXIO;
  4460. shp = scsi_register(shtp, sizeof(gdth_ext_str));
  4461. if (!shp)
  4462. return -ENOMEM;
  4463. ha = HADATA(shp);
  4464. error = -ENODEV;
  4465. if (!gdth_init_isa(isa_bios,ha))
  4466. goto out_host_put;
  4467. /* controller found and initialized */
  4468. printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
  4469. isa_bios, ha->irq, ha->drq);
  4470. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4471. if (error) {
  4472. printk("GDT-ISA: Unable to allocate IRQ\n");
  4473. goto out_host_put;
  4474. }
  4475. error = request_dma(ha->drq, "gdth");
  4476. if (error) {
  4477. printk("GDT-ISA: Unable to allocate DMA channel\n");
  4478. goto out_free_irq;
  4479. }
  4480. set_dma_mode(ha->drq,DMA_MODE_CASCADE);
  4481. enable_dma(ha->drq);
  4482. shp->unchecked_isa_dma = 1;
  4483. shp->irq = ha->irq;
  4484. shp->dma_channel = ha->drq;
  4485. hanum = gdth_ctr_count;
  4486. gdth_ctr_tab[gdth_ctr_count++] = shp;
  4487. NUMDATA(shp)->hanum = (ushort)hanum;
  4488. ha->pccb = CMDDATA(shp);
  4489. ha->ccb_phys = 0L;
  4490. ha->pdev = NULL;
  4491. error = -ENOMEM;
  4492. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4493. &scratch_dma_handle);
  4494. if (!ha->pscratch)
  4495. goto out_dec_counters;
  4496. ha->scratch_phys = scratch_dma_handle;
  4497. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4498. &scratch_dma_handle);
  4499. if (!ha->pmsg)
  4500. goto out_free_pscratch;
  4501. ha->msg_phys = scratch_dma_handle;
  4502. #ifdef INT_COAL
  4503. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4504. sizeof(gdth_coal_status) * MAXOFFSETS,
  4505. &scratch_dma_handle);
  4506. if (!ha->coal_stat)
  4507. goto out_free_pmsg;
  4508. ha->coal_stat_phys = scratch_dma_handle;
  4509. #endif
  4510. ha->scratch_busy = FALSE;
  4511. ha->req_first = NULL;
  4512. ha->tid_cnt = MAX_HDRIVES;
  4513. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4514. ha->tid_cnt = max_ids;
  4515. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4516. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4517. ha->scan_mode = rescan ? 0x10 : 0;
  4518. error = -ENODEV;
  4519. if (!gdth_search_drives(hanum)) {
  4520. printk("GDT-ISA: Error during device scan\n");
  4521. goto out_free_coal_stat;
  4522. }
  4523. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4524. hdr_channel = ha->bus_cnt;
  4525. ha->virt_bus = hdr_channel;
  4526. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4527. shp->max_cmd_len = 16;
  4528. shp->max_id = ha->tid_cnt;
  4529. shp->max_lun = MAXLUN;
  4530. shp->max_channel = ha->bus_cnt;
  4531. spin_lock_init(&ha->smp_lock);
  4532. gdth_enable_int(hanum);
  4533. return 0;
  4534. out_free_coal_stat:
  4535. #ifdef INT_COAL
  4536. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4537. ha->coal_stat, ha->coal_stat_phys);
  4538. out_free_pmsg:
  4539. #endif
  4540. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4541. ha->pmsg, ha->msg_phys);
  4542. out_free_pscratch:
  4543. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4544. ha->pscratch, ha->scratch_phys);
  4545. out_dec_counters:
  4546. gdth_ctr_count--;
  4547. out_free_irq:
  4548. free_irq(ha->irq, ha);
  4549. out_host_put:
  4550. scsi_unregister(shp);
  4551. return error;
  4552. }
  4553. #endif /* CONFIG_ISA */
  4554. #ifdef CONFIG_EISA
  4555. static int gdth_eisa_probe_one(struct scsi_host_template *shtp,
  4556. ushort eisa_slot)
  4557. {
  4558. struct Scsi_Host *shp;
  4559. gdth_ha_str *ha;
  4560. dma_addr_t scratch_dma_handle = 0;
  4561. int error, hanum, i;
  4562. if (!gdth_search_eisa(eisa_slot))
  4563. return -ENXIO;
  4564. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  4565. if (!shp)
  4566. return -ENOMEM;
  4567. ha = HADATA(shp);
  4568. error = -ENODEV;
  4569. if (!gdth_init_eisa(eisa_slot,ha))
  4570. goto out_host_put;
  4571. /* controller found and initialized */
  4572. printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
  4573. eisa_slot >> 12, ha->irq);
  4574. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4575. if (error) {
  4576. printk("GDT-EISA: Unable to allocate IRQ\n");
  4577. goto out_host_put;
  4578. }
  4579. shp->unchecked_isa_dma = 0;
  4580. shp->irq = ha->irq;
  4581. shp->dma_channel = 0xff;
  4582. hanum = gdth_ctr_count;
  4583. gdth_ctr_tab[gdth_ctr_count++] = shp;
  4584. NUMDATA(shp)->hanum = (ushort)hanum;
  4585. TRACE2(("EISA detect Bus 0: hanum %d\n",
  4586. NUMDATA(shp)->hanum));
  4587. ha->pccb = CMDDATA(shp);
  4588. ha->ccb_phys = 0L;
  4589. error = -ENOMEM;
  4590. ha->pdev = NULL;
  4591. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4592. &scratch_dma_handle);
  4593. if (!ha->pscratch)
  4594. goto out_free_irq;
  4595. ha->scratch_phys = scratch_dma_handle;
  4596. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4597. &scratch_dma_handle);
  4598. if (!ha->pmsg)
  4599. goto out_free_pscratch;
  4600. ha->msg_phys = scratch_dma_handle;
  4601. #ifdef INT_COAL
  4602. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4603. sizeof(gdth_coal_status) * MAXOFFSETS,
  4604. &scratch_dma_handle);
  4605. if (!ha->coal_stat)
  4606. goto out_free_pmsg;
  4607. ha->coal_stat_phys = scratch_dma_handle;
  4608. #endif
  4609. ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
  4610. sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
  4611. if (!ha->ccb_phys)
  4612. goto out_free_coal_stat;
  4613. ha->scratch_busy = FALSE;
  4614. ha->req_first = NULL;
  4615. ha->tid_cnt = MAX_HDRIVES;
  4616. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4617. ha->tid_cnt = max_ids;
  4618. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4619. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4620. ha->scan_mode = rescan ? 0x10 : 0;
  4621. if (!gdth_search_drives(hanum)) {
  4622. printk("GDT-EISA: Error during device scan\n");
  4623. error = -ENODEV;
  4624. goto out_free_ccb_phys;
  4625. }
  4626. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4627. hdr_channel = ha->bus_cnt;
  4628. ha->virt_bus = hdr_channel;
  4629. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4630. shp->max_cmd_len = 16;
  4631. shp->max_id = ha->tid_cnt;
  4632. shp->max_lun = MAXLUN;
  4633. shp->max_channel = ha->bus_cnt;
  4634. spin_lock_init(&ha->smp_lock);
  4635. gdth_enable_int(hanum);
  4636. return 0;
  4637. out_free_ccb_phys:
  4638. pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
  4639. PCI_DMA_BIDIRECTIONAL);
  4640. out_free_coal_stat:
  4641. #ifdef INT_COAL
  4642. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4643. ha->coal_stat, ha->coal_stat_phys);
  4644. out_free_pmsg:
  4645. #endif
  4646. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4647. ha->pmsg, ha->msg_phys);
  4648. out_free_pscratch:
  4649. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4650. ha->pscratch, ha->scratch_phys);
  4651. out_free_irq:
  4652. free_irq(ha->irq, ha);
  4653. gdth_ctr_count--;
  4654. out_host_put:
  4655. scsi_unregister(shp);
  4656. return error;
  4657. }
  4658. #endif /* CONFIG_EISA */
  4659. #ifdef CONFIG_PCI
  4660. static int gdth_pci_probe_one(struct scsi_host_template *shtp,
  4661. gdth_pci_str *pcistr, int ctr)
  4662. {
  4663. struct Scsi_Host *shp;
  4664. gdth_ha_str *ha;
  4665. dma_addr_t scratch_dma_handle = 0;
  4666. int error, hanum, i;
  4667. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  4668. if (!shp)
  4669. return -ENOMEM;
  4670. ha = HADATA(shp);
  4671. error = -ENODEV;
  4672. if (!gdth_init_pci(&pcistr[ctr],ha))
  4673. goto out_host_put;
  4674. /* controller found and initialized */
  4675. printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
  4676. pcistr[ctr].pdev->bus->number,
  4677. PCI_SLOT(pcistr[ctr].pdev->devfn),
  4678. ha->irq);
  4679. error = request_irq(ha->irq, gdth_interrupt,
  4680. IRQF_DISABLED|IRQF_SHARED, "gdth", ha);
  4681. if (error) {
  4682. printk("GDT-PCI: Unable to allocate IRQ\n");
  4683. goto out_host_put;
  4684. }
  4685. shp->unchecked_isa_dma = 0;
  4686. shp->irq = ha->irq;
  4687. shp->dma_channel = 0xff;
  4688. hanum = gdth_ctr_count;
  4689. gdth_ctr_tab[gdth_ctr_count++] = shp;
  4690. NUMDATA(shp)->hanum = (ushort)hanum;
  4691. ha->pccb = CMDDATA(shp);
  4692. ha->ccb_phys = 0L;
  4693. error = -ENOMEM;
  4694. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4695. &scratch_dma_handle);
  4696. if (!ha->pscratch)
  4697. goto out_free_irq;
  4698. ha->scratch_phys = scratch_dma_handle;
  4699. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4700. &scratch_dma_handle);
  4701. if (!ha->pmsg)
  4702. goto out_free_pscratch;
  4703. ha->msg_phys = scratch_dma_handle;
  4704. #ifdef INT_COAL
  4705. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4706. sizeof(gdth_coal_status) * MAXOFFSETS,
  4707. &scratch_dma_handle);
  4708. if (!ha->coal_stat)
  4709. goto out_free_pmsg;
  4710. ha->coal_stat_phys = scratch_dma_handle;
  4711. #endif
  4712. ha->scratch_busy = FALSE;
  4713. ha->req_first = NULL;
  4714. ha->tid_cnt = pcistr[ctr].pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
  4715. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4716. ha->tid_cnt = max_ids;
  4717. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4718. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4719. ha->scan_mode = rescan ? 0x10 : 0;
  4720. error = -ENODEV;
  4721. if (!gdth_search_drives(hanum)) {
  4722. printk("GDT-PCI %d: Error during device scan\n", hanum);
  4723. goto out_free_coal_stat;
  4724. }
  4725. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4726. hdr_channel = ha->bus_cnt;
  4727. ha->virt_bus = hdr_channel;
  4728. /* 64-bit DMA only supported from FW >= x.43 */
  4729. if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) ||
  4730. !ha->dma64_support) {
  4731. if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4732. printk(KERN_WARNING "GDT-PCI %d: "
  4733. "Unable to set 32-bit DMA\n", hanum);
  4734. goto out_free_coal_stat;
  4735. }
  4736. } else {
  4737. shp->max_cmd_len = 16;
  4738. if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
  4739. printk("GDT-PCI %d: 64-bit DMA enabled\n", hanum);
  4740. } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4741. printk(KERN_WARNING "GDT-PCI %d: "
  4742. "Unable to set 64/32-bit DMA\n", hanum);
  4743. goto out_free_coal_stat;
  4744. }
  4745. }
  4746. shp->max_id = ha->tid_cnt;
  4747. shp->max_lun = MAXLUN;
  4748. shp->max_channel = ha->bus_cnt;
  4749. spin_lock_init(&ha->smp_lock);
  4750. gdth_enable_int(hanum);
  4751. return 0;
  4752. out_free_coal_stat:
  4753. #ifdef INT_COAL
  4754. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4755. ha->coal_stat, ha->coal_stat_phys);
  4756. out_free_pmsg:
  4757. #endif
  4758. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4759. ha->pmsg, ha->msg_phys);
  4760. out_free_pscratch:
  4761. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4762. ha->pscratch, ha->scratch_phys);
  4763. out_free_irq:
  4764. free_irq(ha->irq, ha);
  4765. gdth_ctr_count--;
  4766. out_host_put:
  4767. scsi_unregister(shp);
  4768. return error;
  4769. }
  4770. #endif /* CONFIG_PCI */
  4771. #include "scsi_module.c"
  4772. #ifndef MODULE
  4773. __setup("gdth=", option_setup);
  4774. #endif