atmel_usba_udc.c 48 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033
  1. /*
  2. * Driver for the Atmel USBA high speed USB device controller
  3. *
  4. * Copyright (C) 2005-2007 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/io.h>
  15. #include <linux/device.h>
  16. #include <linux/dma-mapping.h>
  17. #include <linux/list.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/usb/ch9.h>
  20. #include <linux/usb/gadget.h>
  21. #include <linux/usb/atmel_usba_udc.h>
  22. #include <linux/delay.h>
  23. #include <asm/gpio.h>
  24. #include <asm/arch/board.h>
  25. #include "atmel_usba_udc.h"
  26. static struct usba_udc the_udc;
  27. static struct usba_ep *usba_ep;
  28. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  29. #include <linux/debugfs.h>
  30. #include <linux/uaccess.h>
  31. static int queue_dbg_open(struct inode *inode, struct file *file)
  32. {
  33. struct usba_ep *ep = inode->i_private;
  34. struct usba_request *req, *req_copy;
  35. struct list_head *queue_data;
  36. queue_data = kmalloc(sizeof(*queue_data), GFP_KERNEL);
  37. if (!queue_data)
  38. return -ENOMEM;
  39. INIT_LIST_HEAD(queue_data);
  40. spin_lock_irq(&ep->udc->lock);
  41. list_for_each_entry(req, &ep->queue, queue) {
  42. req_copy = kmalloc(sizeof(*req_copy), GFP_ATOMIC);
  43. if (!req_copy)
  44. goto fail;
  45. memcpy(req_copy, req, sizeof(*req_copy));
  46. list_add_tail(&req_copy->queue, queue_data);
  47. }
  48. spin_unlock_irq(&ep->udc->lock);
  49. file->private_data = queue_data;
  50. return 0;
  51. fail:
  52. spin_unlock_irq(&ep->udc->lock);
  53. list_for_each_entry_safe(req, req_copy, queue_data, queue) {
  54. list_del(&req->queue);
  55. kfree(req);
  56. }
  57. kfree(queue_data);
  58. return -ENOMEM;
  59. }
  60. /*
  61. * bbbbbbbb llllllll IZS sssss nnnn FDL\n\0
  62. *
  63. * b: buffer address
  64. * l: buffer length
  65. * I/i: interrupt/no interrupt
  66. * Z/z: zero/no zero
  67. * S/s: short ok/short not ok
  68. * s: status
  69. * n: nr_packets
  70. * F/f: submitted/not submitted to FIFO
  71. * D/d: using/not using DMA
  72. * L/l: last transaction/not last transaction
  73. */
  74. static ssize_t queue_dbg_read(struct file *file, char __user *buf,
  75. size_t nbytes, loff_t *ppos)
  76. {
  77. struct list_head *queue = file->private_data;
  78. struct usba_request *req, *tmp_req;
  79. size_t len, remaining, actual = 0;
  80. char tmpbuf[38];
  81. if (!access_ok(VERIFY_WRITE, buf, nbytes))
  82. return -EFAULT;
  83. mutex_lock(&file->f_dentry->d_inode->i_mutex);
  84. list_for_each_entry_safe(req, tmp_req, queue, queue) {
  85. len = snprintf(tmpbuf, sizeof(tmpbuf),
  86. "%8p %08x %c%c%c %5d %c%c%c\n",
  87. req->req.buf, req->req.length,
  88. req->req.no_interrupt ? 'i' : 'I',
  89. req->req.zero ? 'Z' : 'z',
  90. req->req.short_not_ok ? 's' : 'S',
  91. req->req.status,
  92. req->submitted ? 'F' : 'f',
  93. req->using_dma ? 'D' : 'd',
  94. req->last_transaction ? 'L' : 'l');
  95. len = min(len, sizeof(tmpbuf));
  96. if (len > nbytes)
  97. break;
  98. list_del(&req->queue);
  99. kfree(req);
  100. remaining = __copy_to_user(buf, tmpbuf, len);
  101. actual += len - remaining;
  102. if (remaining)
  103. break;
  104. nbytes -= len;
  105. buf += len;
  106. }
  107. mutex_unlock(&file->f_dentry->d_inode->i_mutex);
  108. return actual;
  109. }
  110. static int queue_dbg_release(struct inode *inode, struct file *file)
  111. {
  112. struct list_head *queue_data = file->private_data;
  113. struct usba_request *req, *tmp_req;
  114. list_for_each_entry_safe(req, tmp_req, queue_data, queue) {
  115. list_del(&req->queue);
  116. kfree(req);
  117. }
  118. kfree(queue_data);
  119. return 0;
  120. }
  121. static int regs_dbg_open(struct inode *inode, struct file *file)
  122. {
  123. struct usba_udc *udc;
  124. unsigned int i;
  125. u32 *data;
  126. int ret = -ENOMEM;
  127. mutex_lock(&inode->i_mutex);
  128. udc = inode->i_private;
  129. data = kmalloc(inode->i_size, GFP_KERNEL);
  130. if (!data)
  131. goto out;
  132. spin_lock_irq(&udc->lock);
  133. for (i = 0; i < inode->i_size / 4; i++)
  134. data[i] = __raw_readl(udc->regs + i * 4);
  135. spin_unlock_irq(&udc->lock);
  136. file->private_data = data;
  137. ret = 0;
  138. out:
  139. mutex_unlock(&inode->i_mutex);
  140. return ret;
  141. }
  142. static ssize_t regs_dbg_read(struct file *file, char __user *buf,
  143. size_t nbytes, loff_t *ppos)
  144. {
  145. struct inode *inode = file->f_dentry->d_inode;
  146. int ret;
  147. mutex_lock(&inode->i_mutex);
  148. ret = simple_read_from_buffer(buf, nbytes, ppos,
  149. file->private_data,
  150. file->f_dentry->d_inode->i_size);
  151. mutex_unlock(&inode->i_mutex);
  152. return ret;
  153. }
  154. static int regs_dbg_release(struct inode *inode, struct file *file)
  155. {
  156. kfree(file->private_data);
  157. return 0;
  158. }
  159. const struct file_operations queue_dbg_fops = {
  160. .owner = THIS_MODULE,
  161. .open = queue_dbg_open,
  162. .llseek = no_llseek,
  163. .read = queue_dbg_read,
  164. .release = queue_dbg_release,
  165. };
  166. const struct file_operations regs_dbg_fops = {
  167. .owner = THIS_MODULE,
  168. .open = regs_dbg_open,
  169. .llseek = generic_file_llseek,
  170. .read = regs_dbg_read,
  171. .release = regs_dbg_release,
  172. };
  173. static void usba_ep_init_debugfs(struct usba_udc *udc,
  174. struct usba_ep *ep)
  175. {
  176. struct dentry *ep_root;
  177. ep_root = debugfs_create_dir(ep->ep.name, udc->debugfs_root);
  178. if (!ep_root)
  179. goto err_root;
  180. ep->debugfs_dir = ep_root;
  181. ep->debugfs_queue = debugfs_create_file("queue", 0400, ep_root,
  182. ep, &queue_dbg_fops);
  183. if (!ep->debugfs_queue)
  184. goto err_queue;
  185. if (ep->can_dma) {
  186. ep->debugfs_dma_status
  187. = debugfs_create_u32("dma_status", 0400, ep_root,
  188. &ep->last_dma_status);
  189. if (!ep->debugfs_dma_status)
  190. goto err_dma_status;
  191. }
  192. if (ep_is_control(ep)) {
  193. ep->debugfs_state
  194. = debugfs_create_u32("state", 0400, ep_root,
  195. &ep->state);
  196. if (!ep->debugfs_state)
  197. goto err_state;
  198. }
  199. return;
  200. err_state:
  201. if (ep->can_dma)
  202. debugfs_remove(ep->debugfs_dma_status);
  203. err_dma_status:
  204. debugfs_remove(ep->debugfs_queue);
  205. err_queue:
  206. debugfs_remove(ep_root);
  207. err_root:
  208. dev_err(&ep->udc->pdev->dev,
  209. "failed to create debugfs directory for %s\n", ep->ep.name);
  210. }
  211. static void usba_ep_cleanup_debugfs(struct usba_ep *ep)
  212. {
  213. debugfs_remove(ep->debugfs_queue);
  214. debugfs_remove(ep->debugfs_dma_status);
  215. debugfs_remove(ep->debugfs_state);
  216. debugfs_remove(ep->debugfs_dir);
  217. ep->debugfs_dma_status = NULL;
  218. ep->debugfs_dir = NULL;
  219. }
  220. static void usba_init_debugfs(struct usba_udc *udc)
  221. {
  222. struct dentry *root, *regs;
  223. struct resource *regs_resource;
  224. root = debugfs_create_dir(udc->gadget.name, NULL);
  225. if (IS_ERR(root) || !root)
  226. goto err_root;
  227. udc->debugfs_root = root;
  228. regs = debugfs_create_file("regs", 0400, root, udc, &regs_dbg_fops);
  229. if (!regs)
  230. goto err_regs;
  231. regs_resource = platform_get_resource(udc->pdev, IORESOURCE_MEM,
  232. CTRL_IOMEM_ID);
  233. regs->d_inode->i_size = regs_resource->end - regs_resource->start + 1;
  234. udc->debugfs_regs = regs;
  235. usba_ep_init_debugfs(udc, to_usba_ep(udc->gadget.ep0));
  236. return;
  237. err_regs:
  238. debugfs_remove(root);
  239. err_root:
  240. udc->debugfs_root = NULL;
  241. dev_err(&udc->pdev->dev, "debugfs is not available\n");
  242. }
  243. static void usba_cleanup_debugfs(struct usba_udc *udc)
  244. {
  245. usba_ep_cleanup_debugfs(to_usba_ep(udc->gadget.ep0));
  246. debugfs_remove(udc->debugfs_regs);
  247. debugfs_remove(udc->debugfs_root);
  248. udc->debugfs_regs = NULL;
  249. udc->debugfs_root = NULL;
  250. }
  251. #else
  252. static inline void usba_ep_init_debugfs(struct usba_udc *udc,
  253. struct usba_ep *ep)
  254. {
  255. }
  256. static inline void usba_ep_cleanup_debugfs(struct usba_ep *ep)
  257. {
  258. }
  259. static inline void usba_init_debugfs(struct usba_udc *udc)
  260. {
  261. }
  262. static inline void usba_cleanup_debugfs(struct usba_udc *udc)
  263. {
  264. }
  265. #endif
  266. static int vbus_is_present(struct usba_udc *udc)
  267. {
  268. if (udc->vbus_pin != -1)
  269. return gpio_get_value(udc->vbus_pin);
  270. /* No Vbus detection: Assume always present */
  271. return 1;
  272. }
  273. static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
  274. {
  275. unsigned int transaction_len;
  276. transaction_len = req->req.length - req->req.actual;
  277. req->last_transaction = 1;
  278. if (transaction_len > ep->ep.maxpacket) {
  279. transaction_len = ep->ep.maxpacket;
  280. req->last_transaction = 0;
  281. } else if (transaction_len == ep->ep.maxpacket && req->req.zero)
  282. req->last_transaction = 0;
  283. DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n",
  284. ep->ep.name, req, transaction_len,
  285. req->last_transaction ? ", done" : "");
  286. memcpy_toio(ep->fifo, req->req.buf + req->req.actual, transaction_len);
  287. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  288. req->req.actual += transaction_len;
  289. }
  290. static void submit_request(struct usba_ep *ep, struct usba_request *req)
  291. {
  292. DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d)\n",
  293. ep->ep.name, req, req->req.length);
  294. req->req.actual = 0;
  295. req->submitted = 1;
  296. if (req->using_dma) {
  297. if (req->req.length == 0) {
  298. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  299. return;
  300. }
  301. if (req->req.zero)
  302. usba_ep_writel(ep, CTL_ENB, USBA_SHORT_PACKET);
  303. else
  304. usba_ep_writel(ep, CTL_DIS, USBA_SHORT_PACKET);
  305. usba_dma_writel(ep, ADDRESS, req->req.dma);
  306. usba_dma_writel(ep, CONTROL, req->ctrl);
  307. } else {
  308. next_fifo_transaction(ep, req);
  309. if (req->last_transaction) {
  310. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  311. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  312. } else {
  313. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  314. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  315. }
  316. }
  317. }
  318. static void submit_next_request(struct usba_ep *ep)
  319. {
  320. struct usba_request *req;
  321. if (list_empty(&ep->queue)) {
  322. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY | USBA_RX_BK_RDY);
  323. return;
  324. }
  325. req = list_entry(ep->queue.next, struct usba_request, queue);
  326. if (!req->submitted)
  327. submit_request(ep, req);
  328. }
  329. static void send_status(struct usba_udc *udc, struct usba_ep *ep)
  330. {
  331. ep->state = STATUS_STAGE_IN;
  332. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  333. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  334. }
  335. static void receive_data(struct usba_ep *ep)
  336. {
  337. struct usba_udc *udc = ep->udc;
  338. struct usba_request *req;
  339. unsigned long status;
  340. unsigned int bytecount, nr_busy;
  341. int is_complete = 0;
  342. status = usba_ep_readl(ep, STA);
  343. nr_busy = USBA_BFEXT(BUSY_BANKS, status);
  344. DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy);
  345. while (nr_busy > 0) {
  346. if (list_empty(&ep->queue)) {
  347. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  348. break;
  349. }
  350. req = list_entry(ep->queue.next,
  351. struct usba_request, queue);
  352. bytecount = USBA_BFEXT(BYTE_COUNT, status);
  353. if (status & (1 << 31))
  354. is_complete = 1;
  355. if (req->req.actual + bytecount >= req->req.length) {
  356. is_complete = 1;
  357. bytecount = req->req.length - req->req.actual;
  358. }
  359. memcpy_fromio(req->req.buf + req->req.actual,
  360. ep->fifo, bytecount);
  361. req->req.actual += bytecount;
  362. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  363. if (is_complete) {
  364. DBG(DBG_QUEUE, "%s: request done\n", ep->ep.name);
  365. req->req.status = 0;
  366. list_del_init(&req->queue);
  367. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  368. spin_unlock(&udc->lock);
  369. req->req.complete(&ep->ep, &req->req);
  370. spin_lock(&udc->lock);
  371. }
  372. status = usba_ep_readl(ep, STA);
  373. nr_busy = USBA_BFEXT(BUSY_BANKS, status);
  374. if (is_complete && ep_is_control(ep)) {
  375. send_status(udc, ep);
  376. break;
  377. }
  378. }
  379. }
  380. static void
  381. request_complete(struct usba_ep *ep, struct usba_request *req, int status)
  382. {
  383. struct usba_udc *udc = ep->udc;
  384. WARN_ON(!list_empty(&req->queue));
  385. if (req->req.status == -EINPROGRESS)
  386. req->req.status = status;
  387. if (req->mapped) {
  388. dma_unmap_single(
  389. &udc->pdev->dev, req->req.dma, req->req.length,
  390. ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  391. req->req.dma = DMA_ADDR_INVALID;
  392. req->mapped = 0;
  393. }
  394. DBG(DBG_GADGET | DBG_REQ,
  395. "%s: req %p complete: status %d, actual %u\n",
  396. ep->ep.name, req, req->req.status, req->req.actual);
  397. spin_unlock(&udc->lock);
  398. req->req.complete(&ep->ep, &req->req);
  399. spin_lock(&udc->lock);
  400. }
  401. static void
  402. request_complete_list(struct usba_ep *ep, struct list_head *list, int status)
  403. {
  404. struct usba_request *req, *tmp_req;
  405. list_for_each_entry_safe(req, tmp_req, list, queue) {
  406. list_del_init(&req->queue);
  407. request_complete(ep, req, status);
  408. }
  409. }
  410. static int
  411. usba_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
  412. {
  413. struct usba_ep *ep = to_usba_ep(_ep);
  414. struct usba_udc *udc = ep->udc;
  415. unsigned long flags, ept_cfg, maxpacket;
  416. unsigned int nr_trans;
  417. DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep->ep.name, desc);
  418. maxpacket = le16_to_cpu(desc->wMaxPacketSize) & 0x7ff;
  419. if (((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != ep->index)
  420. || ep->index == 0
  421. || desc->bDescriptorType != USB_DT_ENDPOINT
  422. || maxpacket == 0
  423. || maxpacket > ep->fifo_size) {
  424. DBG(DBG_ERR, "ep_enable: Invalid argument");
  425. return -EINVAL;
  426. }
  427. ep->is_isoc = 0;
  428. ep->is_in = 0;
  429. if (maxpacket <= 8)
  430. ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
  431. else
  432. /* LSB is bit 1, not 0 */
  433. ept_cfg = USBA_BF(EPT_SIZE, fls(maxpacket - 1) - 3);
  434. DBG(DBG_HW, "%s: EPT_SIZE = %lu (maxpacket = %lu)\n",
  435. ep->ep.name, ept_cfg, maxpacket);
  436. if ((desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
  437. ep->is_in = 1;
  438. ept_cfg |= USBA_EPT_DIR_IN;
  439. }
  440. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  441. case USB_ENDPOINT_XFER_CONTROL:
  442. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL);
  443. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE);
  444. break;
  445. case USB_ENDPOINT_XFER_ISOC:
  446. if (!ep->can_isoc) {
  447. DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n",
  448. ep->ep.name);
  449. return -EINVAL;
  450. }
  451. /*
  452. * Bits 11:12 specify number of _additional_
  453. * transactions per microframe.
  454. */
  455. nr_trans = ((le16_to_cpu(desc->wMaxPacketSize) >> 11) & 3) + 1;
  456. if (nr_trans > 3)
  457. return -EINVAL;
  458. ep->is_isoc = 1;
  459. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_ISO);
  460. /*
  461. * Do triple-buffering on high-bandwidth iso endpoints.
  462. */
  463. if (nr_trans > 1 && ep->nr_banks == 3)
  464. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_TRIPLE);
  465. else
  466. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  467. ept_cfg |= USBA_BF(NB_TRANS, nr_trans);
  468. break;
  469. case USB_ENDPOINT_XFER_BULK:
  470. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK);
  471. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  472. break;
  473. case USB_ENDPOINT_XFER_INT:
  474. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_INT);
  475. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  476. break;
  477. }
  478. spin_lock_irqsave(&ep->udc->lock, flags);
  479. if (ep->desc) {
  480. spin_unlock_irqrestore(&ep->udc->lock, flags);
  481. DBG(DBG_ERR, "ep%d already enabled\n", ep->index);
  482. return -EBUSY;
  483. }
  484. ep->desc = desc;
  485. ep->ep.maxpacket = maxpacket;
  486. usba_ep_writel(ep, CFG, ept_cfg);
  487. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  488. if (ep->can_dma) {
  489. u32 ctrl;
  490. usba_writel(udc, INT_ENB,
  491. (usba_readl(udc, INT_ENB)
  492. | USBA_BF(EPT_INT, 1 << ep->index)
  493. | USBA_BF(DMA_INT, 1 << ep->index)));
  494. ctrl = USBA_AUTO_VALID | USBA_INTDIS_DMA;
  495. usba_ep_writel(ep, CTL_ENB, ctrl);
  496. } else {
  497. usba_writel(udc, INT_ENB,
  498. (usba_readl(udc, INT_ENB)
  499. | USBA_BF(EPT_INT, 1 << ep->index)));
  500. }
  501. spin_unlock_irqrestore(&udc->lock, flags);
  502. DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index,
  503. (unsigned long)usba_ep_readl(ep, CFG));
  504. DBG(DBG_HW, "INT_ENB after init: %#08lx\n",
  505. (unsigned long)usba_readl(udc, INT_ENB));
  506. return 0;
  507. }
  508. static int usba_ep_disable(struct usb_ep *_ep)
  509. {
  510. struct usba_ep *ep = to_usba_ep(_ep);
  511. struct usba_udc *udc = ep->udc;
  512. LIST_HEAD(req_list);
  513. unsigned long flags;
  514. DBG(DBG_GADGET, "ep_disable: %s\n", ep->ep.name);
  515. spin_lock_irqsave(&udc->lock, flags);
  516. if (!ep->desc) {
  517. spin_unlock_irqrestore(&udc->lock, flags);
  518. DBG(DBG_ERR, "ep_disable: %s not enabled\n", ep->ep.name);
  519. return -EINVAL;
  520. }
  521. ep->desc = NULL;
  522. list_splice_init(&ep->queue, &req_list);
  523. if (ep->can_dma) {
  524. usba_dma_writel(ep, CONTROL, 0);
  525. usba_dma_writel(ep, ADDRESS, 0);
  526. usba_dma_readl(ep, STATUS);
  527. }
  528. usba_ep_writel(ep, CTL_DIS, USBA_EPT_ENABLE);
  529. usba_writel(udc, INT_ENB,
  530. usba_readl(udc, INT_ENB)
  531. & ~USBA_BF(EPT_INT, 1 << ep->index));
  532. request_complete_list(ep, &req_list, -ESHUTDOWN);
  533. spin_unlock_irqrestore(&udc->lock, flags);
  534. return 0;
  535. }
  536. static struct usb_request *
  537. usba_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
  538. {
  539. struct usba_request *req;
  540. DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags);
  541. req = kzalloc(sizeof(*req), gfp_flags);
  542. if (!req)
  543. return NULL;
  544. INIT_LIST_HEAD(&req->queue);
  545. req->req.dma = DMA_ADDR_INVALID;
  546. return &req->req;
  547. }
  548. static void
  549. usba_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
  550. {
  551. struct usba_request *req = to_usba_req(_req);
  552. DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req);
  553. kfree(req);
  554. }
  555. static int queue_dma(struct usba_udc *udc, struct usba_ep *ep,
  556. struct usba_request *req, gfp_t gfp_flags)
  557. {
  558. unsigned long flags;
  559. int ret;
  560. DBG(DBG_DMA, "%s: req l/%u d/%08x %c%c%c\n",
  561. ep->ep.name, req->req.length, req->req.dma,
  562. req->req.zero ? 'Z' : 'z',
  563. req->req.short_not_ok ? 'S' : 's',
  564. req->req.no_interrupt ? 'I' : 'i');
  565. if (req->req.length > 0x10000) {
  566. /* Lengths from 0 to 65536 (inclusive) are supported */
  567. DBG(DBG_ERR, "invalid request length %u\n", req->req.length);
  568. return -EINVAL;
  569. }
  570. req->using_dma = 1;
  571. if (req->req.dma == DMA_ADDR_INVALID) {
  572. req->req.dma = dma_map_single(
  573. &udc->pdev->dev, req->req.buf, req->req.length,
  574. ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  575. req->mapped = 1;
  576. } else {
  577. dma_sync_single_for_device(
  578. &udc->pdev->dev, req->req.dma, req->req.length,
  579. ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  580. req->mapped = 0;
  581. }
  582. req->ctrl = USBA_BF(DMA_BUF_LEN, req->req.length)
  583. | USBA_DMA_CH_EN | USBA_DMA_END_BUF_IE
  584. | USBA_DMA_END_TR_EN | USBA_DMA_END_TR_IE;
  585. if (ep->is_in)
  586. req->ctrl |= USBA_DMA_END_BUF_EN;
  587. /*
  588. * Add this request to the queue and submit for DMA if
  589. * possible. Check if we're still alive first -- we may have
  590. * received a reset since last time we checked.
  591. */
  592. ret = -ESHUTDOWN;
  593. spin_lock_irqsave(&udc->lock, flags);
  594. if (ep->desc) {
  595. if (list_empty(&ep->queue))
  596. submit_request(ep, req);
  597. list_add_tail(&req->queue, &ep->queue);
  598. ret = 0;
  599. }
  600. spin_unlock_irqrestore(&udc->lock, flags);
  601. return ret;
  602. }
  603. static int
  604. usba_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
  605. {
  606. struct usba_request *req = to_usba_req(_req);
  607. struct usba_ep *ep = to_usba_ep(_ep);
  608. struct usba_udc *udc = ep->udc;
  609. unsigned long flags;
  610. int ret;
  611. DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ, "%s: queue req %p, len %u\n",
  612. ep->ep.name, req, _req->length);
  613. if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN || !ep->desc)
  614. return -ESHUTDOWN;
  615. req->submitted = 0;
  616. req->using_dma = 0;
  617. req->last_transaction = 0;
  618. _req->status = -EINPROGRESS;
  619. _req->actual = 0;
  620. if (ep->can_dma)
  621. return queue_dma(udc, ep, req, gfp_flags);
  622. /* May have received a reset since last time we checked */
  623. ret = -ESHUTDOWN;
  624. spin_lock_irqsave(&udc->lock, flags);
  625. if (ep->desc) {
  626. list_add_tail(&req->queue, &ep->queue);
  627. if (ep->is_in || (ep_is_control(ep)
  628. && (ep->state == DATA_STAGE_IN
  629. || ep->state == STATUS_STAGE_IN)))
  630. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  631. else
  632. usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
  633. ret = 0;
  634. }
  635. spin_unlock_irqrestore(&udc->lock, flags);
  636. return ret;
  637. }
  638. static void
  639. usba_update_req(struct usba_ep *ep, struct usba_request *req, u32 status)
  640. {
  641. req->req.actual = req->req.length - USBA_BFEXT(DMA_BUF_LEN, status);
  642. }
  643. static int stop_dma(struct usba_ep *ep, u32 *pstatus)
  644. {
  645. unsigned int timeout;
  646. u32 status;
  647. /*
  648. * Stop the DMA controller. When writing both CH_EN
  649. * and LINK to 0, the other bits are not affected.
  650. */
  651. usba_dma_writel(ep, CONTROL, 0);
  652. /* Wait for the FIFO to empty */
  653. for (timeout = 40; timeout; --timeout) {
  654. status = usba_dma_readl(ep, STATUS);
  655. if (!(status & USBA_DMA_CH_EN))
  656. break;
  657. udelay(1);
  658. }
  659. if (pstatus)
  660. *pstatus = status;
  661. if (timeout == 0) {
  662. dev_err(&ep->udc->pdev->dev,
  663. "%s: timed out waiting for DMA FIFO to empty\n",
  664. ep->ep.name);
  665. return -ETIMEDOUT;
  666. }
  667. return 0;
  668. }
  669. static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  670. {
  671. struct usba_ep *ep = to_usba_ep(_ep);
  672. struct usba_udc *udc = ep->udc;
  673. struct usba_request *req = to_usba_req(_req);
  674. unsigned long flags;
  675. u32 status;
  676. DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n",
  677. ep->ep.name, req);
  678. spin_lock_irqsave(&udc->lock, flags);
  679. if (req->using_dma) {
  680. /*
  681. * If this request is currently being transferred,
  682. * stop the DMA controller and reset the FIFO.
  683. */
  684. if (ep->queue.next == &req->queue) {
  685. status = usba_dma_readl(ep, STATUS);
  686. if (status & USBA_DMA_CH_EN)
  687. stop_dma(ep, &status);
  688. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  689. ep->last_dma_status = status;
  690. #endif
  691. usba_writel(udc, EPT_RST, 1 << ep->index);
  692. usba_update_req(ep, req, status);
  693. }
  694. }
  695. /*
  696. * Errors should stop the queue from advancing until the
  697. * completion function returns.
  698. */
  699. list_del_init(&req->queue);
  700. request_complete(ep, req, -ECONNRESET);
  701. /* Process the next request if any */
  702. submit_next_request(ep);
  703. spin_unlock_irqrestore(&udc->lock, flags);
  704. return 0;
  705. }
  706. static int usba_ep_set_halt(struct usb_ep *_ep, int value)
  707. {
  708. struct usba_ep *ep = to_usba_ep(_ep);
  709. struct usba_udc *udc = ep->udc;
  710. unsigned long flags;
  711. int ret = 0;
  712. DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep->ep.name,
  713. value ? "set" : "clear");
  714. if (!ep->desc) {
  715. DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n",
  716. ep->ep.name);
  717. return -ENODEV;
  718. }
  719. if (ep->is_isoc) {
  720. DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n",
  721. ep->ep.name);
  722. return -ENOTTY;
  723. }
  724. spin_lock_irqsave(&udc->lock, flags);
  725. /*
  726. * We can't halt IN endpoints while there are still data to be
  727. * transferred
  728. */
  729. if (!list_empty(&ep->queue)
  730. || ((value && ep->is_in && (usba_ep_readl(ep, STA)
  731. & USBA_BF(BUSY_BANKS, -1L))))) {
  732. ret = -EAGAIN;
  733. } else {
  734. if (value)
  735. usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
  736. else
  737. usba_ep_writel(ep, CLR_STA,
  738. USBA_FORCE_STALL | USBA_TOGGLE_CLR);
  739. usba_ep_readl(ep, STA);
  740. }
  741. spin_unlock_irqrestore(&udc->lock, flags);
  742. return ret;
  743. }
  744. static int usba_ep_fifo_status(struct usb_ep *_ep)
  745. {
  746. struct usba_ep *ep = to_usba_ep(_ep);
  747. return USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
  748. }
  749. static void usba_ep_fifo_flush(struct usb_ep *_ep)
  750. {
  751. struct usba_ep *ep = to_usba_ep(_ep);
  752. struct usba_udc *udc = ep->udc;
  753. usba_writel(udc, EPT_RST, 1 << ep->index);
  754. }
  755. static const struct usb_ep_ops usba_ep_ops = {
  756. .enable = usba_ep_enable,
  757. .disable = usba_ep_disable,
  758. .alloc_request = usba_ep_alloc_request,
  759. .free_request = usba_ep_free_request,
  760. .queue = usba_ep_queue,
  761. .dequeue = usba_ep_dequeue,
  762. .set_halt = usba_ep_set_halt,
  763. .fifo_status = usba_ep_fifo_status,
  764. .fifo_flush = usba_ep_fifo_flush,
  765. };
  766. static int usba_udc_get_frame(struct usb_gadget *gadget)
  767. {
  768. struct usba_udc *udc = to_usba_udc(gadget);
  769. return USBA_BFEXT(FRAME_NUMBER, usba_readl(udc, FNUM));
  770. }
  771. static int usba_udc_wakeup(struct usb_gadget *gadget)
  772. {
  773. struct usba_udc *udc = to_usba_udc(gadget);
  774. unsigned long flags;
  775. u32 ctrl;
  776. int ret = -EINVAL;
  777. spin_lock_irqsave(&udc->lock, flags);
  778. if (udc->devstatus & (1 << USB_DEVICE_REMOTE_WAKEUP)) {
  779. ctrl = usba_readl(udc, CTRL);
  780. usba_writel(udc, CTRL, ctrl | USBA_REMOTE_WAKE_UP);
  781. ret = 0;
  782. }
  783. spin_unlock_irqrestore(&udc->lock, flags);
  784. return ret;
  785. }
  786. static int
  787. usba_udc_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
  788. {
  789. struct usba_udc *udc = to_usba_udc(gadget);
  790. unsigned long flags;
  791. spin_lock_irqsave(&udc->lock, flags);
  792. if (is_selfpowered)
  793. udc->devstatus |= 1 << USB_DEVICE_SELF_POWERED;
  794. else
  795. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  796. spin_unlock_irqrestore(&udc->lock, flags);
  797. return 0;
  798. }
  799. static const struct usb_gadget_ops usba_udc_ops = {
  800. .get_frame = usba_udc_get_frame,
  801. .wakeup = usba_udc_wakeup,
  802. .set_selfpowered = usba_udc_set_selfpowered,
  803. };
  804. static struct usb_endpoint_descriptor usba_ep0_desc = {
  805. .bLength = USB_DT_ENDPOINT_SIZE,
  806. .bDescriptorType = USB_DT_ENDPOINT,
  807. .bEndpointAddress = 0,
  808. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  809. .wMaxPacketSize = __constant_cpu_to_le16(64),
  810. /* FIXME: I have no idea what to put here */
  811. .bInterval = 1,
  812. };
  813. static void nop_release(struct device *dev)
  814. {
  815. }
  816. static struct usba_udc the_udc = {
  817. .gadget = {
  818. .ops = &usba_udc_ops,
  819. .ep_list = LIST_HEAD_INIT(the_udc.gadget.ep_list),
  820. .is_dualspeed = 1,
  821. .name = "atmel_usba_udc",
  822. .dev = {
  823. .bus_id = "gadget",
  824. .release = nop_release,
  825. },
  826. },
  827. .lock = SPIN_LOCK_UNLOCKED,
  828. };
  829. /*
  830. * Called with interrupts disabled and udc->lock held.
  831. */
  832. static void reset_all_endpoints(struct usba_udc *udc)
  833. {
  834. struct usba_ep *ep;
  835. struct usba_request *req, *tmp_req;
  836. usba_writel(udc, EPT_RST, ~0UL);
  837. ep = to_usba_ep(udc->gadget.ep0);
  838. list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) {
  839. list_del_init(&req->queue);
  840. request_complete(ep, req, -ECONNRESET);
  841. }
  842. list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
  843. if (ep->desc) {
  844. spin_unlock(&udc->lock);
  845. usba_ep_disable(&ep->ep);
  846. spin_lock(&udc->lock);
  847. }
  848. }
  849. }
  850. static struct usba_ep *get_ep_by_addr(struct usba_udc *udc, u16 wIndex)
  851. {
  852. struct usba_ep *ep;
  853. if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
  854. return to_usba_ep(udc->gadget.ep0);
  855. list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
  856. u8 bEndpointAddress;
  857. if (!ep->desc)
  858. continue;
  859. bEndpointAddress = ep->desc->bEndpointAddress;
  860. if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
  861. continue;
  862. if ((bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)
  863. == (wIndex & USB_ENDPOINT_NUMBER_MASK))
  864. return ep;
  865. }
  866. return NULL;
  867. }
  868. /* Called with interrupts disabled and udc->lock held */
  869. static inline void set_protocol_stall(struct usba_udc *udc, struct usba_ep *ep)
  870. {
  871. usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
  872. ep->state = WAIT_FOR_SETUP;
  873. }
  874. static inline int is_stalled(struct usba_udc *udc, struct usba_ep *ep)
  875. {
  876. if (usba_ep_readl(ep, STA) & USBA_FORCE_STALL)
  877. return 1;
  878. return 0;
  879. }
  880. static inline void set_address(struct usba_udc *udc, unsigned int addr)
  881. {
  882. u32 regval;
  883. DBG(DBG_BUS, "setting address %u...\n", addr);
  884. regval = usba_readl(udc, CTRL);
  885. regval = USBA_BFINS(DEV_ADDR, addr, regval);
  886. usba_writel(udc, CTRL, regval);
  887. }
  888. static int do_test_mode(struct usba_udc *udc)
  889. {
  890. static const char test_packet_buffer[] = {
  891. /* JKJKJKJK * 9 */
  892. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  893. /* JJKKJJKK * 8 */
  894. 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
  895. /* JJKKJJKK * 8 */
  896. 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
  897. /* JJJJJJJKKKKKKK * 8 */
  898. 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  899. 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  900. /* JJJJJJJK * 8 */
  901. 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD,
  902. /* {JKKKKKKK * 10}, JK */
  903. 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E
  904. };
  905. struct usba_ep *ep;
  906. struct device *dev = &udc->pdev->dev;
  907. int test_mode;
  908. test_mode = udc->test_mode;
  909. /* Start from a clean slate */
  910. reset_all_endpoints(udc);
  911. switch (test_mode) {
  912. case 0x0100:
  913. /* Test_J */
  914. usba_writel(udc, TST, USBA_TST_J_MODE);
  915. dev_info(dev, "Entering Test_J mode...\n");
  916. break;
  917. case 0x0200:
  918. /* Test_K */
  919. usba_writel(udc, TST, USBA_TST_K_MODE);
  920. dev_info(dev, "Entering Test_K mode...\n");
  921. break;
  922. case 0x0300:
  923. /*
  924. * Test_SE0_NAK: Force high-speed mode and set up ep0
  925. * for Bulk IN transfers
  926. */
  927. ep = &usba_ep[0];
  928. usba_writel(udc, TST,
  929. USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH));
  930. usba_ep_writel(ep, CFG,
  931. USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
  932. | USBA_EPT_DIR_IN
  933. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
  934. | USBA_BF(BK_NUMBER, 1));
  935. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
  936. set_protocol_stall(udc, ep);
  937. dev_err(dev, "Test_SE0_NAK: ep0 not mapped\n");
  938. } else {
  939. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  940. dev_info(dev, "Entering Test_SE0_NAK mode...\n");
  941. }
  942. break;
  943. case 0x0400:
  944. /* Test_Packet */
  945. ep = &usba_ep[0];
  946. usba_ep_writel(ep, CFG,
  947. USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
  948. | USBA_EPT_DIR_IN
  949. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
  950. | USBA_BF(BK_NUMBER, 1));
  951. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
  952. set_protocol_stall(udc, ep);
  953. dev_err(dev, "Test_Packet: ep0 not mapped\n");
  954. } else {
  955. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  956. usba_writel(udc, TST, USBA_TST_PKT_MODE);
  957. memcpy_toio(ep->fifo, test_packet_buffer,
  958. sizeof(test_packet_buffer));
  959. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  960. dev_info(dev, "Entering Test_Packet mode...\n");
  961. }
  962. break;
  963. default:
  964. dev_err(dev, "Invalid test mode: 0x%04x\n", test_mode);
  965. return -EINVAL;
  966. }
  967. return 0;
  968. }
  969. /* Avoid overly long expressions */
  970. static inline bool feature_is_dev_remote_wakeup(struct usb_ctrlrequest *crq)
  971. {
  972. if (crq->wValue == __constant_cpu_to_le16(USB_DEVICE_REMOTE_WAKEUP))
  973. return true;
  974. return false;
  975. }
  976. static inline bool feature_is_dev_test_mode(struct usb_ctrlrequest *crq)
  977. {
  978. if (crq->wValue == __constant_cpu_to_le16(USB_DEVICE_TEST_MODE))
  979. return true;
  980. return false;
  981. }
  982. static inline bool feature_is_ep_halt(struct usb_ctrlrequest *crq)
  983. {
  984. if (crq->wValue == __constant_cpu_to_le16(USB_ENDPOINT_HALT))
  985. return true;
  986. return false;
  987. }
  988. static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep,
  989. struct usb_ctrlrequest *crq)
  990. {
  991. int retval = 0;;
  992. switch (crq->bRequest) {
  993. case USB_REQ_GET_STATUS: {
  994. u16 status;
  995. if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) {
  996. status = cpu_to_le16(udc->devstatus);
  997. } else if (crq->bRequestType
  998. == (USB_DIR_IN | USB_RECIP_INTERFACE)) {
  999. status = __constant_cpu_to_le16(0);
  1000. } else if (crq->bRequestType
  1001. == (USB_DIR_IN | USB_RECIP_ENDPOINT)) {
  1002. struct usba_ep *target;
  1003. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1004. if (!target)
  1005. goto stall;
  1006. status = 0;
  1007. if (is_stalled(udc, target))
  1008. status |= __constant_cpu_to_le16(1);
  1009. } else
  1010. goto delegate;
  1011. /* Write directly to the FIFO. No queueing is done. */
  1012. if (crq->wLength != __constant_cpu_to_le16(sizeof(status)))
  1013. goto stall;
  1014. ep->state = DATA_STAGE_IN;
  1015. __raw_writew(status, ep->fifo);
  1016. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  1017. break;
  1018. }
  1019. case USB_REQ_CLEAR_FEATURE: {
  1020. if (crq->bRequestType == USB_RECIP_DEVICE) {
  1021. if (feature_is_dev_remote_wakeup(crq))
  1022. udc->devstatus
  1023. &= ~(1 << USB_DEVICE_REMOTE_WAKEUP);
  1024. else
  1025. /* Can't CLEAR_FEATURE TEST_MODE */
  1026. goto stall;
  1027. } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
  1028. struct usba_ep *target;
  1029. if (crq->wLength != __constant_cpu_to_le16(0)
  1030. || !feature_is_ep_halt(crq))
  1031. goto stall;
  1032. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1033. if (!target)
  1034. goto stall;
  1035. usba_ep_writel(target, CLR_STA, USBA_FORCE_STALL);
  1036. if (target->index != 0)
  1037. usba_ep_writel(target, CLR_STA,
  1038. USBA_TOGGLE_CLR);
  1039. } else {
  1040. goto delegate;
  1041. }
  1042. send_status(udc, ep);
  1043. break;
  1044. }
  1045. case USB_REQ_SET_FEATURE: {
  1046. if (crq->bRequestType == USB_RECIP_DEVICE) {
  1047. if (feature_is_dev_test_mode(crq)) {
  1048. send_status(udc, ep);
  1049. ep->state = STATUS_STAGE_TEST;
  1050. udc->test_mode = le16_to_cpu(crq->wIndex);
  1051. return 0;
  1052. } else if (feature_is_dev_remote_wakeup(crq)) {
  1053. udc->devstatus |= 1 << USB_DEVICE_REMOTE_WAKEUP;
  1054. } else {
  1055. goto stall;
  1056. }
  1057. } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
  1058. struct usba_ep *target;
  1059. if (crq->wLength != __constant_cpu_to_le16(0)
  1060. || !feature_is_ep_halt(crq))
  1061. goto stall;
  1062. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1063. if (!target)
  1064. goto stall;
  1065. usba_ep_writel(target, SET_STA, USBA_FORCE_STALL);
  1066. } else
  1067. goto delegate;
  1068. send_status(udc, ep);
  1069. break;
  1070. }
  1071. case USB_REQ_SET_ADDRESS:
  1072. if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
  1073. goto delegate;
  1074. set_address(udc, le16_to_cpu(crq->wValue));
  1075. send_status(udc, ep);
  1076. ep->state = STATUS_STAGE_ADDR;
  1077. break;
  1078. default:
  1079. delegate:
  1080. spin_unlock(&udc->lock);
  1081. retval = udc->driver->setup(&udc->gadget, crq);
  1082. spin_lock(&udc->lock);
  1083. }
  1084. return retval;
  1085. stall:
  1086. pr_err("udc: %s: Invalid setup request: %02x.%02x v%04x i%04x l%d, "
  1087. "halting endpoint...\n",
  1088. ep->ep.name, crq->bRequestType, crq->bRequest,
  1089. le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex),
  1090. le16_to_cpu(crq->wLength));
  1091. set_protocol_stall(udc, ep);
  1092. return -1;
  1093. }
  1094. static void usba_control_irq(struct usba_udc *udc, struct usba_ep *ep)
  1095. {
  1096. struct usba_request *req;
  1097. u32 epstatus;
  1098. u32 epctrl;
  1099. restart:
  1100. epstatus = usba_ep_readl(ep, STA);
  1101. epctrl = usba_ep_readl(ep, CTL);
  1102. DBG(DBG_INT, "%s [%d]: s/%08x c/%08x\n",
  1103. ep->ep.name, ep->state, epstatus, epctrl);
  1104. req = NULL;
  1105. if (!list_empty(&ep->queue))
  1106. req = list_entry(ep->queue.next,
  1107. struct usba_request, queue);
  1108. if ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
  1109. if (req->submitted)
  1110. next_fifo_transaction(ep, req);
  1111. else
  1112. submit_request(ep, req);
  1113. if (req->last_transaction) {
  1114. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  1115. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  1116. }
  1117. goto restart;
  1118. }
  1119. if ((epstatus & epctrl) & USBA_TX_COMPLETE) {
  1120. usba_ep_writel(ep, CLR_STA, USBA_TX_COMPLETE);
  1121. switch (ep->state) {
  1122. case DATA_STAGE_IN:
  1123. usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
  1124. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1125. ep->state = STATUS_STAGE_OUT;
  1126. break;
  1127. case STATUS_STAGE_ADDR:
  1128. /* Activate our new address */
  1129. usba_writel(udc, CTRL, (usba_readl(udc, CTRL)
  1130. | USBA_FADDR_EN));
  1131. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1132. ep->state = WAIT_FOR_SETUP;
  1133. break;
  1134. case STATUS_STAGE_IN:
  1135. if (req) {
  1136. list_del_init(&req->queue);
  1137. request_complete(ep, req, 0);
  1138. submit_next_request(ep);
  1139. }
  1140. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1141. ep->state = WAIT_FOR_SETUP;
  1142. break;
  1143. case STATUS_STAGE_TEST:
  1144. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1145. ep->state = WAIT_FOR_SETUP;
  1146. if (do_test_mode(udc))
  1147. set_protocol_stall(udc, ep);
  1148. break;
  1149. default:
  1150. pr_err("udc: %s: TXCOMP: Invalid endpoint state %d, "
  1151. "halting endpoint...\n",
  1152. ep->ep.name, ep->state);
  1153. set_protocol_stall(udc, ep);
  1154. break;
  1155. }
  1156. goto restart;
  1157. }
  1158. if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
  1159. switch (ep->state) {
  1160. case STATUS_STAGE_OUT:
  1161. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1162. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1163. if (req) {
  1164. list_del_init(&req->queue);
  1165. request_complete(ep, req, 0);
  1166. }
  1167. ep->state = WAIT_FOR_SETUP;
  1168. break;
  1169. case DATA_STAGE_OUT:
  1170. receive_data(ep);
  1171. break;
  1172. default:
  1173. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1174. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1175. pr_err("udc: %s: RXRDY: Invalid endpoint state %d, "
  1176. "halting endpoint...\n",
  1177. ep->ep.name, ep->state);
  1178. set_protocol_stall(udc, ep);
  1179. break;
  1180. }
  1181. goto restart;
  1182. }
  1183. if (epstatus & USBA_RX_SETUP) {
  1184. union {
  1185. struct usb_ctrlrequest crq;
  1186. unsigned long data[2];
  1187. } crq;
  1188. unsigned int pkt_len;
  1189. int ret;
  1190. if (ep->state != WAIT_FOR_SETUP) {
  1191. /*
  1192. * Didn't expect a SETUP packet at this
  1193. * point. Clean up any pending requests (which
  1194. * may be successful).
  1195. */
  1196. int status = -EPROTO;
  1197. /*
  1198. * RXRDY and TXCOMP are dropped when SETUP
  1199. * packets arrive. Just pretend we received
  1200. * the status packet.
  1201. */
  1202. if (ep->state == STATUS_STAGE_OUT
  1203. || ep->state == STATUS_STAGE_IN) {
  1204. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1205. status = 0;
  1206. }
  1207. if (req) {
  1208. list_del_init(&req->queue);
  1209. request_complete(ep, req, status);
  1210. }
  1211. }
  1212. pkt_len = USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
  1213. DBG(DBG_HW, "Packet length: %u\n", pkt_len);
  1214. if (pkt_len != sizeof(crq)) {
  1215. pr_warning("udc: Invalid packet length %u "
  1216. "(expected %lu)\n", pkt_len, sizeof(crq));
  1217. set_protocol_stall(udc, ep);
  1218. return;
  1219. }
  1220. DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
  1221. memcpy_fromio(crq.data, ep->fifo, sizeof(crq));
  1222. /* Free up one bank in the FIFO so that we can
  1223. * generate or receive a reply right away. */
  1224. usba_ep_writel(ep, CLR_STA, USBA_RX_SETUP);
  1225. /* printk(KERN_DEBUG "setup: %d: %02x.%02x\n",
  1226. ep->state, crq.crq.bRequestType,
  1227. crq.crq.bRequest); */
  1228. if (crq.crq.bRequestType & USB_DIR_IN) {
  1229. /*
  1230. * The USB 2.0 spec states that "if wLength is
  1231. * zero, there is no data transfer phase."
  1232. * However, testusb #14 seems to actually
  1233. * expect a data phase even if wLength = 0...
  1234. */
  1235. ep->state = DATA_STAGE_IN;
  1236. } else {
  1237. if (crq.crq.wLength != __constant_cpu_to_le16(0))
  1238. ep->state = DATA_STAGE_OUT;
  1239. else
  1240. ep->state = STATUS_STAGE_IN;
  1241. }
  1242. ret = -1;
  1243. if (ep->index == 0)
  1244. ret = handle_ep0_setup(udc, ep, &crq.crq);
  1245. else {
  1246. spin_unlock(&udc->lock);
  1247. ret = udc->driver->setup(&udc->gadget, &crq.crq);
  1248. spin_lock(&udc->lock);
  1249. }
  1250. DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n",
  1251. crq.crq.bRequestType, crq.crq.bRequest,
  1252. le16_to_cpu(crq.crq.wLength), ep->state, ret);
  1253. if (ret < 0) {
  1254. /* Let the host know that we failed */
  1255. set_protocol_stall(udc, ep);
  1256. }
  1257. }
  1258. }
  1259. static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep)
  1260. {
  1261. struct usba_request *req;
  1262. u32 epstatus;
  1263. u32 epctrl;
  1264. epstatus = usba_ep_readl(ep, STA);
  1265. epctrl = usba_ep_readl(ep, CTL);
  1266. DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n", ep->ep.name, epstatus);
  1267. while ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
  1268. DBG(DBG_BUS, "%s: TX PK ready\n", ep->ep.name);
  1269. if (list_empty(&ep->queue)) {
  1270. dev_warn(&udc->pdev->dev, "ep_irq: queue empty\n");
  1271. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  1272. return;
  1273. }
  1274. req = list_entry(ep->queue.next, struct usba_request, queue);
  1275. if (req->using_dma) {
  1276. /* Send a zero-length packet */
  1277. usba_ep_writel(ep, SET_STA,
  1278. USBA_TX_PK_RDY);
  1279. usba_ep_writel(ep, CTL_DIS,
  1280. USBA_TX_PK_RDY);
  1281. list_del_init(&req->queue);
  1282. submit_next_request(ep);
  1283. request_complete(ep, req, 0);
  1284. } else {
  1285. if (req->submitted)
  1286. next_fifo_transaction(ep, req);
  1287. else
  1288. submit_request(ep, req);
  1289. if (req->last_transaction) {
  1290. list_del_init(&req->queue);
  1291. submit_next_request(ep);
  1292. request_complete(ep, req, 0);
  1293. }
  1294. }
  1295. epstatus = usba_ep_readl(ep, STA);
  1296. epctrl = usba_ep_readl(ep, CTL);
  1297. }
  1298. if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
  1299. DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name);
  1300. receive_data(ep);
  1301. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1302. }
  1303. }
  1304. static void usba_dma_irq(struct usba_udc *udc, struct usba_ep *ep)
  1305. {
  1306. struct usba_request *req;
  1307. u32 status, control, pending;
  1308. status = usba_dma_readl(ep, STATUS);
  1309. control = usba_dma_readl(ep, CONTROL);
  1310. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  1311. ep->last_dma_status = status;
  1312. #endif
  1313. pending = status & control;
  1314. DBG(DBG_INT | DBG_DMA, "dma irq, s/%#08x, c/%#08x\n", status, control);
  1315. if (status & USBA_DMA_CH_EN) {
  1316. dev_err(&udc->pdev->dev,
  1317. "DMA_CH_EN is set after transfer is finished!\n");
  1318. dev_err(&udc->pdev->dev,
  1319. "status=%#08x, pending=%#08x, control=%#08x\n",
  1320. status, pending, control);
  1321. /*
  1322. * try to pretend nothing happened. We might have to
  1323. * do something here...
  1324. */
  1325. }
  1326. if (list_empty(&ep->queue))
  1327. /* Might happen if a reset comes along at the right moment */
  1328. return;
  1329. if (pending & (USBA_DMA_END_TR_ST | USBA_DMA_END_BUF_ST)) {
  1330. req = list_entry(ep->queue.next, struct usba_request, queue);
  1331. usba_update_req(ep, req, status);
  1332. list_del_init(&req->queue);
  1333. submit_next_request(ep);
  1334. request_complete(ep, req, 0);
  1335. }
  1336. }
  1337. static irqreturn_t usba_udc_irq(int irq, void *devid)
  1338. {
  1339. struct usba_udc *udc = devid;
  1340. u32 status;
  1341. u32 dma_status;
  1342. u32 ep_status;
  1343. spin_lock(&udc->lock);
  1344. status = usba_readl(udc, INT_STA);
  1345. DBG(DBG_INT, "irq, status=%#08x\n", status);
  1346. if (status & USBA_DET_SUSPEND) {
  1347. usba_writel(udc, INT_CLR, USBA_DET_SUSPEND);
  1348. DBG(DBG_BUS, "Suspend detected\n");
  1349. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1350. && udc->driver && udc->driver->suspend) {
  1351. spin_unlock(&udc->lock);
  1352. udc->driver->suspend(&udc->gadget);
  1353. spin_lock(&udc->lock);
  1354. }
  1355. }
  1356. if (status & USBA_WAKE_UP) {
  1357. usba_writel(udc, INT_CLR, USBA_WAKE_UP);
  1358. DBG(DBG_BUS, "Wake Up CPU detected\n");
  1359. }
  1360. if (status & USBA_END_OF_RESUME) {
  1361. usba_writel(udc, INT_CLR, USBA_END_OF_RESUME);
  1362. DBG(DBG_BUS, "Resume detected\n");
  1363. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1364. && udc->driver && udc->driver->resume) {
  1365. spin_unlock(&udc->lock);
  1366. udc->driver->resume(&udc->gadget);
  1367. spin_lock(&udc->lock);
  1368. }
  1369. }
  1370. dma_status = USBA_BFEXT(DMA_INT, status);
  1371. if (dma_status) {
  1372. int i;
  1373. for (i = 1; i < USBA_NR_ENDPOINTS; i++)
  1374. if (dma_status & (1 << i))
  1375. usba_dma_irq(udc, &usba_ep[i]);
  1376. }
  1377. ep_status = USBA_BFEXT(EPT_INT, status);
  1378. if (ep_status) {
  1379. int i;
  1380. for (i = 0; i < USBA_NR_ENDPOINTS; i++)
  1381. if (ep_status & (1 << i)) {
  1382. if (ep_is_control(&usba_ep[i]))
  1383. usba_control_irq(udc, &usba_ep[i]);
  1384. else
  1385. usba_ep_irq(udc, &usba_ep[i]);
  1386. }
  1387. }
  1388. if (status & USBA_END_OF_RESET) {
  1389. struct usba_ep *ep0;
  1390. usba_writel(udc, INT_CLR, USBA_END_OF_RESET);
  1391. reset_all_endpoints(udc);
  1392. if (status & USBA_HIGH_SPEED) {
  1393. DBG(DBG_BUS, "High-speed bus reset detected\n");
  1394. udc->gadget.speed = USB_SPEED_HIGH;
  1395. } else {
  1396. DBG(DBG_BUS, "Full-speed bus reset detected\n");
  1397. udc->gadget.speed = USB_SPEED_FULL;
  1398. }
  1399. ep0 = &usba_ep[0];
  1400. ep0->desc = &usba_ep0_desc;
  1401. ep0->state = WAIT_FOR_SETUP;
  1402. usba_ep_writel(ep0, CFG,
  1403. (USBA_BF(EPT_SIZE, EP0_EPT_SIZE)
  1404. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL)
  1405. | USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE)));
  1406. usba_ep_writel(ep0, CTL_ENB,
  1407. USBA_EPT_ENABLE | USBA_RX_SETUP);
  1408. usba_writel(udc, INT_ENB,
  1409. (usba_readl(udc, INT_ENB)
  1410. | USBA_BF(EPT_INT, 1)
  1411. | USBA_DET_SUSPEND
  1412. | USBA_END_OF_RESUME));
  1413. if (!(usba_ep_readl(ep0, CFG) & USBA_EPT_MAPPED))
  1414. dev_warn(&udc->pdev->dev,
  1415. "WARNING: EP0 configuration is invalid!\n");
  1416. }
  1417. spin_unlock(&udc->lock);
  1418. return IRQ_HANDLED;
  1419. }
  1420. static irqreturn_t usba_vbus_irq(int irq, void *devid)
  1421. {
  1422. struct usba_udc *udc = devid;
  1423. int vbus;
  1424. /* debounce */
  1425. udelay(10);
  1426. spin_lock(&udc->lock);
  1427. /* May happen if Vbus pin toggles during probe() */
  1428. if (!udc->driver)
  1429. goto out;
  1430. vbus = gpio_get_value(udc->vbus_pin);
  1431. if (vbus != udc->vbus_prev) {
  1432. if (vbus) {
  1433. usba_writel(udc, CTRL, USBA_EN_USBA);
  1434. usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
  1435. } else {
  1436. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1437. reset_all_endpoints(udc);
  1438. usba_writel(udc, CTRL, 0);
  1439. spin_unlock(&udc->lock);
  1440. udc->driver->disconnect(&udc->gadget);
  1441. spin_lock(&udc->lock);
  1442. }
  1443. udc->vbus_prev = vbus;
  1444. }
  1445. out:
  1446. spin_unlock(&udc->lock);
  1447. return IRQ_HANDLED;
  1448. }
  1449. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  1450. {
  1451. struct usba_udc *udc = &the_udc;
  1452. unsigned long flags;
  1453. int ret;
  1454. if (!udc->pdev)
  1455. return -ENODEV;
  1456. spin_lock_irqsave(&udc->lock, flags);
  1457. if (udc->driver) {
  1458. spin_unlock_irqrestore(&udc->lock, flags);
  1459. return -EBUSY;
  1460. }
  1461. udc->devstatus = 1 << USB_DEVICE_SELF_POWERED;
  1462. udc->driver = driver;
  1463. udc->gadget.dev.driver = &driver->driver;
  1464. spin_unlock_irqrestore(&udc->lock, flags);
  1465. clk_enable(udc->pclk);
  1466. clk_enable(udc->hclk);
  1467. ret = driver->bind(&udc->gadget);
  1468. if (ret) {
  1469. DBG(DBG_ERR, "Could not bind to driver %s: error %d\n",
  1470. driver->driver.name, ret);
  1471. goto err_driver_bind;
  1472. }
  1473. DBG(DBG_GADGET, "registered driver `%s'\n", driver->driver.name);
  1474. udc->vbus_prev = 0;
  1475. if (udc->vbus_pin != -1)
  1476. enable_irq(gpio_to_irq(udc->vbus_pin));
  1477. /* If Vbus is present, enable the controller and wait for reset */
  1478. spin_lock_irqsave(&udc->lock, flags);
  1479. if (vbus_is_present(udc) && udc->vbus_prev == 0) {
  1480. usba_writel(udc, CTRL, USBA_EN_USBA);
  1481. usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
  1482. }
  1483. spin_unlock_irqrestore(&udc->lock, flags);
  1484. return 0;
  1485. err_driver_bind:
  1486. udc->driver = NULL;
  1487. udc->gadget.dev.driver = NULL;
  1488. return ret;
  1489. }
  1490. EXPORT_SYMBOL(usb_gadget_register_driver);
  1491. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1492. {
  1493. struct usba_udc *udc = &the_udc;
  1494. unsigned long flags;
  1495. if (!udc->pdev)
  1496. return -ENODEV;
  1497. if (driver != udc->driver)
  1498. return -EINVAL;
  1499. if (udc->vbus_pin != -1)
  1500. disable_irq(gpio_to_irq(udc->vbus_pin));
  1501. spin_lock_irqsave(&udc->lock, flags);
  1502. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1503. reset_all_endpoints(udc);
  1504. spin_unlock_irqrestore(&udc->lock, flags);
  1505. /* This will also disable the DP pullup */
  1506. usba_writel(udc, CTRL, 0);
  1507. driver->unbind(&udc->gadget);
  1508. udc->gadget.dev.driver = NULL;
  1509. udc->driver = NULL;
  1510. clk_disable(udc->hclk);
  1511. clk_disable(udc->pclk);
  1512. DBG(DBG_GADGET, "unregistered driver `%s'\n", driver->driver.name);
  1513. return 0;
  1514. }
  1515. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1516. static int __init usba_udc_probe(struct platform_device *pdev)
  1517. {
  1518. struct usba_platform_data *pdata = pdev->dev.platform_data;
  1519. struct resource *regs, *fifo;
  1520. struct clk *pclk, *hclk;
  1521. struct usba_udc *udc = &the_udc;
  1522. int irq, ret, i;
  1523. regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
  1524. fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
  1525. if (!regs || !fifo || !pdata)
  1526. return -ENXIO;
  1527. irq = platform_get_irq(pdev, 0);
  1528. if (irq < 0)
  1529. return irq;
  1530. pclk = clk_get(&pdev->dev, "pclk");
  1531. if (IS_ERR(pclk))
  1532. return PTR_ERR(pclk);
  1533. hclk = clk_get(&pdev->dev, "hclk");
  1534. if (IS_ERR(hclk)) {
  1535. ret = PTR_ERR(hclk);
  1536. goto err_get_hclk;
  1537. }
  1538. udc->pdev = pdev;
  1539. udc->pclk = pclk;
  1540. udc->hclk = hclk;
  1541. udc->vbus_pin = -1;
  1542. ret = -ENOMEM;
  1543. udc->regs = ioremap(regs->start, regs->end - regs->start + 1);
  1544. if (!udc->regs) {
  1545. dev_err(&pdev->dev, "Unable to map I/O memory, aborting.\n");
  1546. goto err_map_regs;
  1547. }
  1548. dev_info(&pdev->dev, "MMIO registers at 0x%08lx mapped at %p\n",
  1549. (unsigned long)regs->start, udc->regs);
  1550. udc->fifo = ioremap(fifo->start, fifo->end - fifo->start + 1);
  1551. if (!udc->fifo) {
  1552. dev_err(&pdev->dev, "Unable to map FIFO, aborting.\n");
  1553. goto err_map_fifo;
  1554. }
  1555. dev_info(&pdev->dev, "FIFO at 0x%08lx mapped at %p\n",
  1556. (unsigned long)fifo->start, udc->fifo);
  1557. device_initialize(&udc->gadget.dev);
  1558. udc->gadget.dev.parent = &pdev->dev;
  1559. udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1560. platform_set_drvdata(pdev, udc);
  1561. /* Make sure we start from a clean slate */
  1562. clk_enable(pclk);
  1563. usba_writel(udc, CTRL, 0);
  1564. clk_disable(pclk);
  1565. usba_ep = kmalloc(sizeof(struct usba_ep) * pdata->num_ep,
  1566. GFP_KERNEL);
  1567. if (!usba_ep)
  1568. goto err_alloc_ep;
  1569. the_udc.gadget.ep0 = &usba_ep[0].ep;
  1570. INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
  1571. usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
  1572. usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
  1573. usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
  1574. usba_ep[0].ep.ops = &usba_ep_ops;
  1575. usba_ep[0].ep.name = pdata->ep[0].name;
  1576. usba_ep[0].ep.maxpacket = pdata->ep[0].fifo_size;
  1577. usba_ep[0].udc = &the_udc;
  1578. INIT_LIST_HEAD(&usba_ep[0].queue);
  1579. usba_ep[0].fifo_size = pdata->ep[0].fifo_size;
  1580. usba_ep[0].nr_banks = pdata->ep[0].nr_banks;
  1581. usba_ep[0].index = pdata->ep[0].index;
  1582. usba_ep[0].can_dma = pdata->ep[0].can_dma;
  1583. usba_ep[0].can_isoc = pdata->ep[0].can_isoc;
  1584. for (i = 1; i < pdata->num_ep; i++) {
  1585. struct usba_ep *ep = &usba_ep[i];
  1586. ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
  1587. ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
  1588. ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
  1589. ep->ep.ops = &usba_ep_ops;
  1590. ep->ep.name = pdata->ep[i].name;
  1591. ep->ep.maxpacket = pdata->ep[i].fifo_size;
  1592. ep->udc = &the_udc;
  1593. INIT_LIST_HEAD(&ep->queue);
  1594. ep->fifo_size = pdata->ep[i].fifo_size;
  1595. ep->nr_banks = pdata->ep[i].nr_banks;
  1596. ep->index = pdata->ep[i].index;
  1597. ep->can_dma = pdata->ep[i].can_dma;
  1598. ep->can_isoc = pdata->ep[i].can_isoc;
  1599. list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
  1600. }
  1601. ret = request_irq(irq, usba_udc_irq, 0, "atmel_usba_udc", udc);
  1602. if (ret) {
  1603. dev_err(&pdev->dev, "Cannot request irq %d (error %d)\n",
  1604. irq, ret);
  1605. goto err_request_irq;
  1606. }
  1607. udc->irq = irq;
  1608. ret = device_add(&udc->gadget.dev);
  1609. if (ret) {
  1610. dev_dbg(&pdev->dev, "Could not add gadget: %d\n", ret);
  1611. goto err_device_add;
  1612. }
  1613. if (pdata->vbus_pin >= 0) {
  1614. if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) {
  1615. udc->vbus_pin = pdata->vbus_pin;
  1616. ret = request_irq(gpio_to_irq(udc->vbus_pin),
  1617. usba_vbus_irq, 0,
  1618. "atmel_usba_udc", udc);
  1619. if (ret) {
  1620. gpio_free(udc->vbus_pin);
  1621. udc->vbus_pin = -1;
  1622. dev_warn(&udc->pdev->dev,
  1623. "failed to request vbus irq; "
  1624. "assuming always on\n");
  1625. } else {
  1626. disable_irq(gpio_to_irq(udc->vbus_pin));
  1627. }
  1628. }
  1629. }
  1630. usba_init_debugfs(udc);
  1631. for (i = 1; i < pdata->num_ep; i++)
  1632. usba_ep_init_debugfs(udc, &usba_ep[i]);
  1633. return 0;
  1634. err_device_add:
  1635. free_irq(irq, udc);
  1636. err_request_irq:
  1637. kfree(usba_ep);
  1638. err_alloc_ep:
  1639. iounmap(udc->fifo);
  1640. err_map_fifo:
  1641. iounmap(udc->regs);
  1642. err_map_regs:
  1643. clk_put(hclk);
  1644. err_get_hclk:
  1645. clk_put(pclk);
  1646. platform_set_drvdata(pdev, NULL);
  1647. return ret;
  1648. }
  1649. static int __exit usba_udc_remove(struct platform_device *pdev)
  1650. {
  1651. struct usba_udc *udc;
  1652. int i;
  1653. struct usba_platform_data *pdata = pdev->dev.platform_data;
  1654. udc = platform_get_drvdata(pdev);
  1655. for (i = 1; i < pdata->num_ep; i++)
  1656. usba_ep_cleanup_debugfs(&usba_ep[i]);
  1657. usba_cleanup_debugfs(udc);
  1658. if (udc->vbus_pin != -1)
  1659. gpio_free(udc->vbus_pin);
  1660. free_irq(udc->irq, udc);
  1661. kfree(usba_ep);
  1662. iounmap(udc->fifo);
  1663. iounmap(udc->regs);
  1664. clk_put(udc->hclk);
  1665. clk_put(udc->pclk);
  1666. device_unregister(&udc->gadget.dev);
  1667. return 0;
  1668. }
  1669. static struct platform_driver udc_driver = {
  1670. .remove = __exit_p(usba_udc_remove),
  1671. .driver = {
  1672. .name = "atmel_usba_udc",
  1673. },
  1674. };
  1675. static int __init udc_init(void)
  1676. {
  1677. return platform_driver_probe(&udc_driver, usba_udc_probe);
  1678. }
  1679. module_init(udc_init);
  1680. static void __exit udc_exit(void)
  1681. {
  1682. platform_driver_unregister(&udc_driver);
  1683. }
  1684. module_exit(udc_exit);
  1685. MODULE_DESCRIPTION("Atmel USBA UDC driver");
  1686. MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
  1687. MODULE_LICENSE("GPL");