88pm800.c 15 KB

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  1. /*
  2. * Base driver for Marvell 88PM800
  3. *
  4. * Copyright (C) 2012 Marvell International Ltd.
  5. * Haojian Zhuang <haojian.zhuang@marvell.com>
  6. * Joseph(Yossi) Hanin <yhanin@marvell.com>
  7. * Qiao Zhou <zhouqiao@marvell.com>
  8. *
  9. * This file is subject to the terms and conditions of the GNU General
  10. * Public License. See the file "COPYING" in the main directory of this
  11. * archive for more details.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <linux/kernel.h>
  23. #include <linux/module.h>
  24. #include <linux/err.h>
  25. #include <linux/i2c.h>
  26. #include <linux/mfd/core.h>
  27. #include <linux/mfd/88pm80x.h>
  28. #include <linux/slab.h>
  29. #define PM800_CHIP_ID (0x00)
  30. /* Interrupt Registers */
  31. #define PM800_INT_STATUS1 (0x05)
  32. #define PM800_ONKEY_INT_STS1 (1 << 0)
  33. #define PM800_EXTON_INT_STS1 (1 << 1)
  34. #define PM800_CHG_INT_STS1 (1 << 2)
  35. #define PM800_BAT_INT_STS1 (1 << 3)
  36. #define PM800_RTC_INT_STS1 (1 << 4)
  37. #define PM800_CLASSD_OC_INT_STS1 (1 << 5)
  38. #define PM800_INT_STATUS2 (0x06)
  39. #define PM800_VBAT_INT_STS2 (1 << 0)
  40. #define PM800_VSYS_INT_STS2 (1 << 1)
  41. #define PM800_VCHG_INT_STS2 (1 << 2)
  42. #define PM800_TINT_INT_STS2 (1 << 3)
  43. #define PM800_GPADC0_INT_STS2 (1 << 4)
  44. #define PM800_TBAT_INT_STS2 (1 << 5)
  45. #define PM800_GPADC2_INT_STS2 (1 << 6)
  46. #define PM800_GPADC3_INT_STS2 (1 << 7)
  47. #define PM800_INT_STATUS3 (0x07)
  48. #define PM800_INT_STATUS4 (0x08)
  49. #define PM800_GPIO0_INT_STS4 (1 << 0)
  50. #define PM800_GPIO1_INT_STS4 (1 << 1)
  51. #define PM800_GPIO2_INT_STS4 (1 << 2)
  52. #define PM800_GPIO3_INT_STS4 (1 << 3)
  53. #define PM800_GPIO4_INT_STS4 (1 << 4)
  54. #define PM800_INT_ENA_1 (0x09)
  55. #define PM800_ONKEY_INT_ENA1 (1 << 0)
  56. #define PM800_EXTON_INT_ENA1 (1 << 1)
  57. #define PM800_CHG_INT_ENA1 (1 << 2)
  58. #define PM800_BAT_INT_ENA1 (1 << 3)
  59. #define PM800_RTC_INT_ENA1 (1 << 4)
  60. #define PM800_CLASSD_OC_INT_ENA1 (1 << 5)
  61. #define PM800_INT_ENA_2 (0x0A)
  62. #define PM800_VBAT_INT_ENA2 (1 << 0)
  63. #define PM800_VSYS_INT_ENA2 (1 << 1)
  64. #define PM800_VCHG_INT_ENA2 (1 << 2)
  65. #define PM800_TINT_INT_ENA2 (1 << 3)
  66. #define PM800_INT_ENA_3 (0x0B)
  67. #define PM800_GPADC0_INT_ENA3 (1 << 0)
  68. #define PM800_GPADC1_INT_ENA3 (1 << 1)
  69. #define PM800_GPADC2_INT_ENA3 (1 << 2)
  70. #define PM800_GPADC3_INT_ENA3 (1 << 3)
  71. #define PM800_GPADC4_INT_ENA3 (1 << 4)
  72. #define PM800_INT_ENA_4 (0x0C)
  73. #define PM800_GPIO0_INT_ENA4 (1 << 0)
  74. #define PM800_GPIO1_INT_ENA4 (1 << 1)
  75. #define PM800_GPIO2_INT_ENA4 (1 << 2)
  76. #define PM800_GPIO3_INT_ENA4 (1 << 3)
  77. #define PM800_GPIO4_INT_ENA4 (1 << 4)
  78. /* number of INT_ENA & INT_STATUS regs */
  79. #define PM800_INT_REG_NUM (4)
  80. /* Interrupt Number in 88PM800 */
  81. enum {
  82. PM800_IRQ_ONKEY, /*EN1b0 *//*0 */
  83. PM800_IRQ_EXTON, /*EN1b1 */
  84. PM800_IRQ_CHG, /*EN1b2 */
  85. PM800_IRQ_BAT, /*EN1b3 */
  86. PM800_IRQ_RTC, /*EN1b4 */
  87. PM800_IRQ_CLASSD, /*EN1b5 *//*5 */
  88. PM800_IRQ_VBAT, /*EN2b0 */
  89. PM800_IRQ_VSYS, /*EN2b1 */
  90. PM800_IRQ_VCHG, /*EN2b2 */
  91. PM800_IRQ_TINT, /*EN2b3 */
  92. PM800_IRQ_GPADC0, /*EN3b0 *//*10 */
  93. PM800_IRQ_GPADC1, /*EN3b1 */
  94. PM800_IRQ_GPADC2, /*EN3b2 */
  95. PM800_IRQ_GPADC3, /*EN3b3 */
  96. PM800_IRQ_GPADC4, /*EN3b4 */
  97. PM800_IRQ_GPIO0, /*EN4b0 *//*15 */
  98. PM800_IRQ_GPIO1, /*EN4b1 */
  99. PM800_IRQ_GPIO2, /*EN4b2 */
  100. PM800_IRQ_GPIO3, /*EN4b3 */
  101. PM800_IRQ_GPIO4, /*EN4b4 *//*19 */
  102. PM800_MAX_IRQ,
  103. };
  104. enum {
  105. /* Procida */
  106. PM800_CHIP_A0 = 0x60,
  107. PM800_CHIP_A1 = 0x61,
  108. PM800_CHIP_B0 = 0x62,
  109. PM800_CHIP_C0 = 0x63,
  110. PM800_CHIP_END = PM800_CHIP_C0,
  111. /* Make sure to update this to the last stepping */
  112. PM8XXX_CHIP_END = PM800_CHIP_END
  113. };
  114. static const struct i2c_device_id pm80x_id_table[] = {
  115. {"88PM800", CHIP_PM800},
  116. {} /* NULL terminated */
  117. };
  118. MODULE_DEVICE_TABLE(i2c, pm80x_id_table);
  119. static struct resource rtc_resources[] = {
  120. {
  121. .name = "88pm80x-rtc",
  122. .start = PM800_IRQ_RTC,
  123. .end = PM800_IRQ_RTC,
  124. .flags = IORESOURCE_IRQ,
  125. },
  126. };
  127. static struct mfd_cell rtc_devs[] = {
  128. {
  129. .name = "88pm80x-rtc",
  130. .num_resources = ARRAY_SIZE(rtc_resources),
  131. .resources = &rtc_resources[0],
  132. .id = -1,
  133. },
  134. };
  135. static struct resource onkey_resources[] = {
  136. {
  137. .name = "88pm80x-onkey",
  138. .start = PM800_IRQ_ONKEY,
  139. .end = PM800_IRQ_ONKEY,
  140. .flags = IORESOURCE_IRQ,
  141. },
  142. };
  143. static struct mfd_cell onkey_devs[] = {
  144. {
  145. .name = "88pm80x-onkey",
  146. .num_resources = 1,
  147. .resources = &onkey_resources[0],
  148. .id = -1,
  149. },
  150. };
  151. static const struct regmap_irq pm800_irqs[] = {
  152. /* INT0 */
  153. [PM800_IRQ_ONKEY] = {
  154. .mask = PM800_ONKEY_INT_ENA1,
  155. },
  156. [PM800_IRQ_EXTON] = {
  157. .mask = PM800_EXTON_INT_ENA1,
  158. },
  159. [PM800_IRQ_CHG] = {
  160. .mask = PM800_CHG_INT_ENA1,
  161. },
  162. [PM800_IRQ_BAT] = {
  163. .mask = PM800_BAT_INT_ENA1,
  164. },
  165. [PM800_IRQ_RTC] = {
  166. .mask = PM800_RTC_INT_ENA1,
  167. },
  168. [PM800_IRQ_CLASSD] = {
  169. .mask = PM800_CLASSD_OC_INT_ENA1,
  170. },
  171. /* INT1 */
  172. [PM800_IRQ_VBAT] = {
  173. .reg_offset = 1,
  174. .mask = PM800_VBAT_INT_ENA2,
  175. },
  176. [PM800_IRQ_VSYS] = {
  177. .reg_offset = 1,
  178. .mask = PM800_VSYS_INT_ENA2,
  179. },
  180. [PM800_IRQ_VCHG] = {
  181. .reg_offset = 1,
  182. .mask = PM800_VCHG_INT_ENA2,
  183. },
  184. [PM800_IRQ_TINT] = {
  185. .reg_offset = 1,
  186. .mask = PM800_TINT_INT_ENA2,
  187. },
  188. /* INT2 */
  189. [PM800_IRQ_GPADC0] = {
  190. .reg_offset = 2,
  191. .mask = PM800_GPADC0_INT_ENA3,
  192. },
  193. [PM800_IRQ_GPADC1] = {
  194. .reg_offset = 2,
  195. .mask = PM800_GPADC1_INT_ENA3,
  196. },
  197. [PM800_IRQ_GPADC2] = {
  198. .reg_offset = 2,
  199. .mask = PM800_GPADC2_INT_ENA3,
  200. },
  201. [PM800_IRQ_GPADC3] = {
  202. .reg_offset = 2,
  203. .mask = PM800_GPADC3_INT_ENA3,
  204. },
  205. [PM800_IRQ_GPADC4] = {
  206. .reg_offset = 2,
  207. .mask = PM800_GPADC4_INT_ENA3,
  208. },
  209. /* INT3 */
  210. [PM800_IRQ_GPIO0] = {
  211. .reg_offset = 3,
  212. .mask = PM800_GPIO0_INT_ENA4,
  213. },
  214. [PM800_IRQ_GPIO1] = {
  215. .reg_offset = 3,
  216. .mask = PM800_GPIO1_INT_ENA4,
  217. },
  218. [PM800_IRQ_GPIO2] = {
  219. .reg_offset = 3,
  220. .mask = PM800_GPIO2_INT_ENA4,
  221. },
  222. [PM800_IRQ_GPIO3] = {
  223. .reg_offset = 3,
  224. .mask = PM800_GPIO3_INT_ENA4,
  225. },
  226. [PM800_IRQ_GPIO4] = {
  227. .reg_offset = 3,
  228. .mask = PM800_GPIO4_INT_ENA4,
  229. },
  230. };
  231. static int device_gpadc_init(struct pm80x_chip *chip,
  232. struct pm80x_platform_data *pdata)
  233. {
  234. struct pm80x_subchip *subchip = chip->subchip;
  235. struct regmap *map = subchip->regmap_gpadc;
  236. int data = 0, mask = 0, ret = 0;
  237. if (!map) {
  238. dev_warn(chip->dev,
  239. "Warning: gpadc regmap is not available!\n");
  240. return -EINVAL;
  241. }
  242. /*
  243. * initialize GPADC without activating it turn on GPADC
  244. * measurments
  245. */
  246. ret = regmap_update_bits(map,
  247. PM800_GPADC_MISC_CONFIG2,
  248. PM800_GPADC_MISC_GPFSM_EN,
  249. PM800_GPADC_MISC_GPFSM_EN);
  250. if (ret < 0)
  251. goto out;
  252. /*
  253. * This function configures the ADC as requires for
  254. * CP implementation.CP does not "own" the ADC configuration
  255. * registers and relies on AP.
  256. * Reason: enable automatic ADC measurements needed
  257. * for CP to get VBAT and RF temperature readings.
  258. */
  259. ret = regmap_update_bits(map, PM800_GPADC_MEAS_EN1,
  260. PM800_MEAS_EN1_VBAT, PM800_MEAS_EN1_VBAT);
  261. if (ret < 0)
  262. goto out;
  263. ret = regmap_update_bits(map, PM800_GPADC_MEAS_EN2,
  264. (PM800_MEAS_EN2_RFTMP | PM800_MEAS_GP0_EN),
  265. (PM800_MEAS_EN2_RFTMP | PM800_MEAS_GP0_EN));
  266. if (ret < 0)
  267. goto out;
  268. /*
  269. * the defult of PM800 is GPADC operates at 100Ks/s rate
  270. * and Number of GPADC slots with active current bias prior
  271. * to GPADC sampling = 1 slot for all GPADCs set for
  272. * Temprature mesurmants
  273. */
  274. mask = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN1 |
  275. PM800_GPADC_GP_BIAS_EN2 | PM800_GPADC_GP_BIAS_EN3);
  276. if (pdata && (pdata->batt_det == 0))
  277. data = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN1 |
  278. PM800_GPADC_GP_BIAS_EN2 | PM800_GPADC_GP_BIAS_EN3);
  279. else
  280. data = (PM800_GPADC_GP_BIAS_EN0 | PM800_GPADC_GP_BIAS_EN2 |
  281. PM800_GPADC_GP_BIAS_EN3);
  282. ret = regmap_update_bits(map, PM800_GP_BIAS_ENA1, mask, data);
  283. if (ret < 0)
  284. goto out;
  285. dev_info(chip->dev, "pm800 device_gpadc_init: Done\n");
  286. return 0;
  287. out:
  288. dev_info(chip->dev, "pm800 device_gpadc_init: Failed!\n");
  289. return ret;
  290. }
  291. static int device_irq_init_800(struct pm80x_chip *chip)
  292. {
  293. struct regmap *map = chip->regmap;
  294. unsigned long flags = IRQF_ONESHOT;
  295. int data, mask, ret = -EINVAL;
  296. if (!map || !chip->irq) {
  297. dev_err(chip->dev, "incorrect parameters\n");
  298. return -EINVAL;
  299. }
  300. /*
  301. * irq_mode defines the way of clearing interrupt. it's read-clear by
  302. * default.
  303. */
  304. mask =
  305. PM800_WAKEUP2_INV_INT | PM800_WAKEUP2_INT_CLEAR |
  306. PM800_WAKEUP2_INT_MASK;
  307. data = PM800_WAKEUP2_INT_CLEAR;
  308. ret = regmap_update_bits(map, PM800_WAKEUP2, mask, data);
  309. if (ret < 0)
  310. goto out;
  311. ret =
  312. regmap_add_irq_chip(chip->regmap, chip->irq, flags, -1,
  313. chip->regmap_irq_chip, &chip->irq_data);
  314. out:
  315. return ret;
  316. }
  317. static void device_irq_exit_800(struct pm80x_chip *chip)
  318. {
  319. regmap_del_irq_chip(chip->irq, chip->irq_data);
  320. }
  321. static struct regmap_irq_chip pm800_irq_chip = {
  322. .name = "88pm800",
  323. .irqs = pm800_irqs,
  324. .num_irqs = ARRAY_SIZE(pm800_irqs),
  325. .num_regs = 4,
  326. .status_base = PM800_INT_STATUS1,
  327. .mask_base = PM800_INT_ENA_1,
  328. .ack_base = PM800_INT_STATUS1,
  329. .mask_invert = 1,
  330. };
  331. static int pm800_pages_init(struct pm80x_chip *chip)
  332. {
  333. struct pm80x_subchip *subchip;
  334. struct i2c_client *client = chip->client;
  335. int ret = 0;
  336. subchip = chip->subchip;
  337. if (!subchip || !subchip->power_page_addr || !subchip->gpadc_page_addr)
  338. return -ENODEV;
  339. /* PM800 block power page */
  340. subchip->power_page = i2c_new_dummy(client->adapter,
  341. subchip->power_page_addr);
  342. if (subchip->power_page == NULL) {
  343. ret = -ENODEV;
  344. goto out;
  345. }
  346. subchip->regmap_power = devm_regmap_init_i2c(subchip->power_page,
  347. &pm80x_regmap_config);
  348. if (IS_ERR(subchip->regmap_power)) {
  349. ret = PTR_ERR(subchip->regmap_power);
  350. dev_err(chip->dev,
  351. "Failed to allocate regmap_power: %d\n", ret);
  352. goto out;
  353. }
  354. i2c_set_clientdata(subchip->power_page, chip);
  355. /* PM800 block GPADC */
  356. subchip->gpadc_page = i2c_new_dummy(client->adapter,
  357. subchip->gpadc_page_addr);
  358. if (subchip->gpadc_page == NULL) {
  359. ret = -ENODEV;
  360. goto out;
  361. }
  362. subchip->regmap_gpadc = devm_regmap_init_i2c(subchip->gpadc_page,
  363. &pm80x_regmap_config);
  364. if (IS_ERR(subchip->regmap_gpadc)) {
  365. ret = PTR_ERR(subchip->regmap_gpadc);
  366. dev_err(chip->dev,
  367. "Failed to allocate regmap_gpadc: %d\n", ret);
  368. goto out;
  369. }
  370. i2c_set_clientdata(subchip->gpadc_page, chip);
  371. out:
  372. return ret;
  373. }
  374. static void pm800_pages_exit(struct pm80x_chip *chip)
  375. {
  376. struct pm80x_subchip *subchip;
  377. subchip = chip->subchip;
  378. if (subchip && subchip->power_page)
  379. i2c_unregister_device(subchip->power_page);
  380. if (subchip && subchip->gpadc_page)
  381. i2c_unregister_device(subchip->gpadc_page);
  382. }
  383. static int device_800_init(struct pm80x_chip *chip,
  384. struct pm80x_platform_data *pdata)
  385. {
  386. int ret, pmic_id;
  387. unsigned int val;
  388. ret = regmap_read(chip->regmap, PM800_CHIP_ID, &val);
  389. if (ret < 0) {
  390. dev_err(chip->dev, "Failed to read CHIP ID: %d\n", ret);
  391. goto out;
  392. }
  393. pmic_id = val & PM80X_VERSION_MASK;
  394. if ((pmic_id >= PM800_CHIP_A0) && (pmic_id <= PM800_CHIP_END)) {
  395. chip->version = val;
  396. dev_info(chip->dev,
  397. "88PM80x:Marvell 88PM800 (ID:0x%x) detected\n", val);
  398. } else {
  399. dev_err(chip->dev,
  400. "Failed to detect Marvell 88PM800:ChipID[0x%x]\n", val);
  401. ret = -EINVAL;
  402. goto out;
  403. }
  404. /*
  405. * alarm wake up bit will be clear in device_irq_init(),
  406. * read before that
  407. */
  408. ret = regmap_read(chip->regmap, PM800_RTC_CONTROL, &val);
  409. if (ret < 0) {
  410. dev_err(chip->dev, "Failed to read RTC register: %d\n", ret);
  411. goto out;
  412. }
  413. if (val & PM800_ALARM_WAKEUP) {
  414. if (pdata && pdata->rtc)
  415. pdata->rtc->rtc_wakeup = 1;
  416. }
  417. ret = device_gpadc_init(chip, pdata);
  418. if (ret < 0) {
  419. dev_err(chip->dev, "[%s]Failed to init gpadc\n", __func__);
  420. goto out;
  421. }
  422. chip->regmap_irq_chip = &pm800_irq_chip;
  423. ret = device_irq_init_800(chip);
  424. if (ret < 0) {
  425. dev_err(chip->dev, "[%s]Failed to init pm800 irq\n", __func__);
  426. goto out;
  427. }
  428. ret =
  429. mfd_add_devices(chip->dev, 0, &onkey_devs[0],
  430. ARRAY_SIZE(onkey_devs), &onkey_resources[0], 0,
  431. NULL);
  432. if (ret < 0) {
  433. dev_err(chip->dev, "Failed to add onkey subdev\n");
  434. goto out_dev;
  435. } else
  436. dev_info(chip->dev, "[%s]:Added mfd onkey_devs\n", __func__);
  437. if (pdata && pdata->rtc) {
  438. rtc_devs[0].platform_data = pdata->rtc;
  439. rtc_devs[0].pdata_size = sizeof(struct pm80x_rtc_pdata);
  440. ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0],
  441. ARRAY_SIZE(rtc_devs), NULL, 0, NULL);
  442. if (ret < 0) {
  443. dev_err(chip->dev, "Failed to add rtc subdev\n");
  444. goto out_dev;
  445. } else
  446. dev_info(chip->dev,
  447. "[%s]:Added mfd rtc_devs\n", __func__);
  448. }
  449. return 0;
  450. out_dev:
  451. mfd_remove_devices(chip->dev);
  452. device_irq_exit_800(chip);
  453. out:
  454. return ret;
  455. }
  456. static int pm800_probe(struct i2c_client *client,
  457. const struct i2c_device_id *id)
  458. {
  459. int ret = 0;
  460. struct pm80x_chip *chip;
  461. struct pm80x_platform_data *pdata = client->dev.platform_data;
  462. struct pm80x_subchip *subchip;
  463. ret = pm80x_init(client, id);
  464. if (ret) {
  465. dev_err(&client->dev, "pm800_init fail\n");
  466. goto out_init;
  467. }
  468. chip = i2c_get_clientdata(client);
  469. /* init subchip for PM800 */
  470. subchip =
  471. devm_kzalloc(&client->dev, sizeof(struct pm80x_subchip),
  472. GFP_KERNEL);
  473. if (!subchip) {
  474. ret = -ENOMEM;
  475. goto err_subchip_alloc;
  476. }
  477. /* pm800 has 2 addtional pages to support power and gpadc. */
  478. subchip->power_page_addr = client->addr + 1;
  479. subchip->gpadc_page_addr = client->addr + 2;
  480. chip->subchip = subchip;
  481. ret = pm800_pages_init(chip);
  482. if (ret) {
  483. dev_err(&client->dev, "pm800_pages_init failed!\n");
  484. goto err_page_init;
  485. }
  486. ret = device_800_init(chip, pdata);
  487. if (ret) {
  488. dev_err(chip->dev, "%s id 0x%x failed!\n", __func__, chip->id);
  489. goto err_device_init;
  490. }
  491. if (pdata->plat_config)
  492. pdata->plat_config(chip, pdata);
  493. return 0;
  494. err_device_init:
  495. pm800_pages_exit(chip);
  496. err_page_init:
  497. err_subchip_alloc:
  498. pm80x_deinit();
  499. out_init:
  500. return ret;
  501. }
  502. static int pm800_remove(struct i2c_client *client)
  503. {
  504. struct pm80x_chip *chip = i2c_get_clientdata(client);
  505. mfd_remove_devices(chip->dev);
  506. device_irq_exit_800(chip);
  507. pm800_pages_exit(chip);
  508. pm80x_deinit();
  509. return 0;
  510. }
  511. static struct i2c_driver pm800_driver = {
  512. .driver = {
  513. .name = "88PM800",
  514. .owner = THIS_MODULE,
  515. .pm = &pm80x_pm_ops,
  516. },
  517. .probe = pm800_probe,
  518. .remove = pm800_remove,
  519. .id_table = pm80x_id_table,
  520. };
  521. static int __init pm800_i2c_init(void)
  522. {
  523. return i2c_add_driver(&pm800_driver);
  524. }
  525. subsys_initcall(pm800_i2c_init);
  526. static void __exit pm800_i2c_exit(void)
  527. {
  528. i2c_del_driver(&pm800_driver);
  529. }
  530. module_exit(pm800_i2c_exit);
  531. MODULE_DESCRIPTION("PMIC Driver for Marvell 88PM800");
  532. MODULE_AUTHOR("Qiao Zhou <zhouqiao@marvell.com>");
  533. MODULE_LICENSE("GPL");