iwl-core.c 89 KB

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  1. /******************************************************************************
  2. *
  3. * GPL LICENSE SUMMARY
  4. *
  5. * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of version 2 of the GNU General Public License as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19. * USA
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.GPL.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *****************************************************************************/
  28. #include <linux/kernel.h>
  29. #include <linux/module.h>
  30. #include <linux/etherdevice.h>
  31. #include <net/mac80211.h>
  32. #include "iwl-eeprom.h"
  33. #include "iwl-dev.h" /* FIXME: remove */
  34. #include "iwl-debug.h"
  35. #include "iwl-core.h"
  36. #include "iwl-io.h"
  37. #include "iwl-power.h"
  38. #include "iwl-sta.h"
  39. #include "iwl-helpers.h"
  40. MODULE_DESCRIPTION("iwl core");
  41. MODULE_VERSION(IWLWIFI_VERSION);
  42. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  43. MODULE_LICENSE("GPL");
  44. #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
  45. [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
  46. IWL_RATE_SISO_##s##M_PLCP, \
  47. IWL_RATE_MIMO2_##s##M_PLCP,\
  48. IWL_RATE_MIMO3_##s##M_PLCP,\
  49. IWL_RATE_##r##M_IEEE, \
  50. IWL_RATE_##ip##M_INDEX, \
  51. IWL_RATE_##in##M_INDEX, \
  52. IWL_RATE_##rp##M_INDEX, \
  53. IWL_RATE_##rn##M_INDEX, \
  54. IWL_RATE_##pp##M_INDEX, \
  55. IWL_RATE_##np##M_INDEX }
  56. u32 iwl_debug_level;
  57. EXPORT_SYMBOL(iwl_debug_level);
  58. static irqreturn_t iwl_isr(int irq, void *data);
  59. /*
  60. * Parameter order:
  61. * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
  62. *
  63. * If there isn't a valid next or previous rate then INV is used which
  64. * maps to IWL_RATE_INVALID
  65. *
  66. */
  67. const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
  68. IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
  69. IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
  70. IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
  71. IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
  72. IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
  73. IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
  74. IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
  75. IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
  76. IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
  77. IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
  78. IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
  79. IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  80. IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
  81. /* FIXME:RS: ^^ should be INV (legacy) */
  82. };
  83. EXPORT_SYMBOL(iwl_rates);
  84. /**
  85. * translate ucode response to mac80211 tx status control values
  86. */
  87. void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
  88. struct ieee80211_tx_info *info)
  89. {
  90. struct ieee80211_tx_rate *r = &info->control.rates[0];
  91. info->antenna_sel_tx =
  92. ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
  93. if (rate_n_flags & RATE_MCS_HT_MSK)
  94. r->flags |= IEEE80211_TX_RC_MCS;
  95. if (rate_n_flags & RATE_MCS_GF_MSK)
  96. r->flags |= IEEE80211_TX_RC_GREEN_FIELD;
  97. if (rate_n_flags & RATE_MCS_HT40_MSK)
  98. r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
  99. if (rate_n_flags & RATE_MCS_DUP_MSK)
  100. r->flags |= IEEE80211_TX_RC_DUP_DATA;
  101. if (rate_n_flags & RATE_MCS_SGI_MSK)
  102. r->flags |= IEEE80211_TX_RC_SHORT_GI;
  103. r->idx = iwl_hwrate_to_mac80211_idx(rate_n_flags, info->band);
  104. }
  105. EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
  106. int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
  107. {
  108. int idx = 0;
  109. /* HT rate format */
  110. if (rate_n_flags & RATE_MCS_HT_MSK) {
  111. idx = (rate_n_flags & 0xff);
  112. if (idx >= IWL_RATE_MIMO3_6M_PLCP)
  113. idx = idx - IWL_RATE_MIMO3_6M_PLCP;
  114. else if (idx >= IWL_RATE_MIMO2_6M_PLCP)
  115. idx = idx - IWL_RATE_MIMO2_6M_PLCP;
  116. idx += IWL_FIRST_OFDM_RATE;
  117. /* skip 9M not supported in ht*/
  118. if (idx >= IWL_RATE_9M_INDEX)
  119. idx += 1;
  120. if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
  121. return idx;
  122. /* legacy rate format, search for match in table */
  123. } else {
  124. for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
  125. if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
  126. return idx;
  127. }
  128. return -1;
  129. }
  130. EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
  131. int iwl_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
  132. {
  133. int idx = 0;
  134. int band_offset = 0;
  135. /* HT rate format: mac80211 wants an MCS number, which is just LSB */
  136. if (rate_n_flags & RATE_MCS_HT_MSK) {
  137. idx = (rate_n_flags & 0xff);
  138. return idx;
  139. /* Legacy rate format, search for match in table */
  140. } else {
  141. if (band == IEEE80211_BAND_5GHZ)
  142. band_offset = IWL_FIRST_OFDM_RATE;
  143. for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
  144. if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
  145. return idx - band_offset;
  146. }
  147. return -1;
  148. }
  149. u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant)
  150. {
  151. int i;
  152. u8 ind = ant;
  153. for (i = 0; i < RATE_ANT_NUM - 1; i++) {
  154. ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
  155. if (priv->hw_params.valid_tx_ant & BIT(ind))
  156. return ind;
  157. }
  158. return ant;
  159. }
  160. const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  161. EXPORT_SYMBOL(iwl_bcast_addr);
  162. /* This function both allocates and initializes hw and priv. */
  163. struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
  164. struct ieee80211_ops *hw_ops)
  165. {
  166. struct iwl_priv *priv;
  167. /* mac80211 allocates memory for this device instance, including
  168. * space for this driver's private structure */
  169. struct ieee80211_hw *hw =
  170. ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
  171. if (hw == NULL) {
  172. printk(KERN_ERR "%s: Can not allocate network device\n",
  173. cfg->name);
  174. goto out;
  175. }
  176. priv = hw->priv;
  177. priv->hw = hw;
  178. out:
  179. return hw;
  180. }
  181. EXPORT_SYMBOL(iwl_alloc_all);
  182. void iwl_hw_detect(struct iwl_priv *priv)
  183. {
  184. priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
  185. priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
  186. pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
  187. }
  188. EXPORT_SYMBOL(iwl_hw_detect);
  189. int iwl_hw_nic_init(struct iwl_priv *priv)
  190. {
  191. unsigned long flags;
  192. struct iwl_rx_queue *rxq = &priv->rxq;
  193. int ret;
  194. /* nic_init */
  195. spin_lock_irqsave(&priv->lock, flags);
  196. priv->cfg->ops->lib->apm_ops.init(priv);
  197. iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
  198. spin_unlock_irqrestore(&priv->lock, flags);
  199. ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
  200. priv->cfg->ops->lib->apm_ops.config(priv);
  201. /* Allocate the RX queue, or reset if it is already allocated */
  202. if (!rxq->bd) {
  203. ret = iwl_rx_queue_alloc(priv);
  204. if (ret) {
  205. IWL_ERR(priv, "Unable to initialize Rx queue\n");
  206. return -ENOMEM;
  207. }
  208. } else
  209. iwl_rx_queue_reset(priv, rxq);
  210. iwl_rx_replenish(priv);
  211. iwl_rx_init(priv, rxq);
  212. spin_lock_irqsave(&priv->lock, flags);
  213. rxq->need_update = 1;
  214. iwl_rx_queue_update_write_ptr(priv, rxq);
  215. spin_unlock_irqrestore(&priv->lock, flags);
  216. /* Allocate and init all Tx and Command queues */
  217. ret = iwl_txq_ctx_reset(priv);
  218. if (ret)
  219. return ret;
  220. set_bit(STATUS_INIT, &priv->status);
  221. return 0;
  222. }
  223. EXPORT_SYMBOL(iwl_hw_nic_init);
  224. /*
  225. * QoS support
  226. */
  227. void iwl_activate_qos(struct iwl_priv *priv, u8 force)
  228. {
  229. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  230. return;
  231. priv->qos_data.def_qos_parm.qos_flags = 0;
  232. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  233. !priv->qos_data.qos_cap.q_AP.txop_request)
  234. priv->qos_data.def_qos_parm.qos_flags |=
  235. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  236. if (priv->qos_data.qos_active)
  237. priv->qos_data.def_qos_parm.qos_flags |=
  238. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  239. if (priv->current_ht_config.is_ht)
  240. priv->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
  241. if (force || iwl_is_associated(priv)) {
  242. IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
  243. priv->qos_data.qos_active,
  244. priv->qos_data.def_qos_parm.qos_flags);
  245. iwl_send_cmd_pdu_async(priv, REPLY_QOS_PARAM,
  246. sizeof(struct iwl_qosparam_cmd),
  247. &priv->qos_data.def_qos_parm, NULL);
  248. }
  249. }
  250. EXPORT_SYMBOL(iwl_activate_qos);
  251. /*
  252. * AC CWmin CW max AIFSN TXOP Limit TXOP Limit
  253. * (802.11b) (802.11a/g)
  254. * AC_BK 15 1023 7 0 0
  255. * AC_BE 15 1023 3 0 0
  256. * AC_VI 7 15 2 6.016ms 3.008ms
  257. * AC_VO 3 7 2 3.264ms 1.504ms
  258. */
  259. void iwl_reset_qos(struct iwl_priv *priv)
  260. {
  261. u16 cw_min = 15;
  262. u16 cw_max = 1023;
  263. u8 aifs = 2;
  264. bool is_legacy = false;
  265. unsigned long flags;
  266. int i;
  267. spin_lock_irqsave(&priv->lock, flags);
  268. /* QoS always active in AP and ADHOC mode
  269. * In STA mode wait for association
  270. */
  271. if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
  272. priv->iw_mode == NL80211_IFTYPE_AP)
  273. priv->qos_data.qos_active = 1;
  274. else
  275. priv->qos_data.qos_active = 0;
  276. /* check for legacy mode */
  277. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  278. (priv->active_rate & IWL_OFDM_RATES_MASK) == 0) ||
  279. (priv->iw_mode == NL80211_IFTYPE_STATION &&
  280. (priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK) == 0)) {
  281. cw_min = 31;
  282. is_legacy = 1;
  283. }
  284. if (priv->qos_data.qos_active)
  285. aifs = 3;
  286. /* AC_BE */
  287. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  288. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  289. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  290. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  291. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  292. if (priv->qos_data.qos_active) {
  293. /* AC_BK */
  294. i = 1;
  295. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  296. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  297. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  298. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  299. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  300. /* AC_VI */
  301. i = 2;
  302. priv->qos_data.def_qos_parm.ac[i].cw_min =
  303. cpu_to_le16((cw_min + 1) / 2 - 1);
  304. priv->qos_data.def_qos_parm.ac[i].cw_max =
  305. cpu_to_le16(cw_min);
  306. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  307. if (is_legacy)
  308. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  309. cpu_to_le16(6016);
  310. else
  311. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  312. cpu_to_le16(3008);
  313. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  314. /* AC_VO */
  315. i = 3;
  316. priv->qos_data.def_qos_parm.ac[i].cw_min =
  317. cpu_to_le16((cw_min + 1) / 4 - 1);
  318. priv->qos_data.def_qos_parm.ac[i].cw_max =
  319. cpu_to_le16((cw_min + 1) / 2 - 1);
  320. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  321. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  322. if (is_legacy)
  323. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  324. cpu_to_le16(3264);
  325. else
  326. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  327. cpu_to_le16(1504);
  328. } else {
  329. for (i = 1; i < 4; i++) {
  330. priv->qos_data.def_qos_parm.ac[i].cw_min =
  331. cpu_to_le16(cw_min);
  332. priv->qos_data.def_qos_parm.ac[i].cw_max =
  333. cpu_to_le16(cw_max);
  334. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  335. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  336. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  337. }
  338. }
  339. IWL_DEBUG_QOS(priv, "set QoS to default \n");
  340. spin_unlock_irqrestore(&priv->lock, flags);
  341. }
  342. EXPORT_SYMBOL(iwl_reset_qos);
  343. #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
  344. #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
  345. static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
  346. struct ieee80211_sta_ht_cap *ht_info,
  347. enum ieee80211_band band)
  348. {
  349. u16 max_bit_rate = 0;
  350. u8 rx_chains_num = priv->hw_params.rx_chains_num;
  351. u8 tx_chains_num = priv->hw_params.tx_chains_num;
  352. ht_info->cap = 0;
  353. memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
  354. ht_info->ht_supported = true;
  355. if (priv->cfg->ht_greenfield_support)
  356. ht_info->cap |= IEEE80211_HT_CAP_GRN_FLD;
  357. ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
  358. ht_info->cap |= (IEEE80211_HT_CAP_SM_PS &
  359. (WLAN_HT_CAP_SM_PS_DISABLED << 2));
  360. max_bit_rate = MAX_BIT_RATE_20_MHZ;
  361. if (priv->hw_params.ht40_channel & BIT(band)) {
  362. ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  363. ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
  364. ht_info->mcs.rx_mask[4] = 0x01;
  365. max_bit_rate = MAX_BIT_RATE_40_MHZ;
  366. }
  367. if (priv->cfg->mod_params->amsdu_size_8K)
  368. ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
  369. ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
  370. ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
  371. ht_info->mcs.rx_mask[0] = 0xFF;
  372. if (rx_chains_num >= 2)
  373. ht_info->mcs.rx_mask[1] = 0xFF;
  374. if (rx_chains_num >= 3)
  375. ht_info->mcs.rx_mask[2] = 0xFF;
  376. /* Highest supported Rx data rate */
  377. max_bit_rate *= rx_chains_num;
  378. WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
  379. ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
  380. /* Tx MCS capabilities */
  381. ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
  382. if (tx_chains_num != rx_chains_num) {
  383. ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
  384. ht_info->mcs.tx_params |= ((tx_chains_num - 1) <<
  385. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  386. }
  387. }
  388. static void iwlcore_init_hw_rates(struct iwl_priv *priv,
  389. struct ieee80211_rate *rates)
  390. {
  391. int i;
  392. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  393. rates[i].bitrate = iwl_rates[i].ieee * 5;
  394. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  395. rates[i].hw_value_short = i;
  396. rates[i].flags = 0;
  397. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  398. /*
  399. * If CCK != 1M then set short preamble rate flag.
  400. */
  401. rates[i].flags |=
  402. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  403. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  404. }
  405. }
  406. }
  407. /**
  408. * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
  409. */
  410. int iwlcore_init_geos(struct iwl_priv *priv)
  411. {
  412. struct iwl_channel_info *ch;
  413. struct ieee80211_supported_band *sband;
  414. struct ieee80211_channel *channels;
  415. struct ieee80211_channel *geo_ch;
  416. struct ieee80211_rate *rates;
  417. int i = 0;
  418. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  419. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  420. IWL_DEBUG_INFO(priv, "Geography modes already initialized.\n");
  421. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  422. return 0;
  423. }
  424. channels = kzalloc(sizeof(struct ieee80211_channel) *
  425. priv->channel_count, GFP_KERNEL);
  426. if (!channels)
  427. return -ENOMEM;
  428. rates = kzalloc((sizeof(struct ieee80211_rate) * IWL_RATE_COUNT_LEGACY),
  429. GFP_KERNEL);
  430. if (!rates) {
  431. kfree(channels);
  432. return -ENOMEM;
  433. }
  434. /* 5.2GHz channels start after the 2.4GHz channels */
  435. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  436. sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
  437. /* just OFDM */
  438. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  439. sband->n_bitrates = IWL_RATE_COUNT_LEGACY - IWL_FIRST_OFDM_RATE;
  440. if (priv->cfg->sku & IWL_SKU_N)
  441. iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
  442. IEEE80211_BAND_5GHZ);
  443. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  444. sband->channels = channels;
  445. /* OFDM & CCK */
  446. sband->bitrates = rates;
  447. sband->n_bitrates = IWL_RATE_COUNT_LEGACY;
  448. if (priv->cfg->sku & IWL_SKU_N)
  449. iwlcore_init_ht_hw_capab(priv, &sband->ht_cap,
  450. IEEE80211_BAND_2GHZ);
  451. priv->ieee_channels = channels;
  452. priv->ieee_rates = rates;
  453. for (i = 0; i < priv->channel_count; i++) {
  454. ch = &priv->channel_info[i];
  455. /* FIXME: might be removed if scan is OK */
  456. if (!is_channel_valid(ch))
  457. continue;
  458. if (is_channel_a_band(ch))
  459. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  460. else
  461. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  462. geo_ch = &sband->channels[sband->n_channels++];
  463. geo_ch->center_freq =
  464. ieee80211_channel_to_frequency(ch->channel);
  465. geo_ch->max_power = ch->max_power_avg;
  466. geo_ch->max_antenna_gain = 0xff;
  467. geo_ch->hw_value = ch->channel;
  468. if (is_channel_valid(ch)) {
  469. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  470. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  471. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  472. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  473. if (ch->flags & EEPROM_CHANNEL_RADAR)
  474. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  475. geo_ch->flags |= ch->ht40_extension_channel;
  476. if (ch->max_power_avg > priv->tx_power_device_lmt)
  477. priv->tx_power_device_lmt = ch->max_power_avg;
  478. } else {
  479. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  480. }
  481. IWL_DEBUG_INFO(priv, "Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
  482. ch->channel, geo_ch->center_freq,
  483. is_channel_a_band(ch) ? "5.2" : "2.4",
  484. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  485. "restricted" : "valid",
  486. geo_ch->flags);
  487. }
  488. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  489. priv->cfg->sku & IWL_SKU_A) {
  490. IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
  491. "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
  492. priv->pci_dev->device,
  493. priv->pci_dev->subsystem_device);
  494. priv->cfg->sku &= ~IWL_SKU_A;
  495. }
  496. IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  497. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  498. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  499. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  500. return 0;
  501. }
  502. EXPORT_SYMBOL(iwlcore_init_geos);
  503. /*
  504. * iwlcore_free_geos - undo allocations in iwlcore_init_geos
  505. */
  506. void iwlcore_free_geos(struct iwl_priv *priv)
  507. {
  508. kfree(priv->ieee_channels);
  509. kfree(priv->ieee_rates);
  510. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  511. }
  512. EXPORT_SYMBOL(iwlcore_free_geos);
  513. /*
  514. * iwlcore_rts_tx_cmd_flag: Set rts/cts. 3945 and 4965 only share this
  515. * function.
  516. */
  517. void iwlcore_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
  518. __le32 *tx_flags)
  519. {
  520. if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  521. *tx_flags |= TX_CMD_FLG_RTS_MSK;
  522. *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  523. } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  524. *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  525. *tx_flags |= TX_CMD_FLG_CTS_MSK;
  526. }
  527. }
  528. EXPORT_SYMBOL(iwlcore_rts_tx_cmd_flag);
  529. static bool is_single_rx_stream(struct iwl_priv *priv)
  530. {
  531. return !priv->current_ht_config.is_ht ||
  532. priv->current_ht_config.single_chain_sufficient;
  533. }
  534. static u8 iwl_is_channel_extension(struct iwl_priv *priv,
  535. enum ieee80211_band band,
  536. u16 channel, u8 extension_chan_offset)
  537. {
  538. const struct iwl_channel_info *ch_info;
  539. ch_info = iwl_get_channel_info(priv, band, channel);
  540. if (!is_channel_valid(ch_info))
  541. return 0;
  542. if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
  543. return !(ch_info->ht40_extension_channel &
  544. IEEE80211_CHAN_NO_HT40PLUS);
  545. else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
  546. return !(ch_info->ht40_extension_channel &
  547. IEEE80211_CHAN_NO_HT40MINUS);
  548. return 0;
  549. }
  550. u8 iwl_is_ht40_tx_allowed(struct iwl_priv *priv,
  551. struct ieee80211_sta_ht_cap *sta_ht_inf)
  552. {
  553. struct iwl_ht_config *ht_conf = &priv->current_ht_config;
  554. if (!ht_conf->is_ht || !ht_conf->is_40mhz)
  555. return 0;
  556. /* We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
  557. * the bit will not set if it is pure 40MHz case
  558. */
  559. if (sta_ht_inf) {
  560. if (!sta_ht_inf->ht_supported)
  561. return 0;
  562. }
  563. #ifdef CONFIG_IWLWIFI_DEBUG
  564. if (priv->disable_ht40)
  565. return 0;
  566. #endif
  567. return iwl_is_channel_extension(priv, priv->band,
  568. le16_to_cpu(priv->staging_rxon.channel),
  569. ht_conf->extension_chan_offset);
  570. }
  571. EXPORT_SYMBOL(iwl_is_ht40_tx_allowed);
  572. static u16 iwl_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
  573. {
  574. u16 new_val = 0;
  575. u16 beacon_factor = 0;
  576. beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
  577. new_val = beacon_val / beacon_factor;
  578. if (!new_val)
  579. new_val = max_beacon_val;
  580. return new_val;
  581. }
  582. void iwl_setup_rxon_timing(struct iwl_priv *priv)
  583. {
  584. u64 tsf;
  585. s32 interval_tm, rem;
  586. unsigned long flags;
  587. struct ieee80211_conf *conf = NULL;
  588. u16 beacon_int;
  589. conf = ieee80211_get_hw_conf(priv->hw);
  590. spin_lock_irqsave(&priv->lock, flags);
  591. priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
  592. priv->rxon_timing.listen_interval = cpu_to_le16(conf->listen_interval);
  593. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  594. beacon_int = priv->beacon_int;
  595. priv->rxon_timing.atim_window = 0;
  596. } else {
  597. beacon_int = priv->vif->bss_conf.beacon_int;
  598. /* TODO: we need to get atim_window from upper stack
  599. * for now we set to 0 */
  600. priv->rxon_timing.atim_window = 0;
  601. }
  602. beacon_int = iwl_adjust_beacon_interval(beacon_int,
  603. priv->hw_params.max_beacon_itrvl * 1024);
  604. priv->rxon_timing.beacon_interval = cpu_to_le16(beacon_int);
  605. tsf = priv->timestamp; /* tsf is modifed by do_div: copy it */
  606. interval_tm = beacon_int * 1024;
  607. rem = do_div(tsf, interval_tm);
  608. priv->rxon_timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
  609. spin_unlock_irqrestore(&priv->lock, flags);
  610. IWL_DEBUG_ASSOC(priv,
  611. "beacon interval %d beacon timer %d beacon tim %d\n",
  612. le16_to_cpu(priv->rxon_timing.beacon_interval),
  613. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  614. le16_to_cpu(priv->rxon_timing.atim_window));
  615. }
  616. EXPORT_SYMBOL(iwl_setup_rxon_timing);
  617. void iwl_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
  618. {
  619. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  620. if (hw_decrypt)
  621. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  622. else
  623. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  624. }
  625. EXPORT_SYMBOL(iwl_set_rxon_hwcrypto);
  626. /**
  627. * iwl_check_rxon_cmd - validate RXON structure is valid
  628. *
  629. * NOTE: This is really only useful during development and can eventually
  630. * be #ifdef'd out once the driver is stable and folks aren't actively
  631. * making changes
  632. */
  633. int iwl_check_rxon_cmd(struct iwl_priv *priv)
  634. {
  635. int error = 0;
  636. int counter = 1;
  637. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  638. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  639. error |= le32_to_cpu(rxon->flags &
  640. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  641. RXON_FLG_RADAR_DETECT_MSK));
  642. if (error)
  643. IWL_WARN(priv, "check 24G fields %d | %d\n",
  644. counter++, error);
  645. } else {
  646. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  647. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  648. if (error)
  649. IWL_WARN(priv, "check 52 fields %d | %d\n",
  650. counter++, error);
  651. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  652. if (error)
  653. IWL_WARN(priv, "check 52 CCK %d | %d\n",
  654. counter++, error);
  655. }
  656. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  657. if (error)
  658. IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
  659. /* make sure basic rates 6Mbps and 1Mbps are supported */
  660. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  661. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  662. if (error)
  663. IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
  664. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  665. if (error)
  666. IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
  667. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  668. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  669. if (error)
  670. IWL_WARN(priv, "check CCK and short slot %d | %d\n",
  671. counter++, error);
  672. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  673. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  674. if (error)
  675. IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
  676. counter++, error);
  677. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  678. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  679. if (error)
  680. IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
  681. counter++, error);
  682. if (error)
  683. IWL_WARN(priv, "Tuning to channel %d\n",
  684. le16_to_cpu(rxon->channel));
  685. if (error) {
  686. IWL_ERR(priv, "Not a valid iwl_rxon_assoc_cmd field values\n");
  687. return -1;
  688. }
  689. return 0;
  690. }
  691. EXPORT_SYMBOL(iwl_check_rxon_cmd);
  692. /**
  693. * iwl_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  694. * @priv: staging_rxon is compared to active_rxon
  695. *
  696. * If the RXON structure is changing enough to require a new tune,
  697. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  698. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  699. */
  700. int iwl_full_rxon_required(struct iwl_priv *priv)
  701. {
  702. /* These items are only settable from the full RXON command */
  703. if (!(iwl_is_associated(priv)) ||
  704. compare_ether_addr(priv->staging_rxon.bssid_addr,
  705. priv->active_rxon.bssid_addr) ||
  706. compare_ether_addr(priv->staging_rxon.node_addr,
  707. priv->active_rxon.node_addr) ||
  708. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  709. priv->active_rxon.wlap_bssid_addr) ||
  710. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  711. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  712. (priv->staging_rxon.air_propagation !=
  713. priv->active_rxon.air_propagation) ||
  714. (priv->staging_rxon.ofdm_ht_single_stream_basic_rates !=
  715. priv->active_rxon.ofdm_ht_single_stream_basic_rates) ||
  716. (priv->staging_rxon.ofdm_ht_dual_stream_basic_rates !=
  717. priv->active_rxon.ofdm_ht_dual_stream_basic_rates) ||
  718. (priv->staging_rxon.ofdm_ht_triple_stream_basic_rates !=
  719. priv->active_rxon.ofdm_ht_triple_stream_basic_rates) ||
  720. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  721. return 1;
  722. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  723. * be updated with the RXON_ASSOC command -- however only some
  724. * flag transitions are allowed using RXON_ASSOC */
  725. /* Check if we are not switching bands */
  726. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  727. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  728. return 1;
  729. /* Check if we are switching association toggle */
  730. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  731. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  732. return 1;
  733. return 0;
  734. }
  735. EXPORT_SYMBOL(iwl_full_rxon_required);
  736. u8 iwl_rate_get_lowest_plcp(struct iwl_priv *priv)
  737. {
  738. int i;
  739. int rate_mask;
  740. /* Set rate mask*/
  741. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  742. rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
  743. else
  744. rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
  745. /* Find lowest valid rate */
  746. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  747. i = iwl_rates[i].next_ieee) {
  748. if (rate_mask & (1 << i))
  749. return iwl_rates[i].plcp;
  750. }
  751. /* No valid rate was found. Assign the lowest one */
  752. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)
  753. return IWL_RATE_1M_PLCP;
  754. else
  755. return IWL_RATE_6M_PLCP;
  756. }
  757. EXPORT_SYMBOL(iwl_rate_get_lowest_plcp);
  758. void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_config *ht_conf)
  759. {
  760. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  761. if (!ht_conf->is_ht) {
  762. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
  763. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK |
  764. RXON_FLG_HT40_PROT_MSK |
  765. RXON_FLG_HT_PROT_MSK);
  766. return;
  767. }
  768. /* FIXME: if the definition of ht_protection changed, the "translation"
  769. * will be needed for rxon->flags
  770. */
  771. rxon->flags |= cpu_to_le32(ht_conf->ht_protection << RXON_FLG_HT_OPERATING_MODE_POS);
  772. /* Set up channel bandwidth:
  773. * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
  774. /* clear the HT channel mode before set the mode */
  775. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MSK |
  776. RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  777. if (iwl_is_ht40_tx_allowed(priv, NULL)) {
  778. /* pure ht40 */
  779. if (ht_conf->ht_protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
  780. rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
  781. /* Note: control channel is opposite of extension channel */
  782. switch (ht_conf->extension_chan_offset) {
  783. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  784. rxon->flags &= ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  785. break;
  786. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  787. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  788. break;
  789. }
  790. } else {
  791. /* Note: control channel is opposite of extension channel */
  792. switch (ht_conf->extension_chan_offset) {
  793. case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
  794. rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  795. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  796. break;
  797. case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
  798. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  799. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
  800. break;
  801. case IEEE80211_HT_PARAM_CHA_SEC_NONE:
  802. default:
  803. /* channel location only valid if in Mixed mode */
  804. IWL_ERR(priv, "invalid extension channel offset\n");
  805. break;
  806. }
  807. }
  808. } else {
  809. rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
  810. }
  811. if (priv->cfg->ops->hcmd->set_rxon_chain)
  812. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  813. IWL_DEBUG_ASSOC(priv, "rxon flags 0x%X operation mode :0x%X "
  814. "extension channel offset 0x%x\n",
  815. le32_to_cpu(rxon->flags), ht_conf->ht_protection,
  816. ht_conf->extension_chan_offset);
  817. return;
  818. }
  819. EXPORT_SYMBOL(iwl_set_rxon_ht);
  820. #define IWL_NUM_RX_CHAINS_MULTIPLE 3
  821. #define IWL_NUM_RX_CHAINS_SINGLE 2
  822. #define IWL_NUM_IDLE_CHAINS_DUAL 2
  823. #define IWL_NUM_IDLE_CHAINS_SINGLE 1
  824. /*
  825. * Determine how many receiver/antenna chains to use.
  826. *
  827. * More provides better reception via diversity. Fewer saves power
  828. * at the expense of throughput, but only when not in powersave to
  829. * start with.
  830. *
  831. * MIMO (dual stream) requires at least 2, but works better with 3.
  832. * This does not determine *which* chains to use, just how many.
  833. */
  834. static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
  835. {
  836. /* # of Rx chains to use when expecting MIMO. */
  837. if (is_single_rx_stream(priv))
  838. return IWL_NUM_RX_CHAINS_SINGLE;
  839. else
  840. return IWL_NUM_RX_CHAINS_MULTIPLE;
  841. }
  842. /*
  843. * When we are in power saving, there's no difference between
  844. * using multiple chains or just a single chain, but due to the
  845. * lack of SM PS we lose a lot of throughput if we use just a
  846. * single chain.
  847. *
  848. * Therefore, use the active count here (which will use multiple
  849. * chains unless connected to a legacy AP).
  850. */
  851. static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
  852. {
  853. return active_cnt;
  854. }
  855. /* up to 4 chains */
  856. static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
  857. {
  858. u8 res;
  859. res = (chain_bitmap & BIT(0)) >> 0;
  860. res += (chain_bitmap & BIT(1)) >> 1;
  861. res += (chain_bitmap & BIT(2)) >> 2;
  862. res += (chain_bitmap & BIT(3)) >> 3;
  863. return res;
  864. }
  865. /**
  866. * iwl_is_monitor_mode - Determine if interface in monitor mode
  867. *
  868. * priv->iw_mode is set in add_interface, but add_interface is
  869. * never called for monitor mode. The only way mac80211 informs us about
  870. * monitor mode is through configuring filters (call to configure_filter).
  871. */
  872. bool iwl_is_monitor_mode(struct iwl_priv *priv)
  873. {
  874. return !!(priv->staging_rxon.filter_flags & RXON_FILTER_PROMISC_MSK);
  875. }
  876. EXPORT_SYMBOL(iwl_is_monitor_mode);
  877. /**
  878. * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
  879. *
  880. * Selects how many and which Rx receivers/antennas/chains to use.
  881. * This should not be used for scan command ... it puts data in wrong place.
  882. */
  883. void iwl_set_rxon_chain(struct iwl_priv *priv)
  884. {
  885. bool is_single = is_single_rx_stream(priv);
  886. bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
  887. u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
  888. u32 active_chains;
  889. u16 rx_chain;
  890. /* Tell uCode which antennas are actually connected.
  891. * Before first association, we assume all antennas are connected.
  892. * Just after first association, iwl_chain_noise_calibration()
  893. * checks which antennas actually *are* connected. */
  894. if (priv->chain_noise_data.active_chains)
  895. active_chains = priv->chain_noise_data.active_chains;
  896. else
  897. active_chains = priv->hw_params.valid_rx_ant;
  898. rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
  899. /* How many receivers should we use? */
  900. active_rx_cnt = iwl_get_active_rx_chain_count(priv);
  901. idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
  902. /* correct rx chain count according hw settings
  903. * and chain noise calibration
  904. */
  905. valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
  906. if (valid_rx_cnt < active_rx_cnt)
  907. active_rx_cnt = valid_rx_cnt;
  908. if (valid_rx_cnt < idle_rx_cnt)
  909. idle_rx_cnt = valid_rx_cnt;
  910. rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
  911. rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
  912. /* copied from 'iwl_bg_request_scan()' */
  913. /* Force use of chains B and C (0x6) for Rx for 4965
  914. * Avoid A (0x1) because of its off-channel reception on A-band.
  915. * MIMO is not used here, but value is required */
  916. if (iwl_is_monitor_mode(priv) &&
  917. !(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) &&
  918. ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_4965)) {
  919. rx_chain = ANT_ABC << RXON_RX_CHAIN_VALID_POS;
  920. rx_chain |= ANT_BC << RXON_RX_CHAIN_FORCE_SEL_POS;
  921. rx_chain |= ANT_ABC << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
  922. rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
  923. }
  924. priv->staging_rxon.rx_chain = cpu_to_le16(rx_chain);
  925. if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
  926. priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
  927. else
  928. priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
  929. IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
  930. priv->staging_rxon.rx_chain,
  931. active_rx_cnt, idle_rx_cnt);
  932. WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
  933. active_rx_cnt < idle_rx_cnt);
  934. }
  935. EXPORT_SYMBOL(iwl_set_rxon_chain);
  936. /**
  937. * iwl_set_rxon_channel - Set the phymode and channel values in staging RXON
  938. * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
  939. * @channel: Any channel valid for the requested phymode
  940. * In addition to setting the staging RXON, priv->phymode is also set.
  941. *
  942. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  943. * in the staging RXON flag structure based on the phymode
  944. */
  945. int iwl_set_rxon_channel(struct iwl_priv *priv, struct ieee80211_channel *ch)
  946. {
  947. enum ieee80211_band band = ch->band;
  948. u16 channel = ieee80211_frequency_to_channel(ch->center_freq);
  949. if (!iwl_get_channel_info(priv, band, channel)) {
  950. IWL_DEBUG_INFO(priv, "Could not set channel to %d [%d]\n",
  951. channel, band);
  952. return -EINVAL;
  953. }
  954. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  955. (priv->band == band))
  956. return 0;
  957. priv->staging_rxon.channel = cpu_to_le16(channel);
  958. if (band == IEEE80211_BAND_5GHZ)
  959. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  960. else
  961. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  962. priv->band = band;
  963. IWL_DEBUG_INFO(priv, "Staging channel set to %d [%d]\n", channel, band);
  964. return 0;
  965. }
  966. EXPORT_SYMBOL(iwl_set_rxon_channel);
  967. void iwl_set_flags_for_band(struct iwl_priv *priv,
  968. enum ieee80211_band band)
  969. {
  970. if (band == IEEE80211_BAND_5GHZ) {
  971. priv->staging_rxon.flags &=
  972. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  973. | RXON_FLG_CCK_MSK);
  974. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  975. } else {
  976. /* Copied from iwl_post_associate() */
  977. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  978. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  979. else
  980. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  981. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  982. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  983. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  984. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  985. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  986. }
  987. }
  988. /*
  989. * initialize rxon structure with default values from eeprom
  990. */
  991. void iwl_connection_init_rx_config(struct iwl_priv *priv, int mode)
  992. {
  993. const struct iwl_channel_info *ch_info;
  994. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  995. switch (mode) {
  996. case NL80211_IFTYPE_AP:
  997. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  998. break;
  999. case NL80211_IFTYPE_STATION:
  1000. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1001. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1002. break;
  1003. case NL80211_IFTYPE_ADHOC:
  1004. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1005. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1006. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1007. RXON_FILTER_ACCEPT_GRP_MSK;
  1008. break;
  1009. default:
  1010. IWL_ERR(priv, "Unsupported interface type %d\n", mode);
  1011. break;
  1012. }
  1013. #if 0
  1014. /* TODO: Figure out when short_preamble would be set and cache from
  1015. * that */
  1016. if (!hw_to_local(priv->hw)->short_preamble)
  1017. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1018. else
  1019. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1020. #endif
  1021. ch_info = iwl_get_channel_info(priv, priv->band,
  1022. le16_to_cpu(priv->active_rxon.channel));
  1023. if (!ch_info)
  1024. ch_info = &priv->channel_info[0];
  1025. /*
  1026. * in some case A channels are all non IBSS
  1027. * in this case force B/G channel
  1028. */
  1029. if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
  1030. !(is_channel_ibss(ch_info)))
  1031. ch_info = &priv->channel_info[0];
  1032. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  1033. priv->band = ch_info->band;
  1034. iwl_set_flags_for_band(priv, priv->band);
  1035. priv->staging_rxon.ofdm_basic_rates =
  1036. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1037. priv->staging_rxon.cck_basic_rates =
  1038. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1039. /* clear both MIX and PURE40 mode flag */
  1040. priv->staging_rxon.flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED |
  1041. RXON_FLG_CHANNEL_MODE_PURE_40);
  1042. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1043. memcpy(priv->staging_rxon.wlap_bssid_addr, priv->mac_addr, ETH_ALEN);
  1044. priv->staging_rxon.ofdm_ht_single_stream_basic_rates = 0xff;
  1045. priv->staging_rxon.ofdm_ht_dual_stream_basic_rates = 0xff;
  1046. priv->staging_rxon.ofdm_ht_triple_stream_basic_rates = 0xff;
  1047. }
  1048. EXPORT_SYMBOL(iwl_connection_init_rx_config);
  1049. static void iwl_set_rate(struct iwl_priv *priv)
  1050. {
  1051. const struct ieee80211_supported_band *hw = NULL;
  1052. struct ieee80211_rate *rate;
  1053. int i;
  1054. hw = iwl_get_hw_mode(priv, priv->band);
  1055. if (!hw) {
  1056. IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
  1057. return;
  1058. }
  1059. priv->active_rate = 0;
  1060. priv->active_rate_basic = 0;
  1061. for (i = 0; i < hw->n_bitrates; i++) {
  1062. rate = &(hw->bitrates[i]);
  1063. if (rate->hw_value < IWL_RATE_COUNT_LEGACY)
  1064. priv->active_rate |= (1 << rate->hw_value);
  1065. }
  1066. IWL_DEBUG_RATE(priv, "Set active_rate = %0x, active_rate_basic = %0x\n",
  1067. priv->active_rate, priv->active_rate_basic);
  1068. /*
  1069. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  1070. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  1071. * OFDM
  1072. */
  1073. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  1074. priv->staging_rxon.cck_basic_rates =
  1075. ((priv->active_rate_basic &
  1076. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  1077. else
  1078. priv->staging_rxon.cck_basic_rates =
  1079. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1080. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  1081. priv->staging_rxon.ofdm_basic_rates =
  1082. ((priv->active_rate_basic &
  1083. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  1084. IWL_FIRST_OFDM_RATE) & 0xFF;
  1085. else
  1086. priv->staging_rxon.ofdm_basic_rates =
  1087. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1088. }
  1089. void iwl_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
  1090. {
  1091. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1092. struct iwl_rxon_cmd *rxon = (void *)&priv->active_rxon;
  1093. struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
  1094. if (!le32_to_cpu(csa->status)) {
  1095. rxon->channel = csa->channel;
  1096. priv->staging_rxon.channel = csa->channel;
  1097. IWL_DEBUG_11H(priv, "CSA notif: channel %d\n",
  1098. le16_to_cpu(csa->channel));
  1099. } else
  1100. IWL_ERR(priv, "CSA notif (fail) : channel %d\n",
  1101. le16_to_cpu(csa->channel));
  1102. }
  1103. EXPORT_SYMBOL(iwl_rx_csa);
  1104. #ifdef CONFIG_IWLWIFI_DEBUG
  1105. static void iwl_print_rx_config_cmd(struct iwl_priv *priv)
  1106. {
  1107. struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
  1108. IWL_DEBUG_RADIO(priv, "RX CONFIG:\n");
  1109. iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  1110. IWL_DEBUG_RADIO(priv, "u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  1111. IWL_DEBUG_RADIO(priv, "u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  1112. IWL_DEBUG_RADIO(priv, "u32 filter_flags: 0x%08x\n",
  1113. le32_to_cpu(rxon->filter_flags));
  1114. IWL_DEBUG_RADIO(priv, "u8 dev_type: 0x%x\n", rxon->dev_type);
  1115. IWL_DEBUG_RADIO(priv, "u8 ofdm_basic_rates: 0x%02x\n",
  1116. rxon->ofdm_basic_rates);
  1117. IWL_DEBUG_RADIO(priv, "u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  1118. IWL_DEBUG_RADIO(priv, "u8[6] node_addr: %pM\n", rxon->node_addr);
  1119. IWL_DEBUG_RADIO(priv, "u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  1120. IWL_DEBUG_RADIO(priv, "u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  1121. }
  1122. #endif
  1123. /**
  1124. * iwl_irq_handle_error - called for HW or SW error interrupt from card
  1125. */
  1126. void iwl_irq_handle_error(struct iwl_priv *priv)
  1127. {
  1128. /* Set the FW error flag -- cleared on iwl_down */
  1129. set_bit(STATUS_FW_ERROR, &priv->status);
  1130. /* Cancel currently queued command. */
  1131. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  1132. #ifdef CONFIG_IWLWIFI_DEBUG
  1133. if (iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) {
  1134. priv->cfg->ops->lib->dump_nic_error_log(priv);
  1135. priv->cfg->ops->lib->dump_nic_event_log(priv);
  1136. iwl_print_rx_config_cmd(priv);
  1137. }
  1138. #endif
  1139. wake_up_interruptible(&priv->wait_command_queue);
  1140. /* Keep the restart process from trying to send host
  1141. * commands by clearing the INIT status bit */
  1142. clear_bit(STATUS_READY, &priv->status);
  1143. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1144. IWL_DEBUG(priv, IWL_DL_FW_ERRORS,
  1145. "Restarting adapter due to uCode error.\n");
  1146. if (priv->cfg->mod_params->restart_fw)
  1147. queue_work(priv->workqueue, &priv->restart);
  1148. }
  1149. }
  1150. EXPORT_SYMBOL(iwl_irq_handle_error);
  1151. int iwl_apm_stop_master(struct iwl_priv *priv)
  1152. {
  1153. int ret = 0;
  1154. /* stop device's busmaster DMA activity */
  1155. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  1156. ret = iwl_poll_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
  1157. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  1158. if (ret)
  1159. IWL_WARN(priv, "Master Disable Timed Out, 100 usec\n");
  1160. IWL_DEBUG_INFO(priv, "stop master\n");
  1161. return ret;
  1162. }
  1163. EXPORT_SYMBOL(iwl_apm_stop_master);
  1164. void iwl_apm_stop(struct iwl_priv *priv)
  1165. {
  1166. IWL_DEBUG_INFO(priv, "Stop card, put in low power state\n");
  1167. /* Stop device's DMA activity */
  1168. iwl_apm_stop_master(priv);
  1169. /* Reset the entire device */
  1170. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  1171. udelay(10);
  1172. /*
  1173. * Clear "initialization complete" bit to move adapter from
  1174. * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
  1175. */
  1176. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  1177. }
  1178. EXPORT_SYMBOL(iwl_apm_stop);
  1179. /*
  1180. * Start up NIC's basic functionality after it has been reset
  1181. * (e.g. after platform boot, or shutdown via iwl_apm_stop())
  1182. * NOTE: This does not load uCode nor start the embedded processor
  1183. */
  1184. int iwl_apm_init(struct iwl_priv *priv)
  1185. {
  1186. int ret = 0;
  1187. u16 lctl;
  1188. IWL_DEBUG_INFO(priv, "Init card's basic functions\n");
  1189. /*
  1190. * Use "set_bit" below rather than "write", to preserve any hardware
  1191. * bits already set by default after reset.
  1192. */
  1193. /* Disable L0S exit timer (platform NMI Work/Around) */
  1194. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  1195. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  1196. /*
  1197. * Disable L0s without affecting L1;
  1198. * don't wait for ICH L0s (ICH bug W/A)
  1199. */
  1200. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  1201. CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
  1202. /* Set FH wait threshold to maximum (HW error during stress W/A) */
  1203. iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
  1204. /*
  1205. * Enable HAP INTA (interrupt from management bus) to
  1206. * wake device's PCI Express link L1a -> L0s
  1207. * NOTE: This is no-op for 3945 (non-existant bit)
  1208. */
  1209. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1210. CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
  1211. /*
  1212. * HW bug W/A - costs negligible power consumption ...
  1213. * Check if BIOS (or OS) enabled L1-ASPM on this device
  1214. */
  1215. if (priv->cfg->set_l0s) {
  1216. lctl = iwl_pcie_link_ctl(priv);
  1217. if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
  1218. PCI_CFG_LINK_CTRL_VAL_L1_EN) {
  1219. /* L1-ASPM enabled; disable(!) L0S */
  1220. iwl_set_bit(priv, CSR_GIO_REG,
  1221. CSR_GIO_REG_VAL_L0S_ENABLED);
  1222. IWL_DEBUG_POWER(priv, "L1 Enabled; Disabling L0S\n");
  1223. } else {
  1224. /* L1-ASPM disabled; enable(!) L0S */
  1225. iwl_clear_bit(priv, CSR_GIO_REG,
  1226. CSR_GIO_REG_VAL_L0S_ENABLED);
  1227. IWL_DEBUG_POWER(priv, "L1 Disabled; Enabling L0S\n");
  1228. }
  1229. }
  1230. /* Configure analog phase-lock-loop before activating to D0A */
  1231. if (priv->cfg->pll_cfg_val)
  1232. iwl_set_bit(priv, CSR_ANA_PLL_CFG, priv->cfg->pll_cfg_val);
  1233. /*
  1234. * Set "initialization complete" bit to move adapter from
  1235. * D0U* --> D0A* (powered-up active) state.
  1236. */
  1237. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  1238. /*
  1239. * Wait for clock stabilization; once stabilized, access to
  1240. * device-internal resources is supported, e.g. iwl_write_prph()
  1241. * and accesses to uCode SRAM.
  1242. */
  1243. ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
  1244. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  1245. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  1246. if (ret < 0) {
  1247. IWL_DEBUG_INFO(priv, "Failed to init the card\n");
  1248. goto out;
  1249. }
  1250. /*
  1251. * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
  1252. * BSM (Boostrap State Machine) is only in 3945 and 4965;
  1253. * later devices (i.e. 5000 and later) have non-volatile SRAM,
  1254. * and don't need BSM to restore data after power-saving sleep.
  1255. *
  1256. * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
  1257. * do not disable clocks. This preserves any hardware bits already
  1258. * set by default in "CLK_CTRL_REG" after reset.
  1259. */
  1260. if (priv->cfg->use_bsm)
  1261. iwl_write_prph(priv, APMG_CLK_EN_REG,
  1262. APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
  1263. else
  1264. iwl_write_prph(priv, APMG_CLK_EN_REG,
  1265. APMG_CLK_VAL_DMA_CLK_RQT);
  1266. udelay(20);
  1267. /* Disable L1-Active */
  1268. iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  1269. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  1270. out:
  1271. return ret;
  1272. }
  1273. EXPORT_SYMBOL(iwl_apm_init);
  1274. void iwl_configure_filter(struct ieee80211_hw *hw,
  1275. unsigned int changed_flags,
  1276. unsigned int *total_flags,
  1277. u64 multicast)
  1278. {
  1279. struct iwl_priv *priv = hw->priv;
  1280. __le32 *filter_flags = &priv->staging_rxon.filter_flags;
  1281. IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
  1282. changed_flags, *total_flags);
  1283. if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
  1284. if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
  1285. *filter_flags |= RXON_FILTER_PROMISC_MSK;
  1286. else
  1287. *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
  1288. }
  1289. if (changed_flags & FIF_ALLMULTI) {
  1290. if (*total_flags & FIF_ALLMULTI)
  1291. *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
  1292. else
  1293. *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
  1294. }
  1295. if (changed_flags & FIF_CONTROL) {
  1296. if (*total_flags & FIF_CONTROL)
  1297. *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
  1298. else
  1299. *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
  1300. }
  1301. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  1302. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  1303. *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
  1304. else
  1305. *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
  1306. }
  1307. /* We avoid iwl_commit_rxon here to commit the new filter flags
  1308. * since mac80211 will call ieee80211_hw_config immediately.
  1309. * (mc_list is not supported at this time). Otherwise, we need to
  1310. * queue a background iwl_commit_rxon work.
  1311. */
  1312. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  1313. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  1314. }
  1315. EXPORT_SYMBOL(iwl_configure_filter);
  1316. int iwl_set_hw_params(struct iwl_priv *priv)
  1317. {
  1318. priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
  1319. priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
  1320. if (priv->cfg->mod_params->amsdu_size_8K)
  1321. priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
  1322. else
  1323. priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
  1324. priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
  1325. if (priv->cfg->mod_params->disable_11n)
  1326. priv->cfg->sku &= ~IWL_SKU_N;
  1327. /* Device-specific setup */
  1328. return priv->cfg->ops->lib->set_hw_params(priv);
  1329. }
  1330. EXPORT_SYMBOL(iwl_set_hw_params);
  1331. int iwl_init_drv(struct iwl_priv *priv)
  1332. {
  1333. int ret;
  1334. priv->ibss_beacon = NULL;
  1335. spin_lock_init(&priv->lock);
  1336. spin_lock_init(&priv->sta_lock);
  1337. spin_lock_init(&priv->hcmd_lock);
  1338. INIT_LIST_HEAD(&priv->free_frames);
  1339. mutex_init(&priv->mutex);
  1340. /* Clear the driver's (not device's) station table */
  1341. iwl_clear_stations_table(priv);
  1342. priv->ieee_channels = NULL;
  1343. priv->ieee_rates = NULL;
  1344. priv->band = IEEE80211_BAND_2GHZ;
  1345. priv->iw_mode = NL80211_IFTYPE_STATION;
  1346. /* Choose which receivers/antennas to use */
  1347. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1348. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1349. iwl_init_scan_params(priv);
  1350. iwl_reset_qos(priv);
  1351. priv->qos_data.qos_active = 0;
  1352. priv->qos_data.qos_cap.val = 0;
  1353. priv->rates_mask = IWL_RATES_MASK;
  1354. /* Set the tx_power_user_lmt to the lowest power level
  1355. * this value will get overwritten by channel max power avg
  1356. * from eeprom */
  1357. priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
  1358. ret = iwl_init_channel_map(priv);
  1359. if (ret) {
  1360. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  1361. goto err;
  1362. }
  1363. ret = iwlcore_init_geos(priv);
  1364. if (ret) {
  1365. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  1366. goto err_free_channel_map;
  1367. }
  1368. iwlcore_init_hw_rates(priv, priv->ieee_rates);
  1369. return 0;
  1370. err_free_channel_map:
  1371. iwl_free_channel_map(priv);
  1372. err:
  1373. return ret;
  1374. }
  1375. EXPORT_SYMBOL(iwl_init_drv);
  1376. int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
  1377. {
  1378. int ret = 0;
  1379. s8 prev_tx_power = priv->tx_power_user_lmt;
  1380. if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
  1381. IWL_WARN(priv, "Requested user TXPOWER %d below lower limit %d.\n",
  1382. tx_power,
  1383. IWL_TX_POWER_TARGET_POWER_MIN);
  1384. return -EINVAL;
  1385. }
  1386. if (tx_power > priv->tx_power_device_lmt) {
  1387. IWL_WARN(priv,
  1388. "Requested user TXPOWER %d above upper limit %d.\n",
  1389. tx_power, priv->tx_power_device_lmt);
  1390. return -EINVAL;
  1391. }
  1392. if (priv->tx_power_user_lmt != tx_power)
  1393. force = true;
  1394. /* if nic is not up don't send command */
  1395. if (iwl_is_ready_rf(priv)) {
  1396. priv->tx_power_user_lmt = tx_power;
  1397. if (force && priv->cfg->ops->lib->send_tx_power)
  1398. ret = priv->cfg->ops->lib->send_tx_power(priv);
  1399. else if (!priv->cfg->ops->lib->send_tx_power)
  1400. ret = -EOPNOTSUPP;
  1401. /*
  1402. * if fail to set tx_power, restore the orig. tx power
  1403. */
  1404. if (ret)
  1405. priv->tx_power_user_lmt = prev_tx_power;
  1406. }
  1407. /*
  1408. * Even this is an async host command, the command
  1409. * will always report success from uCode
  1410. * So once driver can placing the command into the queue
  1411. * successfully, driver can use priv->tx_power_user_lmt
  1412. * to reflect the current tx power
  1413. */
  1414. return ret;
  1415. }
  1416. EXPORT_SYMBOL(iwl_set_tx_power);
  1417. void iwl_uninit_drv(struct iwl_priv *priv)
  1418. {
  1419. iwl_calib_free_results(priv);
  1420. iwlcore_free_geos(priv);
  1421. iwl_free_channel_map(priv);
  1422. kfree(priv->scan);
  1423. }
  1424. EXPORT_SYMBOL(iwl_uninit_drv);
  1425. #define ICT_COUNT (PAGE_SIZE/sizeof(u32))
  1426. /* Free dram table */
  1427. void iwl_free_isr_ict(struct iwl_priv *priv)
  1428. {
  1429. if (priv->ict_tbl_vir) {
  1430. pci_free_consistent(priv->pci_dev, (sizeof(u32) * ICT_COUNT) +
  1431. PAGE_SIZE, priv->ict_tbl_vir,
  1432. priv->ict_tbl_dma);
  1433. priv->ict_tbl_vir = NULL;
  1434. }
  1435. }
  1436. EXPORT_SYMBOL(iwl_free_isr_ict);
  1437. /* allocate dram shared table it is a PAGE_SIZE aligned
  1438. * also reset all data related to ICT table interrupt.
  1439. */
  1440. int iwl_alloc_isr_ict(struct iwl_priv *priv)
  1441. {
  1442. if (priv->cfg->use_isr_legacy)
  1443. return 0;
  1444. /* allocate shrared data table */
  1445. priv->ict_tbl_vir = pci_alloc_consistent(priv->pci_dev, (sizeof(u32) *
  1446. ICT_COUNT) + PAGE_SIZE,
  1447. &priv->ict_tbl_dma);
  1448. if (!priv->ict_tbl_vir)
  1449. return -ENOMEM;
  1450. /* align table to PAGE_SIZE boundry */
  1451. priv->aligned_ict_tbl_dma = ALIGN(priv->ict_tbl_dma, PAGE_SIZE);
  1452. IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
  1453. (unsigned long long)priv->ict_tbl_dma,
  1454. (unsigned long long)priv->aligned_ict_tbl_dma,
  1455. (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
  1456. priv->ict_tbl = priv->ict_tbl_vir +
  1457. (priv->aligned_ict_tbl_dma - priv->ict_tbl_dma);
  1458. IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
  1459. priv->ict_tbl, priv->ict_tbl_vir,
  1460. (int)(priv->aligned_ict_tbl_dma - priv->ict_tbl_dma));
  1461. /* reset table and index to all 0 */
  1462. memset(priv->ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
  1463. priv->ict_index = 0;
  1464. /* add periodic RX interrupt */
  1465. priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
  1466. return 0;
  1467. }
  1468. EXPORT_SYMBOL(iwl_alloc_isr_ict);
  1469. /* Device is going up inform it about using ICT interrupt table,
  1470. * also we need to tell the driver to start using ICT interrupt.
  1471. */
  1472. int iwl_reset_ict(struct iwl_priv *priv)
  1473. {
  1474. u32 val;
  1475. unsigned long flags;
  1476. if (!priv->ict_tbl_vir)
  1477. return 0;
  1478. spin_lock_irqsave(&priv->lock, flags);
  1479. iwl_disable_interrupts(priv);
  1480. memset(&priv->ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
  1481. val = priv->aligned_ict_tbl_dma >> PAGE_SHIFT;
  1482. val |= CSR_DRAM_INT_TBL_ENABLE;
  1483. val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
  1484. IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
  1485. "aligned dma address %Lx\n",
  1486. val, (unsigned long long)priv->aligned_ict_tbl_dma);
  1487. iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
  1488. priv->use_ict = true;
  1489. priv->ict_index = 0;
  1490. iwl_write32(priv, CSR_INT, priv->inta_mask);
  1491. iwl_enable_interrupts(priv);
  1492. spin_unlock_irqrestore(&priv->lock, flags);
  1493. return 0;
  1494. }
  1495. EXPORT_SYMBOL(iwl_reset_ict);
  1496. /* Device is going down disable ict interrupt usage */
  1497. void iwl_disable_ict(struct iwl_priv *priv)
  1498. {
  1499. unsigned long flags;
  1500. spin_lock_irqsave(&priv->lock, flags);
  1501. priv->use_ict = false;
  1502. spin_unlock_irqrestore(&priv->lock, flags);
  1503. }
  1504. EXPORT_SYMBOL(iwl_disable_ict);
  1505. /* interrupt handler using ict table, with this interrupt driver will
  1506. * stop using INTA register to get device's interrupt, reading this register
  1507. * is expensive, device will write interrupts in ICT dram table, increment
  1508. * index then will fire interrupt to driver, driver will OR all ICT table
  1509. * entries from current index up to table entry with 0 value. the result is
  1510. * the interrupt we need to service, driver will set the entries back to 0 and
  1511. * set index.
  1512. */
  1513. irqreturn_t iwl_isr_ict(int irq, void *data)
  1514. {
  1515. struct iwl_priv *priv = data;
  1516. u32 inta, inta_mask;
  1517. u32 val = 0;
  1518. if (!priv)
  1519. return IRQ_NONE;
  1520. /* dram interrupt table not set yet,
  1521. * use legacy interrupt.
  1522. */
  1523. if (!priv->use_ict)
  1524. return iwl_isr(irq, data);
  1525. spin_lock(&priv->lock);
  1526. /* Disable (but don't clear!) interrupts here to avoid
  1527. * back-to-back ISRs and sporadic interrupts from our NIC.
  1528. * If we have something to service, the tasklet will re-enable ints.
  1529. * If we *don't* have something, we'll re-enable before leaving here.
  1530. */
  1531. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  1532. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1533. /* Ignore interrupt if there's nothing in NIC to service.
  1534. * This may be due to IRQ shared with another device,
  1535. * or due to sporadic interrupts thrown from our NIC. */
  1536. if (!priv->ict_tbl[priv->ict_index]) {
  1537. IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
  1538. goto none;
  1539. }
  1540. /* read all entries that not 0 start with ict_index */
  1541. while (priv->ict_tbl[priv->ict_index]) {
  1542. val |= le32_to_cpu(priv->ict_tbl[priv->ict_index]);
  1543. IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
  1544. priv->ict_index,
  1545. le32_to_cpu(priv->ict_tbl[priv->ict_index]));
  1546. priv->ict_tbl[priv->ict_index] = 0;
  1547. priv->ict_index = iwl_queue_inc_wrap(priv->ict_index,
  1548. ICT_COUNT);
  1549. }
  1550. /* We should not get this value, just ignore it. */
  1551. if (val == 0xffffffff)
  1552. val = 0;
  1553. inta = (0xff & val) | ((0xff00 & val) << 16);
  1554. IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
  1555. inta, inta_mask, val);
  1556. inta &= priv->inta_mask;
  1557. priv->inta |= inta;
  1558. /* iwl_irq_tasklet() will service interrupts and re-enable them */
  1559. if (likely(inta))
  1560. tasklet_schedule(&priv->irq_tasklet);
  1561. else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta) {
  1562. /* Allow interrupt if was disabled by this handler and
  1563. * no tasklet was schedules, We should not enable interrupt,
  1564. * tasklet will enable it.
  1565. */
  1566. iwl_enable_interrupts(priv);
  1567. }
  1568. spin_unlock(&priv->lock);
  1569. return IRQ_HANDLED;
  1570. none:
  1571. /* re-enable interrupts here since we don't have anything to service.
  1572. * only Re-enable if disabled by irq.
  1573. */
  1574. if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
  1575. iwl_enable_interrupts(priv);
  1576. spin_unlock(&priv->lock);
  1577. return IRQ_NONE;
  1578. }
  1579. EXPORT_SYMBOL(iwl_isr_ict);
  1580. static irqreturn_t iwl_isr(int irq, void *data)
  1581. {
  1582. struct iwl_priv *priv = data;
  1583. u32 inta, inta_mask;
  1584. #ifdef CONFIG_IWLWIFI_DEBUG
  1585. u32 inta_fh;
  1586. #endif
  1587. if (!priv)
  1588. return IRQ_NONE;
  1589. spin_lock(&priv->lock);
  1590. /* Disable (but don't clear!) interrupts here to avoid
  1591. * back-to-back ISRs and sporadic interrupts from our NIC.
  1592. * If we have something to service, the tasklet will re-enable ints.
  1593. * If we *don't* have something, we'll re-enable before leaving here. */
  1594. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  1595. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1596. /* Discover which interrupts are active/pending */
  1597. inta = iwl_read32(priv, CSR_INT);
  1598. /* Ignore interrupt if there's nothing in NIC to service.
  1599. * This may be due to IRQ shared with another device,
  1600. * or due to sporadic interrupts thrown from our NIC. */
  1601. if (!inta) {
  1602. IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
  1603. goto none;
  1604. }
  1605. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  1606. /* Hardware disappeared. It might have already raised
  1607. * an interrupt */
  1608. IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
  1609. goto unplugged;
  1610. }
  1611. #ifdef CONFIG_IWLWIFI_DEBUG
  1612. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1613. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1614. IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
  1615. "fh 0x%08x\n", inta, inta_mask, inta_fh);
  1616. }
  1617. #endif
  1618. priv->inta |= inta;
  1619. /* iwl_irq_tasklet() will service interrupts and re-enable them */
  1620. if (likely(inta))
  1621. tasklet_schedule(&priv->irq_tasklet);
  1622. else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
  1623. iwl_enable_interrupts(priv);
  1624. unplugged:
  1625. spin_unlock(&priv->lock);
  1626. return IRQ_HANDLED;
  1627. none:
  1628. /* re-enable interrupts here since we don't have anything to service. */
  1629. /* only Re-enable if diabled by irq and no schedules tasklet. */
  1630. if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->inta)
  1631. iwl_enable_interrupts(priv);
  1632. spin_unlock(&priv->lock);
  1633. return IRQ_NONE;
  1634. }
  1635. irqreturn_t iwl_isr_legacy(int irq, void *data)
  1636. {
  1637. struct iwl_priv *priv = data;
  1638. u32 inta, inta_mask;
  1639. u32 inta_fh;
  1640. if (!priv)
  1641. return IRQ_NONE;
  1642. spin_lock(&priv->lock);
  1643. /* Disable (but don't clear!) interrupts here to avoid
  1644. * back-to-back ISRs and sporadic interrupts from our NIC.
  1645. * If we have something to service, the tasklet will re-enable ints.
  1646. * If we *don't* have something, we'll re-enable before leaving here. */
  1647. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  1648. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  1649. /* Discover which interrupts are active/pending */
  1650. inta = iwl_read32(priv, CSR_INT);
  1651. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1652. /* Ignore interrupt if there's nothing in NIC to service.
  1653. * This may be due to IRQ shared with another device,
  1654. * or due to sporadic interrupts thrown from our NIC. */
  1655. if (!inta && !inta_fh) {
  1656. IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n");
  1657. goto none;
  1658. }
  1659. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  1660. /* Hardware disappeared. It might have already raised
  1661. * an interrupt */
  1662. IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
  1663. goto unplugged;
  1664. }
  1665. IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  1666. inta, inta_mask, inta_fh);
  1667. inta &= ~CSR_INT_BIT_SCD;
  1668. /* iwl_irq_tasklet() will service interrupts and re-enable them */
  1669. if (likely(inta || inta_fh))
  1670. tasklet_schedule(&priv->irq_tasklet);
  1671. unplugged:
  1672. spin_unlock(&priv->lock);
  1673. return IRQ_HANDLED;
  1674. none:
  1675. /* re-enable interrupts here since we don't have anything to service. */
  1676. /* only Re-enable if diabled by irq */
  1677. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1678. iwl_enable_interrupts(priv);
  1679. spin_unlock(&priv->lock);
  1680. return IRQ_NONE;
  1681. }
  1682. EXPORT_SYMBOL(iwl_isr_legacy);
  1683. int iwl_send_bt_config(struct iwl_priv *priv)
  1684. {
  1685. struct iwl_bt_cmd bt_cmd = {
  1686. .flags = BT_COEX_MODE_4W,
  1687. .lead_time = BT_LEAD_TIME_DEF,
  1688. .max_kill = BT_MAX_KILL_DEF,
  1689. .kill_ack_mask = 0,
  1690. .kill_cts_mask = 0,
  1691. };
  1692. return iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  1693. sizeof(struct iwl_bt_cmd), &bt_cmd);
  1694. }
  1695. EXPORT_SYMBOL(iwl_send_bt_config);
  1696. int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
  1697. {
  1698. u32 stat_flags = 0;
  1699. struct iwl_host_cmd cmd = {
  1700. .id = REPLY_STATISTICS_CMD,
  1701. .flags = flags,
  1702. .len = sizeof(stat_flags),
  1703. .data = (u8 *) &stat_flags,
  1704. };
  1705. return iwl_send_cmd(priv, &cmd);
  1706. }
  1707. EXPORT_SYMBOL(iwl_send_statistics_request);
  1708. /**
  1709. * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
  1710. * using sample data 100 bytes apart. If these sample points are good,
  1711. * it's a pretty good bet that everything between them is good, too.
  1712. */
  1713. static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
  1714. {
  1715. u32 val;
  1716. int ret = 0;
  1717. u32 errcnt = 0;
  1718. u32 i;
  1719. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1720. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  1721. /* read data comes through single port, auto-incr addr */
  1722. /* NOTE: Use the debugless read so we don't flood kernel log
  1723. * if IWL_DL_IO is set */
  1724. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1725. i + IWL49_RTC_INST_LOWER_BOUND);
  1726. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1727. if (val != le32_to_cpu(*image)) {
  1728. ret = -EIO;
  1729. errcnt++;
  1730. if (errcnt >= 3)
  1731. break;
  1732. }
  1733. }
  1734. return ret;
  1735. }
  1736. /**
  1737. * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
  1738. * looking at all data.
  1739. */
  1740. static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
  1741. u32 len)
  1742. {
  1743. u32 val;
  1744. u32 save_len = len;
  1745. int ret = 0;
  1746. u32 errcnt;
  1747. IWL_DEBUG_INFO(priv, "ucode inst image size is %u\n", len);
  1748. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  1749. IWL49_RTC_INST_LOWER_BOUND);
  1750. errcnt = 0;
  1751. for (; len > 0; len -= sizeof(u32), image++) {
  1752. /* read data comes through single port, auto-incr addr */
  1753. /* NOTE: Use the debugless read so we don't flood kernel log
  1754. * if IWL_DL_IO is set */
  1755. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1756. if (val != le32_to_cpu(*image)) {
  1757. IWL_ERR(priv, "uCode INST section is invalid at "
  1758. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  1759. save_len - len, val, le32_to_cpu(*image));
  1760. ret = -EIO;
  1761. errcnt++;
  1762. if (errcnt >= 20)
  1763. break;
  1764. }
  1765. }
  1766. if (!errcnt)
  1767. IWL_DEBUG_INFO(priv,
  1768. "ucode image in INSTRUCTION memory is good\n");
  1769. return ret;
  1770. }
  1771. /**
  1772. * iwl_verify_ucode - determine which instruction image is in SRAM,
  1773. * and verify its contents
  1774. */
  1775. int iwl_verify_ucode(struct iwl_priv *priv)
  1776. {
  1777. __le32 *image;
  1778. u32 len;
  1779. int ret;
  1780. /* Try bootstrap */
  1781. image = (__le32 *)priv->ucode_boot.v_addr;
  1782. len = priv->ucode_boot.len;
  1783. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1784. if (!ret) {
  1785. IWL_DEBUG_INFO(priv, "Bootstrap uCode is good in inst SRAM\n");
  1786. return 0;
  1787. }
  1788. /* Try initialize */
  1789. image = (__le32 *)priv->ucode_init.v_addr;
  1790. len = priv->ucode_init.len;
  1791. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1792. if (!ret) {
  1793. IWL_DEBUG_INFO(priv, "Initialize uCode is good in inst SRAM\n");
  1794. return 0;
  1795. }
  1796. /* Try runtime/protocol */
  1797. image = (__le32 *)priv->ucode_code.v_addr;
  1798. len = priv->ucode_code.len;
  1799. ret = iwlcore_verify_inst_sparse(priv, image, len);
  1800. if (!ret) {
  1801. IWL_DEBUG_INFO(priv, "Runtime uCode is good in inst SRAM\n");
  1802. return 0;
  1803. }
  1804. IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  1805. /* Since nothing seems to match, show first several data entries in
  1806. * instruction SRAM, so maybe visual inspection will give a clue.
  1807. * Selection of bootstrap image (vs. other images) is arbitrary. */
  1808. image = (__le32 *)priv->ucode_boot.v_addr;
  1809. len = priv->ucode_boot.len;
  1810. ret = iwl_verify_inst_full(priv, image, len);
  1811. return ret;
  1812. }
  1813. EXPORT_SYMBOL(iwl_verify_ucode);
  1814. void iwl_rf_kill_ct_config(struct iwl_priv *priv)
  1815. {
  1816. struct iwl_ct_kill_config cmd;
  1817. struct iwl_ct_kill_throttling_config adv_cmd;
  1818. unsigned long flags;
  1819. int ret = 0;
  1820. spin_lock_irqsave(&priv->lock, flags);
  1821. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1822. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  1823. spin_unlock_irqrestore(&priv->lock, flags);
  1824. priv->thermal_throttle.ct_kill_toggle = false;
  1825. if (priv->cfg->support_ct_kill_exit) {
  1826. adv_cmd.critical_temperature_enter =
  1827. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  1828. adv_cmd.critical_temperature_exit =
  1829. cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
  1830. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  1831. sizeof(adv_cmd), &adv_cmd);
  1832. if (ret)
  1833. IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
  1834. else
  1835. IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
  1836. "succeeded, "
  1837. "critical temperature enter is %d,"
  1838. "exit is %d\n",
  1839. priv->hw_params.ct_kill_threshold,
  1840. priv->hw_params.ct_kill_exit_threshold);
  1841. } else {
  1842. cmd.critical_temperature_R =
  1843. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  1844. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  1845. sizeof(cmd), &cmd);
  1846. if (ret)
  1847. IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
  1848. else
  1849. IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
  1850. "succeeded, "
  1851. "critical temperature is %d\n",
  1852. priv->hw_params.ct_kill_threshold);
  1853. }
  1854. }
  1855. EXPORT_SYMBOL(iwl_rf_kill_ct_config);
  1856. /*
  1857. * CARD_STATE_CMD
  1858. *
  1859. * Use: Sets the device's internal card state to enable, disable, or halt
  1860. *
  1861. * When in the 'enable' state the card operates as normal.
  1862. * When in the 'disable' state, the card enters into a low power mode.
  1863. * When in the 'halt' state, the card is shut down and must be fully
  1864. * restarted to come back on.
  1865. */
  1866. int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
  1867. {
  1868. struct iwl_host_cmd cmd = {
  1869. .id = REPLY_CARD_STATE_CMD,
  1870. .len = sizeof(u32),
  1871. .data = &flags,
  1872. .flags = meta_flag,
  1873. };
  1874. return iwl_send_cmd(priv, &cmd);
  1875. }
  1876. void iwl_rx_pm_sleep_notif(struct iwl_priv *priv,
  1877. struct iwl_rx_mem_buffer *rxb)
  1878. {
  1879. #ifdef CONFIG_IWLWIFI_DEBUG
  1880. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1881. struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
  1882. IWL_DEBUG_RX(priv, "sleep mode: %d, src: %d\n",
  1883. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  1884. #endif
  1885. }
  1886. EXPORT_SYMBOL(iwl_rx_pm_sleep_notif);
  1887. void iwl_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
  1888. struct iwl_rx_mem_buffer *rxb)
  1889. {
  1890. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1891. u32 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  1892. IWL_DEBUG_RADIO(priv, "Dumping %d bytes of unhandled "
  1893. "notification for %s:\n", len,
  1894. get_cmd_string(pkt->hdr.cmd));
  1895. iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw, len);
  1896. }
  1897. EXPORT_SYMBOL(iwl_rx_pm_debug_statistics_notif);
  1898. void iwl_rx_reply_error(struct iwl_priv *priv,
  1899. struct iwl_rx_mem_buffer *rxb)
  1900. {
  1901. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  1902. IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
  1903. "seq 0x%04X ser 0x%08X\n",
  1904. le32_to_cpu(pkt->u.err_resp.error_type),
  1905. get_cmd_string(pkt->u.err_resp.cmd_id),
  1906. pkt->u.err_resp.cmd_id,
  1907. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  1908. le32_to_cpu(pkt->u.err_resp.error_info));
  1909. }
  1910. EXPORT_SYMBOL(iwl_rx_reply_error);
  1911. void iwl_clear_isr_stats(struct iwl_priv *priv)
  1912. {
  1913. memset(&priv->isr_stats, 0, sizeof(priv->isr_stats));
  1914. }
  1915. int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  1916. const struct ieee80211_tx_queue_params *params)
  1917. {
  1918. struct iwl_priv *priv = hw->priv;
  1919. unsigned long flags;
  1920. int q;
  1921. IWL_DEBUG_MAC80211(priv, "enter\n");
  1922. if (!iwl_is_ready_rf(priv)) {
  1923. IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
  1924. return -EIO;
  1925. }
  1926. if (queue >= AC_NUM) {
  1927. IWL_DEBUG_MAC80211(priv, "leave - queue >= AC_NUM %d\n", queue);
  1928. return 0;
  1929. }
  1930. q = AC_NUM - 1 - queue;
  1931. spin_lock_irqsave(&priv->lock, flags);
  1932. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  1933. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  1934. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  1935. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  1936. cpu_to_le16((params->txop * 32));
  1937. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  1938. priv->qos_data.qos_active = 1;
  1939. if (priv->iw_mode == NL80211_IFTYPE_AP)
  1940. iwl_activate_qos(priv, 1);
  1941. else if (priv->assoc_id && iwl_is_associated(priv))
  1942. iwl_activate_qos(priv, 0);
  1943. spin_unlock_irqrestore(&priv->lock, flags);
  1944. IWL_DEBUG_MAC80211(priv, "leave\n");
  1945. return 0;
  1946. }
  1947. EXPORT_SYMBOL(iwl_mac_conf_tx);
  1948. static void iwl_ht_conf(struct iwl_priv *priv,
  1949. struct ieee80211_bss_conf *bss_conf)
  1950. {
  1951. struct iwl_ht_config *ht_conf = &priv->current_ht_config;
  1952. struct ieee80211_sta *sta;
  1953. IWL_DEBUG_MAC80211(priv, "enter: \n");
  1954. if (!ht_conf->is_ht)
  1955. return;
  1956. ht_conf->ht_protection =
  1957. bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
  1958. ht_conf->non_GF_STA_present =
  1959. !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
  1960. ht_conf->single_chain_sufficient = false;
  1961. switch (priv->iw_mode) {
  1962. case NL80211_IFTYPE_STATION:
  1963. rcu_read_lock();
  1964. sta = ieee80211_find_sta(priv->hw, priv->bssid);
  1965. if (sta) {
  1966. struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
  1967. int maxstreams;
  1968. maxstreams = (ht_cap->mcs.tx_params &
  1969. IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
  1970. >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
  1971. maxstreams += 1;
  1972. if ((ht_cap->mcs.rx_mask[1] == 0) &&
  1973. (ht_cap->mcs.rx_mask[2] == 0))
  1974. ht_conf->single_chain_sufficient = true;
  1975. if (maxstreams <= 1)
  1976. ht_conf->single_chain_sufficient = true;
  1977. } else {
  1978. /*
  1979. * If at all, this can only happen through a race
  1980. * when the AP disconnects us while we're still
  1981. * setting up the connection, in that case mac80211
  1982. * will soon tell us about that.
  1983. */
  1984. ht_conf->single_chain_sufficient = true;
  1985. }
  1986. rcu_read_unlock();
  1987. break;
  1988. case NL80211_IFTYPE_ADHOC:
  1989. ht_conf->single_chain_sufficient = true;
  1990. break;
  1991. default:
  1992. break;
  1993. }
  1994. IWL_DEBUG_MAC80211(priv, "leave\n");
  1995. }
  1996. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  1997. void iwl_bss_info_changed(struct ieee80211_hw *hw,
  1998. struct ieee80211_vif *vif,
  1999. struct ieee80211_bss_conf *bss_conf,
  2000. u32 changes)
  2001. {
  2002. struct iwl_priv *priv = hw->priv;
  2003. int ret;
  2004. IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes);
  2005. if (!iwl_is_alive(priv))
  2006. return;
  2007. mutex_lock(&priv->mutex);
  2008. if (changes & BSS_CHANGED_BEACON &&
  2009. priv->iw_mode == NL80211_IFTYPE_AP) {
  2010. dev_kfree_skb(priv->ibss_beacon);
  2011. priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
  2012. }
  2013. if (changes & BSS_CHANGED_BEACON_INT) {
  2014. priv->beacon_int = bss_conf->beacon_int;
  2015. /* TODO: in AP mode, do something to make this take effect */
  2016. }
  2017. if (changes & BSS_CHANGED_BSSID) {
  2018. IWL_DEBUG_MAC80211(priv, "BSSID %pM\n", bss_conf->bssid);
  2019. /*
  2020. * If there is currently a HW scan going on in the
  2021. * background then we need to cancel it else the RXON
  2022. * below/in post_associate will fail.
  2023. */
  2024. if (iwl_scan_cancel_timeout(priv, 100)) {
  2025. IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
  2026. IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
  2027. mutex_unlock(&priv->mutex);
  2028. return;
  2029. }
  2030. /* mac80211 only sets assoc when in STATION mode */
  2031. if (priv->iw_mode == NL80211_IFTYPE_ADHOC ||
  2032. bss_conf->assoc) {
  2033. memcpy(priv->staging_rxon.bssid_addr,
  2034. bss_conf->bssid, ETH_ALEN);
  2035. /* currently needed in a few places */
  2036. memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
  2037. } else {
  2038. priv->staging_rxon.filter_flags &=
  2039. ~RXON_FILTER_ASSOC_MSK;
  2040. }
  2041. }
  2042. /*
  2043. * This needs to be after setting the BSSID in case
  2044. * mac80211 decides to do both changes at once because
  2045. * it will invoke post_associate.
  2046. */
  2047. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  2048. changes & BSS_CHANGED_BEACON) {
  2049. struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
  2050. if (beacon)
  2051. iwl_mac_beacon_update(hw, beacon);
  2052. }
  2053. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  2054. IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n",
  2055. bss_conf->use_short_preamble);
  2056. if (bss_conf->use_short_preamble)
  2057. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2058. else
  2059. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2060. }
  2061. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  2062. IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot);
  2063. if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
  2064. priv->staging_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
  2065. else
  2066. priv->staging_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  2067. }
  2068. if (changes & BSS_CHANGED_BASIC_RATES) {
  2069. /* XXX use this information
  2070. *
  2071. * To do that, remove code from iwl_set_rate() and put something
  2072. * like this here:
  2073. *
  2074. if (A-band)
  2075. priv->staging_rxon.ofdm_basic_rates =
  2076. bss_conf->basic_rates;
  2077. else
  2078. priv->staging_rxon.ofdm_basic_rates =
  2079. bss_conf->basic_rates >> 4;
  2080. priv->staging_rxon.cck_basic_rates =
  2081. bss_conf->basic_rates & 0xF;
  2082. */
  2083. }
  2084. if (changes & BSS_CHANGED_HT) {
  2085. iwl_ht_conf(priv, bss_conf);
  2086. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2087. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2088. }
  2089. if (changes & BSS_CHANGED_ASSOC) {
  2090. IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc);
  2091. if (bss_conf->assoc) {
  2092. priv->assoc_id = bss_conf->aid;
  2093. priv->beacon_int = bss_conf->beacon_int;
  2094. priv->timestamp = bss_conf->timestamp;
  2095. priv->assoc_capability = bss_conf->assoc_capability;
  2096. iwl_led_associate(priv);
  2097. /*
  2098. * We have just associated, don't start scan too early
  2099. * leave time for EAPOL exchange to complete.
  2100. *
  2101. * XXX: do this in mac80211
  2102. */
  2103. priv->next_scan_jiffies = jiffies +
  2104. IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
  2105. if (!iwl_is_rfkill(priv))
  2106. priv->cfg->ops->lib->post_associate(priv);
  2107. } else {
  2108. priv->assoc_id = 0;
  2109. iwl_led_disassociate(priv);
  2110. }
  2111. }
  2112. if (changes && iwl_is_associated(priv) && priv->assoc_id) {
  2113. IWL_DEBUG_MAC80211(priv, "Changes (%#x) while associated\n",
  2114. changes);
  2115. ret = iwl_send_rxon_assoc(priv);
  2116. if (!ret) {
  2117. /* Sync active_rxon with latest change. */
  2118. memcpy((void *)&priv->active_rxon,
  2119. &priv->staging_rxon,
  2120. sizeof(struct iwl_rxon_cmd));
  2121. }
  2122. }
  2123. mutex_unlock(&priv->mutex);
  2124. IWL_DEBUG_MAC80211(priv, "leave\n");
  2125. }
  2126. EXPORT_SYMBOL(iwl_bss_info_changed);
  2127. int iwl_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  2128. {
  2129. struct iwl_priv *priv = hw->priv;
  2130. unsigned long flags;
  2131. __le64 timestamp;
  2132. IWL_DEBUG_MAC80211(priv, "enter\n");
  2133. if (!iwl_is_ready_rf(priv)) {
  2134. IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
  2135. return -EIO;
  2136. }
  2137. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  2138. IWL_DEBUG_MAC80211(priv, "leave - not IBSS\n");
  2139. return -EIO;
  2140. }
  2141. spin_lock_irqsave(&priv->lock, flags);
  2142. if (priv->ibss_beacon)
  2143. dev_kfree_skb(priv->ibss_beacon);
  2144. priv->ibss_beacon = skb;
  2145. priv->assoc_id = 0;
  2146. timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
  2147. priv->timestamp = le64_to_cpu(timestamp);
  2148. IWL_DEBUG_MAC80211(priv, "leave\n");
  2149. spin_unlock_irqrestore(&priv->lock, flags);
  2150. iwl_reset_qos(priv);
  2151. priv->cfg->ops->lib->post_associate(priv);
  2152. return 0;
  2153. }
  2154. EXPORT_SYMBOL(iwl_mac_beacon_update);
  2155. int iwl_set_mode(struct iwl_priv *priv, int mode)
  2156. {
  2157. if (mode == NL80211_IFTYPE_ADHOC) {
  2158. const struct iwl_channel_info *ch_info;
  2159. ch_info = iwl_get_channel_info(priv,
  2160. priv->band,
  2161. le16_to_cpu(priv->staging_rxon.channel));
  2162. if (!ch_info || !is_channel_ibss(ch_info)) {
  2163. IWL_ERR(priv, "channel %d not IBSS channel\n",
  2164. le16_to_cpu(priv->staging_rxon.channel));
  2165. return -EINVAL;
  2166. }
  2167. }
  2168. iwl_connection_init_rx_config(priv, mode);
  2169. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2170. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2171. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  2172. iwl_clear_stations_table(priv);
  2173. /* dont commit rxon if rf-kill is on*/
  2174. if (!iwl_is_ready_rf(priv))
  2175. return -EAGAIN;
  2176. iwlcore_commit_rxon(priv);
  2177. return 0;
  2178. }
  2179. EXPORT_SYMBOL(iwl_set_mode);
  2180. int iwl_mac_add_interface(struct ieee80211_hw *hw,
  2181. struct ieee80211_if_init_conf *conf)
  2182. {
  2183. struct iwl_priv *priv = hw->priv;
  2184. unsigned long flags;
  2185. IWL_DEBUG_MAC80211(priv, "enter: type %d\n", conf->type);
  2186. if (priv->vif) {
  2187. IWL_DEBUG_MAC80211(priv, "leave - vif != NULL\n");
  2188. return -EOPNOTSUPP;
  2189. }
  2190. spin_lock_irqsave(&priv->lock, flags);
  2191. priv->vif = conf->vif;
  2192. priv->iw_mode = conf->type;
  2193. spin_unlock_irqrestore(&priv->lock, flags);
  2194. mutex_lock(&priv->mutex);
  2195. if (conf->mac_addr) {
  2196. IWL_DEBUG_MAC80211(priv, "Set %pM\n", conf->mac_addr);
  2197. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  2198. }
  2199. if (iwl_set_mode(priv, conf->type) == -EAGAIN)
  2200. /* we are not ready, will run again when ready */
  2201. set_bit(STATUS_MODE_PENDING, &priv->status);
  2202. mutex_unlock(&priv->mutex);
  2203. IWL_DEBUG_MAC80211(priv, "leave\n");
  2204. return 0;
  2205. }
  2206. EXPORT_SYMBOL(iwl_mac_add_interface);
  2207. void iwl_mac_remove_interface(struct ieee80211_hw *hw,
  2208. struct ieee80211_if_init_conf *conf)
  2209. {
  2210. struct iwl_priv *priv = hw->priv;
  2211. IWL_DEBUG_MAC80211(priv, "enter\n");
  2212. mutex_lock(&priv->mutex);
  2213. if (iwl_is_ready_rf(priv)) {
  2214. iwl_scan_cancel_timeout(priv, 100);
  2215. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2216. iwlcore_commit_rxon(priv);
  2217. }
  2218. if (priv->vif == conf->vif) {
  2219. priv->vif = NULL;
  2220. memset(priv->bssid, 0, ETH_ALEN);
  2221. }
  2222. mutex_unlock(&priv->mutex);
  2223. IWL_DEBUG_MAC80211(priv, "leave\n");
  2224. }
  2225. EXPORT_SYMBOL(iwl_mac_remove_interface);
  2226. /**
  2227. * iwl_mac_config - mac80211 config callback
  2228. *
  2229. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  2230. * be set inappropriately and the driver currently sets the hardware up to
  2231. * use it whenever needed.
  2232. */
  2233. int iwl_mac_config(struct ieee80211_hw *hw, u32 changed)
  2234. {
  2235. struct iwl_priv *priv = hw->priv;
  2236. const struct iwl_channel_info *ch_info;
  2237. struct ieee80211_conf *conf = &hw->conf;
  2238. struct iwl_ht_config *ht_conf = &priv->current_ht_config;
  2239. unsigned long flags = 0;
  2240. int ret = 0;
  2241. u16 ch;
  2242. int scan_active = 0;
  2243. mutex_lock(&priv->mutex);
  2244. IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n",
  2245. conf->channel->hw_value, changed);
  2246. if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
  2247. test_bit(STATUS_SCANNING, &priv->status))) {
  2248. scan_active = 1;
  2249. IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
  2250. }
  2251. /* during scanning mac80211 will delay channel setting until
  2252. * scan finish with changed = 0
  2253. */
  2254. if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
  2255. if (scan_active)
  2256. goto set_ch_out;
  2257. ch = ieee80211_frequency_to_channel(conf->channel->center_freq);
  2258. ch_info = iwl_get_channel_info(priv, conf->channel->band, ch);
  2259. if (!is_channel_valid(ch_info)) {
  2260. IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
  2261. ret = -EINVAL;
  2262. goto set_ch_out;
  2263. }
  2264. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  2265. !is_channel_ibss(ch_info)) {
  2266. IWL_ERR(priv, "channel %d in band %d not "
  2267. "IBSS channel\n",
  2268. conf->channel->hw_value, conf->channel->band);
  2269. ret = -EINVAL;
  2270. goto set_ch_out;
  2271. }
  2272. if (iwl_is_associated(priv) &&
  2273. (le16_to_cpu(priv->active_rxon.channel) != ch) &&
  2274. priv->cfg->ops->lib->set_channel_switch) {
  2275. ret = priv->cfg->ops->lib->set_channel_switch(priv,
  2276. ch);
  2277. goto out;
  2278. }
  2279. spin_lock_irqsave(&priv->lock, flags);
  2280. /* Configure HT40 channels */
  2281. ht_conf->is_ht = conf_is_ht(conf);
  2282. if (ht_conf->is_ht) {
  2283. if (conf_is_ht40_minus(conf)) {
  2284. ht_conf->extension_chan_offset =
  2285. IEEE80211_HT_PARAM_CHA_SEC_BELOW;
  2286. ht_conf->is_40mhz = true;
  2287. } else if (conf_is_ht40_plus(conf)) {
  2288. ht_conf->extension_chan_offset =
  2289. IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
  2290. ht_conf->is_40mhz = true;
  2291. } else {
  2292. ht_conf->extension_chan_offset =
  2293. IEEE80211_HT_PARAM_CHA_SEC_NONE;
  2294. ht_conf->is_40mhz = false;
  2295. }
  2296. } else
  2297. ht_conf->is_40mhz = false;
  2298. /* Default to no protection. Protection mode will later be set
  2299. * from BSS config in iwl_ht_conf */
  2300. ht_conf->ht_protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
  2301. /* if we are switching from ht to 2.4 clear flags
  2302. * from any ht related info since 2.4 does not
  2303. * support ht */
  2304. if ((le16_to_cpu(priv->staging_rxon.channel) != ch))
  2305. priv->staging_rxon.flags = 0;
  2306. iwl_set_rxon_channel(priv, conf->channel);
  2307. iwl_set_flags_for_band(priv, conf->channel->band);
  2308. spin_unlock_irqrestore(&priv->lock, flags);
  2309. set_ch_out:
  2310. /* The list of supported rates and rate mask can be different
  2311. * for each band; since the band may have changed, reset
  2312. * the rate mask to what mac80211 lists */
  2313. iwl_set_rate(priv);
  2314. }
  2315. if (changed & (IEEE80211_CONF_CHANGE_PS |
  2316. IEEE80211_CONF_CHANGE_IDLE)) {
  2317. ret = iwl_power_update_mode(priv, false);
  2318. if (ret)
  2319. IWL_DEBUG_MAC80211(priv, "Error setting sleep level\n");
  2320. }
  2321. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  2322. IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
  2323. priv->tx_power_user_lmt, conf->power_level);
  2324. iwl_set_tx_power(priv, conf->power_level, false);
  2325. }
  2326. /* call to ensure that 4965 rx_chain is set properly in monitor mode */
  2327. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2328. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2329. if (!iwl_is_ready(priv)) {
  2330. IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
  2331. goto out;
  2332. }
  2333. if (scan_active)
  2334. goto out;
  2335. if (memcmp(&priv->active_rxon,
  2336. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  2337. iwlcore_commit_rxon(priv);
  2338. else
  2339. IWL_DEBUG_INFO(priv, "Not re-sending same RXON configuration.\n");
  2340. out:
  2341. IWL_DEBUG_MAC80211(priv, "leave\n");
  2342. mutex_unlock(&priv->mutex);
  2343. return ret;
  2344. }
  2345. EXPORT_SYMBOL(iwl_mac_config);
  2346. int iwl_mac_get_tx_stats(struct ieee80211_hw *hw,
  2347. struct ieee80211_tx_queue_stats *stats)
  2348. {
  2349. struct iwl_priv *priv = hw->priv;
  2350. int i, avail;
  2351. struct iwl_tx_queue *txq;
  2352. struct iwl_queue *q;
  2353. unsigned long flags;
  2354. IWL_DEBUG_MAC80211(priv, "enter\n");
  2355. if (!iwl_is_ready_rf(priv)) {
  2356. IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
  2357. return -EIO;
  2358. }
  2359. spin_lock_irqsave(&priv->lock, flags);
  2360. for (i = 0; i < AC_NUM; i++) {
  2361. txq = &priv->txq[i];
  2362. q = &txq->q;
  2363. avail = iwl_queue_space(q);
  2364. stats[i].len = q->n_window - avail;
  2365. stats[i].limit = q->n_window - q->high_mark;
  2366. stats[i].count = q->n_window;
  2367. }
  2368. spin_unlock_irqrestore(&priv->lock, flags);
  2369. IWL_DEBUG_MAC80211(priv, "leave\n");
  2370. return 0;
  2371. }
  2372. EXPORT_SYMBOL(iwl_mac_get_tx_stats);
  2373. void iwl_mac_reset_tsf(struct ieee80211_hw *hw)
  2374. {
  2375. struct iwl_priv *priv = hw->priv;
  2376. unsigned long flags;
  2377. mutex_lock(&priv->mutex);
  2378. IWL_DEBUG_MAC80211(priv, "enter\n");
  2379. spin_lock_irqsave(&priv->lock, flags);
  2380. memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_config));
  2381. spin_unlock_irqrestore(&priv->lock, flags);
  2382. iwl_reset_qos(priv);
  2383. spin_lock_irqsave(&priv->lock, flags);
  2384. priv->assoc_id = 0;
  2385. priv->assoc_capability = 0;
  2386. priv->assoc_station_added = 0;
  2387. /* new association get rid of ibss beacon skb */
  2388. if (priv->ibss_beacon)
  2389. dev_kfree_skb(priv->ibss_beacon);
  2390. priv->ibss_beacon = NULL;
  2391. priv->beacon_int = priv->vif->bss_conf.beacon_int;
  2392. priv->timestamp = 0;
  2393. if ((priv->iw_mode == NL80211_IFTYPE_STATION))
  2394. priv->beacon_int = 0;
  2395. spin_unlock_irqrestore(&priv->lock, flags);
  2396. if (!iwl_is_ready_rf(priv)) {
  2397. IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
  2398. mutex_unlock(&priv->mutex);
  2399. return;
  2400. }
  2401. /* we are restarting association process
  2402. * clear RXON_FILTER_ASSOC_MSK bit
  2403. */
  2404. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  2405. iwl_scan_cancel_timeout(priv, 100);
  2406. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2407. iwlcore_commit_rxon(priv);
  2408. }
  2409. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  2410. IWL_DEBUG_MAC80211(priv, "leave - not in IBSS\n");
  2411. mutex_unlock(&priv->mutex);
  2412. return;
  2413. }
  2414. iwl_set_rate(priv);
  2415. mutex_unlock(&priv->mutex);
  2416. IWL_DEBUG_MAC80211(priv, "leave\n");
  2417. }
  2418. EXPORT_SYMBOL(iwl_mac_reset_tsf);
  2419. int iwl_alloc_txq_mem(struct iwl_priv *priv)
  2420. {
  2421. if (!priv->txq)
  2422. priv->txq = kzalloc(
  2423. sizeof(struct iwl_tx_queue) * priv->cfg->num_of_queues,
  2424. GFP_KERNEL);
  2425. if (!priv->txq) {
  2426. IWL_ERR(priv, "Not enough memory for txq \n");
  2427. return -ENOMEM;
  2428. }
  2429. return 0;
  2430. }
  2431. EXPORT_SYMBOL(iwl_alloc_txq_mem);
  2432. void iwl_free_txq_mem(struct iwl_priv *priv)
  2433. {
  2434. kfree(priv->txq);
  2435. priv->txq = NULL;
  2436. }
  2437. EXPORT_SYMBOL(iwl_free_txq_mem);
  2438. #ifdef CONFIG_IWLWIFI_DEBUGFS
  2439. #define IWL_TRAFFIC_DUMP_SIZE (IWL_TRAFFIC_ENTRY_SIZE * IWL_TRAFFIC_ENTRIES)
  2440. void iwl_reset_traffic_log(struct iwl_priv *priv)
  2441. {
  2442. priv->tx_traffic_idx = 0;
  2443. priv->rx_traffic_idx = 0;
  2444. if (priv->tx_traffic)
  2445. memset(priv->tx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
  2446. if (priv->rx_traffic)
  2447. memset(priv->rx_traffic, 0, IWL_TRAFFIC_DUMP_SIZE);
  2448. }
  2449. int iwl_alloc_traffic_mem(struct iwl_priv *priv)
  2450. {
  2451. u32 traffic_size = IWL_TRAFFIC_DUMP_SIZE;
  2452. if (iwl_debug_level & IWL_DL_TX) {
  2453. if (!priv->tx_traffic) {
  2454. priv->tx_traffic =
  2455. kzalloc(traffic_size, GFP_KERNEL);
  2456. if (!priv->tx_traffic)
  2457. return -ENOMEM;
  2458. }
  2459. }
  2460. if (iwl_debug_level & IWL_DL_RX) {
  2461. if (!priv->rx_traffic) {
  2462. priv->rx_traffic =
  2463. kzalloc(traffic_size, GFP_KERNEL);
  2464. if (!priv->rx_traffic)
  2465. return -ENOMEM;
  2466. }
  2467. }
  2468. iwl_reset_traffic_log(priv);
  2469. return 0;
  2470. }
  2471. EXPORT_SYMBOL(iwl_alloc_traffic_mem);
  2472. void iwl_free_traffic_mem(struct iwl_priv *priv)
  2473. {
  2474. kfree(priv->tx_traffic);
  2475. priv->tx_traffic = NULL;
  2476. kfree(priv->rx_traffic);
  2477. priv->rx_traffic = NULL;
  2478. }
  2479. EXPORT_SYMBOL(iwl_free_traffic_mem);
  2480. void iwl_dbg_log_tx_data_frame(struct iwl_priv *priv,
  2481. u16 length, struct ieee80211_hdr *header)
  2482. {
  2483. __le16 fc;
  2484. u16 len;
  2485. if (likely(!(iwl_debug_level & IWL_DL_TX)))
  2486. return;
  2487. if (!priv->tx_traffic)
  2488. return;
  2489. fc = header->frame_control;
  2490. if (ieee80211_is_data(fc)) {
  2491. len = (length > IWL_TRAFFIC_ENTRY_SIZE)
  2492. ? IWL_TRAFFIC_ENTRY_SIZE : length;
  2493. memcpy((priv->tx_traffic +
  2494. (priv->tx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
  2495. header, len);
  2496. priv->tx_traffic_idx =
  2497. (priv->tx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
  2498. }
  2499. }
  2500. EXPORT_SYMBOL(iwl_dbg_log_tx_data_frame);
  2501. void iwl_dbg_log_rx_data_frame(struct iwl_priv *priv,
  2502. u16 length, struct ieee80211_hdr *header)
  2503. {
  2504. __le16 fc;
  2505. u16 len;
  2506. if (likely(!(iwl_debug_level & IWL_DL_RX)))
  2507. return;
  2508. if (!priv->rx_traffic)
  2509. return;
  2510. fc = header->frame_control;
  2511. if (ieee80211_is_data(fc)) {
  2512. len = (length > IWL_TRAFFIC_ENTRY_SIZE)
  2513. ? IWL_TRAFFIC_ENTRY_SIZE : length;
  2514. memcpy((priv->rx_traffic +
  2515. (priv->rx_traffic_idx * IWL_TRAFFIC_ENTRY_SIZE)),
  2516. header, len);
  2517. priv->rx_traffic_idx =
  2518. (priv->rx_traffic_idx + 1) % IWL_TRAFFIC_ENTRIES;
  2519. }
  2520. }
  2521. EXPORT_SYMBOL(iwl_dbg_log_rx_data_frame);
  2522. const char *get_mgmt_string(int cmd)
  2523. {
  2524. switch (cmd) {
  2525. IWL_CMD(MANAGEMENT_ASSOC_REQ);
  2526. IWL_CMD(MANAGEMENT_ASSOC_RESP);
  2527. IWL_CMD(MANAGEMENT_REASSOC_REQ);
  2528. IWL_CMD(MANAGEMENT_REASSOC_RESP);
  2529. IWL_CMD(MANAGEMENT_PROBE_REQ);
  2530. IWL_CMD(MANAGEMENT_PROBE_RESP);
  2531. IWL_CMD(MANAGEMENT_BEACON);
  2532. IWL_CMD(MANAGEMENT_ATIM);
  2533. IWL_CMD(MANAGEMENT_DISASSOC);
  2534. IWL_CMD(MANAGEMENT_AUTH);
  2535. IWL_CMD(MANAGEMENT_DEAUTH);
  2536. IWL_CMD(MANAGEMENT_ACTION);
  2537. default:
  2538. return "UNKNOWN";
  2539. }
  2540. }
  2541. const char *get_ctrl_string(int cmd)
  2542. {
  2543. switch (cmd) {
  2544. IWL_CMD(CONTROL_BACK_REQ);
  2545. IWL_CMD(CONTROL_BACK);
  2546. IWL_CMD(CONTROL_PSPOLL);
  2547. IWL_CMD(CONTROL_RTS);
  2548. IWL_CMD(CONTROL_CTS);
  2549. IWL_CMD(CONTROL_ACK);
  2550. IWL_CMD(CONTROL_CFEND);
  2551. IWL_CMD(CONTROL_CFENDACK);
  2552. default:
  2553. return "UNKNOWN";
  2554. }
  2555. }
  2556. void iwl_clear_tx_stats(struct iwl_priv *priv)
  2557. {
  2558. memset(&priv->tx_stats, 0, sizeof(struct traffic_stats));
  2559. }
  2560. void iwl_clear_rx_stats(struct iwl_priv *priv)
  2561. {
  2562. memset(&priv->rx_stats, 0, sizeof(struct traffic_stats));
  2563. }
  2564. /*
  2565. * if CONFIG_IWLWIFI_DEBUGFS defined, iwl_update_stats function will
  2566. * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass.
  2567. * Use debugFs to display the rx/rx_statistics
  2568. * if CONFIG_IWLWIFI_DEBUGFS not being defined, then no MGMT and CTRL
  2569. * information will be recorded, but DATA pkt still will be recorded
  2570. * for the reason of iwl_led.c need to control the led blinking based on
  2571. * number of tx and rx data.
  2572. *
  2573. */
  2574. void iwl_update_stats(struct iwl_priv *priv, bool is_tx, __le16 fc, u16 len)
  2575. {
  2576. struct traffic_stats *stats;
  2577. if (is_tx)
  2578. stats = &priv->tx_stats;
  2579. else
  2580. stats = &priv->rx_stats;
  2581. if (ieee80211_is_mgmt(fc)) {
  2582. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  2583. case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
  2584. stats->mgmt[MANAGEMENT_ASSOC_REQ]++;
  2585. break;
  2586. case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
  2587. stats->mgmt[MANAGEMENT_ASSOC_RESP]++;
  2588. break;
  2589. case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
  2590. stats->mgmt[MANAGEMENT_REASSOC_REQ]++;
  2591. break;
  2592. case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
  2593. stats->mgmt[MANAGEMENT_REASSOC_RESP]++;
  2594. break;
  2595. case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ):
  2596. stats->mgmt[MANAGEMENT_PROBE_REQ]++;
  2597. break;
  2598. case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
  2599. stats->mgmt[MANAGEMENT_PROBE_RESP]++;
  2600. break;
  2601. case cpu_to_le16(IEEE80211_STYPE_BEACON):
  2602. stats->mgmt[MANAGEMENT_BEACON]++;
  2603. break;
  2604. case cpu_to_le16(IEEE80211_STYPE_ATIM):
  2605. stats->mgmt[MANAGEMENT_ATIM]++;
  2606. break;
  2607. case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
  2608. stats->mgmt[MANAGEMENT_DISASSOC]++;
  2609. break;
  2610. case cpu_to_le16(IEEE80211_STYPE_AUTH):
  2611. stats->mgmt[MANAGEMENT_AUTH]++;
  2612. break;
  2613. case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
  2614. stats->mgmt[MANAGEMENT_DEAUTH]++;
  2615. break;
  2616. case cpu_to_le16(IEEE80211_STYPE_ACTION):
  2617. stats->mgmt[MANAGEMENT_ACTION]++;
  2618. break;
  2619. }
  2620. } else if (ieee80211_is_ctl(fc)) {
  2621. switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
  2622. case cpu_to_le16(IEEE80211_STYPE_BACK_REQ):
  2623. stats->ctrl[CONTROL_BACK_REQ]++;
  2624. break;
  2625. case cpu_to_le16(IEEE80211_STYPE_BACK):
  2626. stats->ctrl[CONTROL_BACK]++;
  2627. break;
  2628. case cpu_to_le16(IEEE80211_STYPE_PSPOLL):
  2629. stats->ctrl[CONTROL_PSPOLL]++;
  2630. break;
  2631. case cpu_to_le16(IEEE80211_STYPE_RTS):
  2632. stats->ctrl[CONTROL_RTS]++;
  2633. break;
  2634. case cpu_to_le16(IEEE80211_STYPE_CTS):
  2635. stats->ctrl[CONTROL_CTS]++;
  2636. break;
  2637. case cpu_to_le16(IEEE80211_STYPE_ACK):
  2638. stats->ctrl[CONTROL_ACK]++;
  2639. break;
  2640. case cpu_to_le16(IEEE80211_STYPE_CFEND):
  2641. stats->ctrl[CONTROL_CFEND]++;
  2642. break;
  2643. case cpu_to_le16(IEEE80211_STYPE_CFENDACK):
  2644. stats->ctrl[CONTROL_CFENDACK]++;
  2645. break;
  2646. }
  2647. } else {
  2648. /* data */
  2649. stats->data_cnt++;
  2650. stats->data_bytes += len;
  2651. }
  2652. }
  2653. EXPORT_SYMBOL(iwl_update_stats);
  2654. #endif
  2655. #ifdef CONFIG_PM
  2656. int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  2657. {
  2658. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2659. /*
  2660. * This function is called when system goes into suspend state
  2661. * mac80211 will call iwl_mac_stop() from the mac80211 suspend function
  2662. * first but since iwl_mac_stop() has no knowledge of who the caller is,
  2663. * it will not call apm_ops.stop() to stop the DMA operation.
  2664. * Calling apm_ops.stop here to make sure we stop the DMA.
  2665. */
  2666. priv->cfg->ops->lib->apm_ops.stop(priv);
  2667. pci_save_state(pdev);
  2668. pci_disable_device(pdev);
  2669. pci_set_power_state(pdev, PCI_D3hot);
  2670. return 0;
  2671. }
  2672. EXPORT_SYMBOL(iwl_pci_suspend);
  2673. int iwl_pci_resume(struct pci_dev *pdev)
  2674. {
  2675. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2676. int ret;
  2677. pci_set_power_state(pdev, PCI_D0);
  2678. ret = pci_enable_device(pdev);
  2679. if (ret)
  2680. return ret;
  2681. pci_restore_state(pdev);
  2682. iwl_enable_interrupts(priv);
  2683. return 0;
  2684. }
  2685. EXPORT_SYMBOL(iwl_pci_resume);
  2686. #endif /* CONFIG_PM */