bnx2x_stats.c 50 KB

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  1. /* bnx2x_stats.c: Broadcom Everest network driver.
  2. *
  3. * Copyright (c) 2007-2012 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10. * Written by: Eliezer Tamir
  11. * Based on code from Michael Chan's bnx2 driver
  12. * UDP CSUM errata workaround by Arik Gendelman
  13. * Slowpath and fastpath rework by Vladislav Zolotarov
  14. * Statistics and Link management by Yitchak Gertner
  15. *
  16. */
  17. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18. #include "bnx2x_stats.h"
  19. #include "bnx2x_cmn.h"
  20. /* Statistics */
  21. /*
  22. * General service functions
  23. */
  24. static inline long bnx2x_hilo(u32 *hiref)
  25. {
  26. u32 lo = *(hiref + 1);
  27. #if (BITS_PER_LONG == 64)
  28. u32 hi = *hiref;
  29. return HILO_U64(hi, lo);
  30. #else
  31. return lo;
  32. #endif
  33. }
  34. static u16 bnx2x_get_port_stats_dma_len(struct bnx2x *bp)
  35. {
  36. u16 res = sizeof(struct host_port_stats) >> 2;
  37. /* if PFC stats are not supported by the MFW, don't DMA them */
  38. if (!(bp->flags & BC_SUPPORTS_PFC_STATS))
  39. res -= (sizeof(u32)*4) >> 2;
  40. return res;
  41. }
  42. /*
  43. * Init service functions
  44. */
  45. /* Post the next statistics ramrod. Protect it with the spin in
  46. * order to ensure the strict order between statistics ramrods
  47. * (each ramrod has a sequence number passed in a
  48. * bp->fw_stats_req->hdr.drv_stats_counter and ramrods must be
  49. * sent in order).
  50. */
  51. static void bnx2x_storm_stats_post(struct bnx2x *bp)
  52. {
  53. if (!bp->stats_pending) {
  54. int rc;
  55. spin_lock_bh(&bp->stats_lock);
  56. if (bp->stats_pending) {
  57. spin_unlock_bh(&bp->stats_lock);
  58. return;
  59. }
  60. bp->fw_stats_req->hdr.drv_stats_counter =
  61. cpu_to_le16(bp->stats_counter++);
  62. DP(BNX2X_MSG_STATS, "Sending statistics ramrod %d\n",
  63. bp->fw_stats_req->hdr.drv_stats_counter);
  64. /* send FW stats ramrod */
  65. rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_STAT_QUERY, 0,
  66. U64_HI(bp->fw_stats_req_mapping),
  67. U64_LO(bp->fw_stats_req_mapping),
  68. NONE_CONNECTION_TYPE);
  69. if (rc == 0)
  70. bp->stats_pending = 1;
  71. spin_unlock_bh(&bp->stats_lock);
  72. }
  73. }
  74. static void bnx2x_hw_stats_post(struct bnx2x *bp)
  75. {
  76. struct dmae_command *dmae = &bp->stats_dmae;
  77. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  78. *stats_comp = DMAE_COMP_VAL;
  79. if (CHIP_REV_IS_SLOW(bp))
  80. return;
  81. /* loader */
  82. if (bp->executer_idx) {
  83. int loader_idx = PMF_DMAE_C(bp);
  84. u32 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
  85. true, DMAE_COMP_GRC);
  86. opcode = bnx2x_dmae_opcode_clr_src_reset(opcode);
  87. memset(dmae, 0, sizeof(struct dmae_command));
  88. dmae->opcode = opcode;
  89. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
  90. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
  91. dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
  92. sizeof(struct dmae_command) *
  93. (loader_idx + 1)) >> 2;
  94. dmae->dst_addr_hi = 0;
  95. dmae->len = sizeof(struct dmae_command) >> 2;
  96. if (CHIP_IS_E1(bp))
  97. dmae->len--;
  98. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
  99. dmae->comp_addr_hi = 0;
  100. dmae->comp_val = 1;
  101. *stats_comp = 0;
  102. bnx2x_post_dmae(bp, dmae, loader_idx);
  103. } else if (bp->func_stx) {
  104. *stats_comp = 0;
  105. bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
  106. }
  107. }
  108. static int bnx2x_stats_comp(struct bnx2x *bp)
  109. {
  110. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  111. int cnt = 10;
  112. might_sleep();
  113. while (*stats_comp != DMAE_COMP_VAL) {
  114. if (!cnt) {
  115. BNX2X_ERR("timeout waiting for stats finished\n");
  116. break;
  117. }
  118. cnt--;
  119. usleep_range(1000, 1000);
  120. }
  121. return 1;
  122. }
  123. /*
  124. * Statistics service functions
  125. */
  126. static void bnx2x_stats_pmf_update(struct bnx2x *bp)
  127. {
  128. struct dmae_command *dmae;
  129. u32 opcode;
  130. int loader_idx = PMF_DMAE_C(bp);
  131. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  132. /* sanity */
  133. if (!bp->port.pmf || !bp->port.port_stx) {
  134. BNX2X_ERR("BUG!\n");
  135. return;
  136. }
  137. bp->executer_idx = 0;
  138. opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI, false, 0);
  139. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  140. dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_GRC);
  141. dmae->src_addr_lo = bp->port.port_stx >> 2;
  142. dmae->src_addr_hi = 0;
  143. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
  144. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
  145. dmae->len = DMAE_LEN32_RD_MAX;
  146. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  147. dmae->comp_addr_hi = 0;
  148. dmae->comp_val = 1;
  149. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  150. dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);
  151. dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX;
  152. dmae->src_addr_hi = 0;
  153. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) +
  154. DMAE_LEN32_RD_MAX * 4);
  155. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats) +
  156. DMAE_LEN32_RD_MAX * 4);
  157. dmae->len = bnx2x_get_port_stats_dma_len(bp) - DMAE_LEN32_RD_MAX;
  158. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  159. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  160. dmae->comp_val = DMAE_COMP_VAL;
  161. *stats_comp = 0;
  162. bnx2x_hw_stats_post(bp);
  163. bnx2x_stats_comp(bp);
  164. }
  165. static void bnx2x_port_stats_init(struct bnx2x *bp)
  166. {
  167. struct dmae_command *dmae;
  168. int port = BP_PORT(bp);
  169. u32 opcode;
  170. int loader_idx = PMF_DMAE_C(bp);
  171. u32 mac_addr;
  172. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  173. /* sanity */
  174. if (!bp->link_vars.link_up || !bp->port.pmf) {
  175. BNX2X_ERR("BUG!\n");
  176. return;
  177. }
  178. bp->executer_idx = 0;
  179. /* MCP */
  180. opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
  181. true, DMAE_COMP_GRC);
  182. if (bp->port.port_stx) {
  183. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  184. dmae->opcode = opcode;
  185. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
  186. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
  187. dmae->dst_addr_lo = bp->port.port_stx >> 2;
  188. dmae->dst_addr_hi = 0;
  189. dmae->len = bnx2x_get_port_stats_dma_len(bp);
  190. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  191. dmae->comp_addr_hi = 0;
  192. dmae->comp_val = 1;
  193. }
  194. if (bp->func_stx) {
  195. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  196. dmae->opcode = opcode;
  197. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
  198. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
  199. dmae->dst_addr_lo = bp->func_stx >> 2;
  200. dmae->dst_addr_hi = 0;
  201. dmae->len = sizeof(struct host_func_stats) >> 2;
  202. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  203. dmae->comp_addr_hi = 0;
  204. dmae->comp_val = 1;
  205. }
  206. /* MAC */
  207. opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
  208. true, DMAE_COMP_GRC);
  209. /* EMAC is special */
  210. if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
  211. mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
  212. /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
  213. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  214. dmae->opcode = opcode;
  215. dmae->src_addr_lo = (mac_addr +
  216. EMAC_REG_EMAC_RX_STAT_AC) >> 2;
  217. dmae->src_addr_hi = 0;
  218. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
  219. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
  220. dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
  221. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  222. dmae->comp_addr_hi = 0;
  223. dmae->comp_val = 1;
  224. /* EMAC_REG_EMAC_RX_STAT_AC_28 */
  225. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  226. dmae->opcode = opcode;
  227. dmae->src_addr_lo = (mac_addr +
  228. EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
  229. dmae->src_addr_hi = 0;
  230. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
  231. offsetof(struct emac_stats, rx_stat_falsecarriererrors));
  232. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
  233. offsetof(struct emac_stats, rx_stat_falsecarriererrors));
  234. dmae->len = 1;
  235. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  236. dmae->comp_addr_hi = 0;
  237. dmae->comp_val = 1;
  238. /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
  239. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  240. dmae->opcode = opcode;
  241. dmae->src_addr_lo = (mac_addr +
  242. EMAC_REG_EMAC_TX_STAT_AC) >> 2;
  243. dmae->src_addr_hi = 0;
  244. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
  245. offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
  246. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
  247. offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
  248. dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
  249. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  250. dmae->comp_addr_hi = 0;
  251. dmae->comp_val = 1;
  252. } else {
  253. u32 tx_src_addr_lo, rx_src_addr_lo;
  254. u16 rx_len, tx_len;
  255. /* configure the params according to MAC type */
  256. switch (bp->link_vars.mac_type) {
  257. case MAC_TYPE_BMAC:
  258. mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
  259. NIG_REG_INGRESS_BMAC0_MEM);
  260. /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
  261. BIGMAC_REGISTER_TX_STAT_GTBYT */
  262. if (CHIP_IS_E1x(bp)) {
  263. tx_src_addr_lo = (mac_addr +
  264. BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
  265. tx_len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
  266. BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
  267. rx_src_addr_lo = (mac_addr +
  268. BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
  269. rx_len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
  270. BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
  271. } else {
  272. tx_src_addr_lo = (mac_addr +
  273. BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2;
  274. tx_len = (8 + BIGMAC2_REGISTER_TX_STAT_GTBYT -
  275. BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2;
  276. rx_src_addr_lo = (mac_addr +
  277. BIGMAC2_REGISTER_RX_STAT_GR64) >> 2;
  278. rx_len = (8 + BIGMAC2_REGISTER_RX_STAT_GRIPJ -
  279. BIGMAC2_REGISTER_RX_STAT_GR64) >> 2;
  280. }
  281. break;
  282. case MAC_TYPE_UMAC: /* handled by MSTAT */
  283. case MAC_TYPE_XMAC: /* handled by MSTAT */
  284. default:
  285. mac_addr = port ? GRCBASE_MSTAT1 : GRCBASE_MSTAT0;
  286. tx_src_addr_lo = (mac_addr +
  287. MSTAT_REG_TX_STAT_GTXPOK_LO) >> 2;
  288. rx_src_addr_lo = (mac_addr +
  289. MSTAT_REG_RX_STAT_GR64_LO) >> 2;
  290. tx_len = sizeof(bp->slowpath->
  291. mac_stats.mstat_stats.stats_tx) >> 2;
  292. rx_len = sizeof(bp->slowpath->
  293. mac_stats.mstat_stats.stats_rx) >> 2;
  294. break;
  295. }
  296. /* TX stats */
  297. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  298. dmae->opcode = opcode;
  299. dmae->src_addr_lo = tx_src_addr_lo;
  300. dmae->src_addr_hi = 0;
  301. dmae->len = tx_len;
  302. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
  303. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
  304. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  305. dmae->comp_addr_hi = 0;
  306. dmae->comp_val = 1;
  307. /* RX stats */
  308. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  309. dmae->opcode = opcode;
  310. dmae->src_addr_hi = 0;
  311. dmae->src_addr_lo = rx_src_addr_lo;
  312. dmae->dst_addr_lo =
  313. U64_LO(bnx2x_sp_mapping(bp, mac_stats) + (tx_len << 2));
  314. dmae->dst_addr_hi =
  315. U64_HI(bnx2x_sp_mapping(bp, mac_stats) + (tx_len << 2));
  316. dmae->len = rx_len;
  317. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  318. dmae->comp_addr_hi = 0;
  319. dmae->comp_val = 1;
  320. }
  321. /* NIG */
  322. if (!CHIP_IS_E3(bp)) {
  323. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  324. dmae->opcode = opcode;
  325. dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
  326. NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
  327. dmae->src_addr_hi = 0;
  328. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
  329. offsetof(struct nig_stats, egress_mac_pkt0_lo));
  330. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
  331. offsetof(struct nig_stats, egress_mac_pkt0_lo));
  332. dmae->len = (2*sizeof(u32)) >> 2;
  333. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  334. dmae->comp_addr_hi = 0;
  335. dmae->comp_val = 1;
  336. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  337. dmae->opcode = opcode;
  338. dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
  339. NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
  340. dmae->src_addr_hi = 0;
  341. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
  342. offsetof(struct nig_stats, egress_mac_pkt1_lo));
  343. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
  344. offsetof(struct nig_stats, egress_mac_pkt1_lo));
  345. dmae->len = (2*sizeof(u32)) >> 2;
  346. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  347. dmae->comp_addr_hi = 0;
  348. dmae->comp_val = 1;
  349. }
  350. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  351. dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
  352. true, DMAE_COMP_PCI);
  353. dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
  354. NIG_REG_STAT0_BRB_DISCARD) >> 2;
  355. dmae->src_addr_hi = 0;
  356. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats));
  357. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats));
  358. dmae->len = (sizeof(struct nig_stats) - 4*sizeof(u32)) >> 2;
  359. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  360. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  361. dmae->comp_val = DMAE_COMP_VAL;
  362. *stats_comp = 0;
  363. }
  364. static void bnx2x_func_stats_init(struct bnx2x *bp)
  365. {
  366. struct dmae_command *dmae = &bp->stats_dmae;
  367. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  368. /* sanity */
  369. if (!bp->func_stx) {
  370. BNX2X_ERR("BUG!\n");
  371. return;
  372. }
  373. bp->executer_idx = 0;
  374. memset(dmae, 0, sizeof(struct dmae_command));
  375. dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
  376. true, DMAE_COMP_PCI);
  377. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
  378. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
  379. dmae->dst_addr_lo = bp->func_stx >> 2;
  380. dmae->dst_addr_hi = 0;
  381. dmae->len = sizeof(struct host_func_stats) >> 2;
  382. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  383. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  384. dmae->comp_val = DMAE_COMP_VAL;
  385. *stats_comp = 0;
  386. }
  387. static void bnx2x_stats_start(struct bnx2x *bp)
  388. {
  389. if (bp->port.pmf)
  390. bnx2x_port_stats_init(bp);
  391. else if (bp->func_stx)
  392. bnx2x_func_stats_init(bp);
  393. bnx2x_hw_stats_post(bp);
  394. bnx2x_storm_stats_post(bp);
  395. }
  396. static void bnx2x_stats_pmf_start(struct bnx2x *bp)
  397. {
  398. bnx2x_stats_comp(bp);
  399. bnx2x_stats_pmf_update(bp);
  400. bnx2x_stats_start(bp);
  401. }
  402. static void bnx2x_stats_restart(struct bnx2x *bp)
  403. {
  404. bnx2x_stats_comp(bp);
  405. bnx2x_stats_start(bp);
  406. }
  407. static void bnx2x_bmac_stats_update(struct bnx2x *bp)
  408. {
  409. struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
  410. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  411. struct {
  412. u32 lo;
  413. u32 hi;
  414. } diff;
  415. if (CHIP_IS_E1x(bp)) {
  416. struct bmac1_stats *new = bnx2x_sp(bp, mac_stats.bmac1_stats);
  417. /* the macros below will use "bmac1_stats" type */
  418. UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
  419. UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
  420. UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
  421. UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
  422. UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
  423. UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
  424. UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
  425. UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
  426. UPDATE_STAT64(rx_stat_grxpf, rx_stat_mac_xpf);
  427. UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
  428. UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
  429. UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
  430. UPDATE_STAT64(tx_stat_gt127,
  431. tx_stat_etherstatspkts65octetsto127octets);
  432. UPDATE_STAT64(tx_stat_gt255,
  433. tx_stat_etherstatspkts128octetsto255octets);
  434. UPDATE_STAT64(tx_stat_gt511,
  435. tx_stat_etherstatspkts256octetsto511octets);
  436. UPDATE_STAT64(tx_stat_gt1023,
  437. tx_stat_etherstatspkts512octetsto1023octets);
  438. UPDATE_STAT64(tx_stat_gt1518,
  439. tx_stat_etherstatspkts1024octetsto1522octets);
  440. UPDATE_STAT64(tx_stat_gt2047, tx_stat_mac_2047);
  441. UPDATE_STAT64(tx_stat_gt4095, tx_stat_mac_4095);
  442. UPDATE_STAT64(tx_stat_gt9216, tx_stat_mac_9216);
  443. UPDATE_STAT64(tx_stat_gt16383, tx_stat_mac_16383);
  444. UPDATE_STAT64(tx_stat_gterr,
  445. tx_stat_dot3statsinternalmactransmiterrors);
  446. UPDATE_STAT64(tx_stat_gtufl, tx_stat_mac_ufl);
  447. } else {
  448. struct bmac2_stats *new = bnx2x_sp(bp, mac_stats.bmac2_stats);
  449. /* the macros below will use "bmac2_stats" type */
  450. UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
  451. UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
  452. UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
  453. UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
  454. UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
  455. UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
  456. UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
  457. UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
  458. UPDATE_STAT64(rx_stat_grxpf, rx_stat_mac_xpf);
  459. UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
  460. UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
  461. UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
  462. UPDATE_STAT64(tx_stat_gt127,
  463. tx_stat_etherstatspkts65octetsto127octets);
  464. UPDATE_STAT64(tx_stat_gt255,
  465. tx_stat_etherstatspkts128octetsto255octets);
  466. UPDATE_STAT64(tx_stat_gt511,
  467. tx_stat_etherstatspkts256octetsto511octets);
  468. UPDATE_STAT64(tx_stat_gt1023,
  469. tx_stat_etherstatspkts512octetsto1023octets);
  470. UPDATE_STAT64(tx_stat_gt1518,
  471. tx_stat_etherstatspkts1024octetsto1522octets);
  472. UPDATE_STAT64(tx_stat_gt2047, tx_stat_mac_2047);
  473. UPDATE_STAT64(tx_stat_gt4095, tx_stat_mac_4095);
  474. UPDATE_STAT64(tx_stat_gt9216, tx_stat_mac_9216);
  475. UPDATE_STAT64(tx_stat_gt16383, tx_stat_mac_16383);
  476. UPDATE_STAT64(tx_stat_gterr,
  477. tx_stat_dot3statsinternalmactransmiterrors);
  478. UPDATE_STAT64(tx_stat_gtufl, tx_stat_mac_ufl);
  479. /* collect PFC stats */
  480. pstats->pfc_frames_tx_hi = new->tx_stat_gtpp_hi;
  481. pstats->pfc_frames_tx_lo = new->tx_stat_gtpp_lo;
  482. pstats->pfc_frames_rx_hi = new->rx_stat_grpp_hi;
  483. pstats->pfc_frames_rx_lo = new->rx_stat_grpp_lo;
  484. }
  485. estats->pause_frames_received_hi =
  486. pstats->mac_stx[1].rx_stat_mac_xpf_hi;
  487. estats->pause_frames_received_lo =
  488. pstats->mac_stx[1].rx_stat_mac_xpf_lo;
  489. estats->pause_frames_sent_hi =
  490. pstats->mac_stx[1].tx_stat_outxoffsent_hi;
  491. estats->pause_frames_sent_lo =
  492. pstats->mac_stx[1].tx_stat_outxoffsent_lo;
  493. estats->pfc_frames_received_hi =
  494. pstats->pfc_frames_rx_hi;
  495. estats->pfc_frames_received_lo =
  496. pstats->pfc_frames_rx_lo;
  497. estats->pfc_frames_sent_hi =
  498. pstats->pfc_frames_tx_hi;
  499. estats->pfc_frames_sent_lo =
  500. pstats->pfc_frames_tx_lo;
  501. }
  502. static void bnx2x_mstat_stats_update(struct bnx2x *bp)
  503. {
  504. struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
  505. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  506. struct mstat_stats *new = bnx2x_sp(bp, mac_stats.mstat_stats);
  507. ADD_STAT64(stats_rx.rx_grerb, rx_stat_ifhcinbadoctets);
  508. ADD_STAT64(stats_rx.rx_grfcs, rx_stat_dot3statsfcserrors);
  509. ADD_STAT64(stats_rx.rx_grund, rx_stat_etherstatsundersizepkts);
  510. ADD_STAT64(stats_rx.rx_grovr, rx_stat_dot3statsframestoolong);
  511. ADD_STAT64(stats_rx.rx_grfrg, rx_stat_etherstatsfragments);
  512. ADD_STAT64(stats_rx.rx_grxcf, rx_stat_maccontrolframesreceived);
  513. ADD_STAT64(stats_rx.rx_grxpf, rx_stat_xoffstateentered);
  514. ADD_STAT64(stats_rx.rx_grxpf, rx_stat_mac_xpf);
  515. ADD_STAT64(stats_tx.tx_gtxpf, tx_stat_outxoffsent);
  516. ADD_STAT64(stats_tx.tx_gtxpf, tx_stat_flowcontroldone);
  517. /* collect pfc stats */
  518. ADD_64(pstats->pfc_frames_tx_hi, new->stats_tx.tx_gtxpp_hi,
  519. pstats->pfc_frames_tx_lo, new->stats_tx.tx_gtxpp_lo);
  520. ADD_64(pstats->pfc_frames_rx_hi, new->stats_rx.rx_grxpp_hi,
  521. pstats->pfc_frames_rx_lo, new->stats_rx.rx_grxpp_lo);
  522. ADD_STAT64(stats_tx.tx_gt64, tx_stat_etherstatspkts64octets);
  523. ADD_STAT64(stats_tx.tx_gt127,
  524. tx_stat_etherstatspkts65octetsto127octets);
  525. ADD_STAT64(stats_tx.tx_gt255,
  526. tx_stat_etherstatspkts128octetsto255octets);
  527. ADD_STAT64(stats_tx.tx_gt511,
  528. tx_stat_etherstatspkts256octetsto511octets);
  529. ADD_STAT64(stats_tx.tx_gt1023,
  530. tx_stat_etherstatspkts512octetsto1023octets);
  531. ADD_STAT64(stats_tx.tx_gt1518,
  532. tx_stat_etherstatspkts1024octetsto1522octets);
  533. ADD_STAT64(stats_tx.tx_gt2047, tx_stat_mac_2047);
  534. ADD_STAT64(stats_tx.tx_gt4095, tx_stat_mac_4095);
  535. ADD_STAT64(stats_tx.tx_gt9216, tx_stat_mac_9216);
  536. ADD_STAT64(stats_tx.tx_gt16383, tx_stat_mac_16383);
  537. ADD_STAT64(stats_tx.tx_gterr,
  538. tx_stat_dot3statsinternalmactransmiterrors);
  539. ADD_STAT64(stats_tx.tx_gtufl, tx_stat_mac_ufl);
  540. estats->etherstatspkts1024octetsto1522octets_hi =
  541. pstats->mac_stx[1].tx_stat_etherstatspkts1024octetsto1522octets_hi;
  542. estats->etherstatspkts1024octetsto1522octets_lo =
  543. pstats->mac_stx[1].tx_stat_etherstatspkts1024octetsto1522octets_lo;
  544. estats->etherstatspktsover1522octets_hi =
  545. pstats->mac_stx[1].tx_stat_mac_2047_hi;
  546. estats->etherstatspktsover1522octets_lo =
  547. pstats->mac_stx[1].tx_stat_mac_2047_lo;
  548. ADD_64(estats->etherstatspktsover1522octets_hi,
  549. pstats->mac_stx[1].tx_stat_mac_4095_hi,
  550. estats->etherstatspktsover1522octets_lo,
  551. pstats->mac_stx[1].tx_stat_mac_4095_lo);
  552. ADD_64(estats->etherstatspktsover1522octets_hi,
  553. pstats->mac_stx[1].tx_stat_mac_9216_hi,
  554. estats->etherstatspktsover1522octets_lo,
  555. pstats->mac_stx[1].tx_stat_mac_9216_lo);
  556. ADD_64(estats->etherstatspktsover1522octets_hi,
  557. pstats->mac_stx[1].tx_stat_mac_16383_hi,
  558. estats->etherstatspktsover1522octets_lo,
  559. pstats->mac_stx[1].tx_stat_mac_16383_lo);
  560. estats->pause_frames_received_hi =
  561. pstats->mac_stx[1].rx_stat_mac_xpf_hi;
  562. estats->pause_frames_received_lo =
  563. pstats->mac_stx[1].rx_stat_mac_xpf_lo;
  564. estats->pause_frames_sent_hi =
  565. pstats->mac_stx[1].tx_stat_outxoffsent_hi;
  566. estats->pause_frames_sent_lo =
  567. pstats->mac_stx[1].tx_stat_outxoffsent_lo;
  568. estats->pfc_frames_received_hi =
  569. pstats->pfc_frames_rx_hi;
  570. estats->pfc_frames_received_lo =
  571. pstats->pfc_frames_rx_lo;
  572. estats->pfc_frames_sent_hi =
  573. pstats->pfc_frames_tx_hi;
  574. estats->pfc_frames_sent_lo =
  575. pstats->pfc_frames_tx_lo;
  576. }
  577. static void bnx2x_emac_stats_update(struct bnx2x *bp)
  578. {
  579. struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac_stats);
  580. struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
  581. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  582. UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
  583. UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
  584. UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
  585. UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
  586. UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
  587. UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
  588. UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
  589. UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
  590. UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
  591. UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
  592. UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
  593. UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
  594. UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
  595. UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
  596. UPDATE_EXTEND_STAT(tx_stat_outxonsent);
  597. UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
  598. UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
  599. UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
  600. UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
  601. UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
  602. UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
  603. UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
  604. UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
  605. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
  606. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
  607. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
  608. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
  609. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
  610. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
  611. UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
  612. UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
  613. estats->pause_frames_received_hi =
  614. pstats->mac_stx[1].rx_stat_xonpauseframesreceived_hi;
  615. estats->pause_frames_received_lo =
  616. pstats->mac_stx[1].rx_stat_xonpauseframesreceived_lo;
  617. ADD_64(estats->pause_frames_received_hi,
  618. pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_hi,
  619. estats->pause_frames_received_lo,
  620. pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_lo);
  621. estats->pause_frames_sent_hi =
  622. pstats->mac_stx[1].tx_stat_outxonsent_hi;
  623. estats->pause_frames_sent_lo =
  624. pstats->mac_stx[1].tx_stat_outxonsent_lo;
  625. ADD_64(estats->pause_frames_sent_hi,
  626. pstats->mac_stx[1].tx_stat_outxoffsent_hi,
  627. estats->pause_frames_sent_lo,
  628. pstats->mac_stx[1].tx_stat_outxoffsent_lo);
  629. }
  630. static int bnx2x_hw_stats_update(struct bnx2x *bp)
  631. {
  632. struct nig_stats *new = bnx2x_sp(bp, nig_stats);
  633. struct nig_stats *old = &(bp->port.old_nig_stats);
  634. struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
  635. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  636. struct {
  637. u32 lo;
  638. u32 hi;
  639. } diff;
  640. switch (bp->link_vars.mac_type) {
  641. case MAC_TYPE_BMAC:
  642. bnx2x_bmac_stats_update(bp);
  643. break;
  644. case MAC_TYPE_EMAC:
  645. bnx2x_emac_stats_update(bp);
  646. break;
  647. case MAC_TYPE_UMAC:
  648. case MAC_TYPE_XMAC:
  649. bnx2x_mstat_stats_update(bp);
  650. break;
  651. case MAC_TYPE_NONE: /* unreached */
  652. DP(BNX2X_MSG_STATS,
  653. "stats updated by DMAE but no MAC active\n");
  654. return -1;
  655. default: /* unreached */
  656. BNX2X_ERR("Unknown MAC type\n");
  657. }
  658. ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
  659. new->brb_discard - old->brb_discard);
  660. ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
  661. new->brb_truncate - old->brb_truncate);
  662. if (!CHIP_IS_E3(bp)) {
  663. UPDATE_STAT64_NIG(egress_mac_pkt0,
  664. etherstatspkts1024octetsto1522octets);
  665. UPDATE_STAT64_NIG(egress_mac_pkt1,
  666. etherstatspktsover1522octets);
  667. }
  668. memcpy(old, new, sizeof(struct nig_stats));
  669. memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
  670. sizeof(struct mac_stx));
  671. estats->brb_drop_hi = pstats->brb_drop_hi;
  672. estats->brb_drop_lo = pstats->brb_drop_lo;
  673. pstats->host_port_stats_counter++;
  674. if (!BP_NOMCP(bp)) {
  675. u32 nig_timer_max =
  676. SHMEM_RD(bp, port_mb[BP_PORT(bp)].stat_nig_timer);
  677. if (nig_timer_max != estats->nig_timer_max) {
  678. estats->nig_timer_max = nig_timer_max;
  679. BNX2X_ERR("NIG timer max (%u)\n",
  680. estats->nig_timer_max);
  681. }
  682. }
  683. return 0;
  684. }
  685. static int bnx2x_storm_stats_update(struct bnx2x *bp)
  686. {
  687. struct tstorm_per_port_stats *tport =
  688. &bp->fw_stats_data->port.tstorm_port_statistics;
  689. struct tstorm_per_pf_stats *tfunc =
  690. &bp->fw_stats_data->pf.tstorm_pf_statistics;
  691. struct host_func_stats *fstats = bnx2x_sp(bp, func_stats);
  692. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  693. struct bnx2x_eth_stats_old *estats_old = &bp->eth_stats_old;
  694. struct stats_counter *counters = &bp->fw_stats_data->storm_counters;
  695. int i;
  696. u16 cur_stats_counter;
  697. /* Make sure we use the value of the counter
  698. * used for sending the last stats ramrod.
  699. */
  700. spin_lock_bh(&bp->stats_lock);
  701. cur_stats_counter = bp->stats_counter - 1;
  702. spin_unlock_bh(&bp->stats_lock);
  703. /* are storm stats valid? */
  704. if (le16_to_cpu(counters->xstats_counter) != cur_stats_counter) {
  705. DP(BNX2X_MSG_STATS,
  706. "stats not updated by xstorm xstorm counter (0x%x) != stats_counter (0x%x)\n",
  707. le16_to_cpu(counters->xstats_counter), bp->stats_counter);
  708. return -EAGAIN;
  709. }
  710. if (le16_to_cpu(counters->ustats_counter) != cur_stats_counter) {
  711. DP(BNX2X_MSG_STATS,
  712. "stats not updated by ustorm ustorm counter (0x%x) != stats_counter (0x%x)\n",
  713. le16_to_cpu(counters->ustats_counter), bp->stats_counter);
  714. return -EAGAIN;
  715. }
  716. if (le16_to_cpu(counters->cstats_counter) != cur_stats_counter) {
  717. DP(BNX2X_MSG_STATS,
  718. "stats not updated by cstorm cstorm counter (0x%x) != stats_counter (0x%x)\n",
  719. le16_to_cpu(counters->cstats_counter), bp->stats_counter);
  720. return -EAGAIN;
  721. }
  722. if (le16_to_cpu(counters->tstats_counter) != cur_stats_counter) {
  723. DP(BNX2X_MSG_STATS,
  724. "stats not updated by tstorm tstorm counter (0x%x) != stats_counter (0x%x)\n",
  725. le16_to_cpu(counters->tstats_counter), bp->stats_counter);
  726. return -EAGAIN;
  727. }
  728. estats->error_bytes_received_hi = 0;
  729. estats->error_bytes_received_lo = 0;
  730. for_each_eth_queue(bp, i) {
  731. struct bnx2x_fastpath *fp = &bp->fp[i];
  732. struct tstorm_per_queue_stats *tclient =
  733. &bp->fw_stats_data->queue_stats[i].
  734. tstorm_queue_statistics;
  735. struct tstorm_per_queue_stats *old_tclient = &fp->old_tclient;
  736. struct ustorm_per_queue_stats *uclient =
  737. &bp->fw_stats_data->queue_stats[i].
  738. ustorm_queue_statistics;
  739. struct ustorm_per_queue_stats *old_uclient = &fp->old_uclient;
  740. struct xstorm_per_queue_stats *xclient =
  741. &bp->fw_stats_data->queue_stats[i].
  742. xstorm_queue_statistics;
  743. struct xstorm_per_queue_stats *old_xclient = &fp->old_xclient;
  744. struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
  745. struct bnx2x_eth_q_stats_old *qstats_old = &fp->eth_q_stats_old;
  746. u32 diff;
  747. DP(BNX2X_MSG_STATS, "queue[%d]: ucast_sent 0x%x, bcast_sent 0x%x mcast_sent 0x%x\n",
  748. i, xclient->ucast_pkts_sent,
  749. xclient->bcast_pkts_sent, xclient->mcast_pkts_sent);
  750. DP(BNX2X_MSG_STATS, "---------------\n");
  751. UPDATE_QSTAT(tclient->rcv_bcast_bytes,
  752. total_broadcast_bytes_received);
  753. UPDATE_QSTAT(tclient->rcv_mcast_bytes,
  754. total_multicast_bytes_received);
  755. UPDATE_QSTAT(tclient->rcv_ucast_bytes,
  756. total_unicast_bytes_received);
  757. /*
  758. * sum to total_bytes_received all
  759. * unicast/multicast/broadcast
  760. */
  761. qstats->total_bytes_received_hi =
  762. qstats->total_broadcast_bytes_received_hi;
  763. qstats->total_bytes_received_lo =
  764. qstats->total_broadcast_bytes_received_lo;
  765. ADD_64(qstats->total_bytes_received_hi,
  766. qstats->total_multicast_bytes_received_hi,
  767. qstats->total_bytes_received_lo,
  768. qstats->total_multicast_bytes_received_lo);
  769. ADD_64(qstats->total_bytes_received_hi,
  770. qstats->total_unicast_bytes_received_hi,
  771. qstats->total_bytes_received_lo,
  772. qstats->total_unicast_bytes_received_lo);
  773. qstats->valid_bytes_received_hi =
  774. qstats->total_bytes_received_hi;
  775. qstats->valid_bytes_received_lo =
  776. qstats->total_bytes_received_lo;
  777. UPDATE_EXTEND_TSTAT(rcv_ucast_pkts,
  778. total_unicast_packets_received);
  779. UPDATE_EXTEND_TSTAT(rcv_mcast_pkts,
  780. total_multicast_packets_received);
  781. UPDATE_EXTEND_TSTAT(rcv_bcast_pkts,
  782. total_broadcast_packets_received);
  783. UPDATE_EXTEND_E_TSTAT(pkts_too_big_discard,
  784. etherstatsoverrsizepkts);
  785. UPDATE_EXTEND_E_TSTAT(no_buff_discard, no_buff_discard);
  786. SUB_EXTEND_USTAT(ucast_no_buff_pkts,
  787. total_unicast_packets_received);
  788. SUB_EXTEND_USTAT(mcast_no_buff_pkts,
  789. total_multicast_packets_received);
  790. SUB_EXTEND_USTAT(bcast_no_buff_pkts,
  791. total_broadcast_packets_received);
  792. UPDATE_EXTEND_E_USTAT(ucast_no_buff_pkts, no_buff_discard);
  793. UPDATE_EXTEND_E_USTAT(mcast_no_buff_pkts, no_buff_discard);
  794. UPDATE_EXTEND_E_USTAT(bcast_no_buff_pkts, no_buff_discard);
  795. UPDATE_QSTAT(xclient->bcast_bytes_sent,
  796. total_broadcast_bytes_transmitted);
  797. UPDATE_QSTAT(xclient->mcast_bytes_sent,
  798. total_multicast_bytes_transmitted);
  799. UPDATE_QSTAT(xclient->ucast_bytes_sent,
  800. total_unicast_bytes_transmitted);
  801. /*
  802. * sum to total_bytes_transmitted all
  803. * unicast/multicast/broadcast
  804. */
  805. qstats->total_bytes_transmitted_hi =
  806. qstats->total_unicast_bytes_transmitted_hi;
  807. qstats->total_bytes_transmitted_lo =
  808. qstats->total_unicast_bytes_transmitted_lo;
  809. ADD_64(qstats->total_bytes_transmitted_hi,
  810. qstats->total_broadcast_bytes_transmitted_hi,
  811. qstats->total_bytes_transmitted_lo,
  812. qstats->total_broadcast_bytes_transmitted_lo);
  813. ADD_64(qstats->total_bytes_transmitted_hi,
  814. qstats->total_multicast_bytes_transmitted_hi,
  815. qstats->total_bytes_transmitted_lo,
  816. qstats->total_multicast_bytes_transmitted_lo);
  817. UPDATE_EXTEND_XSTAT(ucast_pkts_sent,
  818. total_unicast_packets_transmitted);
  819. UPDATE_EXTEND_XSTAT(mcast_pkts_sent,
  820. total_multicast_packets_transmitted);
  821. UPDATE_EXTEND_XSTAT(bcast_pkts_sent,
  822. total_broadcast_packets_transmitted);
  823. UPDATE_EXTEND_TSTAT(checksum_discard,
  824. total_packets_received_checksum_discarded);
  825. UPDATE_EXTEND_TSTAT(ttl0_discard,
  826. total_packets_received_ttl0_discarded);
  827. UPDATE_EXTEND_XSTAT(error_drop_pkts,
  828. total_transmitted_dropped_packets_error);
  829. /* TPA aggregations completed */
  830. UPDATE_EXTEND_E_USTAT(coalesced_events, total_tpa_aggregations);
  831. /* Number of network frames aggregated by TPA */
  832. UPDATE_EXTEND_E_USTAT(coalesced_pkts,
  833. total_tpa_aggregated_frames);
  834. /* Total number of bytes in completed TPA aggregations */
  835. UPDATE_QSTAT(uclient->coalesced_bytes, total_tpa_bytes);
  836. UPDATE_ESTAT_QSTAT_64(total_tpa_bytes);
  837. UPDATE_FSTAT_QSTAT(total_bytes_received);
  838. UPDATE_FSTAT_QSTAT(total_bytes_transmitted);
  839. UPDATE_FSTAT_QSTAT(total_unicast_packets_received);
  840. UPDATE_FSTAT_QSTAT(total_multicast_packets_received);
  841. UPDATE_FSTAT_QSTAT(total_broadcast_packets_received);
  842. UPDATE_FSTAT_QSTAT(total_unicast_packets_transmitted);
  843. UPDATE_FSTAT_QSTAT(total_multicast_packets_transmitted);
  844. UPDATE_FSTAT_QSTAT(total_broadcast_packets_transmitted);
  845. UPDATE_FSTAT_QSTAT(valid_bytes_received);
  846. }
  847. ADD_64(estats->total_bytes_received_hi,
  848. estats->rx_stat_ifhcinbadoctets_hi,
  849. estats->total_bytes_received_lo,
  850. estats->rx_stat_ifhcinbadoctets_lo);
  851. ADD_64(estats->total_bytes_received_hi,
  852. le32_to_cpu(tfunc->rcv_error_bytes.hi),
  853. estats->total_bytes_received_lo,
  854. le32_to_cpu(tfunc->rcv_error_bytes.lo));
  855. ADD_64(estats->error_bytes_received_hi,
  856. le32_to_cpu(tfunc->rcv_error_bytes.hi),
  857. estats->error_bytes_received_lo,
  858. le32_to_cpu(tfunc->rcv_error_bytes.lo));
  859. UPDATE_ESTAT(etherstatsoverrsizepkts, rx_stat_dot3statsframestoolong);
  860. ADD_64(estats->error_bytes_received_hi,
  861. estats->rx_stat_ifhcinbadoctets_hi,
  862. estats->error_bytes_received_lo,
  863. estats->rx_stat_ifhcinbadoctets_lo);
  864. if (bp->port.pmf) {
  865. struct bnx2x_fw_port_stats_old *fwstats = &bp->fw_stats_old;
  866. UPDATE_FW_STAT(mac_filter_discard);
  867. UPDATE_FW_STAT(mf_tag_discard);
  868. UPDATE_FW_STAT(brb_truncate_discard);
  869. UPDATE_FW_STAT(mac_discard);
  870. }
  871. fstats->host_func_stats_start = ++fstats->host_func_stats_end;
  872. bp->stats_pending = 0;
  873. return 0;
  874. }
  875. static void bnx2x_net_stats_update(struct bnx2x *bp)
  876. {
  877. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  878. struct net_device_stats *nstats = &bp->dev->stats;
  879. unsigned long tmp;
  880. int i;
  881. nstats->rx_packets =
  882. bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
  883. bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
  884. bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
  885. nstats->tx_packets =
  886. bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
  887. bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
  888. bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
  889. nstats->rx_bytes = bnx2x_hilo(&estats->total_bytes_received_hi);
  890. nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
  891. tmp = estats->mac_discard;
  892. for_each_rx_queue(bp, i)
  893. tmp += le32_to_cpu(bp->fp[i].old_tclient.checksum_discard);
  894. nstats->rx_dropped = tmp + bp->net_stats_old.rx_dropped;
  895. nstats->tx_dropped = 0;
  896. nstats->multicast =
  897. bnx2x_hilo(&estats->total_multicast_packets_received_hi);
  898. nstats->collisions =
  899. bnx2x_hilo(&estats->tx_stat_etherstatscollisions_hi);
  900. nstats->rx_length_errors =
  901. bnx2x_hilo(&estats->rx_stat_etherstatsundersizepkts_hi) +
  902. bnx2x_hilo(&estats->etherstatsoverrsizepkts_hi);
  903. nstats->rx_over_errors = bnx2x_hilo(&estats->brb_drop_hi) +
  904. bnx2x_hilo(&estats->brb_truncate_hi);
  905. nstats->rx_crc_errors =
  906. bnx2x_hilo(&estats->rx_stat_dot3statsfcserrors_hi);
  907. nstats->rx_frame_errors =
  908. bnx2x_hilo(&estats->rx_stat_dot3statsalignmenterrors_hi);
  909. nstats->rx_fifo_errors = bnx2x_hilo(&estats->no_buff_discard_hi);
  910. nstats->rx_missed_errors = 0;
  911. nstats->rx_errors = nstats->rx_length_errors +
  912. nstats->rx_over_errors +
  913. nstats->rx_crc_errors +
  914. nstats->rx_frame_errors +
  915. nstats->rx_fifo_errors +
  916. nstats->rx_missed_errors;
  917. nstats->tx_aborted_errors =
  918. bnx2x_hilo(&estats->tx_stat_dot3statslatecollisions_hi) +
  919. bnx2x_hilo(&estats->tx_stat_dot3statsexcessivecollisions_hi);
  920. nstats->tx_carrier_errors =
  921. bnx2x_hilo(&estats->rx_stat_dot3statscarriersenseerrors_hi);
  922. nstats->tx_fifo_errors = 0;
  923. nstats->tx_heartbeat_errors = 0;
  924. nstats->tx_window_errors = 0;
  925. nstats->tx_errors = nstats->tx_aborted_errors +
  926. nstats->tx_carrier_errors +
  927. bnx2x_hilo(&estats->tx_stat_dot3statsinternalmactransmiterrors_hi);
  928. }
  929. static void bnx2x_drv_stats_update(struct bnx2x *bp)
  930. {
  931. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  932. int i;
  933. for_each_queue(bp, i) {
  934. struct bnx2x_eth_q_stats *qstats = &bp->fp[i].eth_q_stats;
  935. struct bnx2x_eth_q_stats_old *qstats_old =
  936. &bp->fp[i].eth_q_stats_old;
  937. UPDATE_ESTAT_QSTAT(driver_xoff);
  938. UPDATE_ESTAT_QSTAT(rx_err_discard_pkt);
  939. UPDATE_ESTAT_QSTAT(rx_skb_alloc_failed);
  940. UPDATE_ESTAT_QSTAT(hw_csum_err);
  941. }
  942. }
  943. static bool bnx2x_edebug_stats_stopped(struct bnx2x *bp)
  944. {
  945. u32 val;
  946. if (SHMEM2_HAS(bp, edebug_driver_if[1])) {
  947. val = SHMEM2_RD(bp, edebug_driver_if[1]);
  948. if (val == EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT)
  949. return true;
  950. }
  951. return false;
  952. }
  953. static void bnx2x_stats_update(struct bnx2x *bp)
  954. {
  955. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  956. if (bnx2x_edebug_stats_stopped(bp))
  957. return;
  958. if (*stats_comp != DMAE_COMP_VAL)
  959. return;
  960. if (bp->port.pmf)
  961. bnx2x_hw_stats_update(bp);
  962. if (bnx2x_storm_stats_update(bp) && (bp->stats_pending++ == 3)) {
  963. BNX2X_ERR("storm stats were not updated for 3 times\n");
  964. bnx2x_panic();
  965. return;
  966. }
  967. bnx2x_net_stats_update(bp);
  968. bnx2x_drv_stats_update(bp);
  969. if (netif_msg_timer(bp)) {
  970. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  971. netdev_dbg(bp->dev, "brb drops %u brb truncate %u\n",
  972. estats->brb_drop_lo, estats->brb_truncate_lo);
  973. }
  974. bnx2x_hw_stats_post(bp);
  975. bnx2x_storm_stats_post(bp);
  976. }
  977. static void bnx2x_port_stats_stop(struct bnx2x *bp)
  978. {
  979. struct dmae_command *dmae;
  980. u32 opcode;
  981. int loader_idx = PMF_DMAE_C(bp);
  982. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  983. bp->executer_idx = 0;
  984. opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC, false, 0);
  985. if (bp->port.port_stx) {
  986. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  987. if (bp->func_stx)
  988. dmae->opcode = bnx2x_dmae_opcode_add_comp(
  989. opcode, DMAE_COMP_GRC);
  990. else
  991. dmae->opcode = bnx2x_dmae_opcode_add_comp(
  992. opcode, DMAE_COMP_PCI);
  993. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
  994. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
  995. dmae->dst_addr_lo = bp->port.port_stx >> 2;
  996. dmae->dst_addr_hi = 0;
  997. dmae->len = bnx2x_get_port_stats_dma_len(bp);
  998. if (bp->func_stx) {
  999. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  1000. dmae->comp_addr_hi = 0;
  1001. dmae->comp_val = 1;
  1002. } else {
  1003. dmae->comp_addr_lo =
  1004. U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  1005. dmae->comp_addr_hi =
  1006. U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  1007. dmae->comp_val = DMAE_COMP_VAL;
  1008. *stats_comp = 0;
  1009. }
  1010. }
  1011. if (bp->func_stx) {
  1012. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  1013. dmae->opcode =
  1014. bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);
  1015. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
  1016. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
  1017. dmae->dst_addr_lo = bp->func_stx >> 2;
  1018. dmae->dst_addr_hi = 0;
  1019. dmae->len = sizeof(struct host_func_stats) >> 2;
  1020. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  1021. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  1022. dmae->comp_val = DMAE_COMP_VAL;
  1023. *stats_comp = 0;
  1024. }
  1025. }
  1026. static void bnx2x_stats_stop(struct bnx2x *bp)
  1027. {
  1028. int update = 0;
  1029. bnx2x_stats_comp(bp);
  1030. if (bp->port.pmf)
  1031. update = (bnx2x_hw_stats_update(bp) == 0);
  1032. update |= (bnx2x_storm_stats_update(bp) == 0);
  1033. if (update) {
  1034. bnx2x_net_stats_update(bp);
  1035. if (bp->port.pmf)
  1036. bnx2x_port_stats_stop(bp);
  1037. bnx2x_hw_stats_post(bp);
  1038. bnx2x_stats_comp(bp);
  1039. }
  1040. }
  1041. static void bnx2x_stats_do_nothing(struct bnx2x *bp)
  1042. {
  1043. }
  1044. static const struct {
  1045. void (*action)(struct bnx2x *bp);
  1046. enum bnx2x_stats_state next_state;
  1047. } bnx2x_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
  1048. /* state event */
  1049. {
  1050. /* DISABLED PMF */ {bnx2x_stats_pmf_update, STATS_STATE_DISABLED},
  1051. /* LINK_UP */ {bnx2x_stats_start, STATS_STATE_ENABLED},
  1052. /* UPDATE */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED},
  1053. /* STOP */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED}
  1054. },
  1055. {
  1056. /* ENABLED PMF */ {bnx2x_stats_pmf_start, STATS_STATE_ENABLED},
  1057. /* LINK_UP */ {bnx2x_stats_restart, STATS_STATE_ENABLED},
  1058. /* UPDATE */ {bnx2x_stats_update, STATS_STATE_ENABLED},
  1059. /* STOP */ {bnx2x_stats_stop, STATS_STATE_DISABLED}
  1060. }
  1061. };
  1062. void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
  1063. {
  1064. enum bnx2x_stats_state state;
  1065. if (unlikely(bp->panic))
  1066. return;
  1067. spin_lock_bh(&bp->stats_lock);
  1068. state = bp->stats_state;
  1069. bp->stats_state = bnx2x_stats_stm[state][event].next_state;
  1070. spin_unlock_bh(&bp->stats_lock);
  1071. bnx2x_stats_stm[state][event].action(bp);
  1072. if ((event != STATS_EVENT_UPDATE) || netif_msg_timer(bp))
  1073. DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
  1074. state, event, bp->stats_state);
  1075. }
  1076. static void bnx2x_port_stats_base_init(struct bnx2x *bp)
  1077. {
  1078. struct dmae_command *dmae;
  1079. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  1080. /* sanity */
  1081. if (!bp->port.pmf || !bp->port.port_stx) {
  1082. BNX2X_ERR("BUG!\n");
  1083. return;
  1084. }
  1085. bp->executer_idx = 0;
  1086. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  1087. dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
  1088. true, DMAE_COMP_PCI);
  1089. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
  1090. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
  1091. dmae->dst_addr_lo = bp->port.port_stx >> 2;
  1092. dmae->dst_addr_hi = 0;
  1093. dmae->len = bnx2x_get_port_stats_dma_len(bp);
  1094. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  1095. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  1096. dmae->comp_val = DMAE_COMP_VAL;
  1097. *stats_comp = 0;
  1098. bnx2x_hw_stats_post(bp);
  1099. bnx2x_stats_comp(bp);
  1100. }
  1101. static void bnx2x_func_stats_base_update(struct bnx2x *bp)
  1102. {
  1103. struct dmae_command *dmae = &bp->stats_dmae;
  1104. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  1105. /* sanity */
  1106. if (!bp->func_stx) {
  1107. BNX2X_ERR("BUG!\n");
  1108. return;
  1109. }
  1110. bp->executer_idx = 0;
  1111. memset(dmae, 0, sizeof(struct dmae_command));
  1112. dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
  1113. true, DMAE_COMP_PCI);
  1114. dmae->src_addr_lo = bp->func_stx >> 2;
  1115. dmae->src_addr_hi = 0;
  1116. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
  1117. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
  1118. dmae->len = sizeof(struct host_func_stats) >> 2;
  1119. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  1120. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  1121. dmae->comp_val = DMAE_COMP_VAL;
  1122. *stats_comp = 0;
  1123. bnx2x_hw_stats_post(bp);
  1124. bnx2x_stats_comp(bp);
  1125. }
  1126. /**
  1127. * This function will prepare the statistics ramrod data the way
  1128. * we will only have to increment the statistics counter and
  1129. * send the ramrod each time we have to.
  1130. *
  1131. * @param bp
  1132. */
  1133. static inline void bnx2x_prep_fw_stats_req(struct bnx2x *bp)
  1134. {
  1135. int i;
  1136. int first_queue_query_index;
  1137. struct stats_query_header *stats_hdr = &bp->fw_stats_req->hdr;
  1138. dma_addr_t cur_data_offset;
  1139. struct stats_query_entry *cur_query_entry;
  1140. stats_hdr->cmd_num = bp->fw_stats_num;
  1141. stats_hdr->drv_stats_counter = 0;
  1142. /* storm_counters struct contains the counters of completed
  1143. * statistics requests per storm which are incremented by FW
  1144. * each time it completes hadning a statistics ramrod. We will
  1145. * check these counters in the timer handler and discard a
  1146. * (statistics) ramrod completion.
  1147. */
  1148. cur_data_offset = bp->fw_stats_data_mapping +
  1149. offsetof(struct bnx2x_fw_stats_data, storm_counters);
  1150. stats_hdr->stats_counters_addrs.hi =
  1151. cpu_to_le32(U64_HI(cur_data_offset));
  1152. stats_hdr->stats_counters_addrs.lo =
  1153. cpu_to_le32(U64_LO(cur_data_offset));
  1154. /* prepare to the first stats ramrod (will be completed with
  1155. * the counters equal to zero) - init counters to somethig different.
  1156. */
  1157. memset(&bp->fw_stats_data->storm_counters, 0xff,
  1158. sizeof(struct stats_counter));
  1159. /**** Port FW statistics data ****/
  1160. cur_data_offset = bp->fw_stats_data_mapping +
  1161. offsetof(struct bnx2x_fw_stats_data, port);
  1162. cur_query_entry = &bp->fw_stats_req->query[BNX2X_PORT_QUERY_IDX];
  1163. cur_query_entry->kind = STATS_TYPE_PORT;
  1164. /* For port query index is a DONT CARE */
  1165. cur_query_entry->index = BP_PORT(bp);
  1166. /* For port query funcID is a DONT CARE */
  1167. cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
  1168. cur_query_entry->address.hi = cpu_to_le32(U64_HI(cur_data_offset));
  1169. cur_query_entry->address.lo = cpu_to_le32(U64_LO(cur_data_offset));
  1170. /**** PF FW statistics data ****/
  1171. cur_data_offset = bp->fw_stats_data_mapping +
  1172. offsetof(struct bnx2x_fw_stats_data, pf);
  1173. cur_query_entry = &bp->fw_stats_req->query[BNX2X_PF_QUERY_IDX];
  1174. cur_query_entry->kind = STATS_TYPE_PF;
  1175. /* For PF query index is a DONT CARE */
  1176. cur_query_entry->index = BP_PORT(bp);
  1177. cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
  1178. cur_query_entry->address.hi = cpu_to_le32(U64_HI(cur_data_offset));
  1179. cur_query_entry->address.lo = cpu_to_le32(U64_LO(cur_data_offset));
  1180. /**** FCoE FW statistics data ****/
  1181. if (!NO_FCOE(bp)) {
  1182. cur_data_offset = bp->fw_stats_data_mapping +
  1183. offsetof(struct bnx2x_fw_stats_data, fcoe);
  1184. cur_query_entry =
  1185. &bp->fw_stats_req->query[BNX2X_FCOE_QUERY_IDX];
  1186. cur_query_entry->kind = STATS_TYPE_FCOE;
  1187. /* For FCoE query index is a DONT CARE */
  1188. cur_query_entry->index = BP_PORT(bp);
  1189. cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
  1190. cur_query_entry->address.hi =
  1191. cpu_to_le32(U64_HI(cur_data_offset));
  1192. cur_query_entry->address.lo =
  1193. cpu_to_le32(U64_LO(cur_data_offset));
  1194. }
  1195. /**** Clients' queries ****/
  1196. cur_data_offset = bp->fw_stats_data_mapping +
  1197. offsetof(struct bnx2x_fw_stats_data, queue_stats);
  1198. /* first queue query index depends whether FCoE offloaded request will
  1199. * be included in the ramrod
  1200. */
  1201. if (!NO_FCOE(bp))
  1202. first_queue_query_index = BNX2X_FIRST_QUEUE_QUERY_IDX;
  1203. else
  1204. first_queue_query_index = BNX2X_FIRST_QUEUE_QUERY_IDX - 1;
  1205. for_each_eth_queue(bp, i) {
  1206. cur_query_entry =
  1207. &bp->fw_stats_req->
  1208. query[first_queue_query_index + i];
  1209. cur_query_entry->kind = STATS_TYPE_QUEUE;
  1210. cur_query_entry->index = bnx2x_stats_id(&bp->fp[i]);
  1211. cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
  1212. cur_query_entry->address.hi =
  1213. cpu_to_le32(U64_HI(cur_data_offset));
  1214. cur_query_entry->address.lo =
  1215. cpu_to_le32(U64_LO(cur_data_offset));
  1216. cur_data_offset += sizeof(struct per_queue_stats);
  1217. }
  1218. /* add FCoE queue query if needed */
  1219. if (!NO_FCOE(bp)) {
  1220. cur_query_entry =
  1221. &bp->fw_stats_req->
  1222. query[first_queue_query_index + i];
  1223. cur_query_entry->kind = STATS_TYPE_QUEUE;
  1224. cur_query_entry->index = bnx2x_stats_id(&bp->fp[FCOE_IDX]);
  1225. cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
  1226. cur_query_entry->address.hi =
  1227. cpu_to_le32(U64_HI(cur_data_offset));
  1228. cur_query_entry->address.lo =
  1229. cpu_to_le32(U64_LO(cur_data_offset));
  1230. }
  1231. }
  1232. void bnx2x_stats_init(struct bnx2x *bp)
  1233. {
  1234. int /*abs*/port = BP_PORT(bp);
  1235. int mb_idx = BP_FW_MB_IDX(bp);
  1236. int i;
  1237. bp->stats_pending = 0;
  1238. bp->executer_idx = 0;
  1239. bp->stats_counter = 0;
  1240. /* port and func stats for management */
  1241. if (!BP_NOMCP(bp)) {
  1242. bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx);
  1243. bp->func_stx = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_param);
  1244. } else {
  1245. bp->port.port_stx = 0;
  1246. bp->func_stx = 0;
  1247. }
  1248. DP(BNX2X_MSG_STATS, "port_stx 0x%x func_stx 0x%x\n",
  1249. bp->port.port_stx, bp->func_stx);
  1250. /* pmf should retrieve port statistics from SP on a non-init*/
  1251. if (!bp->stats_init && bp->port.pmf && bp->port.port_stx)
  1252. bnx2x_stats_handle(bp, STATS_EVENT_PMF);
  1253. port = BP_PORT(bp);
  1254. /* port stats */
  1255. memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
  1256. bp->port.old_nig_stats.brb_discard =
  1257. REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
  1258. bp->port.old_nig_stats.brb_truncate =
  1259. REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
  1260. if (!CHIP_IS_E3(bp)) {
  1261. REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
  1262. &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
  1263. REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
  1264. &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2);
  1265. }
  1266. /* function stats */
  1267. for_each_queue(bp, i) {
  1268. struct bnx2x_fastpath *fp = &bp->fp[i];
  1269. memset(&fp->old_tclient, 0, sizeof(fp->old_tclient));
  1270. memset(&fp->old_uclient, 0, sizeof(fp->old_uclient));
  1271. memset(&fp->old_xclient, 0, sizeof(fp->old_xclient));
  1272. if (bp->stats_init) {
  1273. memset(&fp->eth_q_stats, 0, sizeof(fp->eth_q_stats));
  1274. memset(&fp->eth_q_stats_old, 0,
  1275. sizeof(fp->eth_q_stats_old));
  1276. }
  1277. }
  1278. /* Prepare statistics ramrod data */
  1279. bnx2x_prep_fw_stats_req(bp);
  1280. memset(&bp->dev->stats, 0, sizeof(bp->dev->stats));
  1281. if (bp->stats_init) {
  1282. memset(&bp->net_stats_old, 0, sizeof(bp->net_stats_old));
  1283. memset(&bp->fw_stats_old, 0, sizeof(bp->fw_stats_old));
  1284. memset(&bp->eth_stats_old, 0, sizeof(bp->eth_stats_old));
  1285. memset(&bp->eth_stats, 0, sizeof(bp->eth_stats));
  1286. /* Clean SP from previous statistics */
  1287. if (bp->func_stx) {
  1288. memset(bnx2x_sp(bp, func_stats), 0,
  1289. sizeof(struct host_func_stats));
  1290. bnx2x_func_stats_init(bp);
  1291. bnx2x_hw_stats_post(bp);
  1292. bnx2x_stats_comp(bp);
  1293. }
  1294. }
  1295. bp->stats_state = STATS_STATE_DISABLED;
  1296. if (bp->port.pmf && bp->port.port_stx)
  1297. bnx2x_port_stats_base_init(bp);
  1298. /* On a non-init, retrieve previous statistics from SP */
  1299. if (!bp->stats_init && bp->func_stx)
  1300. bnx2x_func_stats_base_update(bp);
  1301. /* mark the end of statistics initializiation */
  1302. bp->stats_init = false;
  1303. }
  1304. void bnx2x_save_statistics(struct bnx2x *bp)
  1305. {
  1306. int i;
  1307. struct net_device_stats *nstats = &bp->dev->stats;
  1308. /* save queue statistics */
  1309. for_each_eth_queue(bp, i) {
  1310. struct bnx2x_fastpath *fp = &bp->fp[i];
  1311. struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
  1312. struct bnx2x_eth_q_stats_old *qstats_old = &fp->eth_q_stats_old;
  1313. UPDATE_QSTAT_OLD(total_unicast_bytes_received_hi);
  1314. UPDATE_QSTAT_OLD(total_unicast_bytes_received_lo);
  1315. UPDATE_QSTAT_OLD(total_broadcast_bytes_received_hi);
  1316. UPDATE_QSTAT_OLD(total_broadcast_bytes_received_lo);
  1317. UPDATE_QSTAT_OLD(total_multicast_bytes_received_hi);
  1318. UPDATE_QSTAT_OLD(total_multicast_bytes_received_lo);
  1319. UPDATE_QSTAT_OLD(total_unicast_bytes_transmitted_hi);
  1320. UPDATE_QSTAT_OLD(total_unicast_bytes_transmitted_lo);
  1321. UPDATE_QSTAT_OLD(total_broadcast_bytes_transmitted_hi);
  1322. UPDATE_QSTAT_OLD(total_broadcast_bytes_transmitted_lo);
  1323. UPDATE_QSTAT_OLD(total_multicast_bytes_transmitted_hi);
  1324. UPDATE_QSTAT_OLD(total_multicast_bytes_transmitted_lo);
  1325. UPDATE_QSTAT_OLD(total_tpa_bytes_hi);
  1326. UPDATE_QSTAT_OLD(total_tpa_bytes_lo);
  1327. }
  1328. /* save net_device_stats statistics */
  1329. bp->net_stats_old.rx_dropped = nstats->rx_dropped;
  1330. /* store port firmware statistics */
  1331. if (bp->port.pmf && IS_MF(bp)) {
  1332. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  1333. struct bnx2x_fw_port_stats_old *fwstats = &bp->fw_stats_old;
  1334. UPDATE_FW_STAT_OLD(mac_filter_discard);
  1335. UPDATE_FW_STAT_OLD(mf_tag_discard);
  1336. UPDATE_FW_STAT_OLD(brb_truncate_discard);
  1337. UPDATE_FW_STAT_OLD(mac_discard);
  1338. }
  1339. }