cnic.c 146 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2012 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #include <linux/prefetch.h>
  28. #include <linux/random.h>
  29. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  30. #define BCM_VLAN 1
  31. #endif
  32. #include <net/ip.h>
  33. #include <net/tcp.h>
  34. #include <net/route.h>
  35. #include <net/ipv6.h>
  36. #include <net/ip6_route.h>
  37. #include <net/ip6_checksum.h>
  38. #include <scsi/iscsi_if.h>
  39. #include "cnic_if.h"
  40. #include "bnx2.h"
  41. #include "bnx2x/bnx2x_reg.h"
  42. #include "bnx2x/bnx2x_fw_defs.h"
  43. #include "bnx2x/bnx2x_hsi.h"
  44. #include "../../../scsi/bnx2i/57xx_iscsi_constants.h"
  45. #include "../../../scsi/bnx2i/57xx_iscsi_hsi.h"
  46. #include "../../../scsi/bnx2fc/bnx2fc_constants.h"
  47. #include "cnic.h"
  48. #include "cnic_defs.h"
  49. #define DRV_MODULE_NAME "cnic"
  50. static char version[] __devinitdata =
  51. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  52. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  53. "Chen (zongxi@broadcom.com");
  54. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  55. MODULE_LICENSE("GPL");
  56. MODULE_VERSION(CNIC_MODULE_VERSION);
  57. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  58. static LIST_HEAD(cnic_dev_list);
  59. static LIST_HEAD(cnic_udev_list);
  60. static DEFINE_RWLOCK(cnic_dev_lock);
  61. static DEFINE_MUTEX(cnic_lock);
  62. static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  63. /* helper function, assuming cnic_lock is held */
  64. static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
  65. {
  66. return rcu_dereference_protected(cnic_ulp_tbl[type],
  67. lockdep_is_held(&cnic_lock));
  68. }
  69. static int cnic_service_bnx2(void *, void *);
  70. static int cnic_service_bnx2x(void *, void *);
  71. static int cnic_ctl(void *, struct cnic_ctl_info *);
  72. static struct cnic_ops cnic_bnx2_ops = {
  73. .cnic_owner = THIS_MODULE,
  74. .cnic_handler = cnic_service_bnx2,
  75. .cnic_ctl = cnic_ctl,
  76. };
  77. static struct cnic_ops cnic_bnx2x_ops = {
  78. .cnic_owner = THIS_MODULE,
  79. .cnic_handler = cnic_service_bnx2x,
  80. .cnic_ctl = cnic_ctl,
  81. };
  82. static struct workqueue_struct *cnic_wq;
  83. static void cnic_shutdown_rings(struct cnic_dev *);
  84. static void cnic_init_rings(struct cnic_dev *);
  85. static int cnic_cm_set_pg(struct cnic_sock *);
  86. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  87. {
  88. struct cnic_uio_dev *udev = uinfo->priv;
  89. struct cnic_dev *dev;
  90. if (!capable(CAP_NET_ADMIN))
  91. return -EPERM;
  92. if (udev->uio_dev != -1)
  93. return -EBUSY;
  94. rtnl_lock();
  95. dev = udev->dev;
  96. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  97. rtnl_unlock();
  98. return -ENODEV;
  99. }
  100. udev->uio_dev = iminor(inode);
  101. cnic_shutdown_rings(dev);
  102. cnic_init_rings(dev);
  103. rtnl_unlock();
  104. return 0;
  105. }
  106. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  107. {
  108. struct cnic_uio_dev *udev = uinfo->priv;
  109. udev->uio_dev = -1;
  110. return 0;
  111. }
  112. static inline void cnic_hold(struct cnic_dev *dev)
  113. {
  114. atomic_inc(&dev->ref_count);
  115. }
  116. static inline void cnic_put(struct cnic_dev *dev)
  117. {
  118. atomic_dec(&dev->ref_count);
  119. }
  120. static inline void csk_hold(struct cnic_sock *csk)
  121. {
  122. atomic_inc(&csk->ref_count);
  123. }
  124. static inline void csk_put(struct cnic_sock *csk)
  125. {
  126. atomic_dec(&csk->ref_count);
  127. }
  128. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  129. {
  130. struct cnic_dev *cdev;
  131. read_lock(&cnic_dev_lock);
  132. list_for_each_entry(cdev, &cnic_dev_list, list) {
  133. if (netdev == cdev->netdev) {
  134. cnic_hold(cdev);
  135. read_unlock(&cnic_dev_lock);
  136. return cdev;
  137. }
  138. }
  139. read_unlock(&cnic_dev_lock);
  140. return NULL;
  141. }
  142. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  143. {
  144. atomic_inc(&ulp_ops->ref_count);
  145. }
  146. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  147. {
  148. atomic_dec(&ulp_ops->ref_count);
  149. }
  150. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  151. {
  152. struct cnic_local *cp = dev->cnic_priv;
  153. struct cnic_eth_dev *ethdev = cp->ethdev;
  154. struct drv_ctl_info info;
  155. struct drv_ctl_io *io = &info.data.io;
  156. info.cmd = DRV_CTL_CTX_WR_CMD;
  157. io->cid_addr = cid_addr;
  158. io->offset = off;
  159. io->data = val;
  160. ethdev->drv_ctl(dev->netdev, &info);
  161. }
  162. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  163. {
  164. struct cnic_local *cp = dev->cnic_priv;
  165. struct cnic_eth_dev *ethdev = cp->ethdev;
  166. struct drv_ctl_info info;
  167. struct drv_ctl_io *io = &info.data.io;
  168. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  169. io->offset = off;
  170. io->dma_addr = addr;
  171. ethdev->drv_ctl(dev->netdev, &info);
  172. }
  173. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  174. {
  175. struct cnic_local *cp = dev->cnic_priv;
  176. struct cnic_eth_dev *ethdev = cp->ethdev;
  177. struct drv_ctl_info info;
  178. struct drv_ctl_l2_ring *ring = &info.data.ring;
  179. if (start)
  180. info.cmd = DRV_CTL_START_L2_CMD;
  181. else
  182. info.cmd = DRV_CTL_STOP_L2_CMD;
  183. ring->cid = cid;
  184. ring->client_id = cl_id;
  185. ethdev->drv_ctl(dev->netdev, &info);
  186. }
  187. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  188. {
  189. struct cnic_local *cp = dev->cnic_priv;
  190. struct cnic_eth_dev *ethdev = cp->ethdev;
  191. struct drv_ctl_info info;
  192. struct drv_ctl_io *io = &info.data.io;
  193. info.cmd = DRV_CTL_IO_WR_CMD;
  194. io->offset = off;
  195. io->data = val;
  196. ethdev->drv_ctl(dev->netdev, &info);
  197. }
  198. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  199. {
  200. struct cnic_local *cp = dev->cnic_priv;
  201. struct cnic_eth_dev *ethdev = cp->ethdev;
  202. struct drv_ctl_info info;
  203. struct drv_ctl_io *io = &info.data.io;
  204. info.cmd = DRV_CTL_IO_RD_CMD;
  205. io->offset = off;
  206. ethdev->drv_ctl(dev->netdev, &info);
  207. return io->data;
  208. }
  209. static void cnic_ulp_ctl(struct cnic_dev *dev, int ulp_type, bool reg)
  210. {
  211. struct cnic_local *cp = dev->cnic_priv;
  212. struct cnic_eth_dev *ethdev = cp->ethdev;
  213. struct drv_ctl_info info;
  214. struct fcoe_capabilities *fcoe_cap =
  215. &info.data.register_data.fcoe_features;
  216. if (reg) {
  217. info.cmd = DRV_CTL_ULP_REGISTER_CMD;
  218. if (ulp_type == CNIC_ULP_FCOE && dev->fcoe_cap)
  219. memcpy(fcoe_cap, dev->fcoe_cap, sizeof(*fcoe_cap));
  220. } else {
  221. info.cmd = DRV_CTL_ULP_UNREGISTER_CMD;
  222. }
  223. info.data.ulp_type = ulp_type;
  224. ethdev->drv_ctl(dev->netdev, &info);
  225. }
  226. static int cnic_in_use(struct cnic_sock *csk)
  227. {
  228. return test_bit(SK_F_INUSE, &csk->flags);
  229. }
  230. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  231. {
  232. struct cnic_local *cp = dev->cnic_priv;
  233. struct cnic_eth_dev *ethdev = cp->ethdev;
  234. struct drv_ctl_info info;
  235. info.cmd = cmd;
  236. info.data.credit.credit_count = count;
  237. ethdev->drv_ctl(dev->netdev, &info);
  238. }
  239. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  240. {
  241. u32 i;
  242. if (!cp->ctx_tbl)
  243. return -EINVAL;
  244. for (i = 0; i < cp->max_cid_space; i++) {
  245. if (cp->ctx_tbl[i].cid == cid) {
  246. *l5_cid = i;
  247. return 0;
  248. }
  249. }
  250. return -EINVAL;
  251. }
  252. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  253. struct cnic_sock *csk)
  254. {
  255. struct iscsi_path path_req;
  256. char *buf = NULL;
  257. u16 len = 0;
  258. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  259. struct cnic_ulp_ops *ulp_ops;
  260. struct cnic_uio_dev *udev = cp->udev;
  261. int rc = 0, retry = 0;
  262. if (!udev || udev->uio_dev == -1)
  263. return -ENODEV;
  264. if (csk) {
  265. len = sizeof(path_req);
  266. buf = (char *) &path_req;
  267. memset(&path_req, 0, len);
  268. msg_type = ISCSI_KEVENT_PATH_REQ;
  269. path_req.handle = (u64) csk->l5_cid;
  270. if (test_bit(SK_F_IPV6, &csk->flags)) {
  271. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  272. sizeof(struct in6_addr));
  273. path_req.ip_addr_len = 16;
  274. } else {
  275. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  276. sizeof(struct in_addr));
  277. path_req.ip_addr_len = 4;
  278. }
  279. path_req.vlan_id = csk->vlan_id;
  280. path_req.pmtu = csk->mtu;
  281. }
  282. while (retry < 3) {
  283. rc = 0;
  284. rcu_read_lock();
  285. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  286. if (ulp_ops)
  287. rc = ulp_ops->iscsi_nl_send_msg(
  288. cp->ulp_handle[CNIC_ULP_ISCSI],
  289. msg_type, buf, len);
  290. rcu_read_unlock();
  291. if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
  292. break;
  293. msleep(100);
  294. retry++;
  295. }
  296. return rc;
  297. }
  298. static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
  299. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  300. char *buf, u16 len)
  301. {
  302. int rc = -EINVAL;
  303. switch (msg_type) {
  304. case ISCSI_UEVENT_PATH_UPDATE: {
  305. struct cnic_local *cp;
  306. u32 l5_cid;
  307. struct cnic_sock *csk;
  308. struct iscsi_path *path_resp;
  309. if (len < sizeof(*path_resp))
  310. break;
  311. path_resp = (struct iscsi_path *) buf;
  312. cp = dev->cnic_priv;
  313. l5_cid = (u32) path_resp->handle;
  314. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  315. break;
  316. rcu_read_lock();
  317. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  318. rc = -ENODEV;
  319. rcu_read_unlock();
  320. break;
  321. }
  322. csk = &cp->csk_tbl[l5_cid];
  323. csk_hold(csk);
  324. if (cnic_in_use(csk) &&
  325. test_bit(SK_F_CONNECT_START, &csk->flags)) {
  326. csk->vlan_id = path_resp->vlan_id;
  327. memcpy(csk->ha, path_resp->mac_addr, 6);
  328. if (test_bit(SK_F_IPV6, &csk->flags))
  329. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  330. sizeof(struct in6_addr));
  331. else
  332. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  333. sizeof(struct in_addr));
  334. if (is_valid_ether_addr(csk->ha)) {
  335. cnic_cm_set_pg(csk);
  336. } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
  337. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  338. cnic_cm_upcall(cp, csk,
  339. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  340. clear_bit(SK_F_CONNECT_START, &csk->flags);
  341. }
  342. }
  343. csk_put(csk);
  344. rcu_read_unlock();
  345. rc = 0;
  346. }
  347. }
  348. return rc;
  349. }
  350. static int cnic_offld_prep(struct cnic_sock *csk)
  351. {
  352. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  353. return 0;
  354. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  355. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  356. return 0;
  357. }
  358. return 1;
  359. }
  360. static int cnic_close_prep(struct cnic_sock *csk)
  361. {
  362. clear_bit(SK_F_CONNECT_START, &csk->flags);
  363. smp_mb__after_clear_bit();
  364. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  365. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  366. msleep(1);
  367. return 1;
  368. }
  369. return 0;
  370. }
  371. static int cnic_abort_prep(struct cnic_sock *csk)
  372. {
  373. clear_bit(SK_F_CONNECT_START, &csk->flags);
  374. smp_mb__after_clear_bit();
  375. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  376. msleep(1);
  377. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  378. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  379. return 1;
  380. }
  381. return 0;
  382. }
  383. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  384. {
  385. struct cnic_dev *dev;
  386. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  387. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  388. return -EINVAL;
  389. }
  390. mutex_lock(&cnic_lock);
  391. if (cnic_ulp_tbl_prot(ulp_type)) {
  392. pr_err("%s: Type %d has already been registered\n",
  393. __func__, ulp_type);
  394. mutex_unlock(&cnic_lock);
  395. return -EBUSY;
  396. }
  397. read_lock(&cnic_dev_lock);
  398. list_for_each_entry(dev, &cnic_dev_list, list) {
  399. struct cnic_local *cp = dev->cnic_priv;
  400. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  401. }
  402. read_unlock(&cnic_dev_lock);
  403. atomic_set(&ulp_ops->ref_count, 0);
  404. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  405. mutex_unlock(&cnic_lock);
  406. /* Prevent race conditions with netdev_event */
  407. rtnl_lock();
  408. list_for_each_entry(dev, &cnic_dev_list, list) {
  409. struct cnic_local *cp = dev->cnic_priv;
  410. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  411. ulp_ops->cnic_init(dev);
  412. }
  413. rtnl_unlock();
  414. return 0;
  415. }
  416. int cnic_unregister_driver(int ulp_type)
  417. {
  418. struct cnic_dev *dev;
  419. struct cnic_ulp_ops *ulp_ops;
  420. int i = 0;
  421. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  422. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  423. return -EINVAL;
  424. }
  425. mutex_lock(&cnic_lock);
  426. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  427. if (!ulp_ops) {
  428. pr_err("%s: Type %d has not been registered\n",
  429. __func__, ulp_type);
  430. goto out_unlock;
  431. }
  432. read_lock(&cnic_dev_lock);
  433. list_for_each_entry(dev, &cnic_dev_list, list) {
  434. struct cnic_local *cp = dev->cnic_priv;
  435. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  436. pr_err("%s: Type %d still has devices registered\n",
  437. __func__, ulp_type);
  438. read_unlock(&cnic_dev_lock);
  439. goto out_unlock;
  440. }
  441. }
  442. read_unlock(&cnic_dev_lock);
  443. RCU_INIT_POINTER(cnic_ulp_tbl[ulp_type], NULL);
  444. mutex_unlock(&cnic_lock);
  445. synchronize_rcu();
  446. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  447. msleep(100);
  448. i++;
  449. }
  450. if (atomic_read(&ulp_ops->ref_count) != 0)
  451. pr_warn("%s: Failed waiting for ref count to go to zero\n",
  452. __func__);
  453. return 0;
  454. out_unlock:
  455. mutex_unlock(&cnic_lock);
  456. return -EINVAL;
  457. }
  458. static int cnic_start_hw(struct cnic_dev *);
  459. static void cnic_stop_hw(struct cnic_dev *);
  460. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  461. void *ulp_ctx)
  462. {
  463. struct cnic_local *cp = dev->cnic_priv;
  464. struct cnic_ulp_ops *ulp_ops;
  465. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  466. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  467. return -EINVAL;
  468. }
  469. mutex_lock(&cnic_lock);
  470. if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
  471. pr_err("%s: Driver with type %d has not been registered\n",
  472. __func__, ulp_type);
  473. mutex_unlock(&cnic_lock);
  474. return -EAGAIN;
  475. }
  476. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  477. pr_err("%s: Type %d has already been registered to this device\n",
  478. __func__, ulp_type);
  479. mutex_unlock(&cnic_lock);
  480. return -EBUSY;
  481. }
  482. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  483. cp->ulp_handle[ulp_type] = ulp_ctx;
  484. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  485. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  486. cnic_hold(dev);
  487. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  488. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  489. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  490. mutex_unlock(&cnic_lock);
  491. cnic_ulp_ctl(dev, ulp_type, true);
  492. return 0;
  493. }
  494. EXPORT_SYMBOL(cnic_register_driver);
  495. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  496. {
  497. struct cnic_local *cp = dev->cnic_priv;
  498. int i = 0;
  499. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  500. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  501. return -EINVAL;
  502. }
  503. mutex_lock(&cnic_lock);
  504. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  505. RCU_INIT_POINTER(cp->ulp_ops[ulp_type], NULL);
  506. cnic_put(dev);
  507. } else {
  508. pr_err("%s: device not registered to this ulp type %d\n",
  509. __func__, ulp_type);
  510. mutex_unlock(&cnic_lock);
  511. return -EINVAL;
  512. }
  513. mutex_unlock(&cnic_lock);
  514. if (ulp_type == CNIC_ULP_ISCSI)
  515. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  516. else if (ulp_type == CNIC_ULP_FCOE)
  517. dev->fcoe_cap = NULL;
  518. synchronize_rcu();
  519. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  520. i < 20) {
  521. msleep(100);
  522. i++;
  523. }
  524. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  525. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  526. cnic_ulp_ctl(dev, ulp_type, false);
  527. return 0;
  528. }
  529. EXPORT_SYMBOL(cnic_unregister_driver);
  530. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id,
  531. u32 next)
  532. {
  533. id_tbl->start = start_id;
  534. id_tbl->max = size;
  535. id_tbl->next = next;
  536. spin_lock_init(&id_tbl->lock);
  537. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  538. if (!id_tbl->table)
  539. return -ENOMEM;
  540. return 0;
  541. }
  542. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  543. {
  544. kfree(id_tbl->table);
  545. id_tbl->table = NULL;
  546. }
  547. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  548. {
  549. int ret = -1;
  550. id -= id_tbl->start;
  551. if (id >= id_tbl->max)
  552. return ret;
  553. spin_lock(&id_tbl->lock);
  554. if (!test_bit(id, id_tbl->table)) {
  555. set_bit(id, id_tbl->table);
  556. ret = 0;
  557. }
  558. spin_unlock(&id_tbl->lock);
  559. return ret;
  560. }
  561. /* Returns -1 if not successful */
  562. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  563. {
  564. u32 id;
  565. spin_lock(&id_tbl->lock);
  566. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  567. if (id >= id_tbl->max) {
  568. id = -1;
  569. if (id_tbl->next != 0) {
  570. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  571. if (id >= id_tbl->next)
  572. id = -1;
  573. }
  574. }
  575. if (id < id_tbl->max) {
  576. set_bit(id, id_tbl->table);
  577. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  578. id += id_tbl->start;
  579. }
  580. spin_unlock(&id_tbl->lock);
  581. return id;
  582. }
  583. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  584. {
  585. if (id == -1)
  586. return;
  587. id -= id_tbl->start;
  588. if (id >= id_tbl->max)
  589. return;
  590. clear_bit(id, id_tbl->table);
  591. }
  592. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  593. {
  594. int i;
  595. if (!dma->pg_arr)
  596. return;
  597. for (i = 0; i < dma->num_pages; i++) {
  598. if (dma->pg_arr[i]) {
  599. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  600. dma->pg_arr[i], dma->pg_map_arr[i]);
  601. dma->pg_arr[i] = NULL;
  602. }
  603. }
  604. if (dma->pgtbl) {
  605. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  606. dma->pgtbl, dma->pgtbl_map);
  607. dma->pgtbl = NULL;
  608. }
  609. kfree(dma->pg_arr);
  610. dma->pg_arr = NULL;
  611. dma->num_pages = 0;
  612. }
  613. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  614. {
  615. int i;
  616. __le32 *page_table = (__le32 *) dma->pgtbl;
  617. for (i = 0; i < dma->num_pages; i++) {
  618. /* Each entry needs to be in big endian format. */
  619. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  620. page_table++;
  621. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  622. page_table++;
  623. }
  624. }
  625. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  626. {
  627. int i;
  628. __le32 *page_table = (__le32 *) dma->pgtbl;
  629. for (i = 0; i < dma->num_pages; i++) {
  630. /* Each entry needs to be in little endian format. */
  631. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  632. page_table++;
  633. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  634. page_table++;
  635. }
  636. }
  637. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  638. int pages, int use_pg_tbl)
  639. {
  640. int i, size;
  641. struct cnic_local *cp = dev->cnic_priv;
  642. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  643. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  644. if (dma->pg_arr == NULL)
  645. return -ENOMEM;
  646. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  647. dma->num_pages = pages;
  648. for (i = 0; i < pages; i++) {
  649. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  650. BCM_PAGE_SIZE,
  651. &dma->pg_map_arr[i],
  652. GFP_ATOMIC);
  653. if (dma->pg_arr[i] == NULL)
  654. goto error;
  655. }
  656. if (!use_pg_tbl)
  657. return 0;
  658. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  659. ~(BCM_PAGE_SIZE - 1);
  660. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  661. &dma->pgtbl_map, GFP_ATOMIC);
  662. if (dma->pgtbl == NULL)
  663. goto error;
  664. cp->setup_pgtbl(dev, dma);
  665. return 0;
  666. error:
  667. cnic_free_dma(dev, dma);
  668. return -ENOMEM;
  669. }
  670. static void cnic_free_context(struct cnic_dev *dev)
  671. {
  672. struct cnic_local *cp = dev->cnic_priv;
  673. int i;
  674. for (i = 0; i < cp->ctx_blks; i++) {
  675. if (cp->ctx_arr[i].ctx) {
  676. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  677. cp->ctx_arr[i].ctx,
  678. cp->ctx_arr[i].mapping);
  679. cp->ctx_arr[i].ctx = NULL;
  680. }
  681. }
  682. }
  683. static void __cnic_free_uio_rings(struct cnic_uio_dev *udev)
  684. {
  685. if (udev->l2_buf) {
  686. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  687. udev->l2_buf, udev->l2_buf_map);
  688. udev->l2_buf = NULL;
  689. }
  690. if (udev->l2_ring) {
  691. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  692. udev->l2_ring, udev->l2_ring_map);
  693. udev->l2_ring = NULL;
  694. }
  695. }
  696. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  697. {
  698. uio_unregister_device(&udev->cnic_uinfo);
  699. __cnic_free_uio_rings(udev);
  700. pci_dev_put(udev->pdev);
  701. kfree(udev);
  702. }
  703. static void cnic_free_uio(struct cnic_uio_dev *udev)
  704. {
  705. if (!udev)
  706. return;
  707. write_lock(&cnic_dev_lock);
  708. list_del_init(&udev->list);
  709. write_unlock(&cnic_dev_lock);
  710. __cnic_free_uio(udev);
  711. }
  712. static void cnic_free_resc(struct cnic_dev *dev)
  713. {
  714. struct cnic_local *cp = dev->cnic_priv;
  715. struct cnic_uio_dev *udev = cp->udev;
  716. if (udev) {
  717. udev->dev = NULL;
  718. cp->udev = NULL;
  719. if (udev->uio_dev == -1)
  720. __cnic_free_uio_rings(udev);
  721. }
  722. cnic_free_context(dev);
  723. kfree(cp->ctx_arr);
  724. cp->ctx_arr = NULL;
  725. cp->ctx_blks = 0;
  726. cnic_free_dma(dev, &cp->gbl_buf_info);
  727. cnic_free_dma(dev, &cp->kwq_info);
  728. cnic_free_dma(dev, &cp->kwq_16_data_info);
  729. cnic_free_dma(dev, &cp->kcq2.dma);
  730. cnic_free_dma(dev, &cp->kcq1.dma);
  731. kfree(cp->iscsi_tbl);
  732. cp->iscsi_tbl = NULL;
  733. kfree(cp->ctx_tbl);
  734. cp->ctx_tbl = NULL;
  735. cnic_free_id_tbl(&cp->fcoe_cid_tbl);
  736. cnic_free_id_tbl(&cp->cid_tbl);
  737. }
  738. static int cnic_alloc_context(struct cnic_dev *dev)
  739. {
  740. struct cnic_local *cp = dev->cnic_priv;
  741. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  742. int i, k, arr_size;
  743. cp->ctx_blk_size = BCM_PAGE_SIZE;
  744. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  745. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  746. sizeof(struct cnic_ctx);
  747. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  748. if (cp->ctx_arr == NULL)
  749. return -ENOMEM;
  750. k = 0;
  751. for (i = 0; i < 2; i++) {
  752. u32 j, reg, off, lo, hi;
  753. if (i == 0)
  754. off = BNX2_PG_CTX_MAP;
  755. else
  756. off = BNX2_ISCSI_CTX_MAP;
  757. reg = cnic_reg_rd_ind(dev, off);
  758. lo = reg >> 16;
  759. hi = reg & 0xffff;
  760. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  761. cp->ctx_arr[k].cid = j;
  762. }
  763. cp->ctx_blks = k;
  764. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  765. cp->ctx_blks = 0;
  766. return -ENOMEM;
  767. }
  768. for (i = 0; i < cp->ctx_blks; i++) {
  769. cp->ctx_arr[i].ctx =
  770. dma_alloc_coherent(&dev->pcidev->dev,
  771. BCM_PAGE_SIZE,
  772. &cp->ctx_arr[i].mapping,
  773. GFP_KERNEL);
  774. if (cp->ctx_arr[i].ctx == NULL)
  775. return -ENOMEM;
  776. }
  777. }
  778. return 0;
  779. }
  780. static u16 cnic_bnx2_next_idx(u16 idx)
  781. {
  782. return idx + 1;
  783. }
  784. static u16 cnic_bnx2_hw_idx(u16 idx)
  785. {
  786. return idx;
  787. }
  788. static u16 cnic_bnx2x_next_idx(u16 idx)
  789. {
  790. idx++;
  791. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  792. idx++;
  793. return idx;
  794. }
  795. static u16 cnic_bnx2x_hw_idx(u16 idx)
  796. {
  797. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  798. idx++;
  799. return idx;
  800. }
  801. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info,
  802. bool use_pg_tbl)
  803. {
  804. int err, i, use_page_tbl = 0;
  805. struct kcqe **kcq;
  806. if (use_pg_tbl)
  807. use_page_tbl = 1;
  808. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, use_page_tbl);
  809. if (err)
  810. return err;
  811. kcq = (struct kcqe **) info->dma.pg_arr;
  812. info->kcq = kcq;
  813. info->next_idx = cnic_bnx2_next_idx;
  814. info->hw_idx = cnic_bnx2_hw_idx;
  815. if (use_pg_tbl)
  816. return 0;
  817. info->next_idx = cnic_bnx2x_next_idx;
  818. info->hw_idx = cnic_bnx2x_hw_idx;
  819. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  820. struct bnx2x_bd_chain_next *next =
  821. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  822. int j = i + 1;
  823. if (j >= KCQ_PAGE_CNT)
  824. j = 0;
  825. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  826. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  827. }
  828. return 0;
  829. }
  830. static int __cnic_alloc_uio_rings(struct cnic_uio_dev *udev, int pages)
  831. {
  832. struct cnic_local *cp = udev->dev->cnic_priv;
  833. if (udev->l2_ring)
  834. return 0;
  835. udev->l2_ring_size = pages * BCM_PAGE_SIZE;
  836. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  837. &udev->l2_ring_map,
  838. GFP_KERNEL | __GFP_COMP);
  839. if (!udev->l2_ring)
  840. return -ENOMEM;
  841. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  842. udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
  843. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  844. &udev->l2_buf_map,
  845. GFP_KERNEL | __GFP_COMP);
  846. if (!udev->l2_buf) {
  847. __cnic_free_uio_rings(udev);
  848. return -ENOMEM;
  849. }
  850. return 0;
  851. }
  852. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  853. {
  854. struct cnic_local *cp = dev->cnic_priv;
  855. struct cnic_uio_dev *udev;
  856. read_lock(&cnic_dev_lock);
  857. list_for_each_entry(udev, &cnic_udev_list, list) {
  858. if (udev->pdev == dev->pcidev) {
  859. udev->dev = dev;
  860. if (__cnic_alloc_uio_rings(udev, pages)) {
  861. udev->dev = NULL;
  862. read_unlock(&cnic_dev_lock);
  863. return -ENOMEM;
  864. }
  865. cp->udev = udev;
  866. read_unlock(&cnic_dev_lock);
  867. return 0;
  868. }
  869. }
  870. read_unlock(&cnic_dev_lock);
  871. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  872. if (!udev)
  873. return -ENOMEM;
  874. udev->uio_dev = -1;
  875. udev->dev = dev;
  876. udev->pdev = dev->pcidev;
  877. if (__cnic_alloc_uio_rings(udev, pages))
  878. goto err_udev;
  879. write_lock(&cnic_dev_lock);
  880. list_add(&udev->list, &cnic_udev_list);
  881. write_unlock(&cnic_dev_lock);
  882. pci_dev_get(udev->pdev);
  883. cp->udev = udev;
  884. return 0;
  885. err_udev:
  886. kfree(udev);
  887. return -ENOMEM;
  888. }
  889. static int cnic_init_uio(struct cnic_dev *dev)
  890. {
  891. struct cnic_local *cp = dev->cnic_priv;
  892. struct cnic_uio_dev *udev = cp->udev;
  893. struct uio_info *uinfo;
  894. int ret = 0;
  895. if (!udev)
  896. return -ENOMEM;
  897. uinfo = &udev->cnic_uinfo;
  898. uinfo->mem[0].addr = pci_resource_start(dev->pcidev, 0);
  899. uinfo->mem[0].internal_addr = dev->regview;
  900. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  901. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  902. uinfo->mem[0].size = MB_GET_CID_ADDR(TX_TSS_CID +
  903. TX_MAX_TSS_RINGS + 1);
  904. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  905. PAGE_MASK;
  906. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  907. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  908. else
  909. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  910. uinfo->name = "bnx2_cnic";
  911. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  912. uinfo->mem[0].size = pci_resource_len(dev->pcidev, 0);
  913. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  914. PAGE_MASK;
  915. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  916. uinfo->name = "bnx2x_cnic";
  917. }
  918. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  919. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  920. uinfo->mem[2].size = udev->l2_ring_size;
  921. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  922. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  923. uinfo->mem[3].size = udev->l2_buf_size;
  924. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  925. uinfo->version = CNIC_MODULE_VERSION;
  926. uinfo->irq = UIO_IRQ_CUSTOM;
  927. uinfo->open = cnic_uio_open;
  928. uinfo->release = cnic_uio_close;
  929. if (udev->uio_dev == -1) {
  930. if (!uinfo->priv) {
  931. uinfo->priv = udev;
  932. ret = uio_register_device(&udev->pdev->dev, uinfo);
  933. }
  934. } else {
  935. cnic_init_rings(dev);
  936. }
  937. return ret;
  938. }
  939. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  940. {
  941. struct cnic_local *cp = dev->cnic_priv;
  942. int ret;
  943. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  944. if (ret)
  945. goto error;
  946. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  947. ret = cnic_alloc_kcq(dev, &cp->kcq1, true);
  948. if (ret)
  949. goto error;
  950. ret = cnic_alloc_context(dev);
  951. if (ret)
  952. goto error;
  953. ret = cnic_alloc_uio_rings(dev, 2);
  954. if (ret)
  955. goto error;
  956. ret = cnic_init_uio(dev);
  957. if (ret)
  958. goto error;
  959. return 0;
  960. error:
  961. cnic_free_resc(dev);
  962. return ret;
  963. }
  964. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  965. {
  966. struct cnic_local *cp = dev->cnic_priv;
  967. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  968. int total_mem, blks, i;
  969. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  970. blks = total_mem / ctx_blk_size;
  971. if (total_mem % ctx_blk_size)
  972. blks++;
  973. if (blks > cp->ethdev->ctx_tbl_len)
  974. return -ENOMEM;
  975. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  976. if (cp->ctx_arr == NULL)
  977. return -ENOMEM;
  978. cp->ctx_blks = blks;
  979. cp->ctx_blk_size = ctx_blk_size;
  980. if (!BNX2X_CHIP_IS_57710(cp->chip_id))
  981. cp->ctx_align = 0;
  982. else
  983. cp->ctx_align = ctx_blk_size;
  984. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  985. for (i = 0; i < blks; i++) {
  986. cp->ctx_arr[i].ctx =
  987. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  988. &cp->ctx_arr[i].mapping,
  989. GFP_KERNEL);
  990. if (cp->ctx_arr[i].ctx == NULL)
  991. return -ENOMEM;
  992. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  993. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  994. cnic_free_context(dev);
  995. cp->ctx_blk_size += cp->ctx_align;
  996. i = -1;
  997. continue;
  998. }
  999. }
  1000. }
  1001. return 0;
  1002. }
  1003. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  1004. {
  1005. struct cnic_local *cp = dev->cnic_priv;
  1006. struct cnic_eth_dev *ethdev = cp->ethdev;
  1007. u32 start_cid = ethdev->starting_cid;
  1008. int i, j, n, ret, pages;
  1009. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  1010. cp->iro_arr = ethdev->iro_arr;
  1011. cp->max_cid_space = MAX_ISCSI_TBL_SZ;
  1012. cp->iscsi_start_cid = start_cid;
  1013. cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
  1014. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  1015. cp->max_cid_space += dev->max_fcoe_conn;
  1016. cp->fcoe_init_cid = ethdev->fcoe_init_cid;
  1017. if (!cp->fcoe_init_cid)
  1018. cp->fcoe_init_cid = 0x10;
  1019. }
  1020. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  1021. GFP_KERNEL);
  1022. if (!cp->iscsi_tbl)
  1023. goto error;
  1024. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  1025. cp->max_cid_space, GFP_KERNEL);
  1026. if (!cp->ctx_tbl)
  1027. goto error;
  1028. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  1029. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  1030. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  1031. }
  1032. for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
  1033. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
  1034. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  1035. PAGE_SIZE;
  1036. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  1037. if (ret)
  1038. return -ENOMEM;
  1039. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  1040. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  1041. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  1042. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  1043. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  1044. off;
  1045. if ((i % n) == (n - 1))
  1046. j++;
  1047. }
  1048. ret = cnic_alloc_kcq(dev, &cp->kcq1, false);
  1049. if (ret)
  1050. goto error;
  1051. if (CNIC_SUPPORTS_FCOE(cp)) {
  1052. ret = cnic_alloc_kcq(dev, &cp->kcq2, true);
  1053. if (ret)
  1054. goto error;
  1055. }
  1056. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  1057. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  1058. if (ret)
  1059. goto error;
  1060. ret = cnic_alloc_bnx2x_context(dev);
  1061. if (ret)
  1062. goto error;
  1063. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  1064. cp->l2_rx_ring_size = 15;
  1065. ret = cnic_alloc_uio_rings(dev, 4);
  1066. if (ret)
  1067. goto error;
  1068. ret = cnic_init_uio(dev);
  1069. if (ret)
  1070. goto error;
  1071. return 0;
  1072. error:
  1073. cnic_free_resc(dev);
  1074. return -ENOMEM;
  1075. }
  1076. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  1077. {
  1078. return cp->max_kwq_idx -
  1079. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  1080. }
  1081. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1082. u32 num_wqes)
  1083. {
  1084. struct cnic_local *cp = dev->cnic_priv;
  1085. struct kwqe *prod_qe;
  1086. u16 prod, sw_prod, i;
  1087. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1088. return -EAGAIN; /* bnx2 is down */
  1089. spin_lock_bh(&cp->cnic_ulp_lock);
  1090. if (num_wqes > cnic_kwq_avail(cp) &&
  1091. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  1092. spin_unlock_bh(&cp->cnic_ulp_lock);
  1093. return -EAGAIN;
  1094. }
  1095. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1096. prod = cp->kwq_prod_idx;
  1097. sw_prod = prod & MAX_KWQ_IDX;
  1098. for (i = 0; i < num_wqes; i++) {
  1099. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1100. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1101. prod++;
  1102. sw_prod = prod & MAX_KWQ_IDX;
  1103. }
  1104. cp->kwq_prod_idx = prod;
  1105. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1106. spin_unlock_bh(&cp->cnic_ulp_lock);
  1107. return 0;
  1108. }
  1109. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1110. union l5cm_specific_data *l5_data)
  1111. {
  1112. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1113. dma_addr_t map;
  1114. map = ctx->kwqe_data_mapping;
  1115. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1116. l5_data->phy_address.hi = (u64) map >> 32;
  1117. return ctx->kwqe_data;
  1118. }
  1119. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1120. u32 type, union l5cm_specific_data *l5_data)
  1121. {
  1122. struct cnic_local *cp = dev->cnic_priv;
  1123. struct l5cm_spe kwqe;
  1124. struct kwqe_16 *kwq[1];
  1125. u16 type_16;
  1126. int ret;
  1127. kwqe.hdr.conn_and_cmd_data =
  1128. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1129. BNX2X_HW_CID(cp, cid)));
  1130. type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
  1131. type_16 |= (cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1132. SPE_HDR_FUNCTION_ID;
  1133. kwqe.hdr.type = cpu_to_le16(type_16);
  1134. kwqe.hdr.reserved1 = 0;
  1135. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1136. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1137. kwq[0] = (struct kwqe_16 *) &kwqe;
  1138. spin_lock_bh(&cp->cnic_ulp_lock);
  1139. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1140. spin_unlock_bh(&cp->cnic_ulp_lock);
  1141. if (ret == 1)
  1142. return 0;
  1143. return ret;
  1144. }
  1145. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1146. struct kcqe *cqes[], u32 num_cqes)
  1147. {
  1148. struct cnic_local *cp = dev->cnic_priv;
  1149. struct cnic_ulp_ops *ulp_ops;
  1150. rcu_read_lock();
  1151. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1152. if (likely(ulp_ops)) {
  1153. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1154. cqes, num_cqes);
  1155. }
  1156. rcu_read_unlock();
  1157. }
  1158. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1159. {
  1160. struct cnic_local *cp = dev->cnic_priv;
  1161. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1162. int hq_bds, pages;
  1163. u32 pfid = cp->pfid;
  1164. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1165. cp->num_ccells = req1->num_ccells_per_conn;
  1166. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1167. cp->num_iscsi_tasks;
  1168. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1169. BNX2X_ISCSI_R2TQE_SIZE;
  1170. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1171. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1172. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1173. cp->num_cqs = req1->num_cqs;
  1174. if (!dev->max_iscsi_conn)
  1175. return 0;
  1176. /* init Tstorm RAM */
  1177. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1178. req1->rq_num_wqes);
  1179. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1180. PAGE_SIZE);
  1181. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1182. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1183. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1184. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1185. req1->num_tasks_per_conn);
  1186. /* init Ustorm RAM */
  1187. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1188. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1189. req1->rq_buffer_size);
  1190. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1191. PAGE_SIZE);
  1192. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1193. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1194. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1195. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1196. req1->num_tasks_per_conn);
  1197. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1198. req1->rq_num_wqes);
  1199. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1200. req1->cq_num_wqes);
  1201. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1202. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1203. /* init Xstorm RAM */
  1204. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1205. PAGE_SIZE);
  1206. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1207. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1208. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1209. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1210. req1->num_tasks_per_conn);
  1211. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1212. hq_bds);
  1213. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1214. req1->num_tasks_per_conn);
  1215. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1216. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1217. /* init Cstorm RAM */
  1218. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1219. PAGE_SIZE);
  1220. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1221. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1222. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1223. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1224. req1->num_tasks_per_conn);
  1225. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1226. req1->cq_num_wqes);
  1227. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1228. hq_bds);
  1229. return 0;
  1230. }
  1231. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1232. {
  1233. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1234. struct cnic_local *cp = dev->cnic_priv;
  1235. u32 pfid = cp->pfid;
  1236. struct iscsi_kcqe kcqe;
  1237. struct kcqe *cqes[1];
  1238. memset(&kcqe, 0, sizeof(kcqe));
  1239. if (!dev->max_iscsi_conn) {
  1240. kcqe.completion_status =
  1241. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1242. goto done;
  1243. }
  1244. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1245. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1246. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1247. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1248. req2->error_bit_map[1]);
  1249. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1250. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1251. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1252. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1253. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1254. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1255. req2->error_bit_map[1]);
  1256. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1257. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1258. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1259. done:
  1260. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1261. cqes[0] = (struct kcqe *) &kcqe;
  1262. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1263. return 0;
  1264. }
  1265. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1266. {
  1267. struct cnic_local *cp = dev->cnic_priv;
  1268. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1269. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1270. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1271. cnic_free_dma(dev, &iscsi->hq_info);
  1272. cnic_free_dma(dev, &iscsi->r2tq_info);
  1273. cnic_free_dma(dev, &iscsi->task_array_info);
  1274. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1275. } else {
  1276. cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
  1277. }
  1278. ctx->cid = 0;
  1279. }
  1280. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1281. {
  1282. u32 cid;
  1283. int ret, pages;
  1284. struct cnic_local *cp = dev->cnic_priv;
  1285. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1286. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1287. if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
  1288. cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
  1289. if (cid == -1) {
  1290. ret = -ENOMEM;
  1291. goto error;
  1292. }
  1293. ctx->cid = cid;
  1294. return 0;
  1295. }
  1296. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1297. if (cid == -1) {
  1298. ret = -ENOMEM;
  1299. goto error;
  1300. }
  1301. ctx->cid = cid;
  1302. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1303. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1304. if (ret)
  1305. goto error;
  1306. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1307. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1308. if (ret)
  1309. goto error;
  1310. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1311. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1312. if (ret)
  1313. goto error;
  1314. return 0;
  1315. error:
  1316. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1317. return ret;
  1318. }
  1319. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1320. struct regpair *ctx_addr)
  1321. {
  1322. struct cnic_local *cp = dev->cnic_priv;
  1323. struct cnic_eth_dev *ethdev = cp->ethdev;
  1324. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1325. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1326. unsigned long align_off = 0;
  1327. dma_addr_t ctx_map;
  1328. void *ctx;
  1329. if (cp->ctx_align) {
  1330. unsigned long mask = cp->ctx_align - 1;
  1331. if (cp->ctx_arr[blk].mapping & mask)
  1332. align_off = cp->ctx_align -
  1333. (cp->ctx_arr[blk].mapping & mask);
  1334. }
  1335. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1336. (off * BNX2X_CONTEXT_MEM_SIZE);
  1337. ctx = cp->ctx_arr[blk].ctx + align_off +
  1338. (off * BNX2X_CONTEXT_MEM_SIZE);
  1339. if (init)
  1340. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1341. ctx_addr->lo = ctx_map & 0xffffffff;
  1342. ctx_addr->hi = (u64) ctx_map >> 32;
  1343. return ctx;
  1344. }
  1345. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1346. u32 num)
  1347. {
  1348. struct cnic_local *cp = dev->cnic_priv;
  1349. struct iscsi_kwqe_conn_offload1 *req1 =
  1350. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1351. struct iscsi_kwqe_conn_offload2 *req2 =
  1352. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1353. struct iscsi_kwqe_conn_offload3 *req3;
  1354. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1355. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1356. u32 cid = ctx->cid;
  1357. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1358. struct iscsi_context *ictx;
  1359. struct regpair context_addr;
  1360. int i, j, n = 2, n_max;
  1361. u8 port = CNIC_PORT(cp);
  1362. ctx->ctx_flags = 0;
  1363. if (!req2->num_additional_wqes)
  1364. return -EINVAL;
  1365. n_max = req2->num_additional_wqes + 2;
  1366. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1367. if (ictx == NULL)
  1368. return -ENOMEM;
  1369. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1370. ictx->xstorm_ag_context.hq_prod = 1;
  1371. ictx->xstorm_st_context.iscsi.first_burst_length =
  1372. ISCSI_DEF_FIRST_BURST_LEN;
  1373. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1374. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1375. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1376. req1->sq_page_table_addr_lo;
  1377. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1378. req1->sq_page_table_addr_hi;
  1379. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1380. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1381. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1382. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1383. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1384. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1385. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1386. iscsi->hq_info.pgtbl[0];
  1387. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1388. iscsi->hq_info.pgtbl[1];
  1389. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1390. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1391. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1392. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1393. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1394. iscsi->r2tq_info.pgtbl[0];
  1395. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1396. iscsi->r2tq_info.pgtbl[1];
  1397. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1398. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1399. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1400. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1401. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1402. BNX2X_ISCSI_PBL_NOT_CACHED;
  1403. ictx->xstorm_st_context.iscsi.flags.flags |=
  1404. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1405. ictx->xstorm_st_context.iscsi.flags.flags |=
  1406. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1407. ictx->xstorm_st_context.common.ethernet.reserved_vlan_type =
  1408. ETH_P_8021Q;
  1409. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) &&
  1410. cp->port_mode == CHIP_2_PORT_MODE) {
  1411. port = 0;
  1412. }
  1413. ictx->xstorm_st_context.common.flags =
  1414. 1 << XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT;
  1415. ictx->xstorm_st_context.common.flags =
  1416. port << XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT;
  1417. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1418. /* TSTORM requires the base address of RQ DB & not PTE */
  1419. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1420. req2->rq_page_table_addr_lo & PAGE_MASK;
  1421. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1422. req2->rq_page_table_addr_hi;
  1423. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1424. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1425. ictx->tstorm_st_context.tcp.flags2 |=
  1426. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1427. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1428. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1429. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1430. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1431. req2->rq_page_table_addr_lo;
  1432. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1433. req2->rq_page_table_addr_hi;
  1434. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1435. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1436. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1437. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1438. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1439. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1440. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1441. iscsi->r2tq_info.pgtbl[0];
  1442. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1443. iscsi->r2tq_info.pgtbl[1];
  1444. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1445. req1->cq_page_table_addr_lo;
  1446. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1447. req1->cq_page_table_addr_hi;
  1448. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1449. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1450. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1451. ictx->ustorm_st_context.task_pbe_cache_index =
  1452. BNX2X_ISCSI_PBL_NOT_CACHED;
  1453. ictx->ustorm_st_context.task_pdu_cache_index =
  1454. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1455. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1456. if (j == 3) {
  1457. if (n >= n_max)
  1458. break;
  1459. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1460. j = 0;
  1461. }
  1462. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1463. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1464. req3->qp_first_pte[j].hi;
  1465. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1466. req3->qp_first_pte[j].lo;
  1467. }
  1468. ictx->ustorm_st_context.task_pbl_base.lo =
  1469. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1470. ictx->ustorm_st_context.task_pbl_base.hi =
  1471. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1472. ictx->ustorm_st_context.tce_phy_addr.lo =
  1473. iscsi->task_array_info.pgtbl[0];
  1474. ictx->ustorm_st_context.tce_phy_addr.hi =
  1475. iscsi->task_array_info.pgtbl[1];
  1476. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1477. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1478. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1479. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1480. ISCSI_DEF_MAX_BURST_LEN;
  1481. ictx->ustorm_st_context.negotiated_rx |=
  1482. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1483. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1484. ictx->cstorm_st_context.hq_pbl_base.lo =
  1485. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1486. ictx->cstorm_st_context.hq_pbl_base.hi =
  1487. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1488. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1489. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1490. ictx->cstorm_st_context.task_pbl_base.lo =
  1491. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1492. ictx->cstorm_st_context.task_pbl_base.hi =
  1493. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1494. /* CSTORM and USTORM initialization is different, CSTORM requires
  1495. * CQ DB base & not PTE addr */
  1496. ictx->cstorm_st_context.cq_db_base.lo =
  1497. req1->cq_page_table_addr_lo & PAGE_MASK;
  1498. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1499. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1500. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1501. for (i = 0; i < cp->num_cqs; i++) {
  1502. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1503. ISCSI_INITIAL_SN;
  1504. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1505. ISCSI_INITIAL_SN;
  1506. }
  1507. ictx->xstorm_ag_context.cdu_reserved =
  1508. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1509. ISCSI_CONNECTION_TYPE);
  1510. ictx->ustorm_ag_context.cdu_usage =
  1511. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1512. ISCSI_CONNECTION_TYPE);
  1513. return 0;
  1514. }
  1515. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1516. u32 num, int *work)
  1517. {
  1518. struct iscsi_kwqe_conn_offload1 *req1;
  1519. struct iscsi_kwqe_conn_offload2 *req2;
  1520. struct cnic_local *cp = dev->cnic_priv;
  1521. struct cnic_context *ctx;
  1522. struct iscsi_kcqe kcqe;
  1523. struct kcqe *cqes[1];
  1524. u32 l5_cid;
  1525. int ret = 0;
  1526. if (num < 2) {
  1527. *work = num;
  1528. return -EINVAL;
  1529. }
  1530. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1531. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1532. if ((num - 2) < req2->num_additional_wqes) {
  1533. *work = num;
  1534. return -EINVAL;
  1535. }
  1536. *work = 2 + req2->num_additional_wqes;
  1537. l5_cid = req1->iscsi_conn_id;
  1538. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1539. return -EINVAL;
  1540. memset(&kcqe, 0, sizeof(kcqe));
  1541. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1542. kcqe.iscsi_conn_id = l5_cid;
  1543. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1544. ctx = &cp->ctx_tbl[l5_cid];
  1545. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1546. kcqe.completion_status =
  1547. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1548. goto done;
  1549. }
  1550. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1551. atomic_dec(&cp->iscsi_conn);
  1552. goto done;
  1553. }
  1554. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1555. if (ret) {
  1556. atomic_dec(&cp->iscsi_conn);
  1557. ret = 0;
  1558. goto done;
  1559. }
  1560. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1561. if (ret < 0) {
  1562. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1563. atomic_dec(&cp->iscsi_conn);
  1564. goto done;
  1565. }
  1566. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1567. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1568. done:
  1569. cqes[0] = (struct kcqe *) &kcqe;
  1570. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1571. return 0;
  1572. }
  1573. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1574. {
  1575. struct cnic_local *cp = dev->cnic_priv;
  1576. struct iscsi_kwqe_conn_update *req =
  1577. (struct iscsi_kwqe_conn_update *) kwqe;
  1578. void *data;
  1579. union l5cm_specific_data l5_data;
  1580. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1581. int ret;
  1582. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1583. return -EINVAL;
  1584. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1585. if (!data)
  1586. return -ENOMEM;
  1587. memcpy(data, kwqe, sizeof(struct kwqe));
  1588. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1589. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1590. return ret;
  1591. }
  1592. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1593. {
  1594. struct cnic_local *cp = dev->cnic_priv;
  1595. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1596. union l5cm_specific_data l5_data;
  1597. int ret;
  1598. u32 hw_cid;
  1599. init_waitqueue_head(&ctx->waitq);
  1600. ctx->wait_cond = 0;
  1601. memset(&l5_data, 0, sizeof(l5_data));
  1602. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1603. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1604. hw_cid, NONE_CONNECTION_TYPE, &l5_data);
  1605. if (ret == 0) {
  1606. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  1607. if (unlikely(test_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags)))
  1608. return -EBUSY;
  1609. }
  1610. return 0;
  1611. }
  1612. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1613. {
  1614. struct cnic_local *cp = dev->cnic_priv;
  1615. struct iscsi_kwqe_conn_destroy *req =
  1616. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1617. u32 l5_cid = req->reserved0;
  1618. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1619. int ret = 0;
  1620. struct iscsi_kcqe kcqe;
  1621. struct kcqe *cqes[1];
  1622. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1623. goto skip_cfc_delete;
  1624. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1625. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1626. if (delta > (2 * HZ))
  1627. delta = 0;
  1628. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1629. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1630. goto destroy_reply;
  1631. }
  1632. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1633. skip_cfc_delete:
  1634. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1635. if (!ret) {
  1636. atomic_dec(&cp->iscsi_conn);
  1637. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1638. }
  1639. destroy_reply:
  1640. memset(&kcqe, 0, sizeof(kcqe));
  1641. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1642. kcqe.iscsi_conn_id = l5_cid;
  1643. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1644. kcqe.iscsi_conn_context_id = req->context_id;
  1645. cqes[0] = (struct kcqe *) &kcqe;
  1646. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1647. return 0;
  1648. }
  1649. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1650. struct l4_kwq_connect_req1 *kwqe1,
  1651. struct l4_kwq_connect_req3 *kwqe3,
  1652. struct l5cm_active_conn_buffer *conn_buf)
  1653. {
  1654. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1655. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1656. &conn_buf->xstorm_conn_buffer;
  1657. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1658. &conn_buf->tstorm_conn_buffer;
  1659. struct regpair context_addr;
  1660. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1661. struct in6_addr src_ip, dst_ip;
  1662. int i;
  1663. u32 *addrp;
  1664. addrp = (u32 *) &conn_addr->local_ip_addr;
  1665. for (i = 0; i < 4; i++, addrp++)
  1666. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1667. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1668. for (i = 0; i < 4; i++, addrp++)
  1669. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1670. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1671. xstorm_buf->context_addr.hi = context_addr.hi;
  1672. xstorm_buf->context_addr.lo = context_addr.lo;
  1673. xstorm_buf->mss = 0xffff;
  1674. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1675. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1676. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1677. xstorm_buf->pseudo_header_checksum =
  1678. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1679. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1680. tstorm_buf->params |=
  1681. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1682. if (kwqe3->ka_timeout) {
  1683. tstorm_buf->ka_enable = 1;
  1684. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1685. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1686. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1687. }
  1688. tstorm_buf->max_rt_time = 0xffffffff;
  1689. }
  1690. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1691. {
  1692. struct cnic_local *cp = dev->cnic_priv;
  1693. u32 pfid = cp->pfid;
  1694. u8 *mac = dev->mac_addr;
  1695. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1696. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1697. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1698. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1699. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1700. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1701. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1702. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1703. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1704. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1705. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1706. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1707. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1708. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1709. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1710. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1711. mac[4]);
  1712. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1713. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1714. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1715. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1716. mac[2]);
  1717. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1718. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[1]);
  1719. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1720. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1721. mac[0]);
  1722. }
  1723. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1724. {
  1725. struct cnic_local *cp = dev->cnic_priv;
  1726. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1727. u16 tstorm_flags = 0;
  1728. if (tcp_ts) {
  1729. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1730. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1731. }
  1732. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1733. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
  1734. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1735. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
  1736. }
  1737. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1738. u32 num, int *work)
  1739. {
  1740. struct cnic_local *cp = dev->cnic_priv;
  1741. struct l4_kwq_connect_req1 *kwqe1 =
  1742. (struct l4_kwq_connect_req1 *) wqes[0];
  1743. struct l4_kwq_connect_req3 *kwqe3;
  1744. struct l5cm_active_conn_buffer *conn_buf;
  1745. struct l5cm_conn_addr_params *conn_addr;
  1746. union l5cm_specific_data l5_data;
  1747. u32 l5_cid = kwqe1->pg_cid;
  1748. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1749. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1750. int ret;
  1751. if (num < 2) {
  1752. *work = num;
  1753. return -EINVAL;
  1754. }
  1755. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1756. *work = 3;
  1757. else
  1758. *work = 2;
  1759. if (num < *work) {
  1760. *work = num;
  1761. return -EINVAL;
  1762. }
  1763. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1764. netdev_err(dev->netdev, "conn_buf size too big\n");
  1765. return -ENOMEM;
  1766. }
  1767. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1768. if (!conn_buf)
  1769. return -ENOMEM;
  1770. memset(conn_buf, 0, sizeof(*conn_buf));
  1771. conn_addr = &conn_buf->conn_addr_buf;
  1772. conn_addr->remote_addr_0 = csk->ha[0];
  1773. conn_addr->remote_addr_1 = csk->ha[1];
  1774. conn_addr->remote_addr_2 = csk->ha[2];
  1775. conn_addr->remote_addr_3 = csk->ha[3];
  1776. conn_addr->remote_addr_4 = csk->ha[4];
  1777. conn_addr->remote_addr_5 = csk->ha[5];
  1778. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1779. struct l4_kwq_connect_req2 *kwqe2 =
  1780. (struct l4_kwq_connect_req2 *) wqes[1];
  1781. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1782. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1783. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1784. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1785. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1786. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1787. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1788. }
  1789. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1790. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1791. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1792. conn_addr->local_tcp_port = kwqe1->src_port;
  1793. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1794. conn_addr->pmtu = kwqe3->pmtu;
  1795. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1796. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1797. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
  1798. cnic_bnx2x_set_tcp_timestamp(dev,
  1799. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1800. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1801. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1802. if (!ret)
  1803. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1804. return ret;
  1805. }
  1806. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1807. {
  1808. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1809. union l5cm_specific_data l5_data;
  1810. int ret;
  1811. memset(&l5_data, 0, sizeof(l5_data));
  1812. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1813. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1814. return ret;
  1815. }
  1816. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1817. {
  1818. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1819. union l5cm_specific_data l5_data;
  1820. int ret;
  1821. memset(&l5_data, 0, sizeof(l5_data));
  1822. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1823. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1824. return ret;
  1825. }
  1826. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1827. {
  1828. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1829. struct l4_kcq kcqe;
  1830. struct kcqe *cqes[1];
  1831. memset(&kcqe, 0, sizeof(kcqe));
  1832. kcqe.pg_host_opaque = req->host_opaque;
  1833. kcqe.pg_cid = req->host_opaque;
  1834. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1835. cqes[0] = (struct kcqe *) &kcqe;
  1836. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1837. return 0;
  1838. }
  1839. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1840. {
  1841. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1842. struct l4_kcq kcqe;
  1843. struct kcqe *cqes[1];
  1844. memset(&kcqe, 0, sizeof(kcqe));
  1845. kcqe.pg_host_opaque = req->pg_host_opaque;
  1846. kcqe.pg_cid = req->pg_cid;
  1847. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1848. cqes[0] = (struct kcqe *) &kcqe;
  1849. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1850. return 0;
  1851. }
  1852. static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
  1853. {
  1854. struct fcoe_kwqe_stat *req;
  1855. struct fcoe_stat_ramrod_params *fcoe_stat;
  1856. union l5cm_specific_data l5_data;
  1857. struct cnic_local *cp = dev->cnic_priv;
  1858. int ret;
  1859. u32 cid;
  1860. req = (struct fcoe_kwqe_stat *) kwqe;
  1861. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1862. fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1863. if (!fcoe_stat)
  1864. return -ENOMEM;
  1865. memset(fcoe_stat, 0, sizeof(*fcoe_stat));
  1866. memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
  1867. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT_FUNC, cid,
  1868. FCOE_CONNECTION_TYPE, &l5_data);
  1869. return ret;
  1870. }
  1871. static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
  1872. u32 num, int *work)
  1873. {
  1874. int ret;
  1875. struct cnic_local *cp = dev->cnic_priv;
  1876. u32 cid;
  1877. struct fcoe_init_ramrod_params *fcoe_init;
  1878. struct fcoe_kwqe_init1 *req1;
  1879. struct fcoe_kwqe_init2 *req2;
  1880. struct fcoe_kwqe_init3 *req3;
  1881. union l5cm_specific_data l5_data;
  1882. if (num < 3) {
  1883. *work = num;
  1884. return -EINVAL;
  1885. }
  1886. req1 = (struct fcoe_kwqe_init1 *) wqes[0];
  1887. req2 = (struct fcoe_kwqe_init2 *) wqes[1];
  1888. req3 = (struct fcoe_kwqe_init3 *) wqes[2];
  1889. if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
  1890. *work = 1;
  1891. return -EINVAL;
  1892. }
  1893. if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
  1894. *work = 2;
  1895. return -EINVAL;
  1896. }
  1897. if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
  1898. netdev_err(dev->netdev, "fcoe_init size too big\n");
  1899. return -ENOMEM;
  1900. }
  1901. fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1902. if (!fcoe_init)
  1903. return -ENOMEM;
  1904. memset(fcoe_init, 0, sizeof(*fcoe_init));
  1905. memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
  1906. memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
  1907. memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
  1908. fcoe_init->eq_pbl_base.lo = cp->kcq2.dma.pgtbl_map & 0xffffffff;
  1909. fcoe_init->eq_pbl_base.hi = (u64) cp->kcq2.dma.pgtbl_map >> 32;
  1910. fcoe_init->eq_pbl_size = cp->kcq2.dma.num_pages;
  1911. fcoe_init->sb_num = cp->status_blk_num;
  1912. fcoe_init->eq_prod = MAX_KCQ_IDX;
  1913. fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
  1914. cp->kcq2.sw_prod_idx = 0;
  1915. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1916. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT_FUNC, cid,
  1917. FCOE_CONNECTION_TYPE, &l5_data);
  1918. *work = 3;
  1919. return ret;
  1920. }
  1921. static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1922. u32 num, int *work)
  1923. {
  1924. int ret = 0;
  1925. u32 cid = -1, l5_cid;
  1926. struct cnic_local *cp = dev->cnic_priv;
  1927. struct fcoe_kwqe_conn_offload1 *req1;
  1928. struct fcoe_kwqe_conn_offload2 *req2;
  1929. struct fcoe_kwqe_conn_offload3 *req3;
  1930. struct fcoe_kwqe_conn_offload4 *req4;
  1931. struct fcoe_conn_offload_ramrod_params *fcoe_offload;
  1932. struct cnic_context *ctx;
  1933. struct fcoe_context *fctx;
  1934. struct regpair ctx_addr;
  1935. union l5cm_specific_data l5_data;
  1936. struct fcoe_kcqe kcqe;
  1937. struct kcqe *cqes[1];
  1938. if (num < 4) {
  1939. *work = num;
  1940. return -EINVAL;
  1941. }
  1942. req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
  1943. req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
  1944. req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
  1945. req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
  1946. *work = 4;
  1947. l5_cid = req1->fcoe_conn_id;
  1948. if (l5_cid >= dev->max_fcoe_conn)
  1949. goto err_reply;
  1950. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1951. ctx = &cp->ctx_tbl[l5_cid];
  1952. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1953. goto err_reply;
  1954. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1955. if (ret) {
  1956. ret = 0;
  1957. goto err_reply;
  1958. }
  1959. cid = ctx->cid;
  1960. fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
  1961. if (fctx) {
  1962. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1963. u32 val;
  1964. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1965. FCOE_CONNECTION_TYPE);
  1966. fctx->xstorm_ag_context.cdu_reserved = val;
  1967. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1968. FCOE_CONNECTION_TYPE);
  1969. fctx->ustorm_ag_context.cdu_usage = val;
  1970. }
  1971. if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
  1972. netdev_err(dev->netdev, "fcoe_offload size too big\n");
  1973. goto err_reply;
  1974. }
  1975. fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1976. if (!fcoe_offload)
  1977. goto err_reply;
  1978. memset(fcoe_offload, 0, sizeof(*fcoe_offload));
  1979. memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
  1980. memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
  1981. memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
  1982. memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
  1983. cid = BNX2X_HW_CID(cp, cid);
  1984. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
  1985. FCOE_CONNECTION_TYPE, &l5_data);
  1986. if (!ret)
  1987. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1988. return ret;
  1989. err_reply:
  1990. if (cid != -1)
  1991. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1992. memset(&kcqe, 0, sizeof(kcqe));
  1993. kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
  1994. kcqe.fcoe_conn_id = req1->fcoe_conn_id;
  1995. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1996. cqes[0] = (struct kcqe *) &kcqe;
  1997. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  1998. return ret;
  1999. }
  2000. static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
  2001. {
  2002. struct fcoe_kwqe_conn_enable_disable *req;
  2003. struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
  2004. union l5cm_specific_data l5_data;
  2005. int ret;
  2006. u32 cid, l5_cid;
  2007. struct cnic_local *cp = dev->cnic_priv;
  2008. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2009. cid = req->context_id;
  2010. l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
  2011. if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
  2012. netdev_err(dev->netdev, "fcoe_enable size too big\n");
  2013. return -ENOMEM;
  2014. }
  2015. fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  2016. if (!fcoe_enable)
  2017. return -ENOMEM;
  2018. memset(fcoe_enable, 0, sizeof(*fcoe_enable));
  2019. memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
  2020. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
  2021. FCOE_CONNECTION_TYPE, &l5_data);
  2022. return ret;
  2023. }
  2024. static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
  2025. {
  2026. struct fcoe_kwqe_conn_enable_disable *req;
  2027. struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
  2028. union l5cm_specific_data l5_data;
  2029. int ret;
  2030. u32 cid, l5_cid;
  2031. struct cnic_local *cp = dev->cnic_priv;
  2032. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2033. cid = req->context_id;
  2034. l5_cid = req->conn_id;
  2035. if (l5_cid >= dev->max_fcoe_conn)
  2036. return -EINVAL;
  2037. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2038. if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
  2039. netdev_err(dev->netdev, "fcoe_disable size too big\n");
  2040. return -ENOMEM;
  2041. }
  2042. fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  2043. if (!fcoe_disable)
  2044. return -ENOMEM;
  2045. memset(fcoe_disable, 0, sizeof(*fcoe_disable));
  2046. memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
  2047. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
  2048. FCOE_CONNECTION_TYPE, &l5_data);
  2049. return ret;
  2050. }
  2051. static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2052. {
  2053. struct fcoe_kwqe_conn_destroy *req;
  2054. union l5cm_specific_data l5_data;
  2055. int ret;
  2056. u32 cid, l5_cid;
  2057. struct cnic_local *cp = dev->cnic_priv;
  2058. struct cnic_context *ctx;
  2059. struct fcoe_kcqe kcqe;
  2060. struct kcqe *cqes[1];
  2061. req = (struct fcoe_kwqe_conn_destroy *) kwqe;
  2062. cid = req->context_id;
  2063. l5_cid = req->conn_id;
  2064. if (l5_cid >= dev->max_fcoe_conn)
  2065. return -EINVAL;
  2066. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2067. ctx = &cp->ctx_tbl[l5_cid];
  2068. init_waitqueue_head(&ctx->waitq);
  2069. ctx->wait_cond = 0;
  2070. memset(&kcqe, 0, sizeof(kcqe));
  2071. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_ERROR;
  2072. memset(&l5_data, 0, sizeof(l5_data));
  2073. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
  2074. FCOE_CONNECTION_TYPE, &l5_data);
  2075. if (ret == 0) {
  2076. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  2077. if (ctx->wait_cond)
  2078. kcqe.completion_status = 0;
  2079. }
  2080. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  2081. queue_delayed_work(cnic_wq, &cp->delete_task, msecs_to_jiffies(2000));
  2082. kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
  2083. kcqe.fcoe_conn_id = req->conn_id;
  2084. kcqe.fcoe_conn_context_id = cid;
  2085. cqes[0] = (struct kcqe *) &kcqe;
  2086. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2087. return ret;
  2088. }
  2089. static void cnic_bnx2x_delete_wait(struct cnic_dev *dev, u32 start_cid)
  2090. {
  2091. struct cnic_local *cp = dev->cnic_priv;
  2092. u32 i;
  2093. for (i = start_cid; i < cp->max_cid_space; i++) {
  2094. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2095. int j;
  2096. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2097. msleep(10);
  2098. for (j = 0; j < 5; j++) {
  2099. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2100. break;
  2101. msleep(20);
  2102. }
  2103. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2104. netdev_warn(dev->netdev, "CID %x not deleted\n",
  2105. ctx->cid);
  2106. }
  2107. }
  2108. static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2109. {
  2110. struct fcoe_kwqe_destroy *req;
  2111. union l5cm_specific_data l5_data;
  2112. struct cnic_local *cp = dev->cnic_priv;
  2113. int ret;
  2114. u32 cid;
  2115. cnic_bnx2x_delete_wait(dev, MAX_ISCSI_TBL_SZ);
  2116. req = (struct fcoe_kwqe_destroy *) kwqe;
  2117. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  2118. memset(&l5_data, 0, sizeof(l5_data));
  2119. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY_FUNC, cid,
  2120. FCOE_CONNECTION_TYPE, &l5_data);
  2121. return ret;
  2122. }
  2123. static void cnic_bnx2x_kwqe_err(struct cnic_dev *dev, struct kwqe *kwqe)
  2124. {
  2125. struct cnic_local *cp = dev->cnic_priv;
  2126. struct kcqe kcqe;
  2127. struct kcqe *cqes[1];
  2128. u32 cid;
  2129. u32 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2130. u32 layer_code = kwqe->kwqe_op_flag & KWQE_LAYER_MASK;
  2131. u32 kcqe_op;
  2132. int ulp_type;
  2133. cid = kwqe->kwqe_info0;
  2134. memset(&kcqe, 0, sizeof(kcqe));
  2135. if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_FCOE) {
  2136. u32 l5_cid = 0;
  2137. ulp_type = CNIC_ULP_FCOE;
  2138. if (opcode == FCOE_KWQE_OPCODE_DISABLE_CONN) {
  2139. struct fcoe_kwqe_conn_enable_disable *req;
  2140. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2141. kcqe_op = FCOE_KCQE_OPCODE_DISABLE_CONN;
  2142. cid = req->context_id;
  2143. l5_cid = req->conn_id;
  2144. } else if (opcode == FCOE_KWQE_OPCODE_DESTROY) {
  2145. kcqe_op = FCOE_KCQE_OPCODE_DESTROY_FUNC;
  2146. } else {
  2147. return;
  2148. }
  2149. kcqe.kcqe_op_flag = kcqe_op << KCQE_FLAGS_OPCODE_SHIFT;
  2150. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_FCOE;
  2151. kcqe.kcqe_info1 = FCOE_KCQE_COMPLETION_STATUS_PARITY_ERROR;
  2152. kcqe.kcqe_info2 = cid;
  2153. kcqe.kcqe_info0 = l5_cid;
  2154. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_ISCSI) {
  2155. ulp_type = CNIC_ULP_ISCSI;
  2156. if (opcode == ISCSI_KWQE_OPCODE_UPDATE_CONN)
  2157. cid = kwqe->kwqe_info1;
  2158. kcqe.kcqe_op_flag = (opcode + 0x10) << KCQE_FLAGS_OPCODE_SHIFT;
  2159. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_ISCSI;
  2160. kcqe.kcqe_info1 = ISCSI_KCQE_COMPLETION_STATUS_PARITY_ERR;
  2161. kcqe.kcqe_info2 = cid;
  2162. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &kcqe.kcqe_info0);
  2163. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L4) {
  2164. struct l4_kcq *l4kcqe = (struct l4_kcq *) &kcqe;
  2165. ulp_type = CNIC_ULP_L4;
  2166. if (opcode == L4_KWQE_OPCODE_VALUE_CONNECT1)
  2167. kcqe_op = L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE;
  2168. else if (opcode == L4_KWQE_OPCODE_VALUE_RESET)
  2169. kcqe_op = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2170. else if (opcode == L4_KWQE_OPCODE_VALUE_CLOSE)
  2171. kcqe_op = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2172. else
  2173. return;
  2174. kcqe.kcqe_op_flag = (kcqe_op << KCQE_FLAGS_OPCODE_SHIFT) |
  2175. KCQE_FLAGS_LAYER_MASK_L4;
  2176. l4kcqe->status = L4_KCQE_COMPLETION_STATUS_PARITY_ERROR;
  2177. l4kcqe->cid = cid;
  2178. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &l4kcqe->conn_id);
  2179. } else {
  2180. return;
  2181. }
  2182. cqes[0] = &kcqe;
  2183. cnic_reply_bnx2x_kcqes(dev, ulp_type, cqes, 1);
  2184. }
  2185. static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
  2186. struct kwqe *wqes[], u32 num_wqes)
  2187. {
  2188. int i, work, ret;
  2189. u32 opcode;
  2190. struct kwqe *kwqe;
  2191. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2192. return -EAGAIN; /* bnx2 is down */
  2193. for (i = 0; i < num_wqes; ) {
  2194. kwqe = wqes[i];
  2195. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2196. work = 1;
  2197. switch (opcode) {
  2198. case ISCSI_KWQE_OPCODE_INIT1:
  2199. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  2200. break;
  2201. case ISCSI_KWQE_OPCODE_INIT2:
  2202. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  2203. break;
  2204. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  2205. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  2206. num_wqes - i, &work);
  2207. break;
  2208. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  2209. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  2210. break;
  2211. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  2212. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  2213. break;
  2214. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  2215. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  2216. &work);
  2217. break;
  2218. case L4_KWQE_OPCODE_VALUE_CLOSE:
  2219. ret = cnic_bnx2x_close(dev, kwqe);
  2220. break;
  2221. case L4_KWQE_OPCODE_VALUE_RESET:
  2222. ret = cnic_bnx2x_reset(dev, kwqe);
  2223. break;
  2224. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  2225. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  2226. break;
  2227. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  2228. ret = cnic_bnx2x_update_pg(dev, kwqe);
  2229. break;
  2230. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  2231. ret = 0;
  2232. break;
  2233. default:
  2234. ret = 0;
  2235. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2236. opcode);
  2237. break;
  2238. }
  2239. if (ret < 0) {
  2240. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2241. opcode);
  2242. /* Possibly bnx2x parity error, send completion
  2243. * to ulp drivers with error code to speed up
  2244. * cleanup and reset recovery.
  2245. */
  2246. if (ret == -EIO || ret == -EAGAIN)
  2247. cnic_bnx2x_kwqe_err(dev, kwqe);
  2248. }
  2249. i += work;
  2250. }
  2251. return 0;
  2252. }
  2253. static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
  2254. struct kwqe *wqes[], u32 num_wqes)
  2255. {
  2256. struct cnic_local *cp = dev->cnic_priv;
  2257. int i, work, ret;
  2258. u32 opcode;
  2259. struct kwqe *kwqe;
  2260. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2261. return -EAGAIN; /* bnx2 is down */
  2262. if (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
  2263. return -EINVAL;
  2264. for (i = 0; i < num_wqes; ) {
  2265. kwqe = wqes[i];
  2266. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2267. work = 1;
  2268. switch (opcode) {
  2269. case FCOE_KWQE_OPCODE_INIT1:
  2270. ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
  2271. num_wqes - i, &work);
  2272. break;
  2273. case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
  2274. ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
  2275. num_wqes - i, &work);
  2276. break;
  2277. case FCOE_KWQE_OPCODE_ENABLE_CONN:
  2278. ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
  2279. break;
  2280. case FCOE_KWQE_OPCODE_DISABLE_CONN:
  2281. ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
  2282. break;
  2283. case FCOE_KWQE_OPCODE_DESTROY_CONN:
  2284. ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
  2285. break;
  2286. case FCOE_KWQE_OPCODE_DESTROY:
  2287. ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
  2288. break;
  2289. case FCOE_KWQE_OPCODE_STAT:
  2290. ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
  2291. break;
  2292. default:
  2293. ret = 0;
  2294. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2295. opcode);
  2296. break;
  2297. }
  2298. if (ret < 0) {
  2299. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2300. opcode);
  2301. /* Possibly bnx2x parity error, send completion
  2302. * to ulp drivers with error code to speed up
  2303. * cleanup and reset recovery.
  2304. */
  2305. if (ret == -EIO || ret == -EAGAIN)
  2306. cnic_bnx2x_kwqe_err(dev, kwqe);
  2307. }
  2308. i += work;
  2309. }
  2310. return 0;
  2311. }
  2312. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  2313. u32 num_wqes)
  2314. {
  2315. int ret = -EINVAL;
  2316. u32 layer_code;
  2317. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2318. return -EAGAIN; /* bnx2x is down */
  2319. if (!num_wqes)
  2320. return 0;
  2321. layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
  2322. switch (layer_code) {
  2323. case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
  2324. case KWQE_FLAGS_LAYER_MASK_L4:
  2325. case KWQE_FLAGS_LAYER_MASK_L2:
  2326. ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
  2327. break;
  2328. case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
  2329. ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
  2330. break;
  2331. }
  2332. return ret;
  2333. }
  2334. static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
  2335. {
  2336. if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
  2337. return KCQE_FLAGS_LAYER_MASK_L4;
  2338. return opflag & KCQE_FLAGS_LAYER_MASK;
  2339. }
  2340. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  2341. {
  2342. struct cnic_local *cp = dev->cnic_priv;
  2343. int i, j, comp = 0;
  2344. i = 0;
  2345. j = 1;
  2346. while (num_cqes) {
  2347. struct cnic_ulp_ops *ulp_ops;
  2348. int ulp_type;
  2349. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  2350. u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
  2351. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  2352. comp++;
  2353. while (j < num_cqes) {
  2354. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  2355. if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
  2356. break;
  2357. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  2358. comp++;
  2359. j++;
  2360. }
  2361. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  2362. ulp_type = CNIC_ULP_RDMA;
  2363. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  2364. ulp_type = CNIC_ULP_ISCSI;
  2365. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
  2366. ulp_type = CNIC_ULP_FCOE;
  2367. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  2368. ulp_type = CNIC_ULP_L4;
  2369. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  2370. goto end;
  2371. else {
  2372. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  2373. kcqe_op_flag);
  2374. goto end;
  2375. }
  2376. rcu_read_lock();
  2377. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2378. if (likely(ulp_ops)) {
  2379. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  2380. cp->completed_kcq + i, j);
  2381. }
  2382. rcu_read_unlock();
  2383. end:
  2384. num_cqes -= j;
  2385. i += j;
  2386. j = 1;
  2387. }
  2388. if (unlikely(comp))
  2389. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  2390. }
  2391. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  2392. {
  2393. struct cnic_local *cp = dev->cnic_priv;
  2394. u16 i, ri, hw_prod, last;
  2395. struct kcqe *kcqe;
  2396. int kcqe_cnt = 0, last_cnt = 0;
  2397. i = ri = last = info->sw_prod_idx;
  2398. ri &= MAX_KCQ_IDX;
  2399. hw_prod = *info->hw_prod_idx_ptr;
  2400. hw_prod = info->hw_idx(hw_prod);
  2401. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  2402. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  2403. cp->completed_kcq[kcqe_cnt++] = kcqe;
  2404. i = info->next_idx(i);
  2405. ri = i & MAX_KCQ_IDX;
  2406. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  2407. last_cnt = kcqe_cnt;
  2408. last = i;
  2409. }
  2410. }
  2411. info->sw_prod_idx = last;
  2412. return last_cnt;
  2413. }
  2414. static int cnic_l2_completion(struct cnic_local *cp)
  2415. {
  2416. u16 hw_cons, sw_cons;
  2417. struct cnic_uio_dev *udev = cp->udev;
  2418. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  2419. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  2420. u32 cmd;
  2421. int comp = 0;
  2422. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  2423. return 0;
  2424. hw_cons = *cp->rx_cons_ptr;
  2425. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  2426. hw_cons++;
  2427. sw_cons = cp->rx_cons;
  2428. while (sw_cons != hw_cons) {
  2429. u8 cqe_fp_flags;
  2430. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  2431. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  2432. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  2433. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  2434. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  2435. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  2436. cmd == RAMROD_CMD_ID_ETH_HALT)
  2437. comp++;
  2438. }
  2439. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  2440. }
  2441. return comp;
  2442. }
  2443. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  2444. {
  2445. u16 rx_cons, tx_cons;
  2446. int comp = 0;
  2447. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  2448. return;
  2449. rx_cons = *cp->rx_cons_ptr;
  2450. tx_cons = *cp->tx_cons_ptr;
  2451. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  2452. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  2453. comp = cnic_l2_completion(cp);
  2454. cp->tx_cons = tx_cons;
  2455. cp->rx_cons = rx_cons;
  2456. if (cp->udev)
  2457. uio_event_notify(&cp->udev->cnic_uinfo);
  2458. }
  2459. if (comp)
  2460. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  2461. }
  2462. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  2463. {
  2464. struct cnic_local *cp = dev->cnic_priv;
  2465. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2466. int kcqe_cnt;
  2467. /* status block index must be read before reading other fields */
  2468. rmb();
  2469. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2470. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  2471. service_kcqes(dev, kcqe_cnt);
  2472. /* Tell compiler that status_blk fields can change. */
  2473. barrier();
  2474. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2475. /* status block index must be read first */
  2476. rmb();
  2477. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2478. }
  2479. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  2480. cnic_chk_pkt_rings(cp);
  2481. return status_idx;
  2482. }
  2483. static int cnic_service_bnx2(void *data, void *status_blk)
  2484. {
  2485. struct cnic_dev *dev = data;
  2486. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2487. struct status_block *sblk = status_blk;
  2488. return sblk->status_idx;
  2489. }
  2490. return cnic_service_bnx2_queues(dev);
  2491. }
  2492. static void cnic_service_bnx2_msix(unsigned long data)
  2493. {
  2494. struct cnic_dev *dev = (struct cnic_dev *) data;
  2495. struct cnic_local *cp = dev->cnic_priv;
  2496. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  2497. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2498. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2499. }
  2500. static void cnic_doirq(struct cnic_dev *dev)
  2501. {
  2502. struct cnic_local *cp = dev->cnic_priv;
  2503. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2504. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  2505. prefetch(cp->status_blk.gen);
  2506. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  2507. tasklet_schedule(&cp->cnic_irq_task);
  2508. }
  2509. }
  2510. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  2511. {
  2512. struct cnic_dev *dev = dev_instance;
  2513. struct cnic_local *cp = dev->cnic_priv;
  2514. if (cp->ack_int)
  2515. cp->ack_int(dev);
  2516. cnic_doirq(dev);
  2517. return IRQ_HANDLED;
  2518. }
  2519. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  2520. u16 index, u8 op, u8 update)
  2521. {
  2522. struct cnic_local *cp = dev->cnic_priv;
  2523. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  2524. COMMAND_REG_INT_ACK);
  2525. struct igu_ack_register igu_ack;
  2526. igu_ack.status_block_index = index;
  2527. igu_ack.sb_id_and_flags =
  2528. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  2529. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  2530. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  2531. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  2532. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2533. }
  2534. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2535. u16 index, u8 op, u8 update)
  2536. {
  2537. struct igu_regular cmd_data;
  2538. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2539. cmd_data.sb_id_and_flags =
  2540. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2541. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2542. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2543. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2544. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2545. }
  2546. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2547. {
  2548. struct cnic_local *cp = dev->cnic_priv;
  2549. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2550. IGU_INT_DISABLE, 0);
  2551. }
  2552. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2553. {
  2554. struct cnic_local *cp = dev->cnic_priv;
  2555. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2556. IGU_INT_DISABLE, 0);
  2557. }
  2558. static void cnic_arm_bnx2x_msix(struct cnic_dev *dev, u32 idx)
  2559. {
  2560. struct cnic_local *cp = dev->cnic_priv;
  2561. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, idx,
  2562. IGU_INT_ENABLE, 1);
  2563. }
  2564. static void cnic_arm_bnx2x_e2_msix(struct cnic_dev *dev, u32 idx)
  2565. {
  2566. struct cnic_local *cp = dev->cnic_priv;
  2567. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, idx,
  2568. IGU_INT_ENABLE, 1);
  2569. }
  2570. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2571. {
  2572. u32 last_status = *info->status_idx_ptr;
  2573. int kcqe_cnt;
  2574. /* status block index must be read before reading the KCQ */
  2575. rmb();
  2576. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2577. service_kcqes(dev, kcqe_cnt);
  2578. /* Tell compiler that sblk fields can change. */
  2579. barrier();
  2580. last_status = *info->status_idx_ptr;
  2581. /* status block index must be read before reading the KCQ */
  2582. rmb();
  2583. }
  2584. return last_status;
  2585. }
  2586. static void cnic_service_bnx2x_bh(unsigned long data)
  2587. {
  2588. struct cnic_dev *dev = (struct cnic_dev *) data;
  2589. struct cnic_local *cp = dev->cnic_priv;
  2590. u32 status_idx, new_status_idx;
  2591. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2592. return;
  2593. while (1) {
  2594. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2595. CNIC_WR16(dev, cp->kcq1.io_addr,
  2596. cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2597. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_FCOE) {
  2598. cp->arm_int(dev, status_idx);
  2599. break;
  2600. }
  2601. new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
  2602. if (new_status_idx != status_idx)
  2603. continue;
  2604. CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
  2605. MAX_KCQ_IDX);
  2606. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2607. status_idx, IGU_INT_ENABLE, 1);
  2608. break;
  2609. }
  2610. }
  2611. static int cnic_service_bnx2x(void *data, void *status_blk)
  2612. {
  2613. struct cnic_dev *dev = data;
  2614. struct cnic_local *cp = dev->cnic_priv;
  2615. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2616. cnic_doirq(dev);
  2617. cnic_chk_pkt_rings(cp);
  2618. return 0;
  2619. }
  2620. static void cnic_ulp_stop_one(struct cnic_local *cp, int if_type)
  2621. {
  2622. struct cnic_ulp_ops *ulp_ops;
  2623. if (if_type == CNIC_ULP_ISCSI)
  2624. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2625. mutex_lock(&cnic_lock);
  2626. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2627. lockdep_is_held(&cnic_lock));
  2628. if (!ulp_ops) {
  2629. mutex_unlock(&cnic_lock);
  2630. return;
  2631. }
  2632. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2633. mutex_unlock(&cnic_lock);
  2634. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2635. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2636. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2637. }
  2638. static void cnic_ulp_stop(struct cnic_dev *dev)
  2639. {
  2640. struct cnic_local *cp = dev->cnic_priv;
  2641. int if_type;
  2642. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++)
  2643. cnic_ulp_stop_one(cp, if_type);
  2644. }
  2645. static void cnic_ulp_start(struct cnic_dev *dev)
  2646. {
  2647. struct cnic_local *cp = dev->cnic_priv;
  2648. int if_type;
  2649. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2650. struct cnic_ulp_ops *ulp_ops;
  2651. mutex_lock(&cnic_lock);
  2652. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2653. lockdep_is_held(&cnic_lock));
  2654. if (!ulp_ops || !ulp_ops->cnic_start) {
  2655. mutex_unlock(&cnic_lock);
  2656. continue;
  2657. }
  2658. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2659. mutex_unlock(&cnic_lock);
  2660. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2661. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2662. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2663. }
  2664. }
  2665. static int cnic_copy_ulp_stats(struct cnic_dev *dev, int ulp_type)
  2666. {
  2667. struct cnic_local *cp = dev->cnic_priv;
  2668. struct cnic_ulp_ops *ulp_ops;
  2669. int rc;
  2670. mutex_lock(&cnic_lock);
  2671. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  2672. if (ulp_ops && ulp_ops->cnic_get_stats)
  2673. rc = ulp_ops->cnic_get_stats(cp->ulp_handle[ulp_type]);
  2674. else
  2675. rc = -ENODEV;
  2676. mutex_unlock(&cnic_lock);
  2677. return rc;
  2678. }
  2679. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2680. {
  2681. struct cnic_dev *dev = data;
  2682. int ulp_type = CNIC_ULP_ISCSI;
  2683. switch (info->cmd) {
  2684. case CNIC_CTL_STOP_CMD:
  2685. cnic_hold(dev);
  2686. cnic_ulp_stop(dev);
  2687. cnic_stop_hw(dev);
  2688. cnic_put(dev);
  2689. break;
  2690. case CNIC_CTL_START_CMD:
  2691. cnic_hold(dev);
  2692. if (!cnic_start_hw(dev))
  2693. cnic_ulp_start(dev);
  2694. cnic_put(dev);
  2695. break;
  2696. case CNIC_CTL_STOP_ISCSI_CMD: {
  2697. struct cnic_local *cp = dev->cnic_priv;
  2698. set_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags);
  2699. queue_delayed_work(cnic_wq, &cp->delete_task, 0);
  2700. break;
  2701. }
  2702. case CNIC_CTL_COMPLETION_CMD: {
  2703. struct cnic_ctl_completion *comp = &info->data.comp;
  2704. u32 cid = BNX2X_SW_CID(comp->cid);
  2705. u32 l5_cid;
  2706. struct cnic_local *cp = dev->cnic_priv;
  2707. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2708. break;
  2709. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2710. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2711. if (unlikely(comp->error)) {
  2712. set_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags);
  2713. netdev_err(dev->netdev,
  2714. "CID %x CFC delete comp error %x\n",
  2715. cid, comp->error);
  2716. }
  2717. ctx->wait_cond = 1;
  2718. wake_up(&ctx->waitq);
  2719. }
  2720. break;
  2721. }
  2722. case CNIC_CTL_FCOE_STATS_GET_CMD:
  2723. ulp_type = CNIC_ULP_FCOE;
  2724. /* fall through */
  2725. case CNIC_CTL_ISCSI_STATS_GET_CMD:
  2726. cnic_hold(dev);
  2727. cnic_copy_ulp_stats(dev, ulp_type);
  2728. cnic_put(dev);
  2729. break;
  2730. default:
  2731. return -EINVAL;
  2732. }
  2733. return 0;
  2734. }
  2735. static void cnic_ulp_init(struct cnic_dev *dev)
  2736. {
  2737. int i;
  2738. struct cnic_local *cp = dev->cnic_priv;
  2739. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2740. struct cnic_ulp_ops *ulp_ops;
  2741. mutex_lock(&cnic_lock);
  2742. ulp_ops = cnic_ulp_tbl_prot(i);
  2743. if (!ulp_ops || !ulp_ops->cnic_init) {
  2744. mutex_unlock(&cnic_lock);
  2745. continue;
  2746. }
  2747. ulp_get(ulp_ops);
  2748. mutex_unlock(&cnic_lock);
  2749. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2750. ulp_ops->cnic_init(dev);
  2751. ulp_put(ulp_ops);
  2752. }
  2753. }
  2754. static void cnic_ulp_exit(struct cnic_dev *dev)
  2755. {
  2756. int i;
  2757. struct cnic_local *cp = dev->cnic_priv;
  2758. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2759. struct cnic_ulp_ops *ulp_ops;
  2760. mutex_lock(&cnic_lock);
  2761. ulp_ops = cnic_ulp_tbl_prot(i);
  2762. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2763. mutex_unlock(&cnic_lock);
  2764. continue;
  2765. }
  2766. ulp_get(ulp_ops);
  2767. mutex_unlock(&cnic_lock);
  2768. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2769. ulp_ops->cnic_exit(dev);
  2770. ulp_put(ulp_ops);
  2771. }
  2772. }
  2773. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2774. {
  2775. struct cnic_dev *dev = csk->dev;
  2776. struct l4_kwq_offload_pg *l4kwqe;
  2777. struct kwqe *wqes[1];
  2778. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2779. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2780. wqes[0] = (struct kwqe *) l4kwqe;
  2781. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2782. l4kwqe->flags =
  2783. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2784. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2785. l4kwqe->da0 = csk->ha[0];
  2786. l4kwqe->da1 = csk->ha[1];
  2787. l4kwqe->da2 = csk->ha[2];
  2788. l4kwqe->da3 = csk->ha[3];
  2789. l4kwqe->da4 = csk->ha[4];
  2790. l4kwqe->da5 = csk->ha[5];
  2791. l4kwqe->sa0 = dev->mac_addr[0];
  2792. l4kwqe->sa1 = dev->mac_addr[1];
  2793. l4kwqe->sa2 = dev->mac_addr[2];
  2794. l4kwqe->sa3 = dev->mac_addr[3];
  2795. l4kwqe->sa4 = dev->mac_addr[4];
  2796. l4kwqe->sa5 = dev->mac_addr[5];
  2797. l4kwqe->etype = ETH_P_IP;
  2798. l4kwqe->ipid_start = DEF_IPID_START;
  2799. l4kwqe->host_opaque = csk->l5_cid;
  2800. if (csk->vlan_id) {
  2801. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2802. l4kwqe->vlan_tag = csk->vlan_id;
  2803. l4kwqe->l2hdr_nbytes += 4;
  2804. }
  2805. return dev->submit_kwqes(dev, wqes, 1);
  2806. }
  2807. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2808. {
  2809. struct cnic_dev *dev = csk->dev;
  2810. struct l4_kwq_update_pg *l4kwqe;
  2811. struct kwqe *wqes[1];
  2812. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2813. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2814. wqes[0] = (struct kwqe *) l4kwqe;
  2815. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2816. l4kwqe->flags =
  2817. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2818. l4kwqe->pg_cid = csk->pg_cid;
  2819. l4kwqe->da0 = csk->ha[0];
  2820. l4kwqe->da1 = csk->ha[1];
  2821. l4kwqe->da2 = csk->ha[2];
  2822. l4kwqe->da3 = csk->ha[3];
  2823. l4kwqe->da4 = csk->ha[4];
  2824. l4kwqe->da5 = csk->ha[5];
  2825. l4kwqe->pg_host_opaque = csk->l5_cid;
  2826. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2827. return dev->submit_kwqes(dev, wqes, 1);
  2828. }
  2829. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2830. {
  2831. struct cnic_dev *dev = csk->dev;
  2832. struct l4_kwq_upload *l4kwqe;
  2833. struct kwqe *wqes[1];
  2834. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2835. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2836. wqes[0] = (struct kwqe *) l4kwqe;
  2837. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2838. l4kwqe->flags =
  2839. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2840. l4kwqe->cid = csk->pg_cid;
  2841. return dev->submit_kwqes(dev, wqes, 1);
  2842. }
  2843. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2844. {
  2845. struct cnic_dev *dev = csk->dev;
  2846. struct l4_kwq_connect_req1 *l4kwqe1;
  2847. struct l4_kwq_connect_req2 *l4kwqe2;
  2848. struct l4_kwq_connect_req3 *l4kwqe3;
  2849. struct kwqe *wqes[3];
  2850. u8 tcp_flags = 0;
  2851. int num_wqes = 2;
  2852. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2853. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2854. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2855. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2856. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2857. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2858. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2859. l4kwqe3->flags =
  2860. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2861. l4kwqe3->ka_timeout = csk->ka_timeout;
  2862. l4kwqe3->ka_interval = csk->ka_interval;
  2863. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2864. l4kwqe3->tos = csk->tos;
  2865. l4kwqe3->ttl = csk->ttl;
  2866. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2867. l4kwqe3->pmtu = csk->mtu;
  2868. l4kwqe3->rcv_buf = csk->rcv_buf;
  2869. l4kwqe3->snd_buf = csk->snd_buf;
  2870. l4kwqe3->seed = csk->seed;
  2871. wqes[0] = (struct kwqe *) l4kwqe1;
  2872. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2873. wqes[1] = (struct kwqe *) l4kwqe2;
  2874. wqes[2] = (struct kwqe *) l4kwqe3;
  2875. num_wqes = 3;
  2876. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2877. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2878. l4kwqe2->flags =
  2879. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2880. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2881. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2882. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2883. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2884. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2885. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2886. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2887. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2888. sizeof(struct tcphdr);
  2889. } else {
  2890. wqes[1] = (struct kwqe *) l4kwqe3;
  2891. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2892. sizeof(struct tcphdr);
  2893. }
  2894. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2895. l4kwqe1->flags =
  2896. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2897. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2898. l4kwqe1->cid = csk->cid;
  2899. l4kwqe1->pg_cid = csk->pg_cid;
  2900. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2901. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2902. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2903. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2904. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2905. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2906. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2907. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2908. if (csk->tcp_flags & SK_TCP_NAGLE)
  2909. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2910. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2911. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2912. if (csk->tcp_flags & SK_TCP_SACK)
  2913. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2914. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2915. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2916. l4kwqe1->tcp_flags = tcp_flags;
  2917. return dev->submit_kwqes(dev, wqes, num_wqes);
  2918. }
  2919. static int cnic_cm_close_req(struct cnic_sock *csk)
  2920. {
  2921. struct cnic_dev *dev = csk->dev;
  2922. struct l4_kwq_close_req *l4kwqe;
  2923. struct kwqe *wqes[1];
  2924. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2925. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2926. wqes[0] = (struct kwqe *) l4kwqe;
  2927. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2928. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2929. l4kwqe->cid = csk->cid;
  2930. return dev->submit_kwqes(dev, wqes, 1);
  2931. }
  2932. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2933. {
  2934. struct cnic_dev *dev = csk->dev;
  2935. struct l4_kwq_reset_req *l4kwqe;
  2936. struct kwqe *wqes[1];
  2937. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2938. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2939. wqes[0] = (struct kwqe *) l4kwqe;
  2940. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2941. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2942. l4kwqe->cid = csk->cid;
  2943. return dev->submit_kwqes(dev, wqes, 1);
  2944. }
  2945. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2946. u32 l5_cid, struct cnic_sock **csk, void *context)
  2947. {
  2948. struct cnic_local *cp = dev->cnic_priv;
  2949. struct cnic_sock *csk1;
  2950. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2951. return -EINVAL;
  2952. if (cp->ctx_tbl) {
  2953. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2954. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2955. return -EAGAIN;
  2956. }
  2957. csk1 = &cp->csk_tbl[l5_cid];
  2958. if (atomic_read(&csk1->ref_count))
  2959. return -EAGAIN;
  2960. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2961. return -EBUSY;
  2962. csk1->dev = dev;
  2963. csk1->cid = cid;
  2964. csk1->l5_cid = l5_cid;
  2965. csk1->ulp_type = ulp_type;
  2966. csk1->context = context;
  2967. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2968. csk1->ka_interval = DEF_KA_INTERVAL;
  2969. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2970. csk1->tos = DEF_TOS;
  2971. csk1->ttl = DEF_TTL;
  2972. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2973. csk1->rcv_buf = DEF_RCV_BUF;
  2974. csk1->snd_buf = DEF_SND_BUF;
  2975. csk1->seed = DEF_SEED;
  2976. *csk = csk1;
  2977. return 0;
  2978. }
  2979. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2980. {
  2981. if (csk->src_port) {
  2982. struct cnic_dev *dev = csk->dev;
  2983. struct cnic_local *cp = dev->cnic_priv;
  2984. cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
  2985. csk->src_port = 0;
  2986. }
  2987. }
  2988. static void cnic_close_conn(struct cnic_sock *csk)
  2989. {
  2990. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2991. cnic_cm_upload_pg(csk);
  2992. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2993. }
  2994. cnic_cm_cleanup(csk);
  2995. }
  2996. static int cnic_cm_destroy(struct cnic_sock *csk)
  2997. {
  2998. if (!cnic_in_use(csk))
  2999. return -EINVAL;
  3000. csk_hold(csk);
  3001. clear_bit(SK_F_INUSE, &csk->flags);
  3002. smp_mb__after_clear_bit();
  3003. while (atomic_read(&csk->ref_count) != 1)
  3004. msleep(1);
  3005. cnic_cm_cleanup(csk);
  3006. csk->flags = 0;
  3007. csk_put(csk);
  3008. return 0;
  3009. }
  3010. static inline u16 cnic_get_vlan(struct net_device *dev,
  3011. struct net_device **vlan_dev)
  3012. {
  3013. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  3014. *vlan_dev = vlan_dev_real_dev(dev);
  3015. return vlan_dev_vlan_id(dev);
  3016. }
  3017. *vlan_dev = dev;
  3018. return 0;
  3019. }
  3020. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  3021. struct dst_entry **dst)
  3022. {
  3023. #if defined(CONFIG_INET)
  3024. struct rtable *rt;
  3025. rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0);
  3026. if (!IS_ERR(rt)) {
  3027. *dst = &rt->dst;
  3028. return 0;
  3029. }
  3030. return PTR_ERR(rt);
  3031. #else
  3032. return -ENETUNREACH;
  3033. #endif
  3034. }
  3035. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  3036. struct dst_entry **dst)
  3037. {
  3038. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  3039. struct flowi6 fl6;
  3040. memset(&fl6, 0, sizeof(fl6));
  3041. fl6.daddr = dst_addr->sin6_addr;
  3042. if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
  3043. fl6.flowi6_oif = dst_addr->sin6_scope_id;
  3044. *dst = ip6_route_output(&init_net, NULL, &fl6);
  3045. if ((*dst)->error) {
  3046. dst_release(*dst);
  3047. *dst = NULL;
  3048. return -ENETUNREACH;
  3049. } else
  3050. return 0;
  3051. #endif
  3052. return -ENETUNREACH;
  3053. }
  3054. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  3055. int ulp_type)
  3056. {
  3057. struct cnic_dev *dev = NULL;
  3058. struct dst_entry *dst;
  3059. struct net_device *netdev = NULL;
  3060. int err = -ENETUNREACH;
  3061. if (dst_addr->sin_family == AF_INET)
  3062. err = cnic_get_v4_route(dst_addr, &dst);
  3063. else if (dst_addr->sin_family == AF_INET6) {
  3064. struct sockaddr_in6 *dst_addr6 =
  3065. (struct sockaddr_in6 *) dst_addr;
  3066. err = cnic_get_v6_route(dst_addr6, &dst);
  3067. } else
  3068. return NULL;
  3069. if (err)
  3070. return NULL;
  3071. if (!dst->dev)
  3072. goto done;
  3073. cnic_get_vlan(dst->dev, &netdev);
  3074. dev = cnic_from_netdev(netdev);
  3075. done:
  3076. dst_release(dst);
  3077. if (dev)
  3078. cnic_put(dev);
  3079. return dev;
  3080. }
  3081. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3082. {
  3083. struct cnic_dev *dev = csk->dev;
  3084. struct cnic_local *cp = dev->cnic_priv;
  3085. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  3086. }
  3087. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3088. {
  3089. struct cnic_dev *dev = csk->dev;
  3090. struct cnic_local *cp = dev->cnic_priv;
  3091. int is_v6, rc = 0;
  3092. struct dst_entry *dst = NULL;
  3093. struct net_device *realdev;
  3094. __be16 local_port;
  3095. u32 port_id;
  3096. if (saddr->local.v6.sin6_family == AF_INET6 &&
  3097. saddr->remote.v6.sin6_family == AF_INET6)
  3098. is_v6 = 1;
  3099. else if (saddr->local.v4.sin_family == AF_INET &&
  3100. saddr->remote.v4.sin_family == AF_INET)
  3101. is_v6 = 0;
  3102. else
  3103. return -EINVAL;
  3104. clear_bit(SK_F_IPV6, &csk->flags);
  3105. if (is_v6) {
  3106. set_bit(SK_F_IPV6, &csk->flags);
  3107. cnic_get_v6_route(&saddr->remote.v6, &dst);
  3108. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  3109. sizeof(struct in6_addr));
  3110. csk->dst_port = saddr->remote.v6.sin6_port;
  3111. local_port = saddr->local.v6.sin6_port;
  3112. } else {
  3113. cnic_get_v4_route(&saddr->remote.v4, &dst);
  3114. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  3115. csk->dst_port = saddr->remote.v4.sin_port;
  3116. local_port = saddr->local.v4.sin_port;
  3117. }
  3118. csk->vlan_id = 0;
  3119. csk->mtu = dev->netdev->mtu;
  3120. if (dst && dst->dev) {
  3121. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  3122. if (realdev == dev->netdev) {
  3123. csk->vlan_id = vlan;
  3124. csk->mtu = dst_mtu(dst);
  3125. }
  3126. }
  3127. port_id = be16_to_cpu(local_port);
  3128. if (port_id >= CNIC_LOCAL_PORT_MIN &&
  3129. port_id < CNIC_LOCAL_PORT_MAX) {
  3130. if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
  3131. port_id = 0;
  3132. } else
  3133. port_id = 0;
  3134. if (!port_id) {
  3135. port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
  3136. if (port_id == -1) {
  3137. rc = -ENOMEM;
  3138. goto err_out;
  3139. }
  3140. local_port = cpu_to_be16(port_id);
  3141. }
  3142. csk->src_port = local_port;
  3143. err_out:
  3144. dst_release(dst);
  3145. return rc;
  3146. }
  3147. static void cnic_init_csk_state(struct cnic_sock *csk)
  3148. {
  3149. csk->state = 0;
  3150. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3151. clear_bit(SK_F_CLOSING, &csk->flags);
  3152. }
  3153. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3154. {
  3155. struct cnic_local *cp = csk->dev->cnic_priv;
  3156. int err = 0;
  3157. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  3158. return -EOPNOTSUPP;
  3159. if (!cnic_in_use(csk))
  3160. return -EINVAL;
  3161. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  3162. return -EINVAL;
  3163. cnic_init_csk_state(csk);
  3164. err = cnic_get_route(csk, saddr);
  3165. if (err)
  3166. goto err_out;
  3167. err = cnic_resolve_addr(csk, saddr);
  3168. if (!err)
  3169. return 0;
  3170. err_out:
  3171. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3172. return err;
  3173. }
  3174. static int cnic_cm_abort(struct cnic_sock *csk)
  3175. {
  3176. struct cnic_local *cp = csk->dev->cnic_priv;
  3177. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  3178. if (!cnic_in_use(csk))
  3179. return -EINVAL;
  3180. if (cnic_abort_prep(csk))
  3181. return cnic_cm_abort_req(csk);
  3182. /* Getting here means that we haven't started connect, or
  3183. * connect was not successful.
  3184. */
  3185. cp->close_conn(csk, opcode);
  3186. if (csk->state != opcode)
  3187. return -EALREADY;
  3188. return 0;
  3189. }
  3190. static int cnic_cm_close(struct cnic_sock *csk)
  3191. {
  3192. if (!cnic_in_use(csk))
  3193. return -EINVAL;
  3194. if (cnic_close_prep(csk)) {
  3195. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3196. return cnic_cm_close_req(csk);
  3197. } else {
  3198. return -EALREADY;
  3199. }
  3200. return 0;
  3201. }
  3202. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  3203. u8 opcode)
  3204. {
  3205. struct cnic_ulp_ops *ulp_ops;
  3206. int ulp_type = csk->ulp_type;
  3207. rcu_read_lock();
  3208. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  3209. if (ulp_ops) {
  3210. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  3211. ulp_ops->cm_connect_complete(csk);
  3212. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3213. ulp_ops->cm_close_complete(csk);
  3214. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  3215. ulp_ops->cm_remote_abort(csk);
  3216. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  3217. ulp_ops->cm_abort_complete(csk);
  3218. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  3219. ulp_ops->cm_remote_close(csk);
  3220. }
  3221. rcu_read_unlock();
  3222. }
  3223. static int cnic_cm_set_pg(struct cnic_sock *csk)
  3224. {
  3225. if (cnic_offld_prep(csk)) {
  3226. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3227. cnic_cm_update_pg(csk);
  3228. else
  3229. cnic_cm_offload_pg(csk);
  3230. }
  3231. return 0;
  3232. }
  3233. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  3234. {
  3235. struct cnic_local *cp = dev->cnic_priv;
  3236. u32 l5_cid = kcqe->pg_host_opaque;
  3237. u8 opcode = kcqe->op_code;
  3238. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  3239. csk_hold(csk);
  3240. if (!cnic_in_use(csk))
  3241. goto done;
  3242. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3243. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3244. goto done;
  3245. }
  3246. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  3247. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  3248. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3249. cnic_cm_upcall(cp, csk,
  3250. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3251. goto done;
  3252. }
  3253. csk->pg_cid = kcqe->pg_cid;
  3254. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3255. cnic_cm_conn_req(csk);
  3256. done:
  3257. csk_put(csk);
  3258. }
  3259. static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
  3260. {
  3261. struct cnic_local *cp = dev->cnic_priv;
  3262. struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
  3263. u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
  3264. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  3265. ctx->timestamp = jiffies;
  3266. ctx->wait_cond = 1;
  3267. wake_up(&ctx->waitq);
  3268. }
  3269. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  3270. {
  3271. struct cnic_local *cp = dev->cnic_priv;
  3272. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  3273. u8 opcode = l4kcqe->op_code;
  3274. u32 l5_cid;
  3275. struct cnic_sock *csk;
  3276. if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
  3277. cnic_process_fcoe_term_conn(dev, kcqe);
  3278. return;
  3279. }
  3280. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  3281. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3282. cnic_cm_process_offld_pg(dev, l4kcqe);
  3283. return;
  3284. }
  3285. l5_cid = l4kcqe->conn_id;
  3286. if (opcode & 0x80)
  3287. l5_cid = l4kcqe->cid;
  3288. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  3289. return;
  3290. csk = &cp->csk_tbl[l5_cid];
  3291. csk_hold(csk);
  3292. if (!cnic_in_use(csk)) {
  3293. csk_put(csk);
  3294. return;
  3295. }
  3296. switch (opcode) {
  3297. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  3298. if (l4kcqe->status != 0) {
  3299. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3300. cnic_cm_upcall(cp, csk,
  3301. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3302. }
  3303. break;
  3304. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  3305. if (l4kcqe->status == 0)
  3306. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  3307. else if (l4kcqe->status ==
  3308. L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
  3309. set_bit(SK_F_HW_ERR, &csk->flags);
  3310. smp_mb__before_clear_bit();
  3311. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3312. cnic_cm_upcall(cp, csk, opcode);
  3313. break;
  3314. case L5CM_RAMROD_CMD_ID_CLOSE:
  3315. if (l4kcqe->status != 0) {
  3316. netdev_warn(dev->netdev, "RAMROD CLOSE compl with "
  3317. "status 0x%x\n", l4kcqe->status);
  3318. opcode = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3319. /* Fall through */
  3320. } else {
  3321. break;
  3322. }
  3323. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3324. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3325. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3326. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3327. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3328. if (l4kcqe->status == L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
  3329. set_bit(SK_F_HW_ERR, &csk->flags);
  3330. cp->close_conn(csk, opcode);
  3331. break;
  3332. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  3333. /* after we already sent CLOSE_REQ */
  3334. if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags) &&
  3335. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags) &&
  3336. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3337. cp->close_conn(csk, L4_KCQE_OPCODE_VALUE_RESET_COMP);
  3338. else
  3339. cnic_cm_upcall(cp, csk, opcode);
  3340. break;
  3341. }
  3342. csk_put(csk);
  3343. }
  3344. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  3345. {
  3346. struct cnic_dev *dev = data;
  3347. int i;
  3348. for (i = 0; i < num; i++)
  3349. cnic_cm_process_kcqe(dev, kcqe[i]);
  3350. }
  3351. static struct cnic_ulp_ops cm_ulp_ops = {
  3352. .indicate_kcqes = cnic_cm_indicate_kcqe,
  3353. };
  3354. static void cnic_cm_free_mem(struct cnic_dev *dev)
  3355. {
  3356. struct cnic_local *cp = dev->cnic_priv;
  3357. kfree(cp->csk_tbl);
  3358. cp->csk_tbl = NULL;
  3359. cnic_free_id_tbl(&cp->csk_port_tbl);
  3360. }
  3361. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  3362. {
  3363. struct cnic_local *cp = dev->cnic_priv;
  3364. u32 port_id;
  3365. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  3366. GFP_KERNEL);
  3367. if (!cp->csk_tbl)
  3368. return -ENOMEM;
  3369. port_id = random32();
  3370. port_id %= CNIC_LOCAL_PORT_RANGE;
  3371. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  3372. CNIC_LOCAL_PORT_MIN, port_id)) {
  3373. cnic_cm_free_mem(dev);
  3374. return -ENOMEM;
  3375. }
  3376. return 0;
  3377. }
  3378. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  3379. {
  3380. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  3381. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  3382. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  3383. csk->state = opcode;
  3384. }
  3385. /* 1. If event opcode matches the expected event in csk->state
  3386. * 2. If the expected event is CLOSE_COMP or RESET_COMP, we accept any
  3387. * event
  3388. * 3. If the expected event is 0, meaning the connection was never
  3389. * never established, we accept the opcode from cm_abort.
  3390. */
  3391. if (opcode == csk->state || csk->state == 0 ||
  3392. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP ||
  3393. csk->state == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
  3394. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  3395. if (csk->state == 0)
  3396. csk->state = opcode;
  3397. return 1;
  3398. }
  3399. }
  3400. return 0;
  3401. }
  3402. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  3403. {
  3404. struct cnic_dev *dev = csk->dev;
  3405. struct cnic_local *cp = dev->cnic_priv;
  3406. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  3407. cnic_cm_upcall(cp, csk, opcode);
  3408. return;
  3409. }
  3410. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3411. cnic_close_conn(csk);
  3412. csk->state = opcode;
  3413. cnic_cm_upcall(cp, csk, opcode);
  3414. }
  3415. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  3416. {
  3417. }
  3418. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  3419. {
  3420. u32 seed;
  3421. seed = random32();
  3422. cnic_ctx_wr(dev, 45, 0, seed);
  3423. return 0;
  3424. }
  3425. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  3426. {
  3427. struct cnic_dev *dev = csk->dev;
  3428. struct cnic_local *cp = dev->cnic_priv;
  3429. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  3430. union l5cm_specific_data l5_data;
  3431. u32 cmd = 0;
  3432. int close_complete = 0;
  3433. switch (opcode) {
  3434. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3435. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3436. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3437. if (cnic_ready_to_close(csk, opcode)) {
  3438. if (test_bit(SK_F_HW_ERR, &csk->flags))
  3439. close_complete = 1;
  3440. else if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3441. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  3442. else
  3443. close_complete = 1;
  3444. }
  3445. break;
  3446. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3447. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  3448. break;
  3449. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3450. close_complete = 1;
  3451. break;
  3452. }
  3453. if (cmd) {
  3454. memset(&l5_data, 0, sizeof(l5_data));
  3455. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  3456. &l5_data);
  3457. } else if (close_complete) {
  3458. ctx->timestamp = jiffies;
  3459. cnic_close_conn(csk);
  3460. cnic_cm_upcall(cp, csk, csk->state);
  3461. }
  3462. }
  3463. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  3464. {
  3465. struct cnic_local *cp = dev->cnic_priv;
  3466. if (!cp->ctx_tbl)
  3467. return;
  3468. if (!netif_running(dev->netdev))
  3469. return;
  3470. cnic_bnx2x_delete_wait(dev, 0);
  3471. cancel_delayed_work(&cp->delete_task);
  3472. flush_workqueue(cnic_wq);
  3473. if (atomic_read(&cp->iscsi_conn) != 0)
  3474. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  3475. atomic_read(&cp->iscsi_conn));
  3476. }
  3477. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  3478. {
  3479. struct cnic_local *cp = dev->cnic_priv;
  3480. u32 pfid = cp->pfid;
  3481. u32 port = CNIC_PORT(cp);
  3482. cnic_init_bnx2x_mac(dev);
  3483. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  3484. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  3485. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  3486. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3487. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  3488. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3489. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  3490. DEF_MAX_DA_COUNT);
  3491. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3492. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  3493. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3494. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  3495. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3496. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  3497. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3498. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  3499. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  3500. DEF_MAX_CWND);
  3501. return 0;
  3502. }
  3503. static void cnic_delete_task(struct work_struct *work)
  3504. {
  3505. struct cnic_local *cp;
  3506. struct cnic_dev *dev;
  3507. u32 i;
  3508. int need_resched = 0;
  3509. cp = container_of(work, struct cnic_local, delete_task.work);
  3510. dev = cp->dev;
  3511. if (test_and_clear_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags)) {
  3512. struct drv_ctl_info info;
  3513. cnic_ulp_stop_one(cp, CNIC_ULP_ISCSI);
  3514. info.cmd = DRV_CTL_ISCSI_STOPPED_CMD;
  3515. cp->ethdev->drv_ctl(dev->netdev, &info);
  3516. }
  3517. for (i = 0; i < cp->max_cid_space; i++) {
  3518. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3519. int err;
  3520. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  3521. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3522. continue;
  3523. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  3524. need_resched = 1;
  3525. continue;
  3526. }
  3527. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3528. continue;
  3529. err = cnic_bnx2x_destroy_ramrod(dev, i);
  3530. cnic_free_bnx2x_conn_resc(dev, i);
  3531. if (!err) {
  3532. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  3533. atomic_dec(&cp->iscsi_conn);
  3534. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  3535. }
  3536. }
  3537. if (need_resched)
  3538. queue_delayed_work(cnic_wq, &cp->delete_task,
  3539. msecs_to_jiffies(10));
  3540. }
  3541. static int cnic_cm_open(struct cnic_dev *dev)
  3542. {
  3543. struct cnic_local *cp = dev->cnic_priv;
  3544. int err;
  3545. err = cnic_cm_alloc_mem(dev);
  3546. if (err)
  3547. return err;
  3548. err = cp->start_cm(dev);
  3549. if (err)
  3550. goto err_out;
  3551. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  3552. dev->cm_create = cnic_cm_create;
  3553. dev->cm_destroy = cnic_cm_destroy;
  3554. dev->cm_connect = cnic_cm_connect;
  3555. dev->cm_abort = cnic_cm_abort;
  3556. dev->cm_close = cnic_cm_close;
  3557. dev->cm_select_dev = cnic_cm_select_dev;
  3558. cp->ulp_handle[CNIC_ULP_L4] = dev;
  3559. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  3560. return 0;
  3561. err_out:
  3562. cnic_cm_free_mem(dev);
  3563. return err;
  3564. }
  3565. static int cnic_cm_shutdown(struct cnic_dev *dev)
  3566. {
  3567. struct cnic_local *cp = dev->cnic_priv;
  3568. int i;
  3569. if (!cp->csk_tbl)
  3570. return 0;
  3571. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  3572. struct cnic_sock *csk = &cp->csk_tbl[i];
  3573. clear_bit(SK_F_INUSE, &csk->flags);
  3574. cnic_cm_cleanup(csk);
  3575. }
  3576. cnic_cm_free_mem(dev);
  3577. return 0;
  3578. }
  3579. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  3580. {
  3581. u32 cid_addr;
  3582. int i;
  3583. cid_addr = GET_CID_ADDR(cid);
  3584. for (i = 0; i < CTX_SIZE; i += 4)
  3585. cnic_ctx_wr(dev, cid_addr, i, 0);
  3586. }
  3587. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  3588. {
  3589. struct cnic_local *cp = dev->cnic_priv;
  3590. int ret = 0, i;
  3591. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  3592. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3593. return 0;
  3594. for (i = 0; i < cp->ctx_blks; i++) {
  3595. int j;
  3596. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  3597. u32 val;
  3598. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  3599. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  3600. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  3601. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  3602. (u64) cp->ctx_arr[i].mapping >> 32);
  3603. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  3604. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  3605. for (j = 0; j < 10; j++) {
  3606. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  3607. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  3608. break;
  3609. udelay(5);
  3610. }
  3611. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  3612. ret = -EBUSY;
  3613. break;
  3614. }
  3615. }
  3616. return ret;
  3617. }
  3618. static void cnic_free_irq(struct cnic_dev *dev)
  3619. {
  3620. struct cnic_local *cp = dev->cnic_priv;
  3621. struct cnic_eth_dev *ethdev = cp->ethdev;
  3622. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3623. cp->disable_int_sync(dev);
  3624. tasklet_kill(&cp->cnic_irq_task);
  3625. free_irq(ethdev->irq_arr[0].vector, dev);
  3626. }
  3627. }
  3628. static int cnic_request_irq(struct cnic_dev *dev)
  3629. {
  3630. struct cnic_local *cp = dev->cnic_priv;
  3631. struct cnic_eth_dev *ethdev = cp->ethdev;
  3632. int err;
  3633. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  3634. if (err)
  3635. tasklet_disable(&cp->cnic_irq_task);
  3636. return err;
  3637. }
  3638. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  3639. {
  3640. struct cnic_local *cp = dev->cnic_priv;
  3641. struct cnic_eth_dev *ethdev = cp->ethdev;
  3642. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3643. int err, i = 0;
  3644. int sblk_num = cp->status_blk_num;
  3645. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3646. BNX2_HC_SB_CONFIG_1;
  3647. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3648. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3649. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3650. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3651. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3652. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  3653. (unsigned long) dev);
  3654. err = cnic_request_irq(dev);
  3655. if (err)
  3656. return err;
  3657. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3658. i < 10) {
  3659. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3660. 1 << (11 + sblk_num));
  3661. udelay(10);
  3662. i++;
  3663. barrier();
  3664. }
  3665. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3666. cnic_free_irq(dev);
  3667. goto failed;
  3668. }
  3669. } else {
  3670. struct status_block *sblk = cp->status_blk.gen;
  3671. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3672. int i = 0;
  3673. while (sblk->status_completion_producer_index && i < 10) {
  3674. CNIC_WR(dev, BNX2_HC_COMMAND,
  3675. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3676. udelay(10);
  3677. i++;
  3678. barrier();
  3679. }
  3680. if (sblk->status_completion_producer_index)
  3681. goto failed;
  3682. }
  3683. return 0;
  3684. failed:
  3685. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3686. return -EBUSY;
  3687. }
  3688. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3689. {
  3690. struct cnic_local *cp = dev->cnic_priv;
  3691. struct cnic_eth_dev *ethdev = cp->ethdev;
  3692. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3693. return;
  3694. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3695. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3696. }
  3697. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3698. {
  3699. struct cnic_local *cp = dev->cnic_priv;
  3700. struct cnic_eth_dev *ethdev = cp->ethdev;
  3701. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3702. return;
  3703. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3704. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3705. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3706. synchronize_irq(ethdev->irq_arr[0].vector);
  3707. }
  3708. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3709. {
  3710. struct cnic_local *cp = dev->cnic_priv;
  3711. struct cnic_eth_dev *ethdev = cp->ethdev;
  3712. struct cnic_uio_dev *udev = cp->udev;
  3713. u32 cid_addr, tx_cid, sb_id;
  3714. u32 val, offset0, offset1, offset2, offset3;
  3715. int i;
  3716. struct tx_bd *txbd;
  3717. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3718. struct status_block *s_blk = cp->status_blk.gen;
  3719. sb_id = cp->status_blk_num;
  3720. tx_cid = 20;
  3721. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3722. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3723. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3724. tx_cid = TX_TSS_CID + sb_id - 1;
  3725. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3726. (TX_TSS_CID << 7));
  3727. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3728. }
  3729. cp->tx_cons = *cp->tx_cons_ptr;
  3730. cid_addr = GET_CID_ADDR(tx_cid);
  3731. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  3732. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3733. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3734. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3735. offset0 = BNX2_L2CTX_TYPE_XI;
  3736. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3737. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3738. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3739. } else {
  3740. cnic_init_context(dev, tx_cid);
  3741. cnic_init_context(dev, tx_cid + 1);
  3742. offset0 = BNX2_L2CTX_TYPE;
  3743. offset1 = BNX2_L2CTX_CMD_TYPE;
  3744. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3745. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3746. }
  3747. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3748. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3749. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3750. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3751. txbd = udev->l2_ring;
  3752. buf_map = udev->l2_buf_map;
  3753. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  3754. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3755. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3756. }
  3757. val = (u64) ring_map >> 32;
  3758. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3759. txbd->tx_bd_haddr_hi = val;
  3760. val = (u64) ring_map & 0xffffffff;
  3761. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3762. txbd->tx_bd_haddr_lo = val;
  3763. }
  3764. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3765. {
  3766. struct cnic_local *cp = dev->cnic_priv;
  3767. struct cnic_eth_dev *ethdev = cp->ethdev;
  3768. struct cnic_uio_dev *udev = cp->udev;
  3769. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3770. int i;
  3771. struct rx_bd *rxbd;
  3772. struct status_block *s_blk = cp->status_blk.gen;
  3773. dma_addr_t ring_map = udev->l2_ring_map;
  3774. sb_id = cp->status_blk_num;
  3775. cnic_init_context(dev, 2);
  3776. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3777. coal_reg = BNX2_HC_COMMAND;
  3778. coal_val = CNIC_RD(dev, coal_reg);
  3779. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3780. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3781. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3782. coal_reg = BNX2_HC_COALESCE_NOW;
  3783. coal_val = 1 << (11 + sb_id);
  3784. }
  3785. i = 0;
  3786. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3787. CNIC_WR(dev, coal_reg, coal_val);
  3788. udelay(10);
  3789. i++;
  3790. barrier();
  3791. }
  3792. cp->rx_cons = *cp->rx_cons_ptr;
  3793. cid_addr = GET_CID_ADDR(2);
  3794. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3795. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3796. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3797. if (sb_id == 0)
  3798. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3799. else
  3800. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3801. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3802. rxbd = udev->l2_ring + BCM_PAGE_SIZE;
  3803. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3804. dma_addr_t buf_map;
  3805. int n = (i % cp->l2_rx_ring_size) + 1;
  3806. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3807. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3808. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3809. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3810. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3811. }
  3812. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3813. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3814. rxbd->rx_bd_haddr_hi = val;
  3815. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3816. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3817. rxbd->rx_bd_haddr_lo = val;
  3818. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3819. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3820. }
  3821. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3822. {
  3823. struct kwqe *wqes[1], l2kwqe;
  3824. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3825. wqes[0] = &l2kwqe;
  3826. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
  3827. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3828. KWQE_OPCODE_SHIFT) | 2;
  3829. dev->submit_kwqes(dev, wqes, 1);
  3830. }
  3831. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3832. {
  3833. struct cnic_local *cp = dev->cnic_priv;
  3834. u32 val;
  3835. val = cp->func << 2;
  3836. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3837. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3838. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3839. dev->mac_addr[0] = (u8) (val >> 8);
  3840. dev->mac_addr[1] = (u8) val;
  3841. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3842. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3843. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3844. dev->mac_addr[2] = (u8) (val >> 24);
  3845. dev->mac_addr[3] = (u8) (val >> 16);
  3846. dev->mac_addr[4] = (u8) (val >> 8);
  3847. dev->mac_addr[5] = (u8) val;
  3848. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3849. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3850. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3851. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3852. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3853. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3854. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3855. }
  3856. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3857. {
  3858. struct cnic_local *cp = dev->cnic_priv;
  3859. struct cnic_eth_dev *ethdev = cp->ethdev;
  3860. struct status_block *sblk = cp->status_blk.gen;
  3861. u32 val, kcq_cid_addr, kwq_cid_addr;
  3862. int err;
  3863. cnic_set_bnx2_mac(dev);
  3864. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3865. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3866. if (BCM_PAGE_BITS > 12)
  3867. val |= (12 - 8) << 4;
  3868. else
  3869. val |= (BCM_PAGE_BITS - 8) << 4;
  3870. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3871. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3872. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3873. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3874. err = cnic_setup_5709_context(dev, 1);
  3875. if (err)
  3876. return err;
  3877. cnic_init_context(dev, KWQ_CID);
  3878. cnic_init_context(dev, KCQ_CID);
  3879. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3880. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3881. cp->max_kwq_idx = MAX_KWQ_IDX;
  3882. cp->kwq_prod_idx = 0;
  3883. cp->kwq_con_idx = 0;
  3884. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3885. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3886. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3887. else
  3888. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3889. /* Initialize the kernel work queue context. */
  3890. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3891. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3892. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3893. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3894. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3895. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3896. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3897. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3898. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3899. val = (u32) cp->kwq_info.pgtbl_map;
  3900. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3901. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3902. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3903. cp->kcq1.sw_prod_idx = 0;
  3904. cp->kcq1.hw_prod_idx_ptr =
  3905. &sblk->status_completion_producer_index;
  3906. cp->kcq1.status_idx_ptr = &sblk->status_idx;
  3907. /* Initialize the kernel complete queue context. */
  3908. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3909. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3910. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3911. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3912. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3913. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3914. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3915. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3916. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3917. val = (u32) cp->kcq1.dma.pgtbl_map;
  3918. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3919. cp->int_num = 0;
  3920. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3921. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3922. u32 sb_id = cp->status_blk_num;
  3923. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3924. cp->kcq1.hw_prod_idx_ptr =
  3925. &msblk->status_completion_producer_index;
  3926. cp->kcq1.status_idx_ptr = &msblk->status_idx;
  3927. cp->kwq_con_idx_ptr = &msblk->status_cmd_consumer_index;
  3928. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3929. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3930. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3931. }
  3932. /* Enable Commnad Scheduler notification when we write to the
  3933. * host producer index of the kernel contexts. */
  3934. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3935. /* Enable Command Scheduler notification when we write to either
  3936. * the Send Queue or Receive Queue producer indexes of the kernel
  3937. * bypass contexts. */
  3938. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3939. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3940. /* Notify COM when the driver post an application buffer. */
  3941. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3942. /* Set the CP and COM doorbells. These two processors polls the
  3943. * doorbell for a non zero value before running. This must be done
  3944. * after setting up the kernel queue contexts. */
  3945. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3946. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3947. cnic_init_bnx2_tx_ring(dev);
  3948. cnic_init_bnx2_rx_ring(dev);
  3949. err = cnic_init_bnx2_irq(dev);
  3950. if (err) {
  3951. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3952. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3953. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3954. return err;
  3955. }
  3956. return 0;
  3957. }
  3958. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3959. {
  3960. struct cnic_local *cp = dev->cnic_priv;
  3961. struct cnic_eth_dev *ethdev = cp->ethdev;
  3962. u32 start_offset = ethdev->ctx_tbl_offset;
  3963. int i;
  3964. for (i = 0; i < cp->ctx_blks; i++) {
  3965. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3966. dma_addr_t map = ctx->mapping;
  3967. if (cp->ctx_align) {
  3968. unsigned long mask = cp->ctx_align - 1;
  3969. map = (map + mask) & ~mask;
  3970. }
  3971. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3972. }
  3973. }
  3974. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3975. {
  3976. struct cnic_local *cp = dev->cnic_priv;
  3977. struct cnic_eth_dev *ethdev = cp->ethdev;
  3978. int err = 0;
  3979. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3980. (unsigned long) dev);
  3981. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  3982. err = cnic_request_irq(dev);
  3983. return err;
  3984. }
  3985. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  3986. u16 sb_id, u8 sb_index,
  3987. u8 disable)
  3988. {
  3989. u32 addr = BAR_CSTRORM_INTMEM +
  3990. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3991. offsetof(struct hc_status_block_data_e1x, index_data) +
  3992. sizeof(struct hc_index_data)*sb_index +
  3993. offsetof(struct hc_index_data, flags);
  3994. u16 flags = CNIC_RD16(dev, addr);
  3995. /* clear and set */
  3996. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  3997. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  3998. HC_INDEX_DATA_HC_ENABLED);
  3999. CNIC_WR16(dev, addr, flags);
  4000. }
  4001. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  4002. {
  4003. struct cnic_local *cp = dev->cnic_priv;
  4004. u8 sb_id = cp->status_blk_num;
  4005. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4006. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  4007. offsetof(struct hc_status_block_data_e1x, index_data) +
  4008. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  4009. offsetof(struct hc_index_data, timeout), 64 / 4);
  4010. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  4011. }
  4012. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  4013. {
  4014. }
  4015. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  4016. struct client_init_ramrod_data *data)
  4017. {
  4018. struct cnic_local *cp = dev->cnic_priv;
  4019. struct cnic_uio_dev *udev = cp->udev;
  4020. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  4021. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  4022. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  4023. int i;
  4024. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4025. u32 val;
  4026. memset(txbd, 0, BCM_PAGE_SIZE);
  4027. buf_map = udev->l2_buf_map;
  4028. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  4029. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  4030. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  4031. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  4032. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  4033. reg_bd->addr_hi = start_bd->addr_hi;
  4034. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  4035. start_bd->nbytes = cpu_to_le16(0x10);
  4036. start_bd->nbd = cpu_to_le16(3);
  4037. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  4038. start_bd->general_data = (UNICAST_ADDRESS <<
  4039. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  4040. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  4041. }
  4042. val = (u64) ring_map >> 32;
  4043. txbd->next_bd.addr_hi = cpu_to_le32(val);
  4044. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  4045. val = (u64) ring_map & 0xffffffff;
  4046. txbd->next_bd.addr_lo = cpu_to_le32(val);
  4047. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  4048. /* Other ramrod params */
  4049. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  4050. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  4051. /* reset xstorm per client statistics */
  4052. if (cli < MAX_STAT_COUNTER_ID) {
  4053. data->general.statistics_zero_flg = 1;
  4054. data->general.statistics_en_flg = 1;
  4055. data->general.statistics_counter_id = cli;
  4056. }
  4057. cp->tx_cons_ptr =
  4058. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  4059. }
  4060. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  4061. struct client_init_ramrod_data *data)
  4062. {
  4063. struct cnic_local *cp = dev->cnic_priv;
  4064. struct cnic_uio_dev *udev = cp->udev;
  4065. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  4066. BCM_PAGE_SIZE);
  4067. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  4068. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  4069. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  4070. int i;
  4071. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4072. int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4073. u32 val;
  4074. dma_addr_t ring_map = udev->l2_ring_map;
  4075. /* General data */
  4076. data->general.client_id = cli;
  4077. data->general.activate_flg = 1;
  4078. data->general.sp_client_id = cli;
  4079. data->general.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  4080. data->general.func_id = cp->pfid;
  4081. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  4082. dma_addr_t buf_map;
  4083. int n = (i % cp->l2_rx_ring_size) + 1;
  4084. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  4085. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  4086. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  4087. }
  4088. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  4089. rxbd->addr_hi = cpu_to_le32(val);
  4090. data->rx.bd_page_base.hi = cpu_to_le32(val);
  4091. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  4092. rxbd->addr_lo = cpu_to_le32(val);
  4093. data->rx.bd_page_base.lo = cpu_to_le32(val);
  4094. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  4095. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  4096. rxcqe->addr_hi = cpu_to_le32(val);
  4097. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  4098. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  4099. rxcqe->addr_lo = cpu_to_le32(val);
  4100. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  4101. /* Other ramrod params */
  4102. data->rx.client_qzone_id = cl_qzone_id;
  4103. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  4104. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  4105. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  4106. data->rx.max_bytes_on_bd = cpu_to_le16(cp->l2_single_buf_size);
  4107. data->rx.outer_vlan_removal_enable_flg = 1;
  4108. data->rx.silent_vlan_removal_flg = 1;
  4109. data->rx.silent_vlan_value = 0;
  4110. data->rx.silent_vlan_mask = 0xffff;
  4111. cp->rx_cons_ptr =
  4112. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  4113. cp->rx_cons = *cp->rx_cons_ptr;
  4114. }
  4115. static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
  4116. {
  4117. struct cnic_local *cp = dev->cnic_priv;
  4118. u32 pfid = cp->pfid;
  4119. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  4120. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  4121. cp->kcq1.sw_prod_idx = 0;
  4122. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4123. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4124. cp->kcq1.hw_prod_idx_ptr =
  4125. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4126. cp->kcq1.status_idx_ptr =
  4127. &sb->sb.running_index[SM_RX_ID];
  4128. } else {
  4129. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  4130. cp->kcq1.hw_prod_idx_ptr =
  4131. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4132. cp->kcq1.status_idx_ptr =
  4133. &sb->sb.running_index[SM_RX_ID];
  4134. }
  4135. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4136. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4137. cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
  4138. USTORM_FCOE_EQ_PROD_OFFSET(pfid);
  4139. cp->kcq2.sw_prod_idx = 0;
  4140. cp->kcq2.hw_prod_idx_ptr =
  4141. &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
  4142. cp->kcq2.status_idx_ptr =
  4143. &sb->sb.running_index[SM_RX_ID];
  4144. }
  4145. }
  4146. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  4147. {
  4148. struct cnic_local *cp = dev->cnic_priv;
  4149. struct cnic_eth_dev *ethdev = cp->ethdev;
  4150. int func = CNIC_FUNC(cp), ret;
  4151. u32 pfid;
  4152. dev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4153. cp->port_mode = CHIP_PORT_MODE_NONE;
  4154. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4155. u32 val;
  4156. pci_read_config_dword(dev->pcidev, PCICFG_ME_REGISTER, &val);
  4157. cp->func = (u8) ((val & ME_REG_ABS_PF_NUM) >>
  4158. ME_REG_ABS_PF_NUM_SHIFT);
  4159. func = CNIC_FUNC(cp);
  4160. val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
  4161. if (!(val & 1))
  4162. val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
  4163. else
  4164. val = (val >> 1) & 1;
  4165. if (val) {
  4166. cp->port_mode = CHIP_4_PORT_MODE;
  4167. cp->pfid = func >> 1;
  4168. } else {
  4169. cp->port_mode = CHIP_2_PORT_MODE;
  4170. cp->pfid = func & 0x6;
  4171. }
  4172. } else {
  4173. cp->pfid = func;
  4174. }
  4175. pfid = cp->pfid;
  4176. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  4177. cp->iscsi_start_cid, 0);
  4178. if (ret)
  4179. return -ENOMEM;
  4180. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4181. ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl, dev->max_fcoe_conn,
  4182. cp->fcoe_start_cid, 0);
  4183. if (ret)
  4184. return -ENOMEM;
  4185. }
  4186. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  4187. cnic_init_bnx2x_kcq(dev);
  4188. /* Only 1 EQ */
  4189. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  4190. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4191. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  4192. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4193. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  4194. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  4195. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4196. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  4197. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  4198. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4199. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  4200. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  4201. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4202. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  4203. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  4204. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4205. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  4206. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  4207. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  4208. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4209. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  4210. HC_INDEX_ISCSI_EQ_CONS);
  4211. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4212. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  4213. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  4214. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4215. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  4216. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  4217. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4218. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  4219. cnic_setup_bnx2x_context(dev);
  4220. ret = cnic_init_bnx2x_irq(dev);
  4221. if (ret)
  4222. return ret;
  4223. return 0;
  4224. }
  4225. static void cnic_init_rings(struct cnic_dev *dev)
  4226. {
  4227. struct cnic_local *cp = dev->cnic_priv;
  4228. struct cnic_uio_dev *udev = cp->udev;
  4229. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4230. return;
  4231. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4232. cnic_init_bnx2_tx_ring(dev);
  4233. cnic_init_bnx2_rx_ring(dev);
  4234. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4235. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4236. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4237. u32 cid = cp->ethdev->iscsi_l2_cid;
  4238. u32 cl_qzone_id;
  4239. struct client_init_ramrod_data *data;
  4240. union l5cm_specific_data l5_data;
  4241. struct ustorm_eth_rx_producers rx_prods = {0};
  4242. u32 off, i, *cid_ptr;
  4243. rx_prods.bd_prod = 0;
  4244. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  4245. barrier();
  4246. cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4247. off = BAR_USTRORM_INTMEM +
  4248. (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) ?
  4249. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  4250. USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
  4251. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  4252. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  4253. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4254. data = udev->l2_buf;
  4255. cid_ptr = udev->l2_buf + 12;
  4256. memset(data, 0, sizeof(*data));
  4257. cnic_init_bnx2x_tx_ring(dev, data);
  4258. cnic_init_bnx2x_rx_ring(dev, data);
  4259. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  4260. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  4261. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4262. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  4263. cid, ETH_CONNECTION_TYPE, &l5_data);
  4264. i = 0;
  4265. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4266. ++i < 10)
  4267. msleep(1);
  4268. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4269. netdev_err(dev->netdev,
  4270. "iSCSI CLIENT_SETUP did not complete\n");
  4271. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4272. cnic_ring_ctl(dev, cid, cli, 1);
  4273. *cid_ptr = cid;
  4274. }
  4275. }
  4276. static void cnic_shutdown_rings(struct cnic_dev *dev)
  4277. {
  4278. struct cnic_local *cp = dev->cnic_priv;
  4279. struct cnic_uio_dev *udev = cp->udev;
  4280. void *rx_ring;
  4281. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4282. return;
  4283. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4284. cnic_shutdown_bnx2_rx_ring(dev);
  4285. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4286. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4287. u32 cid = cp->ethdev->iscsi_l2_cid;
  4288. union l5cm_specific_data l5_data;
  4289. int i;
  4290. cnic_ring_ctl(dev, cid, cli, 0);
  4291. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4292. l5_data.phy_address.lo = cli;
  4293. l5_data.phy_address.hi = 0;
  4294. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  4295. cid, ETH_CONNECTION_TYPE, &l5_data);
  4296. i = 0;
  4297. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4298. ++i < 10)
  4299. msleep(1);
  4300. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4301. netdev_err(dev->netdev,
  4302. "iSCSI CLIENT_HALT did not complete\n");
  4303. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4304. memset(&l5_data, 0, sizeof(l5_data));
  4305. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  4306. cid, NONE_CONNECTION_TYPE, &l5_data);
  4307. msleep(10);
  4308. }
  4309. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4310. rx_ring = udev->l2_ring + BCM_PAGE_SIZE;
  4311. memset(rx_ring, 0, BCM_PAGE_SIZE);
  4312. }
  4313. static int cnic_register_netdev(struct cnic_dev *dev)
  4314. {
  4315. struct cnic_local *cp = dev->cnic_priv;
  4316. struct cnic_eth_dev *ethdev = cp->ethdev;
  4317. int err;
  4318. if (!ethdev)
  4319. return -ENODEV;
  4320. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  4321. return 0;
  4322. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  4323. if (err)
  4324. netdev_err(dev->netdev, "register_cnic failed\n");
  4325. return err;
  4326. }
  4327. static void cnic_unregister_netdev(struct cnic_dev *dev)
  4328. {
  4329. struct cnic_local *cp = dev->cnic_priv;
  4330. struct cnic_eth_dev *ethdev = cp->ethdev;
  4331. if (!ethdev)
  4332. return;
  4333. ethdev->drv_unregister_cnic(dev->netdev);
  4334. }
  4335. static int cnic_start_hw(struct cnic_dev *dev)
  4336. {
  4337. struct cnic_local *cp = dev->cnic_priv;
  4338. struct cnic_eth_dev *ethdev = cp->ethdev;
  4339. int err;
  4340. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4341. return -EALREADY;
  4342. dev->regview = ethdev->io_base;
  4343. pci_dev_get(dev->pcidev);
  4344. cp->func = PCI_FUNC(dev->pcidev->devfn);
  4345. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  4346. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  4347. err = cp->alloc_resc(dev);
  4348. if (err) {
  4349. netdev_err(dev->netdev, "allocate resource failure\n");
  4350. goto err1;
  4351. }
  4352. err = cp->start_hw(dev);
  4353. if (err)
  4354. goto err1;
  4355. err = cnic_cm_open(dev);
  4356. if (err)
  4357. goto err1;
  4358. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  4359. cp->enable_int(dev);
  4360. return 0;
  4361. err1:
  4362. cp->free_resc(dev);
  4363. pci_dev_put(dev->pcidev);
  4364. return err;
  4365. }
  4366. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  4367. {
  4368. cnic_disable_bnx2_int_sync(dev);
  4369. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  4370. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  4371. cnic_init_context(dev, KWQ_CID);
  4372. cnic_init_context(dev, KCQ_CID);
  4373. cnic_setup_5709_context(dev, 0);
  4374. cnic_free_irq(dev);
  4375. cnic_free_resc(dev);
  4376. }
  4377. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  4378. {
  4379. struct cnic_local *cp = dev->cnic_priv;
  4380. cnic_free_irq(dev);
  4381. *cp->kcq1.hw_prod_idx_ptr = 0;
  4382. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4383. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
  4384. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  4385. cnic_free_resc(dev);
  4386. }
  4387. static void cnic_stop_hw(struct cnic_dev *dev)
  4388. {
  4389. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4390. struct cnic_local *cp = dev->cnic_priv;
  4391. int i = 0;
  4392. /* Need to wait for the ring shutdown event to complete
  4393. * before clearing the CNIC_UP flag.
  4394. */
  4395. while (cp->udev->uio_dev != -1 && i < 15) {
  4396. msleep(100);
  4397. i++;
  4398. }
  4399. cnic_shutdown_rings(dev);
  4400. cp->stop_cm(dev);
  4401. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  4402. RCU_INIT_POINTER(cp->ulp_ops[CNIC_ULP_L4], NULL);
  4403. synchronize_rcu();
  4404. cnic_cm_shutdown(dev);
  4405. cp->stop_hw(dev);
  4406. pci_dev_put(dev->pcidev);
  4407. }
  4408. }
  4409. static void cnic_free_dev(struct cnic_dev *dev)
  4410. {
  4411. int i = 0;
  4412. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  4413. msleep(100);
  4414. i++;
  4415. }
  4416. if (atomic_read(&dev->ref_count) != 0)
  4417. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  4418. netdev_info(dev->netdev, "Removed CNIC device\n");
  4419. dev_put(dev->netdev);
  4420. kfree(dev);
  4421. }
  4422. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  4423. struct pci_dev *pdev)
  4424. {
  4425. struct cnic_dev *cdev;
  4426. struct cnic_local *cp;
  4427. int alloc_size;
  4428. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  4429. cdev = kzalloc(alloc_size , GFP_KERNEL);
  4430. if (cdev == NULL) {
  4431. netdev_err(dev, "allocate dev struct failure\n");
  4432. return NULL;
  4433. }
  4434. cdev->netdev = dev;
  4435. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  4436. cdev->register_device = cnic_register_device;
  4437. cdev->unregister_device = cnic_unregister_device;
  4438. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  4439. cp = cdev->cnic_priv;
  4440. cp->dev = cdev;
  4441. cp->l2_single_buf_size = 0x400;
  4442. cp->l2_rx_ring_size = 3;
  4443. spin_lock_init(&cp->cnic_ulp_lock);
  4444. netdev_info(dev, "Added CNIC device\n");
  4445. return cdev;
  4446. }
  4447. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  4448. {
  4449. struct pci_dev *pdev;
  4450. struct cnic_dev *cdev;
  4451. struct cnic_local *cp;
  4452. struct cnic_eth_dev *ethdev = NULL;
  4453. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4454. probe = symbol_get(bnx2_cnic_probe);
  4455. if (probe) {
  4456. ethdev = (*probe)(dev);
  4457. symbol_put(bnx2_cnic_probe);
  4458. }
  4459. if (!ethdev)
  4460. return NULL;
  4461. pdev = ethdev->pdev;
  4462. if (!pdev)
  4463. return NULL;
  4464. dev_hold(dev);
  4465. pci_dev_get(pdev);
  4466. if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  4467. pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
  4468. (pdev->revision < 0x10)) {
  4469. pci_dev_put(pdev);
  4470. goto cnic_err;
  4471. }
  4472. pci_dev_put(pdev);
  4473. cdev = cnic_alloc_dev(dev, pdev);
  4474. if (cdev == NULL)
  4475. goto cnic_err;
  4476. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  4477. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  4478. cp = cdev->cnic_priv;
  4479. cp->ethdev = ethdev;
  4480. cdev->pcidev = pdev;
  4481. cp->chip_id = ethdev->chip_id;
  4482. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4483. cp->cnic_ops = &cnic_bnx2_ops;
  4484. cp->start_hw = cnic_start_bnx2_hw;
  4485. cp->stop_hw = cnic_stop_bnx2_hw;
  4486. cp->setup_pgtbl = cnic_setup_page_tbl;
  4487. cp->alloc_resc = cnic_alloc_bnx2_resc;
  4488. cp->free_resc = cnic_free_resc;
  4489. cp->start_cm = cnic_cm_init_bnx2_hw;
  4490. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  4491. cp->enable_int = cnic_enable_bnx2_int;
  4492. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  4493. cp->close_conn = cnic_close_bnx2_conn;
  4494. return cdev;
  4495. cnic_err:
  4496. dev_put(dev);
  4497. return NULL;
  4498. }
  4499. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  4500. {
  4501. struct pci_dev *pdev;
  4502. struct cnic_dev *cdev;
  4503. struct cnic_local *cp;
  4504. struct cnic_eth_dev *ethdev = NULL;
  4505. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4506. probe = symbol_get(bnx2x_cnic_probe);
  4507. if (probe) {
  4508. ethdev = (*probe)(dev);
  4509. symbol_put(bnx2x_cnic_probe);
  4510. }
  4511. if (!ethdev)
  4512. return NULL;
  4513. pdev = ethdev->pdev;
  4514. if (!pdev)
  4515. return NULL;
  4516. dev_hold(dev);
  4517. cdev = cnic_alloc_dev(dev, pdev);
  4518. if (cdev == NULL) {
  4519. dev_put(dev);
  4520. return NULL;
  4521. }
  4522. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  4523. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  4524. cp = cdev->cnic_priv;
  4525. cp->ethdev = ethdev;
  4526. cdev->pcidev = pdev;
  4527. cp->chip_id = ethdev->chip_id;
  4528. cdev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4529. if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
  4530. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4531. if (CNIC_SUPPORTS_FCOE(cp))
  4532. cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
  4533. if (cdev->max_fcoe_conn > BNX2X_FCOE_NUM_CONNECTIONS)
  4534. cdev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS;
  4535. memcpy(cdev->mac_addr, ethdev->iscsi_mac, 6);
  4536. cp->cnic_ops = &cnic_bnx2x_ops;
  4537. cp->start_hw = cnic_start_bnx2x_hw;
  4538. cp->stop_hw = cnic_stop_bnx2x_hw;
  4539. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  4540. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  4541. cp->free_resc = cnic_free_resc;
  4542. cp->start_cm = cnic_cm_init_bnx2x_hw;
  4543. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  4544. cp->enable_int = cnic_enable_bnx2x_int;
  4545. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  4546. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4547. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  4548. cp->arm_int = cnic_arm_bnx2x_e2_msix;
  4549. } else {
  4550. cp->ack_int = cnic_ack_bnx2x_msix;
  4551. cp->arm_int = cnic_arm_bnx2x_msix;
  4552. }
  4553. cp->close_conn = cnic_close_bnx2x_conn;
  4554. return cdev;
  4555. }
  4556. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  4557. {
  4558. struct ethtool_drvinfo drvinfo;
  4559. struct cnic_dev *cdev = NULL;
  4560. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  4561. memset(&drvinfo, 0, sizeof(drvinfo));
  4562. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  4563. if (!strcmp(drvinfo.driver, "bnx2"))
  4564. cdev = init_bnx2_cnic(dev);
  4565. if (!strcmp(drvinfo.driver, "bnx2x"))
  4566. cdev = init_bnx2x_cnic(dev);
  4567. if (cdev) {
  4568. write_lock(&cnic_dev_lock);
  4569. list_add(&cdev->list, &cnic_dev_list);
  4570. write_unlock(&cnic_dev_lock);
  4571. }
  4572. }
  4573. return cdev;
  4574. }
  4575. static void cnic_rcv_netevent(struct cnic_local *cp, unsigned long event,
  4576. u16 vlan_id)
  4577. {
  4578. int if_type;
  4579. rcu_read_lock();
  4580. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4581. struct cnic_ulp_ops *ulp_ops;
  4582. void *ctx;
  4583. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  4584. if (!ulp_ops || !ulp_ops->indicate_netevent)
  4585. continue;
  4586. ctx = cp->ulp_handle[if_type];
  4587. ulp_ops->indicate_netevent(ctx, event, vlan_id);
  4588. }
  4589. rcu_read_unlock();
  4590. }
  4591. /* netdev event handler */
  4592. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  4593. void *ptr)
  4594. {
  4595. struct net_device *netdev = ptr;
  4596. struct cnic_dev *dev;
  4597. int new_dev = 0;
  4598. dev = cnic_from_netdev(netdev);
  4599. if (!dev && (event == NETDEV_REGISTER || netif_running(netdev))) {
  4600. /* Check for the hot-plug device */
  4601. dev = is_cnic_dev(netdev);
  4602. if (dev) {
  4603. new_dev = 1;
  4604. cnic_hold(dev);
  4605. }
  4606. }
  4607. if (dev) {
  4608. struct cnic_local *cp = dev->cnic_priv;
  4609. if (new_dev)
  4610. cnic_ulp_init(dev);
  4611. else if (event == NETDEV_UNREGISTER)
  4612. cnic_ulp_exit(dev);
  4613. if (event == NETDEV_UP || (new_dev && netif_running(netdev))) {
  4614. if (cnic_register_netdev(dev) != 0) {
  4615. cnic_put(dev);
  4616. goto done;
  4617. }
  4618. if (!cnic_start_hw(dev))
  4619. cnic_ulp_start(dev);
  4620. }
  4621. cnic_rcv_netevent(cp, event, 0);
  4622. if (event == NETDEV_GOING_DOWN) {
  4623. cnic_ulp_stop(dev);
  4624. cnic_stop_hw(dev);
  4625. cnic_unregister_netdev(dev);
  4626. } else if (event == NETDEV_UNREGISTER) {
  4627. write_lock(&cnic_dev_lock);
  4628. list_del_init(&dev->list);
  4629. write_unlock(&cnic_dev_lock);
  4630. cnic_put(dev);
  4631. cnic_free_dev(dev);
  4632. goto done;
  4633. }
  4634. cnic_put(dev);
  4635. } else {
  4636. struct net_device *realdev;
  4637. u16 vid;
  4638. vid = cnic_get_vlan(netdev, &realdev);
  4639. if (realdev) {
  4640. dev = cnic_from_netdev(realdev);
  4641. if (dev) {
  4642. vid |= VLAN_TAG_PRESENT;
  4643. cnic_rcv_netevent(dev->cnic_priv, event, vid);
  4644. cnic_put(dev);
  4645. }
  4646. }
  4647. }
  4648. done:
  4649. return NOTIFY_DONE;
  4650. }
  4651. static struct notifier_block cnic_netdev_notifier = {
  4652. .notifier_call = cnic_netdev_event
  4653. };
  4654. static void cnic_release(void)
  4655. {
  4656. struct cnic_dev *dev;
  4657. struct cnic_uio_dev *udev;
  4658. while (!list_empty(&cnic_dev_list)) {
  4659. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  4660. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4661. cnic_ulp_stop(dev);
  4662. cnic_stop_hw(dev);
  4663. }
  4664. cnic_ulp_exit(dev);
  4665. cnic_unregister_netdev(dev);
  4666. list_del_init(&dev->list);
  4667. cnic_free_dev(dev);
  4668. }
  4669. while (!list_empty(&cnic_udev_list)) {
  4670. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4671. list);
  4672. cnic_free_uio(udev);
  4673. }
  4674. }
  4675. static int __init cnic_init(void)
  4676. {
  4677. int rc = 0;
  4678. pr_info("%s", version);
  4679. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4680. if (rc) {
  4681. cnic_release();
  4682. return rc;
  4683. }
  4684. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4685. if (!cnic_wq) {
  4686. cnic_release();
  4687. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4688. return -ENOMEM;
  4689. }
  4690. return 0;
  4691. }
  4692. static void __exit cnic_exit(void)
  4693. {
  4694. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4695. cnic_release();
  4696. destroy_workqueue(cnic_wq);
  4697. }
  4698. module_init(cnic_init);
  4699. module_exit(cnic_exit);