radeon.h 41 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #ifndef __RADEON_H__
  29. #define __RADEON_H__
  30. /* TODO: Here are things that needs to be done :
  31. * - surface allocator & initializer : (bit like scratch reg) should
  32. * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  33. * related to surface
  34. * - WB : write back stuff (do it bit like scratch reg things)
  35. * - Vblank : look at Jesse's rework and what we should do
  36. * - r600/r700: gart & cp
  37. * - cs : clean cs ioctl use bitmap & things like that.
  38. * - power management stuff
  39. * - Barrier in gart code
  40. * - Unmappabled vram ?
  41. * - TESTING, TESTING, TESTING
  42. */
  43. /* Initialization path:
  44. * We expect that acceleration initialization might fail for various
  45. * reasons even thought we work hard to make it works on most
  46. * configurations. In order to still have a working userspace in such
  47. * situation the init path must succeed up to the memory controller
  48. * initialization point. Failure before this point are considered as
  49. * fatal error. Here is the init callchain :
  50. * radeon_device_init perform common structure, mutex initialization
  51. * asic_init setup the GPU memory layout and perform all
  52. * one time initialization (failure in this
  53. * function are considered fatal)
  54. * asic_startup setup the GPU acceleration, in order to
  55. * follow guideline the first thing this
  56. * function should do is setting the GPU
  57. * memory controller (only MC setup failure
  58. * are considered as fatal)
  59. */
  60. #include <asm/atomic.h>
  61. #include <linux/wait.h>
  62. #include <linux/list.h>
  63. #include <linux/kref.h>
  64. #include <ttm/ttm_bo_api.h>
  65. #include <ttm/ttm_bo_driver.h>
  66. #include <ttm/ttm_placement.h>
  67. #include <ttm/ttm_module.h>
  68. #include "radeon_family.h"
  69. #include "radeon_mode.h"
  70. #include "radeon_reg.h"
  71. /*
  72. * Modules parameters.
  73. */
  74. extern int radeon_no_wb;
  75. extern int radeon_modeset;
  76. extern int radeon_dynclks;
  77. extern int radeon_r4xx_atom;
  78. extern int radeon_agpmode;
  79. extern int radeon_vram_limit;
  80. extern int radeon_gart_size;
  81. extern int radeon_benchmarking;
  82. extern int radeon_testing;
  83. extern int radeon_connector_table;
  84. extern int radeon_tv;
  85. extern int radeon_new_pll;
  86. extern int radeon_dynpm;
  87. extern int radeon_audio;
  88. /*
  89. * Copy from radeon_drv.h so we don't have to include both and have conflicting
  90. * symbol;
  91. */
  92. #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
  93. #define RADEON_IB_POOL_SIZE 16
  94. #define RADEON_DEBUGFS_MAX_NUM_FILES 32
  95. #define RADEONFB_CONN_LIMIT 4
  96. #define RADEON_BIOS_NUM_SCRATCH 8
  97. /*
  98. * Errata workarounds.
  99. */
  100. enum radeon_pll_errata {
  101. CHIP_ERRATA_R300_CG = 0x00000001,
  102. CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
  103. CHIP_ERRATA_PLL_DELAY = 0x00000004
  104. };
  105. struct radeon_device;
  106. /*
  107. * BIOS.
  108. */
  109. bool radeon_get_bios(struct radeon_device *rdev);
  110. /*
  111. * Dummy page
  112. */
  113. struct radeon_dummy_page {
  114. struct page *page;
  115. dma_addr_t addr;
  116. };
  117. int radeon_dummy_page_init(struct radeon_device *rdev);
  118. void radeon_dummy_page_fini(struct radeon_device *rdev);
  119. /*
  120. * Clocks
  121. */
  122. struct radeon_clock {
  123. struct radeon_pll p1pll;
  124. struct radeon_pll p2pll;
  125. struct radeon_pll spll;
  126. struct radeon_pll mpll;
  127. /* 10 Khz units */
  128. uint32_t default_mclk;
  129. uint32_t default_sclk;
  130. };
  131. /*
  132. * Power management
  133. */
  134. int radeon_pm_init(struct radeon_device *rdev);
  135. void radeon_pm_compute_clocks(struct radeon_device *rdev);
  136. void radeon_combios_get_power_modes(struct radeon_device *rdev);
  137. void radeon_atombios_get_power_modes(struct radeon_device *rdev);
  138. /*
  139. * Fences.
  140. */
  141. struct radeon_fence_driver {
  142. uint32_t scratch_reg;
  143. atomic_t seq;
  144. uint32_t last_seq;
  145. unsigned long count_timeout;
  146. wait_queue_head_t queue;
  147. rwlock_t lock;
  148. struct list_head created;
  149. struct list_head emited;
  150. struct list_head signaled;
  151. bool initialized;
  152. };
  153. struct radeon_fence {
  154. struct radeon_device *rdev;
  155. struct kref kref;
  156. struct list_head list;
  157. /* protected by radeon_fence.lock */
  158. uint32_t seq;
  159. unsigned long timeout;
  160. bool emited;
  161. bool signaled;
  162. };
  163. int radeon_fence_driver_init(struct radeon_device *rdev);
  164. void radeon_fence_driver_fini(struct radeon_device *rdev);
  165. int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
  166. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
  167. void radeon_fence_process(struct radeon_device *rdev);
  168. bool radeon_fence_signaled(struct radeon_fence *fence);
  169. int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
  170. int radeon_fence_wait_next(struct radeon_device *rdev);
  171. int radeon_fence_wait_last(struct radeon_device *rdev);
  172. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
  173. void radeon_fence_unref(struct radeon_fence **fence);
  174. /*
  175. * Tiling registers
  176. */
  177. struct radeon_surface_reg {
  178. struct radeon_bo *bo;
  179. };
  180. #define RADEON_GEM_MAX_SURFACES 8
  181. /*
  182. * TTM.
  183. */
  184. struct radeon_mman {
  185. struct ttm_bo_global_ref bo_global_ref;
  186. struct ttm_global_reference mem_global_ref;
  187. struct ttm_bo_device bdev;
  188. bool mem_global_referenced;
  189. bool initialized;
  190. };
  191. struct radeon_bo {
  192. /* Protected by gem.mutex */
  193. struct list_head list;
  194. /* Protected by tbo.reserved */
  195. u32 placements[3];
  196. struct ttm_placement placement;
  197. struct ttm_buffer_object tbo;
  198. struct ttm_bo_kmap_obj kmap;
  199. unsigned pin_count;
  200. void *kptr;
  201. u32 tiling_flags;
  202. u32 pitch;
  203. int surface_reg;
  204. /* Constant after initialization */
  205. struct radeon_device *rdev;
  206. struct drm_gem_object *gobj;
  207. };
  208. struct radeon_bo_list {
  209. struct list_head list;
  210. struct radeon_bo *bo;
  211. uint64_t gpu_offset;
  212. unsigned rdomain;
  213. unsigned wdomain;
  214. u32 tiling_flags;
  215. };
  216. /*
  217. * GEM objects.
  218. */
  219. struct radeon_gem {
  220. struct mutex mutex;
  221. struct list_head objects;
  222. };
  223. int radeon_gem_init(struct radeon_device *rdev);
  224. void radeon_gem_fini(struct radeon_device *rdev);
  225. int radeon_gem_object_create(struct radeon_device *rdev, int size,
  226. int alignment, int initial_domain,
  227. bool discardable, bool kernel,
  228. struct drm_gem_object **obj);
  229. int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
  230. uint64_t *gpu_addr);
  231. void radeon_gem_object_unpin(struct drm_gem_object *obj);
  232. /*
  233. * GART structures, functions & helpers
  234. */
  235. struct radeon_mc;
  236. struct radeon_gart_table_ram {
  237. volatile uint32_t *ptr;
  238. };
  239. struct radeon_gart_table_vram {
  240. struct radeon_bo *robj;
  241. volatile uint32_t *ptr;
  242. };
  243. union radeon_gart_table {
  244. struct radeon_gart_table_ram ram;
  245. struct radeon_gart_table_vram vram;
  246. };
  247. #define RADEON_GPU_PAGE_SIZE 4096
  248. struct radeon_gart {
  249. dma_addr_t table_addr;
  250. unsigned num_gpu_pages;
  251. unsigned num_cpu_pages;
  252. unsigned table_size;
  253. union radeon_gart_table table;
  254. struct page **pages;
  255. dma_addr_t *pages_addr;
  256. bool ready;
  257. };
  258. int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
  259. void radeon_gart_table_ram_free(struct radeon_device *rdev);
  260. int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
  261. void radeon_gart_table_vram_free(struct radeon_device *rdev);
  262. int radeon_gart_init(struct radeon_device *rdev);
  263. void radeon_gart_fini(struct radeon_device *rdev);
  264. void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
  265. int pages);
  266. int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
  267. int pages, struct page **pagelist);
  268. /*
  269. * GPU MC structures, functions & helpers
  270. */
  271. struct radeon_mc {
  272. resource_size_t aper_size;
  273. resource_size_t aper_base;
  274. resource_size_t agp_base;
  275. /* for some chips with <= 32MB we need to lie
  276. * about vram size near mc fb location */
  277. u64 mc_vram_size;
  278. u64 gtt_location;
  279. u64 gtt_size;
  280. u64 gtt_start;
  281. u64 gtt_end;
  282. u64 vram_location;
  283. u64 vram_start;
  284. u64 vram_end;
  285. unsigned vram_width;
  286. u64 real_vram_size;
  287. int vram_mtrr;
  288. bool vram_is_ddr;
  289. bool igp_sideport_enabled;
  290. };
  291. int radeon_mc_setup(struct radeon_device *rdev);
  292. bool radeon_combios_sideport_present(struct radeon_device *rdev);
  293. bool radeon_atombios_sideport_present(struct radeon_device *rdev);
  294. /*
  295. * GPU scratch registers structures, functions & helpers
  296. */
  297. struct radeon_scratch {
  298. unsigned num_reg;
  299. bool free[32];
  300. uint32_t reg[32];
  301. };
  302. int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
  303. void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
  304. /*
  305. * IRQS.
  306. */
  307. struct radeon_irq {
  308. bool installed;
  309. bool sw_int;
  310. /* FIXME: use a define max crtc rather than hardcode it */
  311. bool crtc_vblank_int[2];
  312. /* FIXME: use defines for max hpd/dacs */
  313. bool hpd[6];
  314. spinlock_t sw_lock;
  315. int sw_refcount;
  316. };
  317. int radeon_irq_kms_init(struct radeon_device *rdev);
  318. void radeon_irq_kms_fini(struct radeon_device *rdev);
  319. void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
  320. void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
  321. /*
  322. * CP & ring.
  323. */
  324. struct radeon_ib {
  325. struct list_head list;
  326. unsigned long idx;
  327. uint64_t gpu_addr;
  328. struct radeon_fence *fence;
  329. uint32_t *ptr;
  330. uint32_t length_dw;
  331. };
  332. /*
  333. * locking -
  334. * mutex protects scheduled_ibs, ready, alloc_bm
  335. */
  336. struct radeon_ib_pool {
  337. struct mutex mutex;
  338. struct radeon_bo *robj;
  339. struct list_head scheduled_ibs;
  340. struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
  341. bool ready;
  342. DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
  343. };
  344. struct radeon_cp {
  345. struct radeon_bo *ring_obj;
  346. volatile uint32_t *ring;
  347. unsigned rptr;
  348. unsigned wptr;
  349. unsigned wptr_old;
  350. unsigned ring_size;
  351. unsigned ring_free_dw;
  352. int count_dw;
  353. uint64_t gpu_addr;
  354. uint32_t align_mask;
  355. uint32_t ptr_mask;
  356. struct mutex mutex;
  357. bool ready;
  358. };
  359. /*
  360. * R6xx+ IH ring
  361. */
  362. struct r600_ih {
  363. struct radeon_bo *ring_obj;
  364. volatile uint32_t *ring;
  365. unsigned rptr;
  366. unsigned wptr;
  367. unsigned wptr_old;
  368. unsigned ring_size;
  369. uint64_t gpu_addr;
  370. uint32_t ptr_mask;
  371. spinlock_t lock;
  372. bool enabled;
  373. };
  374. struct r600_blit {
  375. struct mutex mutex;
  376. struct radeon_bo *shader_obj;
  377. u64 shader_gpu_addr;
  378. u32 vs_offset, ps_offset;
  379. u32 state_offset;
  380. u32 state_len;
  381. u32 vb_used, vb_total;
  382. struct radeon_ib *vb_ib;
  383. };
  384. int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
  385. void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
  386. int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
  387. int radeon_ib_pool_init(struct radeon_device *rdev);
  388. void radeon_ib_pool_fini(struct radeon_device *rdev);
  389. int radeon_ib_test(struct radeon_device *rdev);
  390. /* Ring access between begin & end cannot sleep */
  391. void radeon_ring_free_size(struct radeon_device *rdev);
  392. int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
  393. void radeon_ring_unlock_commit(struct radeon_device *rdev);
  394. void radeon_ring_unlock_undo(struct radeon_device *rdev);
  395. int radeon_ring_test(struct radeon_device *rdev);
  396. int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
  397. void radeon_ring_fini(struct radeon_device *rdev);
  398. /*
  399. * CS.
  400. */
  401. struct radeon_cs_reloc {
  402. struct drm_gem_object *gobj;
  403. struct radeon_bo *robj;
  404. struct radeon_bo_list lobj;
  405. uint32_t handle;
  406. uint32_t flags;
  407. };
  408. struct radeon_cs_chunk {
  409. uint32_t chunk_id;
  410. uint32_t length_dw;
  411. int kpage_idx[2];
  412. uint32_t *kpage[2];
  413. uint32_t *kdata;
  414. void __user *user_ptr;
  415. int last_copied_page;
  416. int last_page_index;
  417. };
  418. struct radeon_cs_parser {
  419. struct device *dev;
  420. struct radeon_device *rdev;
  421. struct drm_file *filp;
  422. /* chunks */
  423. unsigned nchunks;
  424. struct radeon_cs_chunk *chunks;
  425. uint64_t *chunks_array;
  426. /* IB */
  427. unsigned idx;
  428. /* relocations */
  429. unsigned nrelocs;
  430. struct radeon_cs_reloc *relocs;
  431. struct radeon_cs_reloc **relocs_ptr;
  432. struct list_head validated;
  433. /* indices of various chunks */
  434. int chunk_ib_idx;
  435. int chunk_relocs_idx;
  436. struct radeon_ib *ib;
  437. void *track;
  438. unsigned family;
  439. int parser_error;
  440. };
  441. extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
  442. extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
  443. static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
  444. {
  445. struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
  446. u32 pg_idx, pg_offset;
  447. u32 idx_value = 0;
  448. int new_page;
  449. pg_idx = (idx * 4) / PAGE_SIZE;
  450. pg_offset = (idx * 4) % PAGE_SIZE;
  451. if (ibc->kpage_idx[0] == pg_idx)
  452. return ibc->kpage[0][pg_offset/4];
  453. if (ibc->kpage_idx[1] == pg_idx)
  454. return ibc->kpage[1][pg_offset/4];
  455. new_page = radeon_cs_update_pages(p, pg_idx);
  456. if (new_page < 0) {
  457. p->parser_error = new_page;
  458. return 0;
  459. }
  460. idx_value = ibc->kpage[new_page][pg_offset/4];
  461. return idx_value;
  462. }
  463. struct radeon_cs_packet {
  464. unsigned idx;
  465. unsigned type;
  466. unsigned reg;
  467. unsigned opcode;
  468. int count;
  469. unsigned one_reg_wr;
  470. };
  471. typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
  472. struct radeon_cs_packet *pkt,
  473. unsigned idx, unsigned reg);
  474. typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
  475. struct radeon_cs_packet *pkt);
  476. /*
  477. * AGP
  478. */
  479. int radeon_agp_init(struct radeon_device *rdev);
  480. void radeon_agp_resume(struct radeon_device *rdev);
  481. void radeon_agp_fini(struct radeon_device *rdev);
  482. /*
  483. * Writeback
  484. */
  485. struct radeon_wb {
  486. struct radeon_bo *wb_obj;
  487. volatile uint32_t *wb;
  488. uint64_t gpu_addr;
  489. };
  490. /**
  491. * struct radeon_pm - power management datas
  492. * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
  493. * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
  494. * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
  495. * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
  496. * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
  497. * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
  498. * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
  499. * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
  500. * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
  501. * @sclk: GPU clock Mhz (core bandwith depends of this clock)
  502. * @needed_bandwidth: current bandwidth needs
  503. *
  504. * It keeps track of various data needed to take powermanagement decision.
  505. * Bandwith need is used to determine minimun clock of the GPU and memory.
  506. * Equation between gpu/memory clock and available bandwidth is hw dependent
  507. * (type of memory, bus size, efficiency, ...)
  508. */
  509. enum radeon_pm_state {
  510. PM_STATE_DISABLED,
  511. PM_STATE_MINIMUM,
  512. PM_STATE_PAUSED,
  513. PM_STATE_ACTIVE
  514. };
  515. enum radeon_pm_action {
  516. PM_ACTION_NONE,
  517. PM_ACTION_MINIMUM,
  518. PM_ACTION_DOWNCLOCK,
  519. PM_ACTION_UPCLOCK
  520. };
  521. enum radeon_voltage_type {
  522. VOLTAGE_NONE = 0,
  523. VOLTAGE_GPIO,
  524. VOLTAGE_VDDC,
  525. VOLTAGE_SW
  526. };
  527. enum radeon_pm_state_type {
  528. POWER_STATE_TYPE_DEFAULT,
  529. POWER_STATE_TYPE_POWERSAVE,
  530. POWER_STATE_TYPE_BATTERY,
  531. POWER_STATE_TYPE_BALANCED,
  532. POWER_STATE_TYPE_PERFORMANCE,
  533. };
  534. enum radeon_pm_clock_mode_type {
  535. POWER_MODE_TYPE_DEFAULT,
  536. POWER_MODE_TYPE_LOW,
  537. POWER_MODE_TYPE_MID,
  538. POWER_MODE_TYPE_HIGH,
  539. };
  540. struct radeon_voltage {
  541. enum radeon_voltage_type type;
  542. /* gpio voltage */
  543. struct radeon_gpio_rec gpio;
  544. u32 delay; /* delay in usec from voltage drop to sclk change */
  545. bool active_high; /* voltage drop is active when bit is high */
  546. /* VDDC voltage */
  547. u8 vddc_id; /* index into vddc voltage table */
  548. u8 vddci_id; /* index into vddci voltage table */
  549. bool vddci_enabled;
  550. /* r6xx+ sw */
  551. u32 voltage;
  552. };
  553. struct radeon_pm_non_clock_info {
  554. /* pcie lanes */
  555. int pcie_lanes;
  556. /* standardized non-clock flags */
  557. u32 flags;
  558. };
  559. struct radeon_pm_clock_info {
  560. /* memory clock */
  561. u32 mclk;
  562. /* engine clock */
  563. u32 sclk;
  564. /* voltage info */
  565. struct radeon_voltage voltage;
  566. /* standardized clock flags - not sure we'll need these */
  567. u32 flags;
  568. };
  569. struct radeon_power_state {
  570. enum radeon_pm_state_type type;
  571. /* XXX: use a define for num clock modes */
  572. struct radeon_pm_clock_info clock_info[8];
  573. /* number of valid clock modes in this power state */
  574. int num_clock_modes;
  575. /* currently selected clock mode */
  576. struct radeon_pm_clock_info *current_clock_mode;
  577. struct radeon_pm_clock_info *requested_clock_mode;
  578. struct radeon_pm_clock_info *default_clock_mode;
  579. /* non clock info about this state */
  580. struct radeon_pm_non_clock_info non_clock_info;
  581. bool voltage_drop_active;
  582. };
  583. struct radeon_pm {
  584. struct mutex mutex;
  585. struct work_struct reclock_work;
  586. struct delayed_work idle_work;
  587. enum radeon_pm_state state;
  588. enum radeon_pm_action planned_action;
  589. unsigned long action_timeout;
  590. bool downclocked;
  591. bool vblank_callback;
  592. int active_crtcs;
  593. int req_vblank;
  594. uint32_t min_gpu_engine_clock;
  595. uint32_t min_gpu_memory_clock;
  596. uint32_t min_mode_engine_clock;
  597. uint32_t min_mode_memory_clock;
  598. fixed20_12 max_bandwidth;
  599. fixed20_12 igp_sideport_mclk;
  600. fixed20_12 igp_system_mclk;
  601. fixed20_12 igp_ht_link_clk;
  602. fixed20_12 igp_ht_link_width;
  603. fixed20_12 k8_bandwidth;
  604. fixed20_12 sideport_bandwidth;
  605. fixed20_12 ht_bandwidth;
  606. fixed20_12 core_bandwidth;
  607. fixed20_12 sclk;
  608. fixed20_12 needed_bandwidth;
  609. /* XXX: use a define for num power modes */
  610. struct radeon_power_state power_state[8];
  611. /* number of valid power states */
  612. int num_power_states;
  613. struct radeon_power_state *current_power_state;
  614. struct radeon_power_state *requested_power_state;
  615. struct radeon_power_state *default_power_state;
  616. };
  617. /*
  618. * Benchmarking
  619. */
  620. void radeon_benchmark(struct radeon_device *rdev);
  621. /*
  622. * Testing
  623. */
  624. void radeon_test_moves(struct radeon_device *rdev);
  625. /*
  626. * Debugfs
  627. */
  628. int radeon_debugfs_add_files(struct radeon_device *rdev,
  629. struct drm_info_list *files,
  630. unsigned nfiles);
  631. int radeon_debugfs_fence_init(struct radeon_device *rdev);
  632. int r100_debugfs_rbbm_init(struct radeon_device *rdev);
  633. int r100_debugfs_cp_init(struct radeon_device *rdev);
  634. /*
  635. * ASIC specific functions.
  636. */
  637. struct radeon_asic {
  638. int (*init)(struct radeon_device *rdev);
  639. void (*fini)(struct radeon_device *rdev);
  640. int (*resume)(struct radeon_device *rdev);
  641. int (*suspend)(struct radeon_device *rdev);
  642. void (*vga_set_state)(struct radeon_device *rdev, bool state);
  643. int (*gpu_reset)(struct radeon_device *rdev);
  644. void (*gart_tlb_flush)(struct radeon_device *rdev);
  645. int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
  646. int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
  647. void (*cp_fini)(struct radeon_device *rdev);
  648. void (*cp_disable)(struct radeon_device *rdev);
  649. void (*cp_commit)(struct radeon_device *rdev);
  650. void (*ring_start)(struct radeon_device *rdev);
  651. int (*ring_test)(struct radeon_device *rdev);
  652. void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
  653. int (*irq_set)(struct radeon_device *rdev);
  654. int (*irq_process)(struct radeon_device *rdev);
  655. u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
  656. void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
  657. int (*cs_parse)(struct radeon_cs_parser *p);
  658. int (*copy_blit)(struct radeon_device *rdev,
  659. uint64_t src_offset,
  660. uint64_t dst_offset,
  661. unsigned num_pages,
  662. struct radeon_fence *fence);
  663. int (*copy_dma)(struct radeon_device *rdev,
  664. uint64_t src_offset,
  665. uint64_t dst_offset,
  666. unsigned num_pages,
  667. struct radeon_fence *fence);
  668. int (*copy)(struct radeon_device *rdev,
  669. uint64_t src_offset,
  670. uint64_t dst_offset,
  671. unsigned num_pages,
  672. struct radeon_fence *fence);
  673. uint32_t (*get_engine_clock)(struct radeon_device *rdev);
  674. void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
  675. uint32_t (*get_memory_clock)(struct radeon_device *rdev);
  676. void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
  677. int (*get_pcie_lanes)(struct radeon_device *rdev);
  678. void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
  679. void (*set_clock_gating)(struct radeon_device *rdev, int enable);
  680. int (*set_surface_reg)(struct radeon_device *rdev, int reg,
  681. uint32_t tiling_flags, uint32_t pitch,
  682. uint32_t offset, uint32_t obj_size);
  683. int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
  684. void (*bandwidth_update)(struct radeon_device *rdev);
  685. void (*hpd_init)(struct radeon_device *rdev);
  686. void (*hpd_fini)(struct radeon_device *rdev);
  687. bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  688. void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  689. /* ioctl hw specific callback. Some hw might want to perform special
  690. * operation on specific ioctl. For instance on wait idle some hw
  691. * might want to perform and HDP flush through MMIO as it seems that
  692. * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
  693. * through ring.
  694. */
  695. void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
  696. };
  697. /*
  698. * Asic structures
  699. */
  700. struct r100_asic {
  701. const unsigned *reg_safe_bm;
  702. unsigned reg_safe_bm_size;
  703. u32 hdp_cntl;
  704. };
  705. struct r300_asic {
  706. const unsigned *reg_safe_bm;
  707. unsigned reg_safe_bm_size;
  708. u32 resync_scratch;
  709. u32 hdp_cntl;
  710. };
  711. struct r600_asic {
  712. unsigned max_pipes;
  713. unsigned max_tile_pipes;
  714. unsigned max_simds;
  715. unsigned max_backends;
  716. unsigned max_gprs;
  717. unsigned max_threads;
  718. unsigned max_stack_entries;
  719. unsigned max_hw_contexts;
  720. unsigned max_gs_threads;
  721. unsigned sx_max_export_size;
  722. unsigned sx_max_export_pos_size;
  723. unsigned sx_max_export_smx_size;
  724. unsigned sq_num_cf_insts;
  725. };
  726. struct rv770_asic {
  727. unsigned max_pipes;
  728. unsigned max_tile_pipes;
  729. unsigned max_simds;
  730. unsigned max_backends;
  731. unsigned max_gprs;
  732. unsigned max_threads;
  733. unsigned max_stack_entries;
  734. unsigned max_hw_contexts;
  735. unsigned max_gs_threads;
  736. unsigned sx_max_export_size;
  737. unsigned sx_max_export_pos_size;
  738. unsigned sx_max_export_smx_size;
  739. unsigned sq_num_cf_insts;
  740. unsigned sx_num_of_sets;
  741. unsigned sc_prim_fifo_size;
  742. unsigned sc_hiz_tile_fifo_size;
  743. unsigned sc_earlyz_tile_fifo_fize;
  744. };
  745. union radeon_asic_config {
  746. struct r300_asic r300;
  747. struct r100_asic r100;
  748. struct r600_asic r600;
  749. struct rv770_asic rv770;
  750. };
  751. /*
  752. * IOCTL.
  753. */
  754. int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
  755. struct drm_file *filp);
  756. int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
  757. struct drm_file *filp);
  758. int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
  759. struct drm_file *file_priv);
  760. int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
  761. struct drm_file *file_priv);
  762. int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
  763. struct drm_file *file_priv);
  764. int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
  765. struct drm_file *file_priv);
  766. int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
  767. struct drm_file *filp);
  768. int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
  769. struct drm_file *filp);
  770. int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
  771. struct drm_file *filp);
  772. int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
  773. struct drm_file *filp);
  774. int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
  775. int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
  776. struct drm_file *filp);
  777. int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
  778. struct drm_file *filp);
  779. /*
  780. * Core structure, functions and helpers.
  781. */
  782. typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
  783. typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
  784. struct radeon_device {
  785. struct device *dev;
  786. struct drm_device *ddev;
  787. struct pci_dev *pdev;
  788. /* ASIC */
  789. union radeon_asic_config config;
  790. enum radeon_family family;
  791. unsigned long flags;
  792. int usec_timeout;
  793. enum radeon_pll_errata pll_errata;
  794. int num_gb_pipes;
  795. int num_z_pipes;
  796. int disp_priority;
  797. /* BIOS */
  798. uint8_t *bios;
  799. bool is_atom_bios;
  800. uint16_t bios_header_start;
  801. struct radeon_bo *stollen_vga_memory;
  802. struct fb_info *fbdev_info;
  803. struct radeon_bo *fbdev_rbo;
  804. struct radeon_framebuffer *fbdev_rfb;
  805. /* Register mmio */
  806. resource_size_t rmmio_base;
  807. resource_size_t rmmio_size;
  808. void *rmmio;
  809. radeon_rreg_t mc_rreg;
  810. radeon_wreg_t mc_wreg;
  811. radeon_rreg_t pll_rreg;
  812. radeon_wreg_t pll_wreg;
  813. uint32_t pcie_reg_mask;
  814. radeon_rreg_t pciep_rreg;
  815. radeon_wreg_t pciep_wreg;
  816. struct radeon_clock clock;
  817. struct radeon_mc mc;
  818. struct radeon_gart gart;
  819. struct radeon_mode_info mode_info;
  820. struct radeon_scratch scratch;
  821. struct radeon_mman mman;
  822. struct radeon_fence_driver fence_drv;
  823. struct radeon_cp cp;
  824. struct radeon_ib_pool ib_pool;
  825. struct radeon_irq irq;
  826. struct radeon_asic *asic;
  827. struct radeon_gem gem;
  828. struct radeon_pm pm;
  829. uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
  830. struct mutex cs_mutex;
  831. struct radeon_wb wb;
  832. struct radeon_dummy_page dummy_page;
  833. bool gpu_lockup;
  834. bool shutdown;
  835. bool suspend;
  836. bool need_dma32;
  837. bool accel_working;
  838. struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
  839. const struct firmware *me_fw; /* all family ME firmware */
  840. const struct firmware *pfp_fw; /* r6/700 PFP firmware */
  841. const struct firmware *rlc_fw; /* r6/700 RLC firmware */
  842. struct r600_blit r600_blit;
  843. int msi_enabled; /* msi enabled */
  844. struct r600_ih ih; /* r6/700 interrupt ring */
  845. struct workqueue_struct *wq;
  846. struct work_struct hotplug_work;
  847. int num_crtc; /* number of crtcs */
  848. struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
  849. /* audio stuff */
  850. struct timer_list audio_timer;
  851. int audio_channels;
  852. int audio_rate;
  853. int audio_bits_per_sample;
  854. uint8_t audio_status_bits;
  855. uint8_t audio_category_code;
  856. };
  857. int radeon_device_init(struct radeon_device *rdev,
  858. struct drm_device *ddev,
  859. struct pci_dev *pdev,
  860. uint32_t flags);
  861. void radeon_device_fini(struct radeon_device *rdev);
  862. int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
  863. /* r600 blit */
  864. int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
  865. void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
  866. void r600_kms_blit_copy(struct radeon_device *rdev,
  867. u64 src_gpu_addr, u64 dst_gpu_addr,
  868. int size_bytes);
  869. static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
  870. {
  871. if (reg < rdev->rmmio_size)
  872. return readl(((void __iomem *)rdev->rmmio) + reg);
  873. else {
  874. writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
  875. return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
  876. }
  877. }
  878. static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  879. {
  880. if (reg < rdev->rmmio_size)
  881. writel(v, ((void __iomem *)rdev->rmmio) + reg);
  882. else {
  883. writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
  884. writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
  885. }
  886. }
  887. /*
  888. * Cast helper
  889. */
  890. #define to_radeon_fence(p) ((struct radeon_fence *)(p))
  891. /*
  892. * Registers read & write functions.
  893. */
  894. #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
  895. #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
  896. #define RREG32(reg) r100_mm_rreg(rdev, (reg))
  897. #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
  898. #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
  899. #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  900. #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  901. #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
  902. #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
  903. #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
  904. #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
  905. #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
  906. #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
  907. #define WREG32_P(reg, val, mask) \
  908. do { \
  909. uint32_t tmp_ = RREG32(reg); \
  910. tmp_ &= (mask); \
  911. tmp_ |= ((val) & ~(mask)); \
  912. WREG32(reg, tmp_); \
  913. } while (0)
  914. #define WREG32_PLL_P(reg, val, mask) \
  915. do { \
  916. uint32_t tmp_ = RREG32_PLL(reg); \
  917. tmp_ &= (mask); \
  918. tmp_ |= ((val) & ~(mask)); \
  919. WREG32_PLL(reg, tmp_); \
  920. } while (0)
  921. #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
  922. /*
  923. * Indirect registers accessor
  924. */
  925. static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
  926. {
  927. uint32_t r;
  928. WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  929. r = RREG32(RADEON_PCIE_DATA);
  930. return r;
  931. }
  932. static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  933. {
  934. WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  935. WREG32(RADEON_PCIE_DATA, (v));
  936. }
  937. void r100_pll_errata_after_index(struct radeon_device *rdev);
  938. /*
  939. * ASICs helpers.
  940. */
  941. #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
  942. (rdev->pdev->device == 0x5969))
  943. #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
  944. (rdev->family == CHIP_RV200) || \
  945. (rdev->family == CHIP_RS100) || \
  946. (rdev->family == CHIP_RS200) || \
  947. (rdev->family == CHIP_RV250) || \
  948. (rdev->family == CHIP_RV280) || \
  949. (rdev->family == CHIP_RS300))
  950. #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
  951. (rdev->family == CHIP_RV350) || \
  952. (rdev->family == CHIP_R350) || \
  953. (rdev->family == CHIP_RV380) || \
  954. (rdev->family == CHIP_R420) || \
  955. (rdev->family == CHIP_R423) || \
  956. (rdev->family == CHIP_RV410) || \
  957. (rdev->family == CHIP_RS400) || \
  958. (rdev->family == CHIP_RS480))
  959. #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
  960. #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
  961. #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
  962. /*
  963. * BIOS helpers.
  964. */
  965. #define RBIOS8(i) (rdev->bios[i])
  966. #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
  967. #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
  968. int radeon_combios_init(struct radeon_device *rdev);
  969. void radeon_combios_fini(struct radeon_device *rdev);
  970. int radeon_atombios_init(struct radeon_device *rdev);
  971. void radeon_atombios_fini(struct radeon_device *rdev);
  972. /*
  973. * RING helpers.
  974. */
  975. static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
  976. {
  977. #if DRM_DEBUG_CODE
  978. if (rdev->cp.count_dw <= 0) {
  979. DRM_ERROR("radeon: writting more dword to ring than expected !\n");
  980. }
  981. #endif
  982. rdev->cp.ring[rdev->cp.wptr++] = v;
  983. rdev->cp.wptr &= rdev->cp.ptr_mask;
  984. rdev->cp.count_dw--;
  985. rdev->cp.ring_free_dw--;
  986. }
  987. /*
  988. * ASICs macro.
  989. */
  990. #define radeon_init(rdev) (rdev)->asic->init((rdev))
  991. #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
  992. #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
  993. #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
  994. #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
  995. #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
  996. #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
  997. #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
  998. #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
  999. #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
  1000. #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
  1001. #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
  1002. #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
  1003. #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
  1004. #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
  1005. #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
  1006. #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
  1007. #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
  1008. #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
  1009. #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
  1010. #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
  1011. #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
  1012. #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
  1013. #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
  1014. #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
  1015. #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
  1016. #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
  1017. #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
  1018. #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
  1019. #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
  1020. #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
  1021. #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
  1022. #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
  1023. #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
  1024. /* Common functions */
  1025. /* AGP */
  1026. extern void radeon_agp_disable(struct radeon_device *rdev);
  1027. extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
  1028. extern int radeon_modeset_init(struct radeon_device *rdev);
  1029. extern void radeon_modeset_fini(struct radeon_device *rdev);
  1030. extern bool radeon_card_posted(struct radeon_device *rdev);
  1031. extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
  1032. extern int radeon_clocks_init(struct radeon_device *rdev);
  1033. extern void radeon_clocks_fini(struct radeon_device *rdev);
  1034. extern void radeon_scratch_init(struct radeon_device *rdev);
  1035. extern void radeon_surface_init(struct radeon_device *rdev);
  1036. extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
  1037. extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
  1038. extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  1039. extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
  1040. extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
  1041. /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
  1042. struct r100_mc_save {
  1043. u32 GENMO_WT;
  1044. u32 CRTC_EXT_CNTL;
  1045. u32 CRTC_GEN_CNTL;
  1046. u32 CRTC2_GEN_CNTL;
  1047. u32 CUR_OFFSET;
  1048. u32 CUR2_OFFSET;
  1049. };
  1050. extern void r100_cp_disable(struct radeon_device *rdev);
  1051. extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
  1052. extern void r100_cp_fini(struct radeon_device *rdev);
  1053. extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
  1054. extern int r100_pci_gart_init(struct radeon_device *rdev);
  1055. extern void r100_pci_gart_fini(struct radeon_device *rdev);
  1056. extern int r100_pci_gart_enable(struct radeon_device *rdev);
  1057. extern void r100_pci_gart_disable(struct radeon_device *rdev);
  1058. extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
  1059. extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
  1060. extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
  1061. extern void r100_ib_fini(struct radeon_device *rdev);
  1062. extern int r100_ib_init(struct radeon_device *rdev);
  1063. extern void r100_irq_disable(struct radeon_device *rdev);
  1064. extern int r100_irq_set(struct radeon_device *rdev);
  1065. extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
  1066. extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
  1067. extern void r100_vram_init_sizes(struct radeon_device *rdev);
  1068. extern void r100_wb_disable(struct radeon_device *rdev);
  1069. extern void r100_wb_fini(struct radeon_device *rdev);
  1070. extern int r100_wb_init(struct radeon_device *rdev);
  1071. extern void r100_hdp_reset(struct radeon_device *rdev);
  1072. extern int r100_rb2d_reset(struct radeon_device *rdev);
  1073. extern int r100_cp_reset(struct radeon_device *rdev);
  1074. extern void r100_vga_render_disable(struct radeon_device *rdev);
  1075. extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
  1076. struct radeon_cs_packet *pkt,
  1077. struct radeon_bo *robj);
  1078. extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
  1079. struct radeon_cs_packet *pkt,
  1080. const unsigned *auth, unsigned n,
  1081. radeon_packet0_check_t check);
  1082. extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
  1083. struct radeon_cs_packet *pkt,
  1084. unsigned idx);
  1085. extern void r100_enable_bm(struct radeon_device *rdev);
  1086. extern void r100_set_common_regs(struct radeon_device *rdev);
  1087. /* rv200,rv250,rv280 */
  1088. extern void r200_set_safe_registers(struct radeon_device *rdev);
  1089. /* r300,r350,rv350,rv370,rv380 */
  1090. extern void r300_set_reg_safe(struct radeon_device *rdev);
  1091. extern void r300_mc_program(struct radeon_device *rdev);
  1092. extern void r300_vram_info(struct radeon_device *rdev);
  1093. extern void r300_clock_startup(struct radeon_device *rdev);
  1094. extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
  1095. extern int rv370_pcie_gart_init(struct radeon_device *rdev);
  1096. extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
  1097. extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
  1098. extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
  1099. /* r420,r423,rv410 */
  1100. extern int r420_mc_init(struct radeon_device *rdev);
  1101. extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
  1102. extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
  1103. extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
  1104. extern void r420_pipes_init(struct radeon_device *rdev);
  1105. /* rv515 */
  1106. struct rv515_mc_save {
  1107. u32 d1vga_control;
  1108. u32 d2vga_control;
  1109. u32 vga_render_control;
  1110. u32 vga_hdp_control;
  1111. u32 d1crtc_control;
  1112. u32 d2crtc_control;
  1113. };
  1114. extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
  1115. extern void rv515_vga_render_disable(struct radeon_device *rdev);
  1116. extern void rv515_set_safe_registers(struct radeon_device *rdev);
  1117. extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
  1118. extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
  1119. extern void rv515_clock_startup(struct radeon_device *rdev);
  1120. extern void rv515_debugfs(struct radeon_device *rdev);
  1121. extern int rv515_suspend(struct radeon_device *rdev);
  1122. /* rs400 */
  1123. extern int rs400_gart_init(struct radeon_device *rdev);
  1124. extern int rs400_gart_enable(struct radeon_device *rdev);
  1125. extern void rs400_gart_adjust_size(struct radeon_device *rdev);
  1126. extern void rs400_gart_disable(struct radeon_device *rdev);
  1127. extern void rs400_gart_fini(struct radeon_device *rdev);
  1128. /* rs600 */
  1129. extern void rs600_set_safe_registers(struct radeon_device *rdev);
  1130. extern int rs600_irq_set(struct radeon_device *rdev);
  1131. extern void rs600_irq_disable(struct radeon_device *rdev);
  1132. /* rs690, rs740 */
  1133. extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
  1134. struct drm_display_mode *mode1,
  1135. struct drm_display_mode *mode2);
  1136. /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
  1137. extern bool r600_card_posted(struct radeon_device *rdev);
  1138. extern void r600_cp_stop(struct radeon_device *rdev);
  1139. extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
  1140. extern int r600_cp_resume(struct radeon_device *rdev);
  1141. extern void r600_cp_fini(struct radeon_device *rdev);
  1142. extern int r600_count_pipe_bits(uint32_t val);
  1143. extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
  1144. extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
  1145. extern int r600_pcie_gart_init(struct radeon_device *rdev);
  1146. extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
  1147. extern int r600_ib_test(struct radeon_device *rdev);
  1148. extern int r600_ring_test(struct radeon_device *rdev);
  1149. extern void r600_wb_fini(struct radeon_device *rdev);
  1150. extern int r600_wb_enable(struct radeon_device *rdev);
  1151. extern void r600_wb_disable(struct radeon_device *rdev);
  1152. extern void r600_scratch_init(struct radeon_device *rdev);
  1153. extern int r600_blit_init(struct radeon_device *rdev);
  1154. extern void r600_blit_fini(struct radeon_device *rdev);
  1155. extern int r600_init_microcode(struct radeon_device *rdev);
  1156. extern int r600_gpu_reset(struct radeon_device *rdev);
  1157. /* r600 irq */
  1158. extern int r600_irq_init(struct radeon_device *rdev);
  1159. extern void r600_irq_fini(struct radeon_device *rdev);
  1160. extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
  1161. extern int r600_irq_set(struct radeon_device *rdev);
  1162. extern void r600_irq_suspend(struct radeon_device *rdev);
  1163. /* r600 audio */
  1164. extern int r600_audio_init(struct radeon_device *rdev);
  1165. extern int r600_audio_tmds_index(struct drm_encoder *encoder);
  1166. extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
  1167. extern void r600_audio_fini(struct radeon_device *rdev);
  1168. extern void r600_hdmi_init(struct drm_encoder *encoder);
  1169. extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable);
  1170. extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
  1171. extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
  1172. extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
  1173. int channels,
  1174. int rate,
  1175. int bps,
  1176. uint8_t status_bits,
  1177. uint8_t category_code);
  1178. #include "radeon_object.h"
  1179. #endif