r8a66597-udc.c 42 KB

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  1. /*
  2. * R8A66597 UDC (USB gadget)
  3. *
  4. * Copyright (C) 2006-2009 Renesas Solutions Corp.
  5. *
  6. * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  20. *
  21. */
  22. #include <linux/module.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/delay.h>
  25. #include <linux/io.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/clk.h>
  28. #include <linux/err.h>
  29. #include <linux/slab.h>
  30. #include <linux/usb/ch9.h>
  31. #include <linux/usb/gadget.h>
  32. #include "r8a66597-udc.h"
  33. #define DRIVER_VERSION "2009-08-18"
  34. static const char udc_name[] = "r8a66597_udc";
  35. static const char *r8a66597_ep_name[] = {
  36. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7",
  37. "ep8", "ep9",
  38. };
  39. static void init_controller(struct r8a66597 *r8a66597);
  40. static void disable_controller(struct r8a66597 *r8a66597);
  41. static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req);
  42. static void irq_packet_write(struct r8a66597_ep *ep,
  43. struct r8a66597_request *req);
  44. static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
  45. gfp_t gfp_flags);
  46. static void transfer_complete(struct r8a66597_ep *ep,
  47. struct r8a66597_request *req, int status);
  48. /*-------------------------------------------------------------------------*/
  49. static inline u16 get_usb_speed(struct r8a66597 *r8a66597)
  50. {
  51. return r8a66597_read(r8a66597, DVSTCTR0) & RHST;
  52. }
  53. static void enable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
  54. unsigned long reg)
  55. {
  56. u16 tmp;
  57. tmp = r8a66597_read(r8a66597, INTENB0);
  58. r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
  59. INTENB0);
  60. r8a66597_bset(r8a66597, (1 << pipenum), reg);
  61. r8a66597_write(r8a66597, tmp, INTENB0);
  62. }
  63. static void disable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
  64. unsigned long reg)
  65. {
  66. u16 tmp;
  67. tmp = r8a66597_read(r8a66597, INTENB0);
  68. r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
  69. INTENB0);
  70. r8a66597_bclr(r8a66597, (1 << pipenum), reg);
  71. r8a66597_write(r8a66597, tmp, INTENB0);
  72. }
  73. static void r8a66597_usb_connect(struct r8a66597 *r8a66597)
  74. {
  75. r8a66597_bset(r8a66597, CTRE, INTENB0);
  76. r8a66597_bset(r8a66597, BEMPE | BRDYE, INTENB0);
  77. r8a66597_bset(r8a66597, DPRPU, SYSCFG0);
  78. }
  79. static void r8a66597_usb_disconnect(struct r8a66597 *r8a66597)
  80. __releases(r8a66597->lock)
  81. __acquires(r8a66597->lock)
  82. {
  83. r8a66597_bclr(r8a66597, CTRE, INTENB0);
  84. r8a66597_bclr(r8a66597, BEMPE | BRDYE, INTENB0);
  85. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  86. r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
  87. spin_unlock(&r8a66597->lock);
  88. r8a66597->driver->disconnect(&r8a66597->gadget);
  89. spin_lock(&r8a66597->lock);
  90. disable_controller(r8a66597);
  91. init_controller(r8a66597);
  92. r8a66597_bset(r8a66597, VBSE, INTENB0);
  93. INIT_LIST_HEAD(&r8a66597->ep[0].queue);
  94. }
  95. static inline u16 control_reg_get_pid(struct r8a66597 *r8a66597, u16 pipenum)
  96. {
  97. u16 pid = 0;
  98. unsigned long offset;
  99. if (pipenum == 0)
  100. pid = r8a66597_read(r8a66597, DCPCTR) & PID;
  101. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  102. offset = get_pipectr_addr(pipenum);
  103. pid = r8a66597_read(r8a66597, offset) & PID;
  104. } else
  105. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  106. return pid;
  107. }
  108. static inline void control_reg_set_pid(struct r8a66597 *r8a66597, u16 pipenum,
  109. u16 pid)
  110. {
  111. unsigned long offset;
  112. if (pipenum == 0)
  113. r8a66597_mdfy(r8a66597, pid, PID, DCPCTR);
  114. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  115. offset = get_pipectr_addr(pipenum);
  116. r8a66597_mdfy(r8a66597, pid, PID, offset);
  117. } else
  118. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  119. }
  120. static inline void pipe_start(struct r8a66597 *r8a66597, u16 pipenum)
  121. {
  122. control_reg_set_pid(r8a66597, pipenum, PID_BUF);
  123. }
  124. static inline void pipe_stop(struct r8a66597 *r8a66597, u16 pipenum)
  125. {
  126. control_reg_set_pid(r8a66597, pipenum, PID_NAK);
  127. }
  128. static inline void pipe_stall(struct r8a66597 *r8a66597, u16 pipenum)
  129. {
  130. control_reg_set_pid(r8a66597, pipenum, PID_STALL);
  131. }
  132. static inline u16 control_reg_get(struct r8a66597 *r8a66597, u16 pipenum)
  133. {
  134. u16 ret = 0;
  135. unsigned long offset;
  136. if (pipenum == 0)
  137. ret = r8a66597_read(r8a66597, DCPCTR);
  138. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  139. offset = get_pipectr_addr(pipenum);
  140. ret = r8a66597_read(r8a66597, offset);
  141. } else
  142. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  143. return ret;
  144. }
  145. static inline void control_reg_sqclr(struct r8a66597 *r8a66597, u16 pipenum)
  146. {
  147. unsigned long offset;
  148. pipe_stop(r8a66597, pipenum);
  149. if (pipenum == 0)
  150. r8a66597_bset(r8a66597, SQCLR, DCPCTR);
  151. else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  152. offset = get_pipectr_addr(pipenum);
  153. r8a66597_bset(r8a66597, SQCLR, offset);
  154. } else
  155. printk(KERN_ERR "unexpect pipe num(%d)\n", pipenum);
  156. }
  157. static inline int get_buffer_size(struct r8a66597 *r8a66597, u16 pipenum)
  158. {
  159. u16 tmp;
  160. int size;
  161. if (pipenum == 0) {
  162. tmp = r8a66597_read(r8a66597, DCPCFG);
  163. if ((tmp & R8A66597_CNTMD) != 0)
  164. size = 256;
  165. else {
  166. tmp = r8a66597_read(r8a66597, DCPMAXP);
  167. size = tmp & MAXP;
  168. }
  169. } else {
  170. r8a66597_write(r8a66597, pipenum, PIPESEL);
  171. tmp = r8a66597_read(r8a66597, PIPECFG);
  172. if ((tmp & R8A66597_CNTMD) != 0) {
  173. tmp = r8a66597_read(r8a66597, PIPEBUF);
  174. size = ((tmp >> 10) + 1) * 64;
  175. } else {
  176. tmp = r8a66597_read(r8a66597, PIPEMAXP);
  177. size = tmp & MXPS;
  178. }
  179. }
  180. return size;
  181. }
  182. static inline unsigned short mbw_value(struct r8a66597 *r8a66597)
  183. {
  184. if (r8a66597->pdata->on_chip)
  185. return MBW_32;
  186. else
  187. return MBW_16;
  188. }
  189. static inline void pipe_change(struct r8a66597 *r8a66597, u16 pipenum)
  190. {
  191. struct r8a66597_ep *ep = r8a66597->pipenum2ep[pipenum];
  192. if (ep->use_dma)
  193. return;
  194. r8a66597_mdfy(r8a66597, pipenum, CURPIPE, ep->fifosel);
  195. ndelay(450);
  196. r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
  197. }
  198. static int pipe_buffer_setting(struct r8a66597 *r8a66597,
  199. struct r8a66597_pipe_info *info)
  200. {
  201. u16 bufnum = 0, buf_bsize = 0;
  202. u16 pipecfg = 0;
  203. if (info->pipe == 0)
  204. return -EINVAL;
  205. r8a66597_write(r8a66597, info->pipe, PIPESEL);
  206. if (info->dir_in)
  207. pipecfg |= R8A66597_DIR;
  208. pipecfg |= info->type;
  209. pipecfg |= info->epnum;
  210. switch (info->type) {
  211. case R8A66597_INT:
  212. bufnum = 4 + (info->pipe - R8A66597_BASE_PIPENUM_INT);
  213. buf_bsize = 0;
  214. break;
  215. case R8A66597_BULK:
  216. /* isochronous pipes may be used as bulk pipes */
  217. if (info->pipe >= R8A66597_BASE_PIPENUM_BULK)
  218. bufnum = info->pipe - R8A66597_BASE_PIPENUM_BULK;
  219. else
  220. bufnum = info->pipe - R8A66597_BASE_PIPENUM_ISOC;
  221. bufnum = R8A66597_BASE_BUFNUM + (bufnum * 16);
  222. buf_bsize = 7;
  223. pipecfg |= R8A66597_DBLB;
  224. if (!info->dir_in)
  225. pipecfg |= R8A66597_SHTNAK;
  226. break;
  227. case R8A66597_ISO:
  228. bufnum = R8A66597_BASE_BUFNUM +
  229. (info->pipe - R8A66597_BASE_PIPENUM_ISOC) * 16;
  230. buf_bsize = 7;
  231. break;
  232. }
  233. if (buf_bsize && ((bufnum + 16) >= R8A66597_MAX_BUFNUM)) {
  234. pr_err("r8a66597 pipe memory is insufficient\n");
  235. return -ENOMEM;
  236. }
  237. r8a66597_write(r8a66597, pipecfg, PIPECFG);
  238. r8a66597_write(r8a66597, (buf_bsize << 10) | (bufnum), PIPEBUF);
  239. r8a66597_write(r8a66597, info->maxpacket, PIPEMAXP);
  240. if (info->interval)
  241. info->interval--;
  242. r8a66597_write(r8a66597, info->interval, PIPEPERI);
  243. return 0;
  244. }
  245. static void pipe_buffer_release(struct r8a66597 *r8a66597,
  246. struct r8a66597_pipe_info *info)
  247. {
  248. if (info->pipe == 0)
  249. return;
  250. if (is_bulk_pipe(info->pipe))
  251. r8a66597->bulk--;
  252. else if (is_interrupt_pipe(info->pipe))
  253. r8a66597->interrupt--;
  254. else if (is_isoc_pipe(info->pipe)) {
  255. r8a66597->isochronous--;
  256. if (info->type == R8A66597_BULK)
  257. r8a66597->bulk--;
  258. } else
  259. printk(KERN_ERR "ep_release: unexpect pipenum (%d)\n",
  260. info->pipe);
  261. }
  262. static void pipe_initialize(struct r8a66597_ep *ep)
  263. {
  264. struct r8a66597 *r8a66597 = ep->r8a66597;
  265. r8a66597_mdfy(r8a66597, 0, CURPIPE, ep->fifosel);
  266. r8a66597_write(r8a66597, ACLRM, ep->pipectr);
  267. r8a66597_write(r8a66597, 0, ep->pipectr);
  268. r8a66597_write(r8a66597, SQCLR, ep->pipectr);
  269. if (ep->use_dma) {
  270. r8a66597_mdfy(r8a66597, ep->pipenum, CURPIPE, ep->fifosel);
  271. ndelay(450);
  272. r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
  273. }
  274. }
  275. static void r8a66597_ep_setting(struct r8a66597 *r8a66597,
  276. struct r8a66597_ep *ep,
  277. const struct usb_endpoint_descriptor *desc,
  278. u16 pipenum, int dma)
  279. {
  280. ep->use_dma = 0;
  281. ep->fifoaddr = CFIFO;
  282. ep->fifosel = CFIFOSEL;
  283. ep->fifoctr = CFIFOCTR;
  284. ep->fifotrn = 0;
  285. ep->pipectr = get_pipectr_addr(pipenum);
  286. ep->pipenum = pipenum;
  287. ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  288. r8a66597->pipenum2ep[pipenum] = ep;
  289. r8a66597->epaddr2ep[desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK]
  290. = ep;
  291. INIT_LIST_HEAD(&ep->queue);
  292. }
  293. static void r8a66597_ep_release(struct r8a66597_ep *ep)
  294. {
  295. struct r8a66597 *r8a66597 = ep->r8a66597;
  296. u16 pipenum = ep->pipenum;
  297. if (pipenum == 0)
  298. return;
  299. if (ep->use_dma)
  300. r8a66597->num_dma--;
  301. ep->pipenum = 0;
  302. ep->busy = 0;
  303. ep->use_dma = 0;
  304. }
  305. static int alloc_pipe_config(struct r8a66597_ep *ep,
  306. const struct usb_endpoint_descriptor *desc)
  307. {
  308. struct r8a66597 *r8a66597 = ep->r8a66597;
  309. struct r8a66597_pipe_info info;
  310. int dma = 0;
  311. unsigned char *counter;
  312. int ret;
  313. ep->desc = desc;
  314. if (ep->pipenum) /* already allocated pipe */
  315. return 0;
  316. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  317. case USB_ENDPOINT_XFER_BULK:
  318. if (r8a66597->bulk >= R8A66597_MAX_NUM_BULK) {
  319. if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
  320. printk(KERN_ERR "bulk pipe is insufficient\n");
  321. return -ENODEV;
  322. } else {
  323. info.pipe = R8A66597_BASE_PIPENUM_ISOC
  324. + r8a66597->isochronous;
  325. counter = &r8a66597->isochronous;
  326. }
  327. } else {
  328. info.pipe = R8A66597_BASE_PIPENUM_BULK + r8a66597->bulk;
  329. counter = &r8a66597->bulk;
  330. }
  331. info.type = R8A66597_BULK;
  332. dma = 1;
  333. break;
  334. case USB_ENDPOINT_XFER_INT:
  335. if (r8a66597->interrupt >= R8A66597_MAX_NUM_INT) {
  336. printk(KERN_ERR "interrupt pipe is insufficient\n");
  337. return -ENODEV;
  338. }
  339. info.pipe = R8A66597_BASE_PIPENUM_INT + r8a66597->interrupt;
  340. info.type = R8A66597_INT;
  341. counter = &r8a66597->interrupt;
  342. break;
  343. case USB_ENDPOINT_XFER_ISOC:
  344. if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
  345. printk(KERN_ERR "isochronous pipe is insufficient\n");
  346. return -ENODEV;
  347. }
  348. info.pipe = R8A66597_BASE_PIPENUM_ISOC + r8a66597->isochronous;
  349. info.type = R8A66597_ISO;
  350. counter = &r8a66597->isochronous;
  351. break;
  352. default:
  353. printk(KERN_ERR "unexpect xfer type\n");
  354. return -EINVAL;
  355. }
  356. ep->type = info.type;
  357. info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  358. info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  359. info.interval = desc->bInterval;
  360. if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
  361. info.dir_in = 1;
  362. else
  363. info.dir_in = 0;
  364. ret = pipe_buffer_setting(r8a66597, &info);
  365. if (ret < 0) {
  366. printk(KERN_ERR "pipe_buffer_setting fail\n");
  367. return ret;
  368. }
  369. (*counter)++;
  370. if ((counter == &r8a66597->isochronous) && info.type == R8A66597_BULK)
  371. r8a66597->bulk++;
  372. r8a66597_ep_setting(r8a66597, ep, desc, info.pipe, dma);
  373. pipe_initialize(ep);
  374. return 0;
  375. }
  376. static int free_pipe_config(struct r8a66597_ep *ep)
  377. {
  378. struct r8a66597 *r8a66597 = ep->r8a66597;
  379. struct r8a66597_pipe_info info;
  380. info.pipe = ep->pipenum;
  381. info.type = ep->type;
  382. pipe_buffer_release(r8a66597, &info);
  383. r8a66597_ep_release(ep);
  384. return 0;
  385. }
  386. /*-------------------------------------------------------------------------*/
  387. static void pipe_irq_enable(struct r8a66597 *r8a66597, u16 pipenum)
  388. {
  389. enable_irq_ready(r8a66597, pipenum);
  390. enable_irq_nrdy(r8a66597, pipenum);
  391. }
  392. static void pipe_irq_disable(struct r8a66597 *r8a66597, u16 pipenum)
  393. {
  394. disable_irq_ready(r8a66597, pipenum);
  395. disable_irq_nrdy(r8a66597, pipenum);
  396. }
  397. /* if complete is true, gadget driver complete function is not call */
  398. static void control_end(struct r8a66597 *r8a66597, unsigned ccpl)
  399. {
  400. r8a66597->ep[0].internal_ccpl = ccpl;
  401. pipe_start(r8a66597, 0);
  402. r8a66597_bset(r8a66597, CCPL, DCPCTR);
  403. }
  404. static void start_ep0_write(struct r8a66597_ep *ep,
  405. struct r8a66597_request *req)
  406. {
  407. struct r8a66597 *r8a66597 = ep->r8a66597;
  408. pipe_change(r8a66597, ep->pipenum);
  409. r8a66597_mdfy(r8a66597, ISEL, (ISEL | CURPIPE), CFIFOSEL);
  410. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  411. if (req->req.length == 0) {
  412. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  413. pipe_start(r8a66597, 0);
  414. transfer_complete(ep, req, 0);
  415. } else {
  416. r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
  417. irq_ep0_write(ep, req);
  418. }
  419. }
  420. static void start_packet_write(struct r8a66597_ep *ep,
  421. struct r8a66597_request *req)
  422. {
  423. struct r8a66597 *r8a66597 = ep->r8a66597;
  424. u16 tmp;
  425. pipe_change(r8a66597, ep->pipenum);
  426. disable_irq_empty(r8a66597, ep->pipenum);
  427. pipe_start(r8a66597, ep->pipenum);
  428. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  429. if (unlikely((tmp & FRDY) == 0))
  430. pipe_irq_enable(r8a66597, ep->pipenum);
  431. else
  432. irq_packet_write(ep, req);
  433. }
  434. static void start_packet_read(struct r8a66597_ep *ep,
  435. struct r8a66597_request *req)
  436. {
  437. struct r8a66597 *r8a66597 = ep->r8a66597;
  438. u16 pipenum = ep->pipenum;
  439. if (ep->pipenum == 0) {
  440. r8a66597_mdfy(r8a66597, 0, (ISEL | CURPIPE), CFIFOSEL);
  441. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  442. pipe_start(r8a66597, pipenum);
  443. pipe_irq_enable(r8a66597, pipenum);
  444. } else {
  445. if (ep->use_dma) {
  446. r8a66597_bset(r8a66597, TRCLR, ep->fifosel);
  447. pipe_change(r8a66597, pipenum);
  448. r8a66597_bset(r8a66597, TRENB, ep->fifosel);
  449. r8a66597_write(r8a66597,
  450. (req->req.length + ep->ep.maxpacket - 1)
  451. / ep->ep.maxpacket,
  452. ep->fifotrn);
  453. }
  454. pipe_start(r8a66597, pipenum); /* trigger once */
  455. pipe_irq_enable(r8a66597, pipenum);
  456. }
  457. }
  458. static void start_packet(struct r8a66597_ep *ep, struct r8a66597_request *req)
  459. {
  460. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  461. start_packet_write(ep, req);
  462. else
  463. start_packet_read(ep, req);
  464. }
  465. static void start_ep0(struct r8a66597_ep *ep, struct r8a66597_request *req)
  466. {
  467. u16 ctsq;
  468. ctsq = r8a66597_read(ep->r8a66597, INTSTS0) & CTSQ;
  469. switch (ctsq) {
  470. case CS_RDDS:
  471. start_ep0_write(ep, req);
  472. break;
  473. case CS_WRDS:
  474. start_packet_read(ep, req);
  475. break;
  476. case CS_WRND:
  477. control_end(ep->r8a66597, 0);
  478. break;
  479. default:
  480. printk(KERN_ERR "start_ep0: unexpect ctsq(%x)\n", ctsq);
  481. break;
  482. }
  483. }
  484. static void init_controller(struct r8a66597 *r8a66597)
  485. {
  486. u16 vif = r8a66597->pdata->vif ? LDRV : 0;
  487. u16 irq_sense = r8a66597->irq_sense_low ? INTL : 0;
  488. u16 endian = r8a66597->pdata->endian ? BIGEND : 0;
  489. if (r8a66597->pdata->on_chip) {
  490. if (r8a66597->pdata->buswait)
  491. r8a66597_write(r8a66597, r8a66597->pdata->buswait,
  492. SYSCFG1);
  493. else
  494. r8a66597_write(r8a66597, 0x0f, SYSCFG1);
  495. r8a66597_bset(r8a66597, HSE, SYSCFG0);
  496. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  497. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  498. r8a66597_bset(r8a66597, USBE, SYSCFG0);
  499. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  500. r8a66597_bset(r8a66597, irq_sense, INTENB1);
  501. r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
  502. DMA0CFG);
  503. } else {
  504. r8a66597_bset(r8a66597, vif | endian, PINCFG);
  505. r8a66597_bset(r8a66597, HSE, SYSCFG0); /* High spd */
  506. r8a66597_mdfy(r8a66597, get_xtal_from_pdata(r8a66597->pdata),
  507. XTAL, SYSCFG0);
  508. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  509. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  510. r8a66597_bset(r8a66597, USBE, SYSCFG0);
  511. r8a66597_bset(r8a66597, XCKE, SYSCFG0);
  512. msleep(3);
  513. r8a66597_bset(r8a66597, PLLC, SYSCFG0);
  514. msleep(1);
  515. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  516. r8a66597_bset(r8a66597, irq_sense, INTENB1);
  517. r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
  518. DMA0CFG);
  519. }
  520. }
  521. static void disable_controller(struct r8a66597 *r8a66597)
  522. {
  523. if (r8a66597->pdata->on_chip) {
  524. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  525. /* disable interrupts */
  526. r8a66597_write(r8a66597, 0, INTENB0);
  527. r8a66597_write(r8a66597, 0, INTENB1);
  528. r8a66597_write(r8a66597, 0, BRDYENB);
  529. r8a66597_write(r8a66597, 0, BEMPENB);
  530. r8a66597_write(r8a66597, 0, NRDYENB);
  531. /* clear status */
  532. r8a66597_write(r8a66597, 0, BRDYSTS);
  533. r8a66597_write(r8a66597, 0, NRDYSTS);
  534. r8a66597_write(r8a66597, 0, BEMPSTS);
  535. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  536. r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
  537. } else {
  538. r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
  539. udelay(1);
  540. r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
  541. udelay(1);
  542. udelay(1);
  543. r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
  544. }
  545. }
  546. static void r8a66597_start_xclock(struct r8a66597 *r8a66597)
  547. {
  548. u16 tmp;
  549. if (!r8a66597->pdata->on_chip) {
  550. tmp = r8a66597_read(r8a66597, SYSCFG0);
  551. if (!(tmp & XCKE))
  552. r8a66597_bset(r8a66597, XCKE, SYSCFG0);
  553. }
  554. }
  555. static struct r8a66597_request *get_request_from_ep(struct r8a66597_ep *ep)
  556. {
  557. return list_entry(ep->queue.next, struct r8a66597_request, queue);
  558. }
  559. /*-------------------------------------------------------------------------*/
  560. static void transfer_complete(struct r8a66597_ep *ep,
  561. struct r8a66597_request *req, int status)
  562. __releases(r8a66597->lock)
  563. __acquires(r8a66597->lock)
  564. {
  565. int restart = 0;
  566. if (unlikely(ep->pipenum == 0)) {
  567. if (ep->internal_ccpl) {
  568. ep->internal_ccpl = 0;
  569. return;
  570. }
  571. }
  572. list_del_init(&req->queue);
  573. if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  574. req->req.status = -ESHUTDOWN;
  575. else
  576. req->req.status = status;
  577. if (!list_empty(&ep->queue))
  578. restart = 1;
  579. spin_unlock(&ep->r8a66597->lock);
  580. req->req.complete(&ep->ep, &req->req);
  581. spin_lock(&ep->r8a66597->lock);
  582. if (restart) {
  583. req = get_request_from_ep(ep);
  584. if (ep->desc)
  585. start_packet(ep, req);
  586. }
  587. }
  588. static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req)
  589. {
  590. int i;
  591. u16 tmp;
  592. unsigned bufsize;
  593. size_t size;
  594. void *buf;
  595. u16 pipenum = ep->pipenum;
  596. struct r8a66597 *r8a66597 = ep->r8a66597;
  597. pipe_change(r8a66597, pipenum);
  598. r8a66597_bset(r8a66597, ISEL, ep->fifosel);
  599. i = 0;
  600. do {
  601. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  602. if (i++ > 100000) {
  603. printk(KERN_ERR "pipe0 is busy. maybe cpu i/o bus"
  604. "conflict. please power off this controller.");
  605. return;
  606. }
  607. ndelay(1);
  608. } while ((tmp & FRDY) == 0);
  609. /* prepare parameters */
  610. bufsize = get_buffer_size(r8a66597, pipenum);
  611. buf = req->req.buf + req->req.actual;
  612. size = min(bufsize, req->req.length - req->req.actual);
  613. /* write fifo */
  614. if (req->req.buf) {
  615. if (size > 0)
  616. r8a66597_write_fifo(r8a66597, ep->fifoaddr, buf, size);
  617. if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
  618. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  619. }
  620. /* update parameters */
  621. req->req.actual += size;
  622. /* check transfer finish */
  623. if ((!req->req.zero && (req->req.actual == req->req.length))
  624. || (size % ep->ep.maxpacket)
  625. || (size == 0)) {
  626. disable_irq_ready(r8a66597, pipenum);
  627. disable_irq_empty(r8a66597, pipenum);
  628. } else {
  629. disable_irq_ready(r8a66597, pipenum);
  630. enable_irq_empty(r8a66597, pipenum);
  631. }
  632. pipe_start(r8a66597, pipenum);
  633. }
  634. static void irq_packet_write(struct r8a66597_ep *ep,
  635. struct r8a66597_request *req)
  636. {
  637. u16 tmp;
  638. unsigned bufsize;
  639. size_t size;
  640. void *buf;
  641. u16 pipenum = ep->pipenum;
  642. struct r8a66597 *r8a66597 = ep->r8a66597;
  643. pipe_change(r8a66597, pipenum);
  644. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  645. if (unlikely((tmp & FRDY) == 0)) {
  646. pipe_stop(r8a66597, pipenum);
  647. pipe_irq_disable(r8a66597, pipenum);
  648. printk(KERN_ERR "write fifo not ready. pipnum=%d\n", pipenum);
  649. return;
  650. }
  651. /* prepare parameters */
  652. bufsize = get_buffer_size(r8a66597, pipenum);
  653. buf = req->req.buf + req->req.actual;
  654. size = min(bufsize, req->req.length - req->req.actual);
  655. /* write fifo */
  656. if (req->req.buf) {
  657. r8a66597_write_fifo(r8a66597, ep->fifoaddr, buf, size);
  658. if ((size == 0)
  659. || ((size % ep->ep.maxpacket) != 0)
  660. || ((bufsize != ep->ep.maxpacket)
  661. && (bufsize > size)))
  662. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  663. }
  664. /* update parameters */
  665. req->req.actual += size;
  666. /* check transfer finish */
  667. if ((!req->req.zero && (req->req.actual == req->req.length))
  668. || (size % ep->ep.maxpacket)
  669. || (size == 0)) {
  670. disable_irq_ready(r8a66597, pipenum);
  671. enable_irq_empty(r8a66597, pipenum);
  672. } else {
  673. disable_irq_empty(r8a66597, pipenum);
  674. pipe_irq_enable(r8a66597, pipenum);
  675. }
  676. }
  677. static void irq_packet_read(struct r8a66597_ep *ep,
  678. struct r8a66597_request *req)
  679. {
  680. u16 tmp;
  681. int rcv_len, bufsize, req_len;
  682. int size;
  683. void *buf;
  684. u16 pipenum = ep->pipenum;
  685. struct r8a66597 *r8a66597 = ep->r8a66597;
  686. int finish = 0;
  687. pipe_change(r8a66597, pipenum);
  688. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  689. if (unlikely((tmp & FRDY) == 0)) {
  690. req->req.status = -EPIPE;
  691. pipe_stop(r8a66597, pipenum);
  692. pipe_irq_disable(r8a66597, pipenum);
  693. printk(KERN_ERR "read fifo not ready");
  694. return;
  695. }
  696. /* prepare parameters */
  697. rcv_len = tmp & DTLN;
  698. bufsize = get_buffer_size(r8a66597, pipenum);
  699. buf = req->req.buf + req->req.actual;
  700. req_len = req->req.length - req->req.actual;
  701. if (rcv_len < bufsize)
  702. size = min(rcv_len, req_len);
  703. else
  704. size = min(bufsize, req_len);
  705. /* update parameters */
  706. req->req.actual += size;
  707. /* check transfer finish */
  708. if ((!req->req.zero && (req->req.actual == req->req.length))
  709. || (size % ep->ep.maxpacket)
  710. || (size == 0)) {
  711. pipe_stop(r8a66597, pipenum);
  712. pipe_irq_disable(r8a66597, pipenum);
  713. finish = 1;
  714. }
  715. /* read fifo */
  716. if (req->req.buf) {
  717. if (size == 0)
  718. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  719. else
  720. r8a66597_read_fifo(r8a66597, ep->fifoaddr, buf, size);
  721. }
  722. if ((ep->pipenum != 0) && finish)
  723. transfer_complete(ep, req, 0);
  724. }
  725. static void irq_pipe_ready(struct r8a66597 *r8a66597, u16 status, u16 enb)
  726. {
  727. u16 check;
  728. u16 pipenum;
  729. struct r8a66597_ep *ep;
  730. struct r8a66597_request *req;
  731. if ((status & BRDY0) && (enb & BRDY0)) {
  732. r8a66597_write(r8a66597, ~BRDY0, BRDYSTS);
  733. r8a66597_mdfy(r8a66597, 0, CURPIPE, CFIFOSEL);
  734. ep = &r8a66597->ep[0];
  735. req = get_request_from_ep(ep);
  736. irq_packet_read(ep, req);
  737. } else {
  738. for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
  739. check = 1 << pipenum;
  740. if ((status & check) && (enb & check)) {
  741. r8a66597_write(r8a66597, ~check, BRDYSTS);
  742. ep = r8a66597->pipenum2ep[pipenum];
  743. req = get_request_from_ep(ep);
  744. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  745. irq_packet_write(ep, req);
  746. else
  747. irq_packet_read(ep, req);
  748. }
  749. }
  750. }
  751. }
  752. static void irq_pipe_empty(struct r8a66597 *r8a66597, u16 status, u16 enb)
  753. {
  754. u16 tmp;
  755. u16 check;
  756. u16 pipenum;
  757. struct r8a66597_ep *ep;
  758. struct r8a66597_request *req;
  759. if ((status & BEMP0) && (enb & BEMP0)) {
  760. r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
  761. ep = &r8a66597->ep[0];
  762. req = get_request_from_ep(ep);
  763. irq_ep0_write(ep, req);
  764. } else {
  765. for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
  766. check = 1 << pipenum;
  767. if ((status & check) && (enb & check)) {
  768. r8a66597_write(r8a66597, ~check, BEMPSTS);
  769. tmp = control_reg_get(r8a66597, pipenum);
  770. if ((tmp & INBUFM) == 0) {
  771. disable_irq_empty(r8a66597, pipenum);
  772. pipe_irq_disable(r8a66597, pipenum);
  773. pipe_stop(r8a66597, pipenum);
  774. ep = r8a66597->pipenum2ep[pipenum];
  775. req = get_request_from_ep(ep);
  776. if (!list_empty(&ep->queue))
  777. transfer_complete(ep, req, 0);
  778. }
  779. }
  780. }
  781. }
  782. }
  783. static void get_status(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  784. __releases(r8a66597->lock)
  785. __acquires(r8a66597->lock)
  786. {
  787. struct r8a66597_ep *ep;
  788. u16 pid;
  789. u16 status = 0;
  790. u16 w_index = le16_to_cpu(ctrl->wIndex);
  791. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  792. case USB_RECIP_DEVICE:
  793. status = 1 << USB_DEVICE_SELF_POWERED;
  794. break;
  795. case USB_RECIP_INTERFACE:
  796. status = 0;
  797. break;
  798. case USB_RECIP_ENDPOINT:
  799. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  800. pid = control_reg_get_pid(r8a66597, ep->pipenum);
  801. if (pid == PID_STALL)
  802. status = 1 << USB_ENDPOINT_HALT;
  803. else
  804. status = 0;
  805. break;
  806. default:
  807. pipe_stall(r8a66597, 0);
  808. return; /* exit */
  809. }
  810. r8a66597->ep0_data = cpu_to_le16(status);
  811. r8a66597->ep0_req->buf = &r8a66597->ep0_data;
  812. r8a66597->ep0_req->length = 2;
  813. /* AV: what happens if we get called again before that gets through? */
  814. spin_unlock(&r8a66597->lock);
  815. r8a66597_queue(r8a66597->gadget.ep0, r8a66597->ep0_req, GFP_KERNEL);
  816. spin_lock(&r8a66597->lock);
  817. }
  818. static void clear_feature(struct r8a66597 *r8a66597,
  819. struct usb_ctrlrequest *ctrl)
  820. {
  821. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  822. case USB_RECIP_DEVICE:
  823. control_end(r8a66597, 1);
  824. break;
  825. case USB_RECIP_INTERFACE:
  826. control_end(r8a66597, 1);
  827. break;
  828. case USB_RECIP_ENDPOINT: {
  829. struct r8a66597_ep *ep;
  830. struct r8a66597_request *req;
  831. u16 w_index = le16_to_cpu(ctrl->wIndex);
  832. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  833. if (!ep->wedge) {
  834. pipe_stop(r8a66597, ep->pipenum);
  835. control_reg_sqclr(r8a66597, ep->pipenum);
  836. spin_unlock(&r8a66597->lock);
  837. usb_ep_clear_halt(&ep->ep);
  838. spin_lock(&r8a66597->lock);
  839. }
  840. control_end(r8a66597, 1);
  841. req = get_request_from_ep(ep);
  842. if (ep->busy) {
  843. ep->busy = 0;
  844. if (list_empty(&ep->queue))
  845. break;
  846. start_packet(ep, req);
  847. } else if (!list_empty(&ep->queue))
  848. pipe_start(r8a66597, ep->pipenum);
  849. }
  850. break;
  851. default:
  852. pipe_stall(r8a66597, 0);
  853. break;
  854. }
  855. }
  856. static void set_feature(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  857. {
  858. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  859. case USB_RECIP_DEVICE:
  860. control_end(r8a66597, 1);
  861. break;
  862. case USB_RECIP_INTERFACE:
  863. control_end(r8a66597, 1);
  864. break;
  865. case USB_RECIP_ENDPOINT: {
  866. struct r8a66597_ep *ep;
  867. u16 w_index = le16_to_cpu(ctrl->wIndex);
  868. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  869. pipe_stall(r8a66597, ep->pipenum);
  870. control_end(r8a66597, 1);
  871. }
  872. break;
  873. default:
  874. pipe_stall(r8a66597, 0);
  875. break;
  876. }
  877. }
  878. /* if return value is true, call class driver's setup() */
  879. static int setup_packet(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  880. {
  881. u16 *p = (u16 *)ctrl;
  882. unsigned long offset = USBREQ;
  883. int i, ret = 0;
  884. /* read fifo */
  885. r8a66597_write(r8a66597, ~VALID, INTSTS0);
  886. for (i = 0; i < 4; i++)
  887. p[i] = r8a66597_read(r8a66597, offset + i*2);
  888. /* check request */
  889. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  890. switch (ctrl->bRequest) {
  891. case USB_REQ_GET_STATUS:
  892. get_status(r8a66597, ctrl);
  893. break;
  894. case USB_REQ_CLEAR_FEATURE:
  895. clear_feature(r8a66597, ctrl);
  896. break;
  897. case USB_REQ_SET_FEATURE:
  898. set_feature(r8a66597, ctrl);
  899. break;
  900. default:
  901. ret = 1;
  902. break;
  903. }
  904. } else
  905. ret = 1;
  906. return ret;
  907. }
  908. static void r8a66597_update_usb_speed(struct r8a66597 *r8a66597)
  909. {
  910. u16 speed = get_usb_speed(r8a66597);
  911. switch (speed) {
  912. case HSMODE:
  913. r8a66597->gadget.speed = USB_SPEED_HIGH;
  914. break;
  915. case FSMODE:
  916. r8a66597->gadget.speed = USB_SPEED_FULL;
  917. break;
  918. default:
  919. r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
  920. printk(KERN_ERR "USB speed unknown\n");
  921. }
  922. }
  923. static void irq_device_state(struct r8a66597 *r8a66597)
  924. {
  925. u16 dvsq;
  926. dvsq = r8a66597_read(r8a66597, INTSTS0) & DVSQ;
  927. r8a66597_write(r8a66597, ~DVST, INTSTS0);
  928. if (dvsq == DS_DFLT) {
  929. /* bus reset */
  930. spin_unlock(&r8a66597->lock);
  931. r8a66597->driver->disconnect(&r8a66597->gadget);
  932. spin_lock(&r8a66597->lock);
  933. r8a66597_update_usb_speed(r8a66597);
  934. }
  935. if (r8a66597->old_dvsq == DS_CNFG && dvsq != DS_CNFG)
  936. r8a66597_update_usb_speed(r8a66597);
  937. if ((dvsq == DS_CNFG || dvsq == DS_ADDS)
  938. && r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  939. r8a66597_update_usb_speed(r8a66597);
  940. r8a66597->old_dvsq = dvsq;
  941. }
  942. static void irq_control_stage(struct r8a66597 *r8a66597)
  943. __releases(r8a66597->lock)
  944. __acquires(r8a66597->lock)
  945. {
  946. struct usb_ctrlrequest ctrl;
  947. u16 ctsq;
  948. ctsq = r8a66597_read(r8a66597, INTSTS0) & CTSQ;
  949. r8a66597_write(r8a66597, ~CTRT, INTSTS0);
  950. switch (ctsq) {
  951. case CS_IDST: {
  952. struct r8a66597_ep *ep;
  953. struct r8a66597_request *req;
  954. ep = &r8a66597->ep[0];
  955. req = get_request_from_ep(ep);
  956. transfer_complete(ep, req, 0);
  957. }
  958. break;
  959. case CS_RDDS:
  960. case CS_WRDS:
  961. case CS_WRND:
  962. if (setup_packet(r8a66597, &ctrl)) {
  963. spin_unlock(&r8a66597->lock);
  964. if (r8a66597->driver->setup(&r8a66597->gadget, &ctrl)
  965. < 0)
  966. pipe_stall(r8a66597, 0);
  967. spin_lock(&r8a66597->lock);
  968. }
  969. break;
  970. case CS_RDSS:
  971. case CS_WRSS:
  972. control_end(r8a66597, 0);
  973. break;
  974. default:
  975. printk(KERN_ERR "ctrl_stage: unexpect ctsq(%x)\n", ctsq);
  976. break;
  977. }
  978. }
  979. static irqreturn_t r8a66597_irq(int irq, void *_r8a66597)
  980. {
  981. struct r8a66597 *r8a66597 = _r8a66597;
  982. u16 intsts0;
  983. u16 intenb0;
  984. u16 brdysts, nrdysts, bempsts;
  985. u16 brdyenb, nrdyenb, bempenb;
  986. u16 savepipe;
  987. u16 mask0;
  988. spin_lock(&r8a66597->lock);
  989. intsts0 = r8a66597_read(r8a66597, INTSTS0);
  990. intenb0 = r8a66597_read(r8a66597, INTENB0);
  991. savepipe = r8a66597_read(r8a66597, CFIFOSEL);
  992. mask0 = intsts0 & intenb0;
  993. if (mask0) {
  994. brdysts = r8a66597_read(r8a66597, BRDYSTS);
  995. nrdysts = r8a66597_read(r8a66597, NRDYSTS);
  996. bempsts = r8a66597_read(r8a66597, BEMPSTS);
  997. brdyenb = r8a66597_read(r8a66597, BRDYENB);
  998. nrdyenb = r8a66597_read(r8a66597, NRDYENB);
  999. bempenb = r8a66597_read(r8a66597, BEMPENB);
  1000. if (mask0 & VBINT) {
  1001. r8a66597_write(r8a66597, 0xffff & ~VBINT,
  1002. INTSTS0);
  1003. r8a66597_start_xclock(r8a66597);
  1004. /* start vbus sampling */
  1005. r8a66597->old_vbus = r8a66597_read(r8a66597, INTSTS0)
  1006. & VBSTS;
  1007. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1008. mod_timer(&r8a66597->timer,
  1009. jiffies + msecs_to_jiffies(50));
  1010. }
  1011. if (intsts0 & DVSQ)
  1012. irq_device_state(r8a66597);
  1013. if ((intsts0 & BRDY) && (intenb0 & BRDYE)
  1014. && (brdysts & brdyenb))
  1015. irq_pipe_ready(r8a66597, brdysts, brdyenb);
  1016. if ((intsts0 & BEMP) && (intenb0 & BEMPE)
  1017. && (bempsts & bempenb))
  1018. irq_pipe_empty(r8a66597, bempsts, bempenb);
  1019. if (intsts0 & CTRT)
  1020. irq_control_stage(r8a66597);
  1021. }
  1022. r8a66597_write(r8a66597, savepipe, CFIFOSEL);
  1023. spin_unlock(&r8a66597->lock);
  1024. return IRQ_HANDLED;
  1025. }
  1026. static void r8a66597_timer(unsigned long _r8a66597)
  1027. {
  1028. struct r8a66597 *r8a66597 = (struct r8a66597 *)_r8a66597;
  1029. unsigned long flags;
  1030. u16 tmp;
  1031. spin_lock_irqsave(&r8a66597->lock, flags);
  1032. tmp = r8a66597_read(r8a66597, SYSCFG0);
  1033. if (r8a66597->scount > 0) {
  1034. tmp = r8a66597_read(r8a66597, INTSTS0) & VBSTS;
  1035. if (tmp == r8a66597->old_vbus) {
  1036. r8a66597->scount--;
  1037. if (r8a66597->scount == 0) {
  1038. if (tmp == VBSTS)
  1039. r8a66597_usb_connect(r8a66597);
  1040. else
  1041. r8a66597_usb_disconnect(r8a66597);
  1042. } else {
  1043. mod_timer(&r8a66597->timer,
  1044. jiffies + msecs_to_jiffies(50));
  1045. }
  1046. } else {
  1047. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1048. r8a66597->old_vbus = tmp;
  1049. mod_timer(&r8a66597->timer,
  1050. jiffies + msecs_to_jiffies(50));
  1051. }
  1052. }
  1053. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1054. }
  1055. /*-------------------------------------------------------------------------*/
  1056. static int r8a66597_enable(struct usb_ep *_ep,
  1057. const struct usb_endpoint_descriptor *desc)
  1058. {
  1059. struct r8a66597_ep *ep;
  1060. ep = container_of(_ep, struct r8a66597_ep, ep);
  1061. return alloc_pipe_config(ep, desc);
  1062. }
  1063. static int r8a66597_disable(struct usb_ep *_ep)
  1064. {
  1065. struct r8a66597_ep *ep;
  1066. struct r8a66597_request *req;
  1067. unsigned long flags;
  1068. ep = container_of(_ep, struct r8a66597_ep, ep);
  1069. BUG_ON(!ep);
  1070. while (!list_empty(&ep->queue)) {
  1071. req = get_request_from_ep(ep);
  1072. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1073. transfer_complete(ep, req, -ECONNRESET);
  1074. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1075. }
  1076. pipe_irq_disable(ep->r8a66597, ep->pipenum);
  1077. return free_pipe_config(ep);
  1078. }
  1079. static struct usb_request *r8a66597_alloc_request(struct usb_ep *_ep,
  1080. gfp_t gfp_flags)
  1081. {
  1082. struct r8a66597_request *req;
  1083. req = kzalloc(sizeof(struct r8a66597_request), gfp_flags);
  1084. if (!req)
  1085. return NULL;
  1086. INIT_LIST_HEAD(&req->queue);
  1087. return &req->req;
  1088. }
  1089. static void r8a66597_free_request(struct usb_ep *_ep, struct usb_request *_req)
  1090. {
  1091. struct r8a66597_request *req;
  1092. req = container_of(_req, struct r8a66597_request, req);
  1093. kfree(req);
  1094. }
  1095. static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
  1096. gfp_t gfp_flags)
  1097. {
  1098. struct r8a66597_ep *ep;
  1099. struct r8a66597_request *req;
  1100. unsigned long flags;
  1101. int request = 0;
  1102. ep = container_of(_ep, struct r8a66597_ep, ep);
  1103. req = container_of(_req, struct r8a66597_request, req);
  1104. if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  1105. return -ESHUTDOWN;
  1106. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1107. if (list_empty(&ep->queue))
  1108. request = 1;
  1109. list_add_tail(&req->queue, &ep->queue);
  1110. req->req.actual = 0;
  1111. req->req.status = -EINPROGRESS;
  1112. if (ep->desc == NULL) /* control */
  1113. start_ep0(ep, req);
  1114. else {
  1115. if (request && !ep->busy)
  1116. start_packet(ep, req);
  1117. }
  1118. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1119. return 0;
  1120. }
  1121. static int r8a66597_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1122. {
  1123. struct r8a66597_ep *ep;
  1124. struct r8a66597_request *req;
  1125. unsigned long flags;
  1126. ep = container_of(_ep, struct r8a66597_ep, ep);
  1127. req = container_of(_req, struct r8a66597_request, req);
  1128. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1129. if (!list_empty(&ep->queue))
  1130. transfer_complete(ep, req, -ECONNRESET);
  1131. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1132. return 0;
  1133. }
  1134. static int r8a66597_set_halt(struct usb_ep *_ep, int value)
  1135. {
  1136. struct r8a66597_ep *ep;
  1137. struct r8a66597_request *req;
  1138. unsigned long flags;
  1139. int ret = 0;
  1140. ep = container_of(_ep, struct r8a66597_ep, ep);
  1141. req = get_request_from_ep(ep);
  1142. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1143. if (!list_empty(&ep->queue)) {
  1144. ret = -EAGAIN;
  1145. goto out;
  1146. }
  1147. if (value) {
  1148. ep->busy = 1;
  1149. pipe_stall(ep->r8a66597, ep->pipenum);
  1150. } else {
  1151. ep->busy = 0;
  1152. ep->wedge = 0;
  1153. pipe_stop(ep->r8a66597, ep->pipenum);
  1154. }
  1155. out:
  1156. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1157. return ret;
  1158. }
  1159. static int r8a66597_set_wedge(struct usb_ep *_ep)
  1160. {
  1161. struct r8a66597_ep *ep;
  1162. unsigned long flags;
  1163. ep = container_of(_ep, struct r8a66597_ep, ep);
  1164. if (!ep || !ep->desc)
  1165. return -EINVAL;
  1166. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1167. ep->wedge = 1;
  1168. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1169. return usb_ep_set_halt(_ep);
  1170. }
  1171. static void r8a66597_fifo_flush(struct usb_ep *_ep)
  1172. {
  1173. struct r8a66597_ep *ep;
  1174. unsigned long flags;
  1175. ep = container_of(_ep, struct r8a66597_ep, ep);
  1176. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1177. if (list_empty(&ep->queue) && !ep->busy) {
  1178. pipe_stop(ep->r8a66597, ep->pipenum);
  1179. r8a66597_bclr(ep->r8a66597, BCLR, ep->fifoctr);
  1180. }
  1181. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1182. }
  1183. static struct usb_ep_ops r8a66597_ep_ops = {
  1184. .enable = r8a66597_enable,
  1185. .disable = r8a66597_disable,
  1186. .alloc_request = r8a66597_alloc_request,
  1187. .free_request = r8a66597_free_request,
  1188. .queue = r8a66597_queue,
  1189. .dequeue = r8a66597_dequeue,
  1190. .set_halt = r8a66597_set_halt,
  1191. .set_wedge = r8a66597_set_wedge,
  1192. .fifo_flush = r8a66597_fifo_flush,
  1193. };
  1194. /*-------------------------------------------------------------------------*/
  1195. static struct r8a66597 *the_controller;
  1196. static int r8a66597_start(struct usb_gadget_driver *driver,
  1197. int (*bind)(struct usb_gadget *))
  1198. {
  1199. struct r8a66597 *r8a66597 = the_controller;
  1200. int retval;
  1201. if (!driver
  1202. || driver->speed != USB_SPEED_HIGH
  1203. || !bind
  1204. || !driver->setup)
  1205. return -EINVAL;
  1206. if (!r8a66597)
  1207. return -ENODEV;
  1208. if (r8a66597->driver)
  1209. return -EBUSY;
  1210. /* hook up the driver */
  1211. driver->driver.bus = NULL;
  1212. r8a66597->driver = driver;
  1213. r8a66597->gadget.dev.driver = &driver->driver;
  1214. retval = device_add(&r8a66597->gadget.dev);
  1215. if (retval) {
  1216. printk(KERN_ERR "device_add error (%d)\n", retval);
  1217. goto error;
  1218. }
  1219. retval = bind(&r8a66597->gadget);
  1220. if (retval) {
  1221. printk(KERN_ERR "bind to driver error (%d)\n", retval);
  1222. device_del(&r8a66597->gadget.dev);
  1223. goto error;
  1224. }
  1225. init_controller(r8a66597);
  1226. r8a66597_bset(r8a66597, VBSE, INTENB0);
  1227. if (r8a66597_read(r8a66597, INTSTS0) & VBSTS) {
  1228. r8a66597_start_xclock(r8a66597);
  1229. /* start vbus sampling */
  1230. r8a66597->old_vbus = r8a66597_read(r8a66597,
  1231. INTSTS0) & VBSTS;
  1232. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1233. mod_timer(&r8a66597->timer, jiffies + msecs_to_jiffies(50));
  1234. }
  1235. return 0;
  1236. error:
  1237. r8a66597->driver = NULL;
  1238. r8a66597->gadget.dev.driver = NULL;
  1239. return retval;
  1240. }
  1241. static int r8a66597_stop(struct usb_gadget_driver *driver)
  1242. {
  1243. struct r8a66597 *r8a66597 = the_controller;
  1244. unsigned long flags;
  1245. if (driver != r8a66597->driver || !driver->unbind)
  1246. return -EINVAL;
  1247. spin_lock_irqsave(&r8a66597->lock, flags);
  1248. if (r8a66597->gadget.speed != USB_SPEED_UNKNOWN)
  1249. r8a66597_usb_disconnect(r8a66597);
  1250. r8a66597_bclr(r8a66597, VBSE, INTENB0);
  1251. disable_controller(r8a66597);
  1252. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1253. driver->unbind(&r8a66597->gadget);
  1254. device_del(&r8a66597->gadget.dev);
  1255. r8a66597->driver = NULL;
  1256. return 0;
  1257. }
  1258. /*-------------------------------------------------------------------------*/
  1259. static int r8a66597_get_frame(struct usb_gadget *_gadget)
  1260. {
  1261. struct r8a66597 *r8a66597 = gadget_to_r8a66597(_gadget);
  1262. return r8a66597_read(r8a66597, FRMNUM) & 0x03FF;
  1263. }
  1264. static struct usb_gadget_ops r8a66597_gadget_ops = {
  1265. .get_frame = r8a66597_get_frame,
  1266. .start = r8a66597_start,
  1267. .stop = r8a66597_stop,
  1268. };
  1269. static int __exit r8a66597_remove(struct platform_device *pdev)
  1270. {
  1271. struct r8a66597 *r8a66597 = dev_get_drvdata(&pdev->dev);
  1272. usb_del_gadget_udc(&r8a66597->gadget);
  1273. del_timer_sync(&r8a66597->timer);
  1274. iounmap(r8a66597->reg);
  1275. free_irq(platform_get_irq(pdev, 0), r8a66597);
  1276. r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
  1277. #ifdef CONFIG_HAVE_CLK
  1278. if (r8a66597->pdata->on_chip) {
  1279. clk_disable(r8a66597->clk);
  1280. clk_put(r8a66597->clk);
  1281. }
  1282. #endif
  1283. kfree(r8a66597);
  1284. return 0;
  1285. }
  1286. static void nop_completion(struct usb_ep *ep, struct usb_request *r)
  1287. {
  1288. }
  1289. static int __init r8a66597_probe(struct platform_device *pdev)
  1290. {
  1291. #ifdef CONFIG_HAVE_CLK
  1292. char clk_name[8];
  1293. #endif
  1294. struct resource *res, *ires;
  1295. int irq;
  1296. void __iomem *reg = NULL;
  1297. struct r8a66597 *r8a66597 = NULL;
  1298. int ret = 0;
  1299. int i;
  1300. unsigned long irq_trigger;
  1301. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1302. if (!res) {
  1303. ret = -ENODEV;
  1304. printk(KERN_ERR "platform_get_resource error.\n");
  1305. goto clean_up;
  1306. }
  1307. ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1308. irq = ires->start;
  1309. irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
  1310. if (irq < 0) {
  1311. ret = -ENODEV;
  1312. printk(KERN_ERR "platform_get_irq error.\n");
  1313. goto clean_up;
  1314. }
  1315. reg = ioremap(res->start, resource_size(res));
  1316. if (reg == NULL) {
  1317. ret = -ENOMEM;
  1318. printk(KERN_ERR "ioremap error.\n");
  1319. goto clean_up;
  1320. }
  1321. /* initialize ucd */
  1322. r8a66597 = kzalloc(sizeof(struct r8a66597), GFP_KERNEL);
  1323. if (r8a66597 == NULL) {
  1324. ret = -ENOMEM;
  1325. printk(KERN_ERR "kzalloc error\n");
  1326. goto clean_up;
  1327. }
  1328. spin_lock_init(&r8a66597->lock);
  1329. dev_set_drvdata(&pdev->dev, r8a66597);
  1330. r8a66597->pdata = pdev->dev.platform_data;
  1331. r8a66597->irq_sense_low = irq_trigger == IRQF_TRIGGER_LOW;
  1332. r8a66597->gadget.ops = &r8a66597_gadget_ops;
  1333. device_initialize(&r8a66597->gadget.dev);
  1334. dev_set_name(&r8a66597->gadget.dev, "gadget");
  1335. r8a66597->gadget.is_dualspeed = 1;
  1336. r8a66597->gadget.dev.parent = &pdev->dev;
  1337. r8a66597->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1338. r8a66597->gadget.dev.release = pdev->dev.release;
  1339. r8a66597->gadget.name = udc_name;
  1340. init_timer(&r8a66597->timer);
  1341. r8a66597->timer.function = r8a66597_timer;
  1342. r8a66597->timer.data = (unsigned long)r8a66597;
  1343. r8a66597->reg = reg;
  1344. #ifdef CONFIG_HAVE_CLK
  1345. if (r8a66597->pdata->on_chip) {
  1346. snprintf(clk_name, sizeof(clk_name), "usb%d", pdev->id);
  1347. r8a66597->clk = clk_get(&pdev->dev, clk_name);
  1348. if (IS_ERR(r8a66597->clk)) {
  1349. dev_err(&pdev->dev, "cannot get clock \"%s\"\n",
  1350. clk_name);
  1351. ret = PTR_ERR(r8a66597->clk);
  1352. goto clean_up;
  1353. }
  1354. clk_enable(r8a66597->clk);
  1355. }
  1356. #endif
  1357. disable_controller(r8a66597); /* make sure controller is disabled */
  1358. ret = request_irq(irq, r8a66597_irq, IRQF_DISABLED | IRQF_SHARED,
  1359. udc_name, r8a66597);
  1360. if (ret < 0) {
  1361. printk(KERN_ERR "request_irq error (%d)\n", ret);
  1362. goto clean_up2;
  1363. }
  1364. INIT_LIST_HEAD(&r8a66597->gadget.ep_list);
  1365. r8a66597->gadget.ep0 = &r8a66597->ep[0].ep;
  1366. INIT_LIST_HEAD(&r8a66597->gadget.ep0->ep_list);
  1367. for (i = 0; i < R8A66597_MAX_NUM_PIPE; i++) {
  1368. struct r8a66597_ep *ep = &r8a66597->ep[i];
  1369. if (i != 0) {
  1370. INIT_LIST_HEAD(&r8a66597->ep[i].ep.ep_list);
  1371. list_add_tail(&r8a66597->ep[i].ep.ep_list,
  1372. &r8a66597->gadget.ep_list);
  1373. }
  1374. ep->r8a66597 = r8a66597;
  1375. INIT_LIST_HEAD(&ep->queue);
  1376. ep->ep.name = r8a66597_ep_name[i];
  1377. ep->ep.ops = &r8a66597_ep_ops;
  1378. ep->ep.maxpacket = 512;
  1379. }
  1380. r8a66597->ep[0].ep.maxpacket = 64;
  1381. r8a66597->ep[0].pipenum = 0;
  1382. r8a66597->ep[0].fifoaddr = CFIFO;
  1383. r8a66597->ep[0].fifosel = CFIFOSEL;
  1384. r8a66597->ep[0].fifoctr = CFIFOCTR;
  1385. r8a66597->ep[0].fifotrn = 0;
  1386. r8a66597->ep[0].pipectr = get_pipectr_addr(0);
  1387. r8a66597->pipenum2ep[0] = &r8a66597->ep[0];
  1388. r8a66597->epaddr2ep[0] = &r8a66597->ep[0];
  1389. the_controller = r8a66597;
  1390. r8a66597->ep0_req = r8a66597_alloc_request(&r8a66597->ep[0].ep,
  1391. GFP_KERNEL);
  1392. if (r8a66597->ep0_req == NULL)
  1393. goto clean_up3;
  1394. r8a66597->ep0_req->complete = nop_completion;
  1395. ret = usb_add_gadget_udc(&pdev->dev, &r8a66597->gadget);
  1396. if (ret)
  1397. goto err_add_udc;
  1398. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  1399. return 0;
  1400. err_add_udc:
  1401. r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
  1402. clean_up3:
  1403. free_irq(irq, r8a66597);
  1404. clean_up2:
  1405. #ifdef CONFIG_HAVE_CLK
  1406. if (r8a66597->pdata->on_chip) {
  1407. clk_disable(r8a66597->clk);
  1408. clk_put(r8a66597->clk);
  1409. }
  1410. #endif
  1411. clean_up:
  1412. if (r8a66597) {
  1413. if (r8a66597->ep0_req)
  1414. r8a66597_free_request(&r8a66597->ep[0].ep,
  1415. r8a66597->ep0_req);
  1416. kfree(r8a66597);
  1417. }
  1418. if (reg)
  1419. iounmap(reg);
  1420. return ret;
  1421. }
  1422. /*-------------------------------------------------------------------------*/
  1423. static struct platform_driver r8a66597_driver = {
  1424. .remove = __exit_p(r8a66597_remove),
  1425. .driver = {
  1426. .name = (char *) udc_name,
  1427. },
  1428. };
  1429. MODULE_ALIAS("platform:r8a66597_udc");
  1430. static int __init r8a66597_udc_init(void)
  1431. {
  1432. return platform_driver_probe(&r8a66597_driver, r8a66597_probe);
  1433. }
  1434. module_init(r8a66597_udc_init);
  1435. static void __exit r8a66597_udc_cleanup(void)
  1436. {
  1437. platform_driver_unregister(&r8a66597_driver);
  1438. }
  1439. module_exit(r8a66597_udc_cleanup);
  1440. MODULE_DESCRIPTION("R8A66597 USB gadget driver");
  1441. MODULE_LICENSE("GPL");
  1442. MODULE_AUTHOR("Yoshihiro Shimoda");