radeon_encoders.c 56 KB

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  1. /*
  2. * Copyright 2007-8 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice shall be included in
  13. * all copies or substantial portions of the Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21. * OTHER DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors: Dave Airlie
  24. * Alex Deucher
  25. */
  26. #include "drmP.h"
  27. #include "drm_crtc_helper.h"
  28. #include "radeon_drm.h"
  29. #include "radeon.h"
  30. #include "atom.h"
  31. extern int atom_debug;
  32. /* evil but including atombios.h is much worse */
  33. bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
  34. struct drm_display_mode *mode);
  35. static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
  36. {
  37. struct drm_device *dev = encoder->dev;
  38. struct radeon_device *rdev = dev->dev_private;
  39. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  40. struct drm_encoder *clone_encoder;
  41. uint32_t index_mask = 0;
  42. int count;
  43. /* DIG routing gets problematic */
  44. if (rdev->family >= CHIP_R600)
  45. return index_mask;
  46. /* LVDS/TV are too wacky */
  47. if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
  48. return index_mask;
  49. /* DVO requires 2x ppll clocks depending on tmds chip */
  50. if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
  51. return index_mask;
  52. count = -1;
  53. list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
  54. struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
  55. count++;
  56. if (clone_encoder == encoder)
  57. continue;
  58. if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
  59. continue;
  60. if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
  61. continue;
  62. else
  63. index_mask |= (1 << count);
  64. }
  65. return index_mask;
  66. }
  67. void radeon_setup_encoder_clones(struct drm_device *dev)
  68. {
  69. struct drm_encoder *encoder;
  70. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  71. encoder->possible_clones = radeon_encoder_clones(encoder);
  72. }
  73. }
  74. uint32_t
  75. radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
  76. {
  77. struct radeon_device *rdev = dev->dev_private;
  78. uint32_t ret = 0;
  79. switch (supported_device) {
  80. case ATOM_DEVICE_CRT1_SUPPORT:
  81. case ATOM_DEVICE_TV1_SUPPORT:
  82. case ATOM_DEVICE_TV2_SUPPORT:
  83. case ATOM_DEVICE_CRT2_SUPPORT:
  84. case ATOM_DEVICE_CV_SUPPORT:
  85. switch (dac) {
  86. case 1: /* dac a */
  87. if ((rdev->family == CHIP_RS300) ||
  88. (rdev->family == CHIP_RS400) ||
  89. (rdev->family == CHIP_RS480))
  90. ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
  91. else if (ASIC_IS_AVIVO(rdev))
  92. ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
  93. else
  94. ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
  95. break;
  96. case 2: /* dac b */
  97. if (ASIC_IS_AVIVO(rdev))
  98. ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
  99. else {
  100. /*if (rdev->family == CHIP_R200)
  101. ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
  102. else*/
  103. ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
  104. }
  105. break;
  106. case 3: /* external dac */
  107. if (ASIC_IS_AVIVO(rdev))
  108. ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
  109. else
  110. ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
  111. break;
  112. }
  113. break;
  114. case ATOM_DEVICE_LCD1_SUPPORT:
  115. if (ASIC_IS_AVIVO(rdev))
  116. ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
  117. else
  118. ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
  119. break;
  120. case ATOM_DEVICE_DFP1_SUPPORT:
  121. if ((rdev->family == CHIP_RS300) ||
  122. (rdev->family == CHIP_RS400) ||
  123. (rdev->family == CHIP_RS480))
  124. ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
  125. else if (ASIC_IS_AVIVO(rdev))
  126. ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
  127. else
  128. ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
  129. break;
  130. case ATOM_DEVICE_LCD2_SUPPORT:
  131. case ATOM_DEVICE_DFP2_SUPPORT:
  132. if ((rdev->family == CHIP_RS600) ||
  133. (rdev->family == CHIP_RS690) ||
  134. (rdev->family == CHIP_RS740))
  135. ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
  136. else if (ASIC_IS_AVIVO(rdev))
  137. ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
  138. else
  139. ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
  140. break;
  141. case ATOM_DEVICE_DFP3_SUPPORT:
  142. ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
  143. break;
  144. }
  145. return ret;
  146. }
  147. static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
  148. {
  149. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  150. switch (radeon_encoder->encoder_id) {
  151. case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  152. case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
  153. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
  154. case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
  155. case ENCODER_OBJECT_ID_INTERNAL_DVO1:
  156. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  157. case ENCODER_OBJECT_ID_INTERNAL_DDI:
  158. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  159. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
  160. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  161. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  162. return true;
  163. default:
  164. return false;
  165. }
  166. }
  167. void
  168. radeon_link_encoder_connector(struct drm_device *dev)
  169. {
  170. struct drm_connector *connector;
  171. struct radeon_connector *radeon_connector;
  172. struct drm_encoder *encoder;
  173. struct radeon_encoder *radeon_encoder;
  174. /* walk the list and link encoders to connectors */
  175. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  176. radeon_connector = to_radeon_connector(connector);
  177. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  178. radeon_encoder = to_radeon_encoder(encoder);
  179. if (radeon_encoder->devices & radeon_connector->devices)
  180. drm_mode_connector_attach_encoder(connector, encoder);
  181. }
  182. }
  183. }
  184. void radeon_encoder_set_active_device(struct drm_encoder *encoder)
  185. {
  186. struct drm_device *dev = encoder->dev;
  187. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  188. struct drm_connector *connector;
  189. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  190. if (connector->encoder == encoder) {
  191. struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  192. radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
  193. DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
  194. radeon_encoder->active_device, radeon_encoder->devices,
  195. radeon_connector->devices, encoder->encoder_type);
  196. }
  197. }
  198. }
  199. struct drm_connector *
  200. radeon_get_connector_for_encoder(struct drm_encoder *encoder)
  201. {
  202. struct drm_device *dev = encoder->dev;
  203. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  204. struct drm_connector *connector;
  205. struct radeon_connector *radeon_connector;
  206. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  207. radeon_connector = to_radeon_connector(connector);
  208. if (radeon_encoder->active_device & radeon_connector->devices)
  209. return connector;
  210. }
  211. return NULL;
  212. }
  213. static struct radeon_connector_atom_dig *
  214. radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder)
  215. {
  216. struct drm_device *dev = encoder->dev;
  217. struct radeon_device *rdev = dev->dev_private;
  218. struct drm_connector *connector;
  219. struct radeon_connector *radeon_connector;
  220. struct radeon_connector_atom_dig *dig_connector;
  221. if (!rdev->is_atom_bios)
  222. return NULL;
  223. connector = radeon_get_connector_for_encoder(encoder);
  224. if (!connector)
  225. return NULL;
  226. radeon_connector = to_radeon_connector(connector);
  227. if (!radeon_connector->con_priv)
  228. return NULL;
  229. dig_connector = radeon_connector->con_priv;
  230. return dig_connector;
  231. }
  232. void radeon_panel_mode_fixup(struct drm_encoder *encoder,
  233. struct drm_display_mode *adjusted_mode)
  234. {
  235. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  236. struct drm_device *dev = encoder->dev;
  237. struct radeon_device *rdev = dev->dev_private;
  238. struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
  239. unsigned hblank = native_mode->htotal - native_mode->hdisplay;
  240. unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
  241. unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
  242. unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
  243. unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
  244. unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
  245. adjusted_mode->clock = native_mode->clock;
  246. adjusted_mode->flags = native_mode->flags;
  247. if (ASIC_IS_AVIVO(rdev)) {
  248. adjusted_mode->hdisplay = native_mode->hdisplay;
  249. adjusted_mode->vdisplay = native_mode->vdisplay;
  250. }
  251. adjusted_mode->htotal = native_mode->hdisplay + hblank;
  252. adjusted_mode->hsync_start = native_mode->hdisplay + hover;
  253. adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
  254. adjusted_mode->vtotal = native_mode->vdisplay + vblank;
  255. adjusted_mode->vsync_start = native_mode->vdisplay + vover;
  256. adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
  257. drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
  258. if (ASIC_IS_AVIVO(rdev)) {
  259. adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
  260. adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
  261. }
  262. adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
  263. adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
  264. adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
  265. adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
  266. adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
  267. adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
  268. }
  269. static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
  270. struct drm_display_mode *mode,
  271. struct drm_display_mode *adjusted_mode)
  272. {
  273. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  274. struct drm_device *dev = encoder->dev;
  275. struct radeon_device *rdev = dev->dev_private;
  276. /* set the active encoder to connector routing */
  277. radeon_encoder_set_active_device(encoder);
  278. drm_mode_set_crtcinfo(adjusted_mode, 0);
  279. /* hw bug */
  280. if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
  281. && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
  282. adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
  283. /* get the native mode for LVDS */
  284. if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
  285. radeon_panel_mode_fixup(encoder, adjusted_mode);
  286. /* get the native mode for TV */
  287. if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
  288. struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
  289. if (tv_dac) {
  290. if (tv_dac->tv_std == TV_STD_NTSC ||
  291. tv_dac->tv_std == TV_STD_NTSC_J ||
  292. tv_dac->tv_std == TV_STD_PAL_M)
  293. radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
  294. else
  295. radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
  296. }
  297. }
  298. if (ASIC_IS_DCE3(rdev) &&
  299. (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
  300. struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
  301. radeon_dp_set_link_config(connector, mode);
  302. }
  303. return true;
  304. }
  305. static void
  306. atombios_dac_setup(struct drm_encoder *encoder, int action)
  307. {
  308. struct drm_device *dev = encoder->dev;
  309. struct radeon_device *rdev = dev->dev_private;
  310. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  311. DAC_ENCODER_CONTROL_PS_ALLOCATION args;
  312. int index = 0;
  313. struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
  314. memset(&args, 0, sizeof(args));
  315. switch (radeon_encoder->encoder_id) {
  316. case ENCODER_OBJECT_ID_INTERNAL_DAC1:
  317. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
  318. index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
  319. break;
  320. case ENCODER_OBJECT_ID_INTERNAL_DAC2:
  321. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
  322. index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
  323. break;
  324. }
  325. args.ucAction = action;
  326. if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
  327. args.ucDacStandard = ATOM_DAC1_PS2;
  328. else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
  329. args.ucDacStandard = ATOM_DAC1_CV;
  330. else {
  331. switch (dac_info->tv_std) {
  332. case TV_STD_PAL:
  333. case TV_STD_PAL_M:
  334. case TV_STD_SCART_PAL:
  335. case TV_STD_SECAM:
  336. case TV_STD_PAL_CN:
  337. args.ucDacStandard = ATOM_DAC1_PAL;
  338. break;
  339. case TV_STD_NTSC:
  340. case TV_STD_NTSC_J:
  341. case TV_STD_PAL_60:
  342. default:
  343. args.ucDacStandard = ATOM_DAC1_NTSC;
  344. break;
  345. }
  346. }
  347. args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
  348. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  349. }
  350. static void
  351. atombios_tv_setup(struct drm_encoder *encoder, int action)
  352. {
  353. struct drm_device *dev = encoder->dev;
  354. struct radeon_device *rdev = dev->dev_private;
  355. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  356. TV_ENCODER_CONTROL_PS_ALLOCATION args;
  357. int index = 0;
  358. struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
  359. memset(&args, 0, sizeof(args));
  360. index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
  361. args.sTVEncoder.ucAction = action;
  362. if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
  363. args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
  364. else {
  365. switch (dac_info->tv_std) {
  366. case TV_STD_NTSC:
  367. args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
  368. break;
  369. case TV_STD_PAL:
  370. args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
  371. break;
  372. case TV_STD_PAL_M:
  373. args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
  374. break;
  375. case TV_STD_PAL_60:
  376. args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
  377. break;
  378. case TV_STD_NTSC_J:
  379. args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
  380. break;
  381. case TV_STD_SCART_PAL:
  382. args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
  383. break;
  384. case TV_STD_SECAM:
  385. args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
  386. break;
  387. case TV_STD_PAL_CN:
  388. args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
  389. break;
  390. default:
  391. args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
  392. break;
  393. }
  394. }
  395. args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
  396. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  397. }
  398. void
  399. atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
  400. {
  401. struct drm_device *dev = encoder->dev;
  402. struct radeon_device *rdev = dev->dev_private;
  403. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  404. ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
  405. int index = 0;
  406. memset(&args, 0, sizeof(args));
  407. index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
  408. args.sXTmdsEncoder.ucEnable = action;
  409. if (radeon_encoder->pixel_clock > 165000)
  410. args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
  411. /*if (pScrn->rgbBits == 8)*/
  412. args.sXTmdsEncoder.ucMisc |= (1 << 1);
  413. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  414. }
  415. static void
  416. atombios_ddia_setup(struct drm_encoder *encoder, int action)
  417. {
  418. struct drm_device *dev = encoder->dev;
  419. struct radeon_device *rdev = dev->dev_private;
  420. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  421. DVO_ENCODER_CONTROL_PS_ALLOCATION args;
  422. int index = 0;
  423. memset(&args, 0, sizeof(args));
  424. index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
  425. args.sDVOEncoder.ucAction = action;
  426. args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
  427. if (radeon_encoder->pixel_clock > 165000)
  428. args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
  429. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  430. }
  431. union lvds_encoder_control {
  432. LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
  433. LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
  434. };
  435. void
  436. atombios_digital_setup(struct drm_encoder *encoder, int action)
  437. {
  438. struct drm_device *dev = encoder->dev;
  439. struct radeon_device *rdev = dev->dev_private;
  440. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  441. struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  442. struct radeon_connector_atom_dig *dig_connector =
  443. radeon_get_atom_connector_priv_from_encoder(encoder);
  444. union lvds_encoder_control args;
  445. int index = 0;
  446. int hdmi_detected = 0;
  447. uint8_t frev, crev;
  448. if (!dig || !dig_connector)
  449. return;
  450. if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
  451. hdmi_detected = 1;
  452. memset(&args, 0, sizeof(args));
  453. switch (radeon_encoder->encoder_id) {
  454. case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  455. index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
  456. break;
  457. case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
  458. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
  459. index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
  460. break;
  461. case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
  462. if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
  463. index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
  464. else
  465. index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
  466. break;
  467. }
  468. if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
  469. return;
  470. switch (frev) {
  471. case 1:
  472. case 2:
  473. switch (crev) {
  474. case 1:
  475. args.v1.ucMisc = 0;
  476. args.v1.ucAction = action;
  477. if (hdmi_detected)
  478. args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
  479. args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
  480. if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
  481. if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
  482. args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
  483. if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
  484. args.v1.ucMisc |= (1 << 1);
  485. } else {
  486. if (dig->linkb)
  487. args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
  488. if (radeon_encoder->pixel_clock > 165000)
  489. args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
  490. /*if (pScrn->rgbBits == 8) */
  491. args.v1.ucMisc |= (1 << 1);
  492. }
  493. break;
  494. case 2:
  495. case 3:
  496. args.v2.ucMisc = 0;
  497. args.v2.ucAction = action;
  498. if (crev == 3) {
  499. if (dig->coherent_mode)
  500. args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
  501. }
  502. if (hdmi_detected)
  503. args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
  504. args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
  505. args.v2.ucTruncate = 0;
  506. args.v2.ucSpatial = 0;
  507. args.v2.ucTemporal = 0;
  508. args.v2.ucFRC = 0;
  509. if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
  510. if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
  511. args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
  512. if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) {
  513. args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
  514. if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
  515. args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
  516. }
  517. if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) {
  518. args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
  519. if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
  520. args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
  521. if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
  522. args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
  523. }
  524. } else {
  525. if (dig->linkb)
  526. args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
  527. if (radeon_encoder->pixel_clock > 165000)
  528. args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
  529. }
  530. break;
  531. default:
  532. DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
  533. break;
  534. }
  535. break;
  536. default:
  537. DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
  538. break;
  539. }
  540. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  541. }
  542. int
  543. atombios_get_encoder_mode(struct drm_encoder *encoder)
  544. {
  545. struct drm_connector *connector;
  546. struct radeon_connector *radeon_connector;
  547. struct radeon_connector_atom_dig *dig_connector;
  548. connector = radeon_get_connector_for_encoder(encoder);
  549. if (!connector)
  550. return 0;
  551. radeon_connector = to_radeon_connector(connector);
  552. switch (connector->connector_type) {
  553. case DRM_MODE_CONNECTOR_DVII:
  554. case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
  555. if (drm_detect_hdmi_monitor(radeon_connector->edid))
  556. return ATOM_ENCODER_MODE_HDMI;
  557. else if (radeon_connector->use_digital)
  558. return ATOM_ENCODER_MODE_DVI;
  559. else
  560. return ATOM_ENCODER_MODE_CRT;
  561. break;
  562. case DRM_MODE_CONNECTOR_DVID:
  563. case DRM_MODE_CONNECTOR_HDMIA:
  564. default:
  565. if (drm_detect_hdmi_monitor(radeon_connector->edid))
  566. return ATOM_ENCODER_MODE_HDMI;
  567. else
  568. return ATOM_ENCODER_MODE_DVI;
  569. break;
  570. case DRM_MODE_CONNECTOR_LVDS:
  571. return ATOM_ENCODER_MODE_LVDS;
  572. break;
  573. case DRM_MODE_CONNECTOR_DisplayPort:
  574. case DRM_MODE_CONNECTOR_eDP:
  575. dig_connector = radeon_connector->con_priv;
  576. if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
  577. (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
  578. return ATOM_ENCODER_MODE_DP;
  579. else if (drm_detect_hdmi_monitor(radeon_connector->edid))
  580. return ATOM_ENCODER_MODE_HDMI;
  581. else
  582. return ATOM_ENCODER_MODE_DVI;
  583. break;
  584. case DRM_MODE_CONNECTOR_DVIA:
  585. case DRM_MODE_CONNECTOR_VGA:
  586. return ATOM_ENCODER_MODE_CRT;
  587. break;
  588. case DRM_MODE_CONNECTOR_Composite:
  589. case DRM_MODE_CONNECTOR_SVIDEO:
  590. case DRM_MODE_CONNECTOR_9PinDIN:
  591. /* fix me */
  592. return ATOM_ENCODER_MODE_TV;
  593. /*return ATOM_ENCODER_MODE_CV;*/
  594. break;
  595. }
  596. }
  597. /*
  598. * DIG Encoder/Transmitter Setup
  599. *
  600. * DCE 3.0/3.1
  601. * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
  602. * Supports up to 3 digital outputs
  603. * - 2 DIG encoder blocks.
  604. * DIG1 can drive UNIPHY link A or link B
  605. * DIG2 can drive UNIPHY link B or LVTMA
  606. *
  607. * DCE 3.2
  608. * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
  609. * Supports up to 5 digital outputs
  610. * - 2 DIG encoder blocks.
  611. * DIG1/2 can drive UNIPHY0/1/2 link A or link B
  612. *
  613. * DCE 4.0
  614. * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B).
  615. * Supports up to 6 digital outputs
  616. * - 6 DIG encoder blocks.
  617. * - DIG to PHY mapping is hardcoded
  618. * DIG1 drives UNIPHY0 link A, A+B
  619. * DIG2 drives UNIPHY0 link B
  620. * DIG3 drives UNIPHY1 link A, A+B
  621. * DIG4 drives UNIPHY1 link B
  622. * DIG5 drives UNIPHY2 link A, A+B
  623. * DIG6 drives UNIPHY2 link B
  624. *
  625. * Routing
  626. * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
  627. * Examples:
  628. * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
  629. * crtc1 -> dig1 -> UNIPHY0 link B -> DP
  630. * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
  631. * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
  632. */
  633. union dig_encoder_control {
  634. DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
  635. DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
  636. DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
  637. };
  638. void
  639. atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
  640. {
  641. struct drm_device *dev = encoder->dev;
  642. struct radeon_device *rdev = dev->dev_private;
  643. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  644. struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  645. struct radeon_connector_atom_dig *dig_connector =
  646. radeon_get_atom_connector_priv_from_encoder(encoder);
  647. union dig_encoder_control args;
  648. int index = 0;
  649. uint8_t frev, crev;
  650. if (!dig || !dig_connector)
  651. return;
  652. memset(&args, 0, sizeof(args));
  653. if (ASIC_IS_DCE4(rdev))
  654. index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
  655. else {
  656. if (dig->dig_encoder)
  657. index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
  658. else
  659. index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
  660. }
  661. if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
  662. return;
  663. args.v1.ucAction = action;
  664. args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
  665. args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
  666. if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
  667. if (dig_connector->dp_clock == 270000)
  668. args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
  669. args.v1.ucLaneNum = dig_connector->dp_lane_count;
  670. } else if (radeon_encoder->pixel_clock > 165000)
  671. args.v1.ucLaneNum = 8;
  672. else
  673. args.v1.ucLaneNum = 4;
  674. if (ASIC_IS_DCE4(rdev)) {
  675. args.v3.acConfig.ucDigSel = dig->dig_encoder;
  676. args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
  677. } else {
  678. switch (radeon_encoder->encoder_id) {
  679. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  680. args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
  681. break;
  682. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  683. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
  684. args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
  685. break;
  686. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  687. args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
  688. break;
  689. }
  690. if (dig->linkb)
  691. args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
  692. else
  693. args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
  694. }
  695. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  696. }
  697. union dig_transmitter_control {
  698. DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
  699. DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
  700. DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
  701. };
  702. void
  703. atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
  704. {
  705. struct drm_device *dev = encoder->dev;
  706. struct radeon_device *rdev = dev->dev_private;
  707. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  708. struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  709. struct radeon_connector_atom_dig *dig_connector =
  710. radeon_get_atom_connector_priv_from_encoder(encoder);
  711. struct drm_connector *connector;
  712. struct radeon_connector *radeon_connector;
  713. union dig_transmitter_control args;
  714. int index = 0;
  715. uint8_t frev, crev;
  716. bool is_dp = false;
  717. int pll_id = 0;
  718. if (!dig || !dig_connector)
  719. return;
  720. connector = radeon_get_connector_for_encoder(encoder);
  721. radeon_connector = to_radeon_connector(connector);
  722. if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
  723. is_dp = true;
  724. memset(&args, 0, sizeof(args));
  725. if (ASIC_IS_DCE32(rdev) || ASIC_IS_DCE4(rdev))
  726. index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
  727. else {
  728. switch (radeon_encoder->encoder_id) {
  729. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  730. index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
  731. break;
  732. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
  733. index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
  734. break;
  735. }
  736. }
  737. if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
  738. return;
  739. args.v1.ucAction = action;
  740. if (action == ATOM_TRANSMITTER_ACTION_INIT) {
  741. args.v1.usInitInfo = radeon_connector->connector_object_id;
  742. } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
  743. args.v1.asMode.ucLaneSel = lane_num;
  744. args.v1.asMode.ucLaneSet = lane_set;
  745. } else {
  746. if (is_dp)
  747. args.v1.usPixelClock =
  748. cpu_to_le16(dig_connector->dp_clock / 10);
  749. else if (radeon_encoder->pixel_clock > 165000)
  750. args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
  751. else
  752. args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
  753. }
  754. if (ASIC_IS_DCE4(rdev)) {
  755. if (is_dp)
  756. args.v3.ucLaneNum = dig_connector->dp_lane_count;
  757. else if (radeon_encoder->pixel_clock > 165000)
  758. args.v3.ucLaneNum = 8;
  759. else
  760. args.v3.ucLaneNum = 4;
  761. if (dig->linkb) {
  762. args.v3.acConfig.ucLinkSel = 1;
  763. args.v3.acConfig.ucEncoderSel = 1;
  764. }
  765. /* Select the PLL for the PHY
  766. * DP PHY should be clocked from external src if there is
  767. * one.
  768. */
  769. if (encoder->crtc) {
  770. struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  771. pll_id = radeon_crtc->pll_id;
  772. }
  773. if (is_dp && rdev->clock.dp_extclk)
  774. args.v3.acConfig.ucRefClkSource = 2; /* external src */
  775. else
  776. args.v3.acConfig.ucRefClkSource = pll_id;
  777. switch (radeon_encoder->encoder_id) {
  778. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  779. args.v3.acConfig.ucTransmitterSel = 0;
  780. break;
  781. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  782. args.v3.acConfig.ucTransmitterSel = 1;
  783. break;
  784. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  785. args.v3.acConfig.ucTransmitterSel = 2;
  786. break;
  787. }
  788. if (is_dp)
  789. args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
  790. else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
  791. if (dig->coherent_mode)
  792. args.v3.acConfig.fCoherentMode = 1;
  793. if (radeon_encoder->pixel_clock > 165000)
  794. args.v3.acConfig.fDualLinkConnector = 1;
  795. }
  796. } else if (ASIC_IS_DCE32(rdev)) {
  797. args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
  798. if (dig->linkb)
  799. args.v2.acConfig.ucLinkSel = 1;
  800. switch (radeon_encoder->encoder_id) {
  801. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  802. args.v2.acConfig.ucTransmitterSel = 0;
  803. break;
  804. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  805. args.v2.acConfig.ucTransmitterSel = 1;
  806. break;
  807. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  808. args.v2.acConfig.ucTransmitterSel = 2;
  809. break;
  810. }
  811. if (is_dp)
  812. args.v2.acConfig.fCoherentMode = 1;
  813. else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
  814. if (dig->coherent_mode)
  815. args.v2.acConfig.fCoherentMode = 1;
  816. if (radeon_encoder->pixel_clock > 165000)
  817. args.v2.acConfig.fDualLinkConnector = 1;
  818. }
  819. } else {
  820. args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
  821. if (dig->dig_encoder)
  822. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
  823. else
  824. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
  825. if ((rdev->flags & RADEON_IS_IGP) &&
  826. (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
  827. if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
  828. if (dig_connector->igp_lane_info & 0x1)
  829. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
  830. else if (dig_connector->igp_lane_info & 0x2)
  831. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
  832. else if (dig_connector->igp_lane_info & 0x4)
  833. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
  834. else if (dig_connector->igp_lane_info & 0x8)
  835. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
  836. } else {
  837. if (dig_connector->igp_lane_info & 0x3)
  838. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
  839. else if (dig_connector->igp_lane_info & 0xc)
  840. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
  841. }
  842. }
  843. if (dig->linkb)
  844. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
  845. else
  846. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
  847. if (is_dp)
  848. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
  849. else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
  850. if (dig->coherent_mode)
  851. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
  852. if (radeon_encoder->pixel_clock > 165000)
  853. args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
  854. }
  855. }
  856. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  857. }
  858. static void
  859. atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
  860. {
  861. struct drm_device *dev = encoder->dev;
  862. struct radeon_device *rdev = dev->dev_private;
  863. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  864. struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  865. ENABLE_YUV_PS_ALLOCATION args;
  866. int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
  867. uint32_t temp, reg;
  868. memset(&args, 0, sizeof(args));
  869. if (rdev->family >= CHIP_R600)
  870. reg = R600_BIOS_3_SCRATCH;
  871. else
  872. reg = RADEON_BIOS_3_SCRATCH;
  873. /* XXX: fix up scratch reg handling */
  874. temp = RREG32(reg);
  875. if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
  876. WREG32(reg, (ATOM_S3_TV1_ACTIVE |
  877. (radeon_crtc->crtc_id << 18)));
  878. else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
  879. WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
  880. else
  881. WREG32(reg, 0);
  882. if (enable)
  883. args.ucEnable = ATOM_ENABLE;
  884. args.ucCRTC = radeon_crtc->crtc_id;
  885. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  886. WREG32(reg, temp);
  887. }
  888. static void
  889. radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
  890. {
  891. struct drm_device *dev = encoder->dev;
  892. struct radeon_device *rdev = dev->dev_private;
  893. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  894. DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
  895. int index = 0;
  896. bool is_dig = false;
  897. memset(&args, 0, sizeof(args));
  898. DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
  899. radeon_encoder->encoder_id, mode, radeon_encoder->devices,
  900. radeon_encoder->active_device);
  901. switch (radeon_encoder->encoder_id) {
  902. case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
  903. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
  904. index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
  905. break;
  906. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  907. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  908. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  909. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
  910. is_dig = true;
  911. break;
  912. case ENCODER_OBJECT_ID_INTERNAL_DVO1:
  913. case ENCODER_OBJECT_ID_INTERNAL_DDI:
  914. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  915. index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
  916. break;
  917. case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  918. index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
  919. break;
  920. case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
  921. if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
  922. index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
  923. else
  924. index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
  925. break;
  926. case ENCODER_OBJECT_ID_INTERNAL_DAC1:
  927. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
  928. if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
  929. index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
  930. else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
  931. index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
  932. else
  933. index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
  934. break;
  935. case ENCODER_OBJECT_ID_INTERNAL_DAC2:
  936. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
  937. if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
  938. index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
  939. else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
  940. index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
  941. else
  942. index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
  943. break;
  944. }
  945. if (is_dig) {
  946. switch (mode) {
  947. case DRM_MODE_DPMS_ON:
  948. if (!ASIC_IS_DCE4(rdev))
  949. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
  950. if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
  951. struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
  952. dp_link_train(encoder, connector);
  953. if (ASIC_IS_DCE4(rdev))
  954. atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
  955. }
  956. break;
  957. case DRM_MODE_DPMS_STANDBY:
  958. case DRM_MODE_DPMS_SUSPEND:
  959. case DRM_MODE_DPMS_OFF:
  960. if (!ASIC_IS_DCE4(rdev))
  961. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
  962. if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
  963. if (ASIC_IS_DCE4(rdev))
  964. atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
  965. }
  966. break;
  967. }
  968. } else {
  969. switch (mode) {
  970. case DRM_MODE_DPMS_ON:
  971. args.ucAction = ATOM_ENABLE;
  972. break;
  973. case DRM_MODE_DPMS_STANDBY:
  974. case DRM_MODE_DPMS_SUSPEND:
  975. case DRM_MODE_DPMS_OFF:
  976. args.ucAction = ATOM_DISABLE;
  977. break;
  978. }
  979. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  980. }
  981. radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  982. }
  983. union crtc_source_param {
  984. SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
  985. SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
  986. };
  987. static void
  988. atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
  989. {
  990. struct drm_device *dev = encoder->dev;
  991. struct radeon_device *rdev = dev->dev_private;
  992. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  993. struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  994. union crtc_source_param args;
  995. int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
  996. uint8_t frev, crev;
  997. struct radeon_encoder_atom_dig *dig;
  998. memset(&args, 0, sizeof(args));
  999. if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
  1000. return;
  1001. switch (frev) {
  1002. case 1:
  1003. switch (crev) {
  1004. case 1:
  1005. default:
  1006. if (ASIC_IS_AVIVO(rdev))
  1007. args.v1.ucCRTC = radeon_crtc->crtc_id;
  1008. else {
  1009. if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
  1010. args.v1.ucCRTC = radeon_crtc->crtc_id;
  1011. } else {
  1012. args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
  1013. }
  1014. }
  1015. switch (radeon_encoder->encoder_id) {
  1016. case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
  1017. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
  1018. args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
  1019. break;
  1020. case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  1021. case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
  1022. if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
  1023. args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
  1024. else
  1025. args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
  1026. break;
  1027. case ENCODER_OBJECT_ID_INTERNAL_DVO1:
  1028. case ENCODER_OBJECT_ID_INTERNAL_DDI:
  1029. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  1030. args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
  1031. break;
  1032. case ENCODER_OBJECT_ID_INTERNAL_DAC1:
  1033. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
  1034. if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
  1035. args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
  1036. else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
  1037. args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
  1038. else
  1039. args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
  1040. break;
  1041. case ENCODER_OBJECT_ID_INTERNAL_DAC2:
  1042. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
  1043. if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
  1044. args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
  1045. else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
  1046. args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
  1047. else
  1048. args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
  1049. break;
  1050. }
  1051. break;
  1052. case 2:
  1053. args.v2.ucCRTC = radeon_crtc->crtc_id;
  1054. args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
  1055. switch (radeon_encoder->encoder_id) {
  1056. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  1057. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  1058. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  1059. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
  1060. dig = radeon_encoder->enc_priv;
  1061. switch (dig->dig_encoder) {
  1062. case 0:
  1063. args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
  1064. break;
  1065. case 1:
  1066. args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
  1067. break;
  1068. case 2:
  1069. args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
  1070. break;
  1071. case 3:
  1072. args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
  1073. break;
  1074. case 4:
  1075. args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
  1076. break;
  1077. case 5:
  1078. args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
  1079. break;
  1080. }
  1081. break;
  1082. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  1083. args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
  1084. break;
  1085. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
  1086. if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
  1087. args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
  1088. else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
  1089. args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
  1090. else
  1091. args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
  1092. break;
  1093. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
  1094. if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
  1095. args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
  1096. else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
  1097. args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
  1098. else
  1099. args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
  1100. break;
  1101. }
  1102. break;
  1103. }
  1104. break;
  1105. default:
  1106. DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
  1107. break;
  1108. }
  1109. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  1110. /* update scratch regs with new routing */
  1111. radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  1112. }
  1113. static void
  1114. atombios_apply_encoder_quirks(struct drm_encoder *encoder,
  1115. struct drm_display_mode *mode)
  1116. {
  1117. struct drm_device *dev = encoder->dev;
  1118. struct radeon_device *rdev = dev->dev_private;
  1119. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1120. struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  1121. /* Funky macbooks */
  1122. if ((dev->pdev->device == 0x71C5) &&
  1123. (dev->pdev->subsystem_vendor == 0x106b) &&
  1124. (dev->pdev->subsystem_device == 0x0080)) {
  1125. if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
  1126. uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
  1127. lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
  1128. lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
  1129. WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
  1130. }
  1131. }
  1132. /* set scaler clears this on some chips */
  1133. /* XXX check DCE4 */
  1134. if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
  1135. if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
  1136. WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
  1137. AVIVO_D1MODE_INTERLEAVE_EN);
  1138. }
  1139. }
  1140. static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
  1141. {
  1142. struct drm_device *dev = encoder->dev;
  1143. struct radeon_device *rdev = dev->dev_private;
  1144. struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  1145. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1146. struct drm_encoder *test_encoder;
  1147. struct radeon_encoder_atom_dig *dig;
  1148. uint32_t dig_enc_in_use = 0;
  1149. if (ASIC_IS_DCE4(rdev)) {
  1150. dig = radeon_encoder->enc_priv;
  1151. switch (radeon_encoder->encoder_id) {
  1152. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  1153. if (dig->linkb)
  1154. return 1;
  1155. else
  1156. return 0;
  1157. break;
  1158. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  1159. if (dig->linkb)
  1160. return 3;
  1161. else
  1162. return 2;
  1163. break;
  1164. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  1165. if (dig->linkb)
  1166. return 5;
  1167. else
  1168. return 4;
  1169. break;
  1170. }
  1171. }
  1172. /* on DCE32 and encoder can driver any block so just crtc id */
  1173. if (ASIC_IS_DCE32(rdev)) {
  1174. return radeon_crtc->crtc_id;
  1175. }
  1176. /* on DCE3 - LVTMA can only be driven by DIGB */
  1177. list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
  1178. struct radeon_encoder *radeon_test_encoder;
  1179. if (encoder == test_encoder)
  1180. continue;
  1181. if (!radeon_encoder_is_digital(test_encoder))
  1182. continue;
  1183. radeon_test_encoder = to_radeon_encoder(test_encoder);
  1184. dig = radeon_test_encoder->enc_priv;
  1185. if (dig->dig_encoder >= 0)
  1186. dig_enc_in_use |= (1 << dig->dig_encoder);
  1187. }
  1188. if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
  1189. if (dig_enc_in_use & 0x2)
  1190. DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
  1191. return 1;
  1192. }
  1193. if (!(dig_enc_in_use & 1))
  1194. return 0;
  1195. return 1;
  1196. }
  1197. static void
  1198. radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
  1199. struct drm_display_mode *mode,
  1200. struct drm_display_mode *adjusted_mode)
  1201. {
  1202. struct drm_device *dev = encoder->dev;
  1203. struct radeon_device *rdev = dev->dev_private;
  1204. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1205. radeon_encoder->pixel_clock = adjusted_mode->clock;
  1206. if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
  1207. if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
  1208. atombios_yuv_setup(encoder, true);
  1209. else
  1210. atombios_yuv_setup(encoder, false);
  1211. }
  1212. switch (radeon_encoder->encoder_id) {
  1213. case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
  1214. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
  1215. case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  1216. case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
  1217. atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
  1218. break;
  1219. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  1220. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  1221. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  1222. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
  1223. if (ASIC_IS_DCE4(rdev)) {
  1224. /* disable the transmitter */
  1225. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
  1226. /* setup and enable the encoder */
  1227. atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
  1228. /* init and enable the transmitter */
  1229. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
  1230. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
  1231. } else {
  1232. /* disable the encoder and transmitter */
  1233. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
  1234. atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
  1235. /* setup and enable the encoder and transmitter */
  1236. atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
  1237. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
  1238. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
  1239. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
  1240. }
  1241. break;
  1242. case ENCODER_OBJECT_ID_INTERNAL_DDI:
  1243. atombios_ddia_setup(encoder, ATOM_ENABLE);
  1244. break;
  1245. case ENCODER_OBJECT_ID_INTERNAL_DVO1:
  1246. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  1247. atombios_external_tmds_setup(encoder, ATOM_ENABLE);
  1248. break;
  1249. case ENCODER_OBJECT_ID_INTERNAL_DAC1:
  1250. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
  1251. case ENCODER_OBJECT_ID_INTERNAL_DAC2:
  1252. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
  1253. atombios_dac_setup(encoder, ATOM_ENABLE);
  1254. if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
  1255. if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
  1256. atombios_tv_setup(encoder, ATOM_ENABLE);
  1257. else
  1258. atombios_tv_setup(encoder, ATOM_DISABLE);
  1259. }
  1260. break;
  1261. }
  1262. atombios_apply_encoder_quirks(encoder, adjusted_mode);
  1263. if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
  1264. r600_hdmi_enable(encoder);
  1265. r600_hdmi_setmode(encoder, adjusted_mode);
  1266. }
  1267. }
  1268. static bool
  1269. atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
  1270. {
  1271. struct drm_device *dev = encoder->dev;
  1272. struct radeon_device *rdev = dev->dev_private;
  1273. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1274. struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  1275. if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
  1276. ATOM_DEVICE_CV_SUPPORT |
  1277. ATOM_DEVICE_CRT_SUPPORT)) {
  1278. DAC_LOAD_DETECTION_PS_ALLOCATION args;
  1279. int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
  1280. uint8_t frev, crev;
  1281. memset(&args, 0, sizeof(args));
  1282. if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
  1283. return false;
  1284. args.sDacload.ucMisc = 0;
  1285. if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
  1286. (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
  1287. args.sDacload.ucDacType = ATOM_DAC_A;
  1288. else
  1289. args.sDacload.ucDacType = ATOM_DAC_B;
  1290. if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
  1291. args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
  1292. else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
  1293. args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
  1294. else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
  1295. args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
  1296. if (crev >= 3)
  1297. args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
  1298. } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
  1299. args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
  1300. if (crev >= 3)
  1301. args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
  1302. }
  1303. atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  1304. return true;
  1305. } else
  1306. return false;
  1307. }
  1308. static enum drm_connector_status
  1309. radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
  1310. {
  1311. struct drm_device *dev = encoder->dev;
  1312. struct radeon_device *rdev = dev->dev_private;
  1313. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1314. struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  1315. uint32_t bios_0_scratch;
  1316. if (!atombios_dac_load_detect(encoder, connector)) {
  1317. DRM_DEBUG_KMS("detect returned false \n");
  1318. return connector_status_unknown;
  1319. }
  1320. if (rdev->family >= CHIP_R600)
  1321. bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
  1322. else
  1323. bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
  1324. DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
  1325. if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
  1326. if (bios_0_scratch & ATOM_S0_CRT1_MASK)
  1327. return connector_status_connected;
  1328. }
  1329. if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
  1330. if (bios_0_scratch & ATOM_S0_CRT2_MASK)
  1331. return connector_status_connected;
  1332. }
  1333. if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
  1334. if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
  1335. return connector_status_connected;
  1336. }
  1337. if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
  1338. if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
  1339. return connector_status_connected; /* CTV */
  1340. else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
  1341. return connector_status_connected; /* STV */
  1342. }
  1343. return connector_status_disconnected;
  1344. }
  1345. static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
  1346. {
  1347. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1348. if (radeon_encoder->active_device &
  1349. (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
  1350. struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  1351. if (dig)
  1352. dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
  1353. }
  1354. radeon_atom_output_lock(encoder, true);
  1355. radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
  1356. /* this is needed for the pll/ss setup to work correctly in some cases */
  1357. atombios_set_encoder_crtc_source(encoder);
  1358. }
  1359. static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
  1360. {
  1361. radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
  1362. radeon_atom_output_lock(encoder, false);
  1363. }
  1364. static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
  1365. {
  1366. struct drm_device *dev = encoder->dev;
  1367. struct radeon_device *rdev = dev->dev_private;
  1368. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1369. struct radeon_encoder_atom_dig *dig;
  1370. radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
  1371. switch (radeon_encoder->encoder_id) {
  1372. case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
  1373. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
  1374. case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  1375. case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
  1376. atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
  1377. break;
  1378. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  1379. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  1380. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  1381. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
  1382. if (ASIC_IS_DCE4(rdev))
  1383. /* disable the transmitter */
  1384. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
  1385. else {
  1386. /* disable the encoder and transmitter */
  1387. atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
  1388. atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
  1389. }
  1390. break;
  1391. case ENCODER_OBJECT_ID_INTERNAL_DDI:
  1392. atombios_ddia_setup(encoder, ATOM_DISABLE);
  1393. break;
  1394. case ENCODER_OBJECT_ID_INTERNAL_DVO1:
  1395. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  1396. atombios_external_tmds_setup(encoder, ATOM_DISABLE);
  1397. break;
  1398. case ENCODER_OBJECT_ID_INTERNAL_DAC1:
  1399. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
  1400. case ENCODER_OBJECT_ID_INTERNAL_DAC2:
  1401. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
  1402. atombios_dac_setup(encoder, ATOM_DISABLE);
  1403. if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
  1404. atombios_tv_setup(encoder, ATOM_DISABLE);
  1405. break;
  1406. }
  1407. if (radeon_encoder_is_digital(encoder)) {
  1408. if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
  1409. r600_hdmi_disable(encoder);
  1410. dig = radeon_encoder->enc_priv;
  1411. dig->dig_encoder = -1;
  1412. }
  1413. radeon_encoder->active_device = 0;
  1414. }
  1415. static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
  1416. .dpms = radeon_atom_encoder_dpms,
  1417. .mode_fixup = radeon_atom_mode_fixup,
  1418. .prepare = radeon_atom_encoder_prepare,
  1419. .mode_set = radeon_atom_encoder_mode_set,
  1420. .commit = radeon_atom_encoder_commit,
  1421. .disable = radeon_atom_encoder_disable,
  1422. /* no detect for TMDS/LVDS yet */
  1423. };
  1424. static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
  1425. .dpms = radeon_atom_encoder_dpms,
  1426. .mode_fixup = radeon_atom_mode_fixup,
  1427. .prepare = radeon_atom_encoder_prepare,
  1428. .mode_set = radeon_atom_encoder_mode_set,
  1429. .commit = radeon_atom_encoder_commit,
  1430. .detect = radeon_atom_dac_detect,
  1431. };
  1432. void radeon_enc_destroy(struct drm_encoder *encoder)
  1433. {
  1434. struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1435. kfree(radeon_encoder->enc_priv);
  1436. drm_encoder_cleanup(encoder);
  1437. kfree(radeon_encoder);
  1438. }
  1439. static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
  1440. .destroy = radeon_enc_destroy,
  1441. };
  1442. struct radeon_encoder_atom_dac *
  1443. radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
  1444. {
  1445. struct drm_device *dev = radeon_encoder->base.dev;
  1446. struct radeon_device *rdev = dev->dev_private;
  1447. struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
  1448. if (!dac)
  1449. return NULL;
  1450. dac->tv_std = radeon_atombios_get_tv_info(rdev);
  1451. return dac;
  1452. }
  1453. struct radeon_encoder_atom_dig *
  1454. radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
  1455. {
  1456. int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
  1457. struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
  1458. if (!dig)
  1459. return NULL;
  1460. /* coherent mode by default */
  1461. dig->coherent_mode = true;
  1462. dig->dig_encoder = -1;
  1463. if (encoder_enum == 2)
  1464. dig->linkb = true;
  1465. else
  1466. dig->linkb = false;
  1467. return dig;
  1468. }
  1469. void
  1470. radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
  1471. {
  1472. struct radeon_device *rdev = dev->dev_private;
  1473. struct drm_encoder *encoder;
  1474. struct radeon_encoder *radeon_encoder;
  1475. /* see if we already added it */
  1476. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1477. radeon_encoder = to_radeon_encoder(encoder);
  1478. if (radeon_encoder->encoder_enum == encoder_enum) {
  1479. radeon_encoder->devices |= supported_device;
  1480. return;
  1481. }
  1482. }
  1483. /* add a new one */
  1484. radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
  1485. if (!radeon_encoder)
  1486. return;
  1487. encoder = &radeon_encoder->base;
  1488. switch (rdev->num_crtc) {
  1489. case 1:
  1490. encoder->possible_crtcs = 0x1;
  1491. break;
  1492. case 2:
  1493. default:
  1494. encoder->possible_crtcs = 0x3;
  1495. break;
  1496. case 6:
  1497. encoder->possible_crtcs = 0x3f;
  1498. break;
  1499. }
  1500. radeon_encoder->enc_priv = NULL;
  1501. radeon_encoder->encoder_enum = encoder_enum;
  1502. radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
  1503. radeon_encoder->devices = supported_device;
  1504. radeon_encoder->rmx_type = RMX_OFF;
  1505. radeon_encoder->underscan_type = UNDERSCAN_OFF;
  1506. switch (radeon_encoder->encoder_id) {
  1507. case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  1508. case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
  1509. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
  1510. case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
  1511. if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
  1512. radeon_encoder->rmx_type = RMX_FULL;
  1513. drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
  1514. radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
  1515. } else {
  1516. drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
  1517. radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
  1518. if (ASIC_IS_AVIVO(rdev))
  1519. radeon_encoder->underscan_type = UNDERSCAN_AUTO;
  1520. }
  1521. drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
  1522. break;
  1523. case ENCODER_OBJECT_ID_INTERNAL_DAC1:
  1524. drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
  1525. radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
  1526. drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
  1527. break;
  1528. case ENCODER_OBJECT_ID_INTERNAL_DAC2:
  1529. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
  1530. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
  1531. drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
  1532. radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
  1533. drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
  1534. break;
  1535. case ENCODER_OBJECT_ID_INTERNAL_DVO1:
  1536. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  1537. case ENCODER_OBJECT_ID_INTERNAL_DDI:
  1538. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  1539. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
  1540. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  1541. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  1542. if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
  1543. radeon_encoder->rmx_type = RMX_FULL;
  1544. drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
  1545. radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
  1546. } else {
  1547. drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
  1548. radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
  1549. if (ASIC_IS_AVIVO(rdev))
  1550. radeon_encoder->underscan_type = UNDERSCAN_AUTO;
  1551. }
  1552. drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
  1553. break;
  1554. }
  1555. }