i2c-omap.c 23 KB

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  1. /*
  2. * TI OMAP I2C master mode driver
  3. *
  4. * Copyright (C) 2003 MontaVista Software, Inc.
  5. * Copyright (C) 2004 Texas Instruments.
  6. *
  7. * Updated to work with multiple I2C interfaces on 24xx by
  8. * Tony Lindgren <tony@atomide.com> and Imre Deak <imre.deak@nokia.com>
  9. * Copyright (C) 2005 Nokia Corporation
  10. *
  11. * Cleaned up by Juha Yrjölä <juha.yrjola@nokia.com>
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License as published by
  15. * the Free Software Foundation; either version 2 of the License, or
  16. * (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26. */
  27. #include <linux/module.h>
  28. #include <linux/delay.h>
  29. #include <linux/i2c.h>
  30. #include <linux/err.h>
  31. #include <linux/interrupt.h>
  32. #include <linux/completion.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/clk.h>
  35. #include <asm/io.h>
  36. /* timeout waiting for the controller to respond */
  37. #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
  38. #define OMAP_I2C_REV_REG 0x00
  39. #define OMAP_I2C_IE_REG 0x04
  40. #define OMAP_I2C_STAT_REG 0x08
  41. #define OMAP_I2C_IV_REG 0x0c
  42. #define OMAP_I2C_SYSS_REG 0x10
  43. #define OMAP_I2C_BUF_REG 0x14
  44. #define OMAP_I2C_CNT_REG 0x18
  45. #define OMAP_I2C_DATA_REG 0x1c
  46. #define OMAP_I2C_SYSC_REG 0x20
  47. #define OMAP_I2C_CON_REG 0x24
  48. #define OMAP_I2C_OA_REG 0x28
  49. #define OMAP_I2C_SA_REG 0x2c
  50. #define OMAP_I2C_PSC_REG 0x30
  51. #define OMAP_I2C_SCLL_REG 0x34
  52. #define OMAP_I2C_SCLH_REG 0x38
  53. #define OMAP_I2C_SYSTEST_REG 0x3c
  54. #define OMAP_I2C_BUFSTAT_REG 0x40
  55. /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
  56. #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
  57. #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
  58. #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
  59. #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
  60. #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
  61. #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
  62. #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
  63. /* I2C Status Register (OMAP_I2C_STAT): */
  64. #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
  65. #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
  66. #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
  67. #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
  68. #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
  69. #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
  70. #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
  71. #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
  72. #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
  73. #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
  74. #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
  75. #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
  76. /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
  77. #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
  78. #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
  79. #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
  80. #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
  81. /* I2C Configuration Register (OMAP_I2C_CON): */
  82. #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
  83. #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
  84. #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
  85. #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
  86. #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
  87. #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
  88. #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
  89. #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
  90. #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
  91. #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
  92. /* I2C SCL time value when Master */
  93. #define OMAP_I2C_SCLL_HSSCLL 8
  94. #define OMAP_I2C_SCLH_HSSCLH 8
  95. /* I2C System Test Register (OMAP_I2C_SYSTEST): */
  96. #ifdef DEBUG
  97. #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
  98. #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
  99. #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
  100. #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
  101. #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
  102. #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
  103. #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
  104. #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
  105. #endif
  106. /* I2C System Status register (OMAP_I2C_SYSS): */
  107. #define OMAP_I2C_SYSS_RDONE (1 << 0) /* Reset Done */
  108. /* I2C System Configuration Register (OMAP_I2C_SYSC): */
  109. #define OMAP_I2C_SYSC_SRST (1 << 1) /* Soft Reset */
  110. struct omap_i2c_dev {
  111. struct device *dev;
  112. void __iomem *base; /* virtual */
  113. int irq;
  114. struct clk *iclk; /* Interface clock */
  115. struct clk *fclk; /* Functional clock */
  116. struct completion cmd_complete;
  117. struct resource *ioarea;
  118. u32 speed; /* Speed of bus in Khz */
  119. u16 cmd_err;
  120. u8 *buf;
  121. size_t buf_len;
  122. struct i2c_adapter adapter;
  123. u8 fifo_size; /* use as flag and value
  124. * fifo_size==0 implies no fifo
  125. * if set, should be trsh+1
  126. */
  127. unsigned rev1:1;
  128. unsigned b_hw:1; /* bad h/w fixes */
  129. unsigned idle:1;
  130. u16 iestate; /* Saved interrupt register */
  131. };
  132. static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
  133. int reg, u16 val)
  134. {
  135. __raw_writew(val, i2c_dev->base + reg);
  136. }
  137. static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
  138. {
  139. return __raw_readw(i2c_dev->base + reg);
  140. }
  141. static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
  142. {
  143. if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
  144. dev->iclk = clk_get(dev->dev, "i2c_ick");
  145. if (IS_ERR(dev->iclk)) {
  146. dev->iclk = NULL;
  147. return -ENODEV;
  148. }
  149. }
  150. dev->fclk = clk_get(dev->dev, "i2c_fck");
  151. if (IS_ERR(dev->fclk)) {
  152. if (dev->iclk != NULL) {
  153. clk_put(dev->iclk);
  154. dev->iclk = NULL;
  155. }
  156. dev->fclk = NULL;
  157. return -ENODEV;
  158. }
  159. return 0;
  160. }
  161. static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
  162. {
  163. clk_put(dev->fclk);
  164. dev->fclk = NULL;
  165. if (dev->iclk != NULL) {
  166. clk_put(dev->iclk);
  167. dev->iclk = NULL;
  168. }
  169. }
  170. static void omap_i2c_unidle(struct omap_i2c_dev *dev)
  171. {
  172. if (dev->iclk != NULL)
  173. clk_enable(dev->iclk);
  174. clk_enable(dev->fclk);
  175. dev->idle = 0;
  176. if (dev->iestate)
  177. omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
  178. }
  179. static void omap_i2c_idle(struct omap_i2c_dev *dev)
  180. {
  181. u16 iv;
  182. dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
  183. omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
  184. if (dev->rev1) {
  185. iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
  186. } else {
  187. omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
  188. /* Flush posted write before the dev->idle store occurs */
  189. omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
  190. }
  191. dev->idle = 1;
  192. clk_disable(dev->fclk);
  193. if (dev->iclk != NULL)
  194. clk_disable(dev->iclk);
  195. }
  196. static int omap_i2c_init(struct omap_i2c_dev *dev)
  197. {
  198. u16 psc = 0, scll = 0, sclh = 0;
  199. u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
  200. unsigned long fclk_rate = 12000000;
  201. unsigned long timeout;
  202. unsigned long internal_clk = 0;
  203. if (!dev->rev1) {
  204. omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
  205. /* For some reason we need to set the EN bit before the
  206. * reset done bit gets set. */
  207. timeout = jiffies + OMAP_I2C_TIMEOUT;
  208. omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
  209. while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
  210. OMAP_I2C_SYSS_RDONE)) {
  211. if (time_after(jiffies, timeout)) {
  212. dev_warn(dev->dev, "timeout waiting "
  213. "for controller reset\n");
  214. return -ETIMEDOUT;
  215. }
  216. msleep(1);
  217. }
  218. }
  219. omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
  220. if (cpu_class_is_omap1()) {
  221. struct clk *armxor_ck;
  222. armxor_ck = clk_get(NULL, "armxor_ck");
  223. if (IS_ERR(armxor_ck))
  224. dev_warn(dev->dev, "Could not get armxor_ck\n");
  225. else {
  226. fclk_rate = clk_get_rate(armxor_ck);
  227. clk_put(armxor_ck);
  228. }
  229. /* TRM for 5912 says the I2C clock must be prescaled to be
  230. * between 7 - 12 MHz. The XOR input clock is typically
  231. * 12, 13 or 19.2 MHz. So we should have code that produces:
  232. *
  233. * XOR MHz Divider Prescaler
  234. * 12 1 0
  235. * 13 2 1
  236. * 19.2 2 1
  237. */
  238. if (fclk_rate > 12000000)
  239. psc = fclk_rate / 12000000;
  240. }
  241. if (cpu_is_omap2430() || cpu_is_omap34xx()) {
  242. /* HSI2C controller internal clk rate should be 19.2 Mhz */
  243. internal_clk = 19200;
  244. fclk_rate = clk_get_rate(dev->fclk) / 1000;
  245. /* Compute prescaler divisor */
  246. psc = fclk_rate / internal_clk;
  247. psc = psc - 1;
  248. /* If configured for High Speed */
  249. if (dev->speed > 400) {
  250. /* For first phase of HS mode */
  251. fsscll = internal_clk / (400 * 2) - 6;
  252. fssclh = internal_clk / (400 * 2) - 6;
  253. /* For second phase of HS mode */
  254. hsscll = fclk_rate / (dev->speed * 2) - 6;
  255. hssclh = fclk_rate / (dev->speed * 2) - 6;
  256. } else {
  257. /* To handle F/S modes */
  258. fsscll = internal_clk / (dev->speed * 2) - 6;
  259. fssclh = internal_clk / (dev->speed * 2) - 6;
  260. }
  261. scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
  262. sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
  263. } else {
  264. /* Program desired operating rate */
  265. fclk_rate /= (psc + 1) * 1000;
  266. if (psc > 2)
  267. psc = 2;
  268. scll = fclk_rate / (dev->speed * 2) - 7 + psc;
  269. sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
  270. }
  271. /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
  272. omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
  273. /* SCL low and high time values */
  274. omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
  275. omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
  276. if (dev->fifo_size)
  277. /* Note: setup required fifo size - 1 */
  278. omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
  279. (dev->fifo_size - 1) << 8 | /* RTRSH */
  280. OMAP_I2C_BUF_RXFIF_CLR |
  281. (dev->fifo_size - 1) | /* XTRSH */
  282. OMAP_I2C_BUF_TXFIF_CLR);
  283. /* Take the I2C module out of reset: */
  284. omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
  285. /* Enable interrupts */
  286. omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
  287. (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
  288. OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
  289. OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
  290. (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
  291. return 0;
  292. }
  293. /*
  294. * Waiting on Bus Busy
  295. */
  296. static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
  297. {
  298. unsigned long timeout;
  299. timeout = jiffies + OMAP_I2C_TIMEOUT;
  300. while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
  301. if (time_after(jiffies, timeout)) {
  302. dev_warn(dev->dev, "timeout waiting for bus ready\n");
  303. return -ETIMEDOUT;
  304. }
  305. msleep(1);
  306. }
  307. return 0;
  308. }
  309. /*
  310. * Low level master read/write transaction.
  311. */
  312. static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
  313. struct i2c_msg *msg, int stop)
  314. {
  315. struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
  316. int r;
  317. u16 w;
  318. dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
  319. msg->addr, msg->len, msg->flags, stop);
  320. if (msg->len == 0)
  321. return -EINVAL;
  322. omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
  323. /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
  324. dev->buf = msg->buf;
  325. dev->buf_len = msg->len;
  326. omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
  327. /* Clear the FIFO Buffers */
  328. w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
  329. w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
  330. omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
  331. init_completion(&dev->cmd_complete);
  332. dev->cmd_err = 0;
  333. w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
  334. /* High speed configuration */
  335. if (dev->speed > 400)
  336. w |= OMAP_I2C_CON_OPMODE_HS;
  337. if (msg->flags & I2C_M_TEN)
  338. w |= OMAP_I2C_CON_XA;
  339. if (!(msg->flags & I2C_M_RD))
  340. w |= OMAP_I2C_CON_TRX;
  341. if (!dev->b_hw && stop)
  342. w |= OMAP_I2C_CON_STP;
  343. omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
  344. /*
  345. * Don't write stt and stp together on some hardware.
  346. */
  347. if (dev->b_hw && stop) {
  348. unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
  349. u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
  350. while (con & OMAP_I2C_CON_STT) {
  351. con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
  352. /* Let the user know if i2c is in a bad state */
  353. if (time_after(jiffies, delay)) {
  354. dev_err(dev->dev, "controller timed out "
  355. "waiting for start condition to finish\n");
  356. return -ETIMEDOUT;
  357. }
  358. cpu_relax();
  359. }
  360. w |= OMAP_I2C_CON_STP;
  361. w &= ~OMAP_I2C_CON_STT;
  362. omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
  363. }
  364. /*
  365. * REVISIT: We should abort the transfer on signals, but the bus goes
  366. * into arbitration and we're currently unable to recover from it.
  367. */
  368. r = wait_for_completion_timeout(&dev->cmd_complete,
  369. OMAP_I2C_TIMEOUT);
  370. dev->buf_len = 0;
  371. if (r < 0)
  372. return r;
  373. if (r == 0) {
  374. dev_err(dev->dev, "controller timed out\n");
  375. omap_i2c_init(dev);
  376. return -ETIMEDOUT;
  377. }
  378. if (likely(!dev->cmd_err))
  379. return 0;
  380. /* We have an error */
  381. if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
  382. OMAP_I2C_STAT_XUDF)) {
  383. omap_i2c_init(dev);
  384. return -EIO;
  385. }
  386. if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
  387. if (msg->flags & I2C_M_IGNORE_NAK)
  388. return 0;
  389. if (stop) {
  390. w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
  391. w |= OMAP_I2C_CON_STP;
  392. omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
  393. }
  394. return -EREMOTEIO;
  395. }
  396. return -EIO;
  397. }
  398. /*
  399. * Prepare controller for a transaction and call omap_i2c_xfer_msg
  400. * to do the work during IRQ processing.
  401. */
  402. static int
  403. omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
  404. {
  405. struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
  406. int i;
  407. int r;
  408. omap_i2c_unidle(dev);
  409. if ((r = omap_i2c_wait_for_bb(dev)) < 0)
  410. goto out;
  411. for (i = 0; i < num; i++) {
  412. r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
  413. if (r != 0)
  414. break;
  415. }
  416. if (r == 0)
  417. r = num;
  418. out:
  419. omap_i2c_idle(dev);
  420. return r;
  421. }
  422. static u32
  423. omap_i2c_func(struct i2c_adapter *adap)
  424. {
  425. return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
  426. }
  427. static inline void
  428. omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
  429. {
  430. dev->cmd_err |= err;
  431. complete(&dev->cmd_complete);
  432. }
  433. static inline void
  434. omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
  435. {
  436. omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
  437. }
  438. static irqreturn_t
  439. omap_i2c_rev1_isr(int this_irq, void *dev_id)
  440. {
  441. struct omap_i2c_dev *dev = dev_id;
  442. u16 iv, w;
  443. if (dev->idle)
  444. return IRQ_NONE;
  445. iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
  446. switch (iv) {
  447. case 0x00: /* None */
  448. break;
  449. case 0x01: /* Arbitration lost */
  450. dev_err(dev->dev, "Arbitration lost\n");
  451. omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
  452. break;
  453. case 0x02: /* No acknowledgement */
  454. omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
  455. omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
  456. break;
  457. case 0x03: /* Register access ready */
  458. omap_i2c_complete_cmd(dev, 0);
  459. break;
  460. case 0x04: /* Receive data ready */
  461. if (dev->buf_len) {
  462. w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
  463. *dev->buf++ = w;
  464. dev->buf_len--;
  465. if (dev->buf_len) {
  466. *dev->buf++ = w >> 8;
  467. dev->buf_len--;
  468. }
  469. } else
  470. dev_err(dev->dev, "RRDY IRQ while no data requested\n");
  471. break;
  472. case 0x05: /* Transmit data ready */
  473. if (dev->buf_len) {
  474. w = *dev->buf++;
  475. dev->buf_len--;
  476. if (dev->buf_len) {
  477. w |= *dev->buf++ << 8;
  478. dev->buf_len--;
  479. }
  480. omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
  481. } else
  482. dev_err(dev->dev, "XRDY IRQ while no data to send\n");
  483. break;
  484. default:
  485. return IRQ_NONE;
  486. }
  487. return IRQ_HANDLED;
  488. }
  489. static irqreturn_t
  490. omap_i2c_isr(int this_irq, void *dev_id)
  491. {
  492. struct omap_i2c_dev *dev = dev_id;
  493. u16 bits;
  494. u16 stat, w;
  495. int err, count = 0;
  496. if (dev->idle)
  497. return IRQ_NONE;
  498. bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
  499. while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
  500. dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
  501. if (count++ == 100) {
  502. dev_warn(dev->dev, "Too much work in one IRQ\n");
  503. break;
  504. }
  505. omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
  506. err = 0;
  507. if (stat & OMAP_I2C_STAT_NACK) {
  508. err |= OMAP_I2C_STAT_NACK;
  509. omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
  510. OMAP_I2C_CON_STP);
  511. }
  512. if (stat & OMAP_I2C_STAT_AL) {
  513. dev_err(dev->dev, "Arbitration lost\n");
  514. err |= OMAP_I2C_STAT_AL;
  515. }
  516. if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
  517. OMAP_I2C_STAT_AL))
  518. omap_i2c_complete_cmd(dev, err);
  519. if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
  520. u8 num_bytes = 1;
  521. if (dev->fifo_size) {
  522. if (stat & OMAP_I2C_STAT_RRDY)
  523. num_bytes = dev->fifo_size;
  524. else
  525. num_bytes = omap_i2c_read_reg(dev,
  526. OMAP_I2C_BUFSTAT_REG);
  527. }
  528. while (num_bytes) {
  529. num_bytes--;
  530. w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
  531. if (dev->buf_len) {
  532. *dev->buf++ = w;
  533. dev->buf_len--;
  534. /* Data reg from 2430 is 8 bit wide */
  535. if (!cpu_is_omap2430() &&
  536. !cpu_is_omap34xx()) {
  537. if (dev->buf_len) {
  538. *dev->buf++ = w >> 8;
  539. dev->buf_len--;
  540. }
  541. }
  542. } else {
  543. if (stat & OMAP_I2C_STAT_RRDY)
  544. dev_err(dev->dev,
  545. "RRDY IRQ while no data"
  546. " requested\n");
  547. if (stat & OMAP_I2C_STAT_RDR)
  548. dev_err(dev->dev,
  549. "RDR IRQ while no data"
  550. " requested\n");
  551. break;
  552. }
  553. }
  554. omap_i2c_ack_stat(dev,
  555. stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
  556. continue;
  557. }
  558. if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
  559. u8 num_bytes = 1;
  560. if (dev->fifo_size) {
  561. if (stat & OMAP_I2C_STAT_XRDY)
  562. num_bytes = dev->fifo_size;
  563. else
  564. num_bytes = omap_i2c_read_reg(dev,
  565. OMAP_I2C_BUFSTAT_REG);
  566. }
  567. while (num_bytes) {
  568. num_bytes--;
  569. w = 0;
  570. if (dev->buf_len) {
  571. w = *dev->buf++;
  572. dev->buf_len--;
  573. /* Data reg from 2430 is 8 bit wide */
  574. if (!cpu_is_omap2430() &&
  575. !cpu_is_omap34xx()) {
  576. if (dev->buf_len) {
  577. w |= *dev->buf++ << 8;
  578. dev->buf_len--;
  579. }
  580. }
  581. } else {
  582. if (stat & OMAP_I2C_STAT_XRDY)
  583. dev_err(dev->dev,
  584. "XRDY IRQ while no "
  585. "data to send\n");
  586. if (stat & OMAP_I2C_STAT_XDR)
  587. dev_err(dev->dev,
  588. "XDR IRQ while no "
  589. "data to send\n");
  590. break;
  591. }
  592. omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
  593. }
  594. omap_i2c_ack_stat(dev,
  595. stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
  596. continue;
  597. }
  598. if (stat & OMAP_I2C_STAT_ROVR) {
  599. dev_err(dev->dev, "Receive overrun\n");
  600. dev->cmd_err |= OMAP_I2C_STAT_ROVR;
  601. }
  602. if (stat & OMAP_I2C_STAT_XUDF) {
  603. dev_err(dev->dev, "Transmit underflow\n");
  604. dev->cmd_err |= OMAP_I2C_STAT_XUDF;
  605. }
  606. }
  607. return count ? IRQ_HANDLED : IRQ_NONE;
  608. }
  609. static const struct i2c_algorithm omap_i2c_algo = {
  610. .master_xfer = omap_i2c_xfer,
  611. .functionality = omap_i2c_func,
  612. };
  613. static int __init
  614. omap_i2c_probe(struct platform_device *pdev)
  615. {
  616. struct omap_i2c_dev *dev;
  617. struct i2c_adapter *adap;
  618. struct resource *mem, *irq, *ioarea;
  619. int r;
  620. u32 speed = 0;
  621. /* NOTE: driver uses the static register mapping */
  622. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  623. if (!mem) {
  624. dev_err(&pdev->dev, "no mem resource?\n");
  625. return -ENODEV;
  626. }
  627. irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  628. if (!irq) {
  629. dev_err(&pdev->dev, "no irq resource?\n");
  630. return -ENODEV;
  631. }
  632. ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
  633. pdev->name);
  634. if (!ioarea) {
  635. dev_err(&pdev->dev, "I2C region already claimed\n");
  636. return -EBUSY;
  637. }
  638. dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
  639. if (!dev) {
  640. r = -ENOMEM;
  641. goto err_release_region;
  642. }
  643. if (pdev->dev.platform_data != NULL)
  644. speed = *(u32 *)pdev->dev.platform_data;
  645. else
  646. speed = 100; /* Defualt speed */
  647. dev->speed = speed;
  648. dev->dev = &pdev->dev;
  649. dev->irq = irq->start;
  650. dev->base = ioremap(mem->start, mem->end - mem->start + 1);
  651. if (!dev->base) {
  652. r = -ENOMEM;
  653. goto err_free_mem;
  654. }
  655. platform_set_drvdata(pdev, dev);
  656. if ((r = omap_i2c_get_clocks(dev)) != 0)
  657. goto err_iounmap;
  658. omap_i2c_unidle(dev);
  659. if (cpu_is_omap15xx())
  660. dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20;
  661. if (cpu_is_omap2430() || cpu_is_omap34xx()) {
  662. u16 s;
  663. /* Set up the fifo size - Get total size */
  664. s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
  665. dev->fifo_size = 0x8 << s;
  666. /*
  667. * Set up notification threshold as half the total available
  668. * size. This is to ensure that we can handle the status on int
  669. * call back latencies.
  670. */
  671. dev->fifo_size = (dev->fifo_size / 2);
  672. dev->b_hw = 1; /* Enable hardware fixes */
  673. }
  674. /* reset ASAP, clearing any IRQs */
  675. omap_i2c_init(dev);
  676. r = request_irq(dev->irq, dev->rev1 ? omap_i2c_rev1_isr : omap_i2c_isr,
  677. 0, pdev->name, dev);
  678. if (r) {
  679. dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
  680. goto err_unuse_clocks;
  681. }
  682. r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
  683. dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
  684. pdev->id, r >> 4, r & 0xf, dev->speed);
  685. adap = &dev->adapter;
  686. i2c_set_adapdata(adap, dev);
  687. adap->owner = THIS_MODULE;
  688. adap->class = I2C_CLASS_HWMON;
  689. strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
  690. adap->algo = &omap_i2c_algo;
  691. adap->dev.parent = &pdev->dev;
  692. /* i2c device drivers may be active on return from add_adapter() */
  693. adap->nr = pdev->id;
  694. r = i2c_add_numbered_adapter(adap);
  695. if (r) {
  696. dev_err(dev->dev, "failure adding adapter\n");
  697. goto err_free_irq;
  698. }
  699. omap_i2c_idle(dev);
  700. return 0;
  701. err_free_irq:
  702. free_irq(dev->irq, dev);
  703. err_unuse_clocks:
  704. omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
  705. omap_i2c_idle(dev);
  706. omap_i2c_put_clocks(dev);
  707. err_iounmap:
  708. iounmap(dev->base);
  709. err_free_mem:
  710. platform_set_drvdata(pdev, NULL);
  711. kfree(dev);
  712. err_release_region:
  713. release_mem_region(mem->start, (mem->end - mem->start) + 1);
  714. return r;
  715. }
  716. static int
  717. omap_i2c_remove(struct platform_device *pdev)
  718. {
  719. struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
  720. struct resource *mem;
  721. platform_set_drvdata(pdev, NULL);
  722. free_irq(dev->irq, dev);
  723. i2c_del_adapter(&dev->adapter);
  724. omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
  725. omap_i2c_put_clocks(dev);
  726. iounmap(dev->base);
  727. kfree(dev);
  728. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  729. release_mem_region(mem->start, (mem->end - mem->start) + 1);
  730. return 0;
  731. }
  732. static struct platform_driver omap_i2c_driver = {
  733. .probe = omap_i2c_probe,
  734. .remove = omap_i2c_remove,
  735. .driver = {
  736. .name = "i2c_omap",
  737. .owner = THIS_MODULE,
  738. },
  739. };
  740. /* I2C may be needed to bring up other drivers */
  741. static int __init
  742. omap_i2c_init_driver(void)
  743. {
  744. return platform_driver_register(&omap_i2c_driver);
  745. }
  746. subsys_initcall(omap_i2c_init_driver);
  747. static void __exit omap_i2c_exit_driver(void)
  748. {
  749. platform_driver_unregister(&omap_i2c_driver);
  750. }
  751. module_exit(omap_i2c_exit_driver);
  752. MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
  753. MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
  754. MODULE_LICENSE("GPL");
  755. MODULE_ALIAS("platform:i2c_omap");