pxa2xx-i2s.c 6.8 KB

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  1. /*
  2. * pxa2xx-i2s.c -- ALSA Soc Audio Layer
  3. *
  4. * Copyright 2005 Wolfson Microelectronics PLC.
  5. * Author: Liam Girdwood
  6. * liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. #include <linux/init.h>
  14. #include <linux/module.h>
  15. #include <linux/device.h>
  16. #include <linux/delay.h>
  17. #include <linux/clk.h>
  18. #include <sound/core.h>
  19. #include <sound/pcm.h>
  20. #include <sound/initval.h>
  21. #include <sound/soc.h>
  22. #include <asm/hardware.h>
  23. #include <asm/arch/pxa-regs.h>
  24. #include <asm/arch/pxa2xx-gpio.h>
  25. #include <asm/arch/audio.h>
  26. #include "pxa2xx-pcm.h"
  27. #include "pxa2xx-i2s.h"
  28. struct pxa_i2s_port {
  29. u32 sadiv;
  30. u32 sacr0;
  31. u32 sacr1;
  32. u32 saimr;
  33. int master;
  34. u32 fmt;
  35. };
  36. static struct pxa_i2s_port pxa_i2s;
  37. static struct clk *clk_i2s;
  38. static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
  39. .name = "I2S PCM Stereo out",
  40. .dev_addr = __PREG(SADR),
  41. .drcmr = &DRCMRTXSADR,
  42. .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
  43. DCMD_BURST32 | DCMD_WIDTH4,
  44. };
  45. static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_in = {
  46. .name = "I2S PCM Stereo in",
  47. .dev_addr = __PREG(SADR),
  48. .drcmr = &DRCMRRXSADR,
  49. .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
  50. DCMD_BURST32 | DCMD_WIDTH4,
  51. };
  52. static struct pxa2xx_gpio gpio_bus[] = {
  53. { /* I2S SoC Slave */
  54. .rx = GPIO29_SDATA_IN_I2S_MD,
  55. .tx = GPIO30_SDATA_OUT_I2S_MD,
  56. .clk = GPIO28_BITCLK_IN_I2S_MD,
  57. .frm = GPIO31_SYNC_I2S_MD,
  58. },
  59. { /* I2S SoC Master */
  60. #ifdef CONFIG_PXA27x
  61. .sys = GPIO113_I2S_SYSCLK_MD,
  62. #else
  63. .sys = GPIO32_SYSCLK_I2S_MD,
  64. #endif
  65. .rx = GPIO29_SDATA_IN_I2S_MD,
  66. .tx = GPIO30_SDATA_OUT_I2S_MD,
  67. .clk = GPIO28_BITCLK_OUT_I2S_MD,
  68. .frm = GPIO31_SYNC_I2S_MD,
  69. },
  70. };
  71. static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream)
  72. {
  73. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  74. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  75. clk_i2s = clk_get(NULL, "I2SCLK");
  76. if (IS_ERR(clk_i2s))
  77. return PTR_ERR(clk_i2s);
  78. if (!cpu_dai->active) {
  79. SACR0 |= SACR0_RST;
  80. SACR0 = 0;
  81. }
  82. return 0;
  83. }
  84. /* wait for I2S controller to be ready */
  85. static int pxa_i2s_wait(void)
  86. {
  87. int i;
  88. /* flush the Rx FIFO */
  89. for(i = 0; i < 16; i++)
  90. SADR;
  91. return 0;
  92. }
  93. static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
  94. unsigned int fmt)
  95. {
  96. /* interface format */
  97. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  98. case SND_SOC_DAIFMT_I2S:
  99. pxa_i2s.fmt = 0;
  100. break;
  101. case SND_SOC_DAIFMT_LEFT_J:
  102. pxa_i2s.fmt = SACR1_AMSL;
  103. break;
  104. }
  105. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  106. case SND_SOC_DAIFMT_CBS_CFS:
  107. pxa_i2s.master = 1;
  108. break;
  109. case SND_SOC_DAIFMT_CBM_CFS:
  110. pxa_i2s.master = 0;
  111. break;
  112. default:
  113. break;
  114. }
  115. return 0;
  116. }
  117. static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
  118. int clk_id, unsigned int freq, int dir)
  119. {
  120. if (clk_id != PXA2XX_I2S_SYSCLK)
  121. return -ENODEV;
  122. if (pxa_i2s.master && dir == SND_SOC_CLOCK_OUT)
  123. pxa_gpio_mode(gpio_bus[pxa_i2s.master].sys);
  124. return 0;
  125. }
  126. static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
  127. struct snd_pcm_hw_params *params)
  128. {
  129. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  130. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  131. pxa_gpio_mode(gpio_bus[pxa_i2s.master].rx);
  132. pxa_gpio_mode(gpio_bus[pxa_i2s.master].tx);
  133. pxa_gpio_mode(gpio_bus[pxa_i2s.master].frm);
  134. pxa_gpio_mode(gpio_bus[pxa_i2s.master].clk);
  135. clk_enable(clk_i2s);
  136. pxa_i2s_wait();
  137. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  138. cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_out;
  139. else
  140. cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_in;
  141. /* is port used by another stream */
  142. if (!(SACR0 & SACR0_ENB)) {
  143. SACR0 = 0;
  144. SACR1 = 0;
  145. if (pxa_i2s.master)
  146. SACR0 |= SACR0_BCKD;
  147. SACR0 |= SACR0_RFTH(14) | SACR0_TFTH(1);
  148. SACR1 |= pxa_i2s.fmt;
  149. }
  150. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  151. SAIMR |= SAIMR_TFS;
  152. else
  153. SAIMR |= SAIMR_RFS;
  154. switch (params_rate(params)) {
  155. case 8000:
  156. SADIV = 0x48;
  157. break;
  158. case 11025:
  159. SADIV = 0x34;
  160. break;
  161. case 16000:
  162. SADIV = 0x24;
  163. break;
  164. case 22050:
  165. SADIV = 0x1a;
  166. break;
  167. case 44100:
  168. SADIV = 0xd;
  169. break;
  170. case 48000:
  171. SADIV = 0xc;
  172. break;
  173. case 96000: /* not in manual and possibly slightly inaccurate */
  174. SADIV = 0x6;
  175. break;
  176. }
  177. return 0;
  178. }
  179. static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
  180. {
  181. int ret = 0;
  182. switch (cmd) {
  183. case SNDRV_PCM_TRIGGER_START:
  184. SACR0 |= SACR0_ENB;
  185. break;
  186. case SNDRV_PCM_TRIGGER_RESUME:
  187. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  188. case SNDRV_PCM_TRIGGER_STOP:
  189. case SNDRV_PCM_TRIGGER_SUSPEND:
  190. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  191. break;
  192. default:
  193. ret = -EINVAL;
  194. }
  195. return ret;
  196. }
  197. static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream)
  198. {
  199. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  200. SACR1 |= SACR1_DRPL;
  201. SAIMR &= ~SAIMR_TFS;
  202. } else {
  203. SACR1 |= SACR1_DREC;
  204. SAIMR &= ~SAIMR_RFS;
  205. }
  206. if (SACR1 & (SACR1_DREC | SACR1_DRPL)) {
  207. SACR0 &= ~SACR0_ENB;
  208. pxa_i2s_wait();
  209. clk_disable(clk_i2s);
  210. }
  211. clk_put(clk_i2s);
  212. }
  213. #ifdef CONFIG_PM
  214. static int pxa2xx_i2s_suspend(struct platform_device *dev,
  215. struct snd_soc_dai *dai)
  216. {
  217. if (!dai->active)
  218. return 0;
  219. /* store registers */
  220. pxa_i2s.sacr0 = SACR0;
  221. pxa_i2s.sacr1 = SACR1;
  222. pxa_i2s.saimr = SAIMR;
  223. pxa_i2s.sadiv = SADIV;
  224. /* deactivate link */
  225. SACR0 &= ~SACR0_ENB;
  226. pxa_i2s_wait();
  227. return 0;
  228. }
  229. static int pxa2xx_i2s_resume(struct platform_device *pdev,
  230. struct snd_soc_dai *dai)
  231. {
  232. if (!dai->active)
  233. return 0;
  234. pxa_i2s_wait();
  235. SACR0 = pxa_i2s.sacr0 &= ~SACR0_ENB;
  236. SACR1 = pxa_i2s.sacr1;
  237. SAIMR = pxa_i2s.saimr;
  238. SADIV = pxa_i2s.sadiv;
  239. SACR0 |= SACR0_ENB;
  240. return 0;
  241. }
  242. #else
  243. #define pxa2xx_i2s_suspend NULL
  244. #define pxa2xx_i2s_resume NULL
  245. #endif
  246. #define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
  247. SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
  248. SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
  249. struct snd_soc_dai pxa_i2s_dai = {
  250. .name = "pxa2xx-i2s",
  251. .id = 0,
  252. .type = SND_SOC_DAI_I2S,
  253. .suspend = pxa2xx_i2s_suspend,
  254. .resume = pxa2xx_i2s_resume,
  255. .playback = {
  256. .channels_min = 2,
  257. .channels_max = 2,
  258. .rates = PXA2XX_I2S_RATES,
  259. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  260. .capture = {
  261. .channels_min = 2,
  262. .channels_max = 2,
  263. .rates = PXA2XX_I2S_RATES,
  264. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  265. .ops = {
  266. .startup = pxa2xx_i2s_startup,
  267. .shutdown = pxa2xx_i2s_shutdown,
  268. .trigger = pxa2xx_i2s_trigger,
  269. .hw_params = pxa2xx_i2s_hw_params,},
  270. .dai_ops = {
  271. .set_fmt = pxa2xx_i2s_set_dai_fmt,
  272. .set_sysclk = pxa2xx_i2s_set_dai_sysclk,
  273. },
  274. };
  275. EXPORT_SYMBOL_GPL(pxa_i2s_dai);
  276. /* Module information */
  277. MODULE_AUTHOR("Liam Girdwood, liam.girdwood@wolfsonmicro.com, www.wolfsonmicro.com");
  278. MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
  279. MODULE_LICENSE("GPL");