gdth.c 174 KB

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  1. /************************************************************************
  2. * Linux driver for *
  3. * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
  4. * Intel Corporation: Storage RAID Controllers *
  5. * *
  6. * gdth.c *
  7. * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
  8. * Copyright (C) 2002-04 Intel Corporation *
  9. * Copyright (C) 2003-06 Adaptec Inc. *
  10. * <achim_leubner@adaptec.com> *
  11. * *
  12. * Additions/Fixes: *
  13. * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
  14. * Johannes Dinner <johannes_dinner@adaptec.com> *
  15. * *
  16. * This program is free software; you can redistribute it and/or modify *
  17. * it under the terms of the GNU General Public License as published *
  18. * by the Free Software Foundation; either version 2 of the License, *
  19. * or (at your option) any later version. *
  20. * *
  21. * This program is distributed in the hope that it will be useful, *
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  24. * GNU General Public License for more details. *
  25. * *
  26. * You should have received a copy of the GNU General Public License *
  27. * along with this kernel; if not, write to the Free Software *
  28. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  29. * *
  30. * Linux kernel 2.6.x supported *
  31. * *
  32. ************************************************************************/
  33. /* All GDT Disk Array Controllers are fully supported by this driver.
  34. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
  35. * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
  36. * list of all controller types.
  37. *
  38. * If you have one or more GDT3000/3020 EISA controllers with
  39. * controller BIOS disabled, you have to set the IRQ values with the
  40. * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
  41. * the IRQ values for the EISA controllers.
  42. *
  43. * After the optional list of IRQ values, other possible
  44. * command line options are:
  45. * disable:Y disable driver
  46. * disable:N enable driver
  47. * reserve_mode:0 reserve no drives for the raw service
  48. * reserve_mode:1 reserve all not init., removable drives
  49. * reserve_mode:2 reserve all not init. drives
  50. * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
  51. * h- controller no., b- channel no.,
  52. * t- target ID, l- LUN
  53. * reverse_scan:Y reverse scan order for PCI controllers
  54. * reverse_scan:N scan PCI controllers like BIOS
  55. * max_ids:x x - target ID count per channel (1..MAXID)
  56. * rescan:Y rescan all channels/IDs
  57. * rescan:N use all devices found until now
  58. * hdr_channel:x x - number of virtual bus for host drives
  59. * shared_access:Y disable driver reserve/release protocol to
  60. * access a shared resource from several nodes,
  61. * appropriate controller firmware required
  62. * shared_access:N enable driver reserve/release protocol
  63. * probe_eisa_isa:Y scan for EISA/ISA controllers
  64. * probe_eisa_isa:N do not scan for EISA/ISA controllers
  65. * force_dma32:Y use only 32 bit DMA mode
  66. * force_dma32:N use 64 bit DMA mode, if supported
  67. *
  68. * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
  69. * max_ids:127,rescan:N,hdr_channel:0,
  70. * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
  71. * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
  72. *
  73. * When loading the gdth driver as a module, the same options are available.
  74. * You can set the IRQs with "IRQ=...". However, the syntax to specify the
  75. * options changes slightly. You must replace all ',' between options
  76. * with ' ' and all ':' with '=' and you must use
  77. * '1' in place of 'Y' and '0' in place of 'N'.
  78. *
  79. * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
  80. * max_ids=127 rescan=0 hdr_channel=0 shared_access=0
  81. * probe_eisa_isa=0 force_dma32=0"
  82. * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
  83. */
  84. /* The meaning of the Scsi_Pointer members in this driver is as follows:
  85. * ptr: Chaining
  86. * this_residual: unused
  87. * buffer: unused
  88. * dma_handle: unused
  89. * buffers_residual: unused
  90. * Status: unused
  91. * Message: unused
  92. * have_data_in: unused
  93. * sent_command: unused
  94. * phase: unused
  95. */
  96. /* interrupt coalescing */
  97. /* #define INT_COAL */
  98. /* statistics */
  99. #define GDTH_STATISTICS
  100. #include <linux/module.h>
  101. #include <linux/version.h>
  102. #include <linux/kernel.h>
  103. #include <linux/types.h>
  104. #include <linux/pci.h>
  105. #include <linux/string.h>
  106. #include <linux/ctype.h>
  107. #include <linux/ioport.h>
  108. #include <linux/delay.h>
  109. #include <linux/interrupt.h>
  110. #include <linux/in.h>
  111. #include <linux/proc_fs.h>
  112. #include <linux/time.h>
  113. #include <linux/timer.h>
  114. #include <linux/dma-mapping.h>
  115. #include <linux/list.h>
  116. #include <linux/smp_lock.h>
  117. #ifdef GDTH_RTC
  118. #include <linux/mc146818rtc.h>
  119. #endif
  120. #include <linux/reboot.h>
  121. #include <asm/dma.h>
  122. #include <asm/system.h>
  123. #include <asm/io.h>
  124. #include <asm/uaccess.h>
  125. #include <linux/spinlock.h>
  126. #include <linux/blkdev.h>
  127. #include <linux/scatterlist.h>
  128. #include "scsi.h"
  129. #include <scsi/scsi_host.h>
  130. #include "gdth.h"
  131. static void gdth_delay(int milliseconds);
  132. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
  133. static irqreturn_t gdth_interrupt(int irq, void *dev_id);
  134. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
  135. int gdth_from_wait, int* pIndex);
  136. static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
  137. Scsi_Cmnd *scp);
  138. static int gdth_async_event(gdth_ha_str *ha);
  139. static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
  140. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority);
  141. static void gdth_next(gdth_ha_str *ha);
  142. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b);
  143. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  144. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  145. ushort idx, gdth_evt_data *evt);
  146. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
  147. static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
  148. gdth_evt_str *estr);
  149. static void gdth_clear_events(void);
  150. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  151. char *buffer, ushort count);
  152. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp);
  153. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive);
  154. static void gdth_enable_int(gdth_ha_str *ha);
  155. static int gdth_test_busy(gdth_ha_str *ha);
  156. static int gdth_get_cmd_index(gdth_ha_str *ha);
  157. static void gdth_release_event(gdth_ha_str *ha);
  158. static int gdth_wait(gdth_ha_str *ha, int index,ulong32 time);
  159. static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
  160. ulong32 p1, ulong64 p2,ulong64 p3);
  161. static int gdth_search_drives(gdth_ha_str *ha);
  162. static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive);
  163. static const char *gdth_ctr_name(gdth_ha_str *ha);
  164. static int gdth_open(struct inode *inode, struct file *filep);
  165. static int gdth_close(struct inode *inode, struct file *filep);
  166. static int gdth_ioctl(struct inode *inode, struct file *filep,
  167. unsigned int cmd, unsigned long arg);
  168. static void gdth_flush(gdth_ha_str *ha);
  169. static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
  170. static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
  171. struct gdth_cmndinfo *cmndinfo);
  172. static void gdth_scsi_done(struct scsi_cmnd *scp);
  173. #ifdef DEBUG_GDTH
  174. static unchar DebugState = DEBUG_GDTH;
  175. #ifdef __SERIAL__
  176. #define MAX_SERBUF 160
  177. static void ser_init(void);
  178. static void ser_puts(char *str);
  179. static void ser_putc(char c);
  180. static int ser_printk(const char *fmt, ...);
  181. static char strbuf[MAX_SERBUF+1];
  182. #ifdef __COM2__
  183. #define COM_BASE 0x2f8
  184. #else
  185. #define COM_BASE 0x3f8
  186. #endif
  187. static void ser_init()
  188. {
  189. unsigned port=COM_BASE;
  190. outb(0x80,port+3);
  191. outb(0,port+1);
  192. /* 19200 Baud, if 9600: outb(12,port) */
  193. outb(6, port);
  194. outb(3,port+3);
  195. outb(0,port+1);
  196. /*
  197. ser_putc('I');
  198. ser_putc(' ');
  199. */
  200. }
  201. static void ser_puts(char *str)
  202. {
  203. char *ptr;
  204. ser_init();
  205. for (ptr=str;*ptr;++ptr)
  206. ser_putc(*ptr);
  207. }
  208. static void ser_putc(char c)
  209. {
  210. unsigned port=COM_BASE;
  211. while ((inb(port+5) & 0x20)==0);
  212. outb(c,port);
  213. if (c==0x0a)
  214. {
  215. while ((inb(port+5) & 0x20)==0);
  216. outb(0x0d,port);
  217. }
  218. }
  219. static int ser_printk(const char *fmt, ...)
  220. {
  221. va_list args;
  222. int i;
  223. va_start(args,fmt);
  224. i = vsprintf(strbuf,fmt,args);
  225. ser_puts(strbuf);
  226. va_end(args);
  227. return i;
  228. }
  229. #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
  230. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
  231. #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
  232. #else /* !__SERIAL__ */
  233. #define TRACE(a) {if (DebugState==1) {printk a;}}
  234. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
  235. #define TRACE3(a) {if (DebugState!=0) {printk a;}}
  236. #endif
  237. #else /* !DEBUG */
  238. #define TRACE(a)
  239. #define TRACE2(a)
  240. #define TRACE3(a)
  241. #endif
  242. #ifdef GDTH_STATISTICS
  243. static ulong32 max_rq=0, max_index=0, max_sg=0;
  244. #ifdef INT_COAL
  245. static ulong32 max_int_coal=0;
  246. #endif
  247. static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
  248. static struct timer_list gdth_timer;
  249. #endif
  250. #define PTR2USHORT(a) (ushort)(ulong)(a)
  251. #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
  252. #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
  253. #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
  254. #ifdef CONFIG_ISA
  255. static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
  256. #endif
  257. #if defined(CONFIG_EISA) || defined(CONFIG_ISA)
  258. static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
  259. #endif
  260. static unchar gdth_polling; /* polling if TRUE */
  261. static int gdth_ctr_count = 0; /* controller count */
  262. static LIST_HEAD(gdth_instances); /* controller list */
  263. static unchar gdth_write_through = FALSE; /* write through */
  264. static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
  265. static int elastidx;
  266. static int eoldidx;
  267. static int major;
  268. #define DIN 1 /* IN data direction */
  269. #define DOU 2 /* OUT data direction */
  270. #define DNO DIN /* no data transfer */
  271. #define DUN DIN /* unknown data direction */
  272. static unchar gdth_direction_tab[0x100] = {
  273. DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
  274. DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
  275. DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
  276. DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
  277. DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
  278. DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
  279. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  280. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  281. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  282. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
  283. DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
  284. DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  285. DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  286. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  287. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  288. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
  289. };
  290. /* LILO and modprobe/insmod parameters */
  291. /* IRQ list for GDT3000/3020 EISA controllers */
  292. static int irq[MAXHA] __initdata =
  293. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  294. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  295. /* disable driver flag */
  296. static int disable __initdata = 0;
  297. /* reserve flag */
  298. static int reserve_mode = 1;
  299. /* reserve list */
  300. static int reserve_list[MAX_RES_ARGS] =
  301. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  302. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  303. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  304. /* scan order for PCI controllers */
  305. static int reverse_scan = 0;
  306. /* virtual channel for the host drives */
  307. static int hdr_channel = 0;
  308. /* max. IDs per channel */
  309. static int max_ids = MAXID;
  310. /* rescan all IDs */
  311. static int rescan = 0;
  312. /* shared access */
  313. static int shared_access = 1;
  314. /* enable support for EISA and ISA controllers */
  315. static int probe_eisa_isa = 0;
  316. /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
  317. static int force_dma32 = 0;
  318. /* parameters for modprobe/insmod */
  319. module_param_array(irq, int, NULL, 0);
  320. module_param(disable, int, 0);
  321. module_param(reserve_mode, int, 0);
  322. module_param_array(reserve_list, int, NULL, 0);
  323. module_param(reverse_scan, int, 0);
  324. module_param(hdr_channel, int, 0);
  325. module_param(max_ids, int, 0);
  326. module_param(rescan, int, 0);
  327. module_param(shared_access, int, 0);
  328. module_param(probe_eisa_isa, int, 0);
  329. module_param(force_dma32, int, 0);
  330. MODULE_AUTHOR("Achim Leubner");
  331. MODULE_LICENSE("GPL");
  332. /* ioctl interface */
  333. static const struct file_operations gdth_fops = {
  334. .ioctl = gdth_ioctl,
  335. .open = gdth_open,
  336. .release = gdth_close,
  337. };
  338. #include "gdth_proc.h"
  339. #include "gdth_proc.c"
  340. static gdth_ha_str *gdth_find_ha(int hanum)
  341. {
  342. gdth_ha_str *ha;
  343. list_for_each_entry(ha, &gdth_instances, list)
  344. if (hanum == ha->hanum)
  345. return ha;
  346. return NULL;
  347. }
  348. static struct gdth_cmndinfo *gdth_get_cmndinfo(gdth_ha_str *ha)
  349. {
  350. struct gdth_cmndinfo *priv = NULL;
  351. ulong flags;
  352. int i;
  353. spin_lock_irqsave(&ha->smp_lock, flags);
  354. for (i=0; i<GDTH_MAXCMDS; ++i) {
  355. if (ha->cmndinfo[i].index == 0) {
  356. priv = &ha->cmndinfo[i];
  357. memset(priv, 0, sizeof(*priv));
  358. priv->index = i+1;
  359. break;
  360. }
  361. }
  362. spin_unlock_irqrestore(&ha->smp_lock, flags);
  363. return priv;
  364. }
  365. static void gdth_put_cmndinfo(struct gdth_cmndinfo *priv)
  366. {
  367. BUG_ON(!priv);
  368. priv->index = 0;
  369. }
  370. static void gdth_delay(int milliseconds)
  371. {
  372. if (milliseconds == 0) {
  373. udelay(1);
  374. } else {
  375. mdelay(milliseconds);
  376. }
  377. }
  378. static void gdth_scsi_done(struct scsi_cmnd *scp)
  379. {
  380. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  381. int internal_command = cmndinfo->internal_command;
  382. TRACE2(("gdth_scsi_done()\n"));
  383. gdth_put_cmndinfo(cmndinfo);
  384. scp->host_scribble = NULL;
  385. if (internal_command)
  386. complete((struct completion *)scp->request);
  387. else
  388. scp->scsi_done(scp);
  389. }
  390. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  391. int timeout, u32 *info)
  392. {
  393. gdth_ha_str *ha = shost_priv(sdev->host);
  394. Scsi_Cmnd *scp;
  395. struct gdth_cmndinfo cmndinfo;
  396. DECLARE_COMPLETION_ONSTACK(wait);
  397. int rval;
  398. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  399. if (!scp)
  400. return -ENOMEM;
  401. scp->sense_buffer = kzalloc(SCSI_SENSE_BUFFERSIZE, GFP_KERNEL);
  402. if (!scp->sense_buffer) {
  403. kfree(scp);
  404. return -ENOMEM;
  405. }
  406. scp->device = sdev;
  407. memset(&cmndinfo, 0, sizeof(cmndinfo));
  408. /* use request field to save the ptr. to completion struct. */
  409. scp->request = (struct request *)&wait;
  410. scp->timeout_per_command = timeout*HZ;
  411. scp->cmd_len = 12;
  412. scp->cmnd = cmnd;
  413. cmndinfo.priority = IOCTL_PRI;
  414. cmndinfo.internal_cmd_str = gdtcmd;
  415. cmndinfo.internal_command = 1;
  416. TRACE(("__gdth_execute() cmd 0x%x\n", scp->cmnd[0]));
  417. __gdth_queuecommand(ha, scp, &cmndinfo);
  418. wait_for_completion(&wait);
  419. rval = cmndinfo.status;
  420. if (info)
  421. *info = cmndinfo.info;
  422. kfree(scp->sense_buffer);
  423. kfree(scp);
  424. return rval;
  425. }
  426. int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
  427. int timeout, u32 *info)
  428. {
  429. struct scsi_device *sdev = scsi_get_host_dev(shost);
  430. int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
  431. scsi_free_host_dev(sdev);
  432. return rval;
  433. }
  434. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
  435. {
  436. *cyls = size /HEADS/SECS;
  437. if (*cyls <= MAXCYLS) {
  438. *heads = HEADS;
  439. *secs = SECS;
  440. } else { /* too high for 64*32 */
  441. *cyls = size /MEDHEADS/MEDSECS;
  442. if (*cyls <= MAXCYLS) {
  443. *heads = MEDHEADS;
  444. *secs = MEDSECS;
  445. } else { /* too high for 127*63 */
  446. *cyls = size /BIGHEADS/BIGSECS;
  447. *heads = BIGHEADS;
  448. *secs = BIGSECS;
  449. }
  450. }
  451. }
  452. /* controller search and initialization functions */
  453. #ifdef CONFIG_EISA
  454. static int __init gdth_search_eisa(ushort eisa_adr)
  455. {
  456. ulong32 id;
  457. TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
  458. id = inl(eisa_adr+ID0REG);
  459. if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
  460. if ((inb(eisa_adr+EISAREG) & 8) == 0)
  461. return 0; /* not EISA configured */
  462. return 1;
  463. }
  464. if (id == GDT3_ID) /* GDT3000 */
  465. return 1;
  466. return 0;
  467. }
  468. #endif /* CONFIG_EISA */
  469. #ifdef CONFIG_ISA
  470. static int __init gdth_search_isa(ulong32 bios_adr)
  471. {
  472. void __iomem *addr;
  473. ulong32 id;
  474. TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
  475. if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
  476. id = readl(addr);
  477. iounmap(addr);
  478. if (id == GDT2_ID) /* GDT2000 */
  479. return 1;
  480. }
  481. return 0;
  482. }
  483. #endif /* CONFIG_ISA */
  484. #ifdef CONFIG_PCI
  485. static bool gdth_search_vortex(ushort device)
  486. {
  487. if (device <= PCI_DEVICE_ID_VORTEX_GDT6555)
  488. return true;
  489. if (device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP &&
  490. device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP)
  491. return true;
  492. if (device == PCI_DEVICE_ID_VORTEX_GDTNEWRX ||
  493. device == PCI_DEVICE_ID_VORTEX_GDTNEWRX2)
  494. return true;
  495. return false;
  496. }
  497. static int gdth_pci_probe_one(gdth_pci_str *pcistr, gdth_ha_str **ha_out);
  498. static int gdth_pci_init_one(struct pci_dev *pdev,
  499. const struct pci_device_id *ent);
  500. static void gdth_pci_remove_one(struct pci_dev *pdev);
  501. static void gdth_remove_one(gdth_ha_str *ha);
  502. /* Vortex only makes RAID controllers.
  503. * We do not really want to specify all 550 ids here, so wildcard match.
  504. */
  505. static const struct pci_device_id gdthtable[] = {
  506. { PCI_VDEVICE(VORTEX, PCI_ANY_ID) },
  507. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SRC) },
  508. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SRC_XSCALE) },
  509. { } /* terminate list */
  510. };
  511. MODULE_DEVICE_TABLE(pci, gdthtable);
  512. static struct pci_driver gdth_pci_driver = {
  513. .name = "gdth",
  514. .id_table = gdthtable,
  515. .probe = gdth_pci_init_one,
  516. .remove = gdth_pci_remove_one,
  517. };
  518. static void gdth_pci_remove_one(struct pci_dev *pdev)
  519. {
  520. gdth_ha_str *ha = pci_get_drvdata(pdev);
  521. pci_set_drvdata(pdev, NULL);
  522. list_del(&ha->list);
  523. gdth_remove_one(ha);
  524. pci_disable_device(pdev);
  525. }
  526. static int gdth_pci_init_one(struct pci_dev *pdev,
  527. const struct pci_device_id *ent)
  528. {
  529. ushort vendor = pdev->vendor;
  530. ushort device = pdev->device;
  531. ulong base0, base1, base2;
  532. int rc;
  533. gdth_pci_str gdth_pcistr;
  534. gdth_ha_str *ha = NULL;
  535. TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
  536. gdth_ctr_count, vendor, device));
  537. memset(&gdth_pcistr, 0, sizeof(gdth_pcistr));
  538. if (vendor == PCI_VENDOR_ID_VORTEX && !gdth_search_vortex(device))
  539. return -ENODEV;
  540. rc = pci_enable_device(pdev);
  541. if (rc)
  542. return rc;
  543. if (gdth_ctr_count >= MAXHA)
  544. return -EBUSY;
  545. /* GDT PCI controller found, resources are already in pdev */
  546. gdth_pcistr.pdev = pdev;
  547. base0 = pci_resource_flags(pdev, 0);
  548. base1 = pci_resource_flags(pdev, 1);
  549. base2 = pci_resource_flags(pdev, 2);
  550. if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
  551. device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
  552. if (!(base0 & IORESOURCE_MEM))
  553. return -ENODEV;
  554. gdth_pcistr.dpmem = pci_resource_start(pdev, 0);
  555. } else { /* GDT6110, GDT6120, .. */
  556. if (!(base0 & IORESOURCE_MEM) ||
  557. !(base2 & IORESOURCE_MEM) ||
  558. !(base1 & IORESOURCE_IO))
  559. return -ENODEV;
  560. gdth_pcistr.dpmem = pci_resource_start(pdev, 2);
  561. gdth_pcistr.io = pci_resource_start(pdev, 1);
  562. }
  563. TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
  564. gdth_pcistr.pdev->bus->number,
  565. PCI_SLOT(gdth_pcistr.pdev->devfn),
  566. gdth_pcistr.irq,
  567. gdth_pcistr.dpmem));
  568. rc = gdth_pci_probe_one(&gdth_pcistr, &ha);
  569. if (rc)
  570. return rc;
  571. return 0;
  572. }
  573. #endif /* CONFIG_PCI */
  574. #ifdef CONFIG_EISA
  575. static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
  576. {
  577. ulong32 retries,id;
  578. unchar prot_ver,eisacf,i,irq_found;
  579. TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
  580. /* disable board interrupts, deinitialize services */
  581. outb(0xff,eisa_adr+EDOORREG);
  582. outb(0x00,eisa_adr+EDENABREG);
  583. outb(0x00,eisa_adr+EINTENABREG);
  584. outb(0xff,eisa_adr+LDOORREG);
  585. retries = INIT_RETRIES;
  586. gdth_delay(20);
  587. while (inb(eisa_adr+EDOORREG) != 0xff) {
  588. if (--retries == 0) {
  589. printk("GDT-EISA: Initialization error (DEINIT failed)\n");
  590. return 0;
  591. }
  592. gdth_delay(1);
  593. TRACE2(("wait for DEINIT: retries=%d\n",retries));
  594. }
  595. prot_ver = inb(eisa_adr+MAILBOXREG);
  596. outb(0xff,eisa_adr+EDOORREG);
  597. if (prot_ver != PROTOCOL_VERSION) {
  598. printk("GDT-EISA: Illegal protocol version\n");
  599. return 0;
  600. }
  601. ha->bmic = eisa_adr;
  602. ha->brd_phys = (ulong32)eisa_adr >> 12;
  603. outl(0,eisa_adr+MAILBOXREG);
  604. outl(0,eisa_adr+MAILBOXREG+4);
  605. outl(0,eisa_adr+MAILBOXREG+8);
  606. outl(0,eisa_adr+MAILBOXREG+12);
  607. /* detect IRQ */
  608. if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
  609. ha->oem_id = OEM_ID_ICP;
  610. ha->type = GDT_EISA;
  611. ha->stype = id;
  612. outl(1,eisa_adr+MAILBOXREG+8);
  613. outb(0xfe,eisa_adr+LDOORREG);
  614. retries = INIT_RETRIES;
  615. gdth_delay(20);
  616. while (inb(eisa_adr+EDOORREG) != 0xfe) {
  617. if (--retries == 0) {
  618. printk("GDT-EISA: Initialization error (get IRQ failed)\n");
  619. return 0;
  620. }
  621. gdth_delay(1);
  622. }
  623. ha->irq = inb(eisa_adr+MAILBOXREG);
  624. outb(0xff,eisa_adr+EDOORREG);
  625. TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
  626. /* check the result */
  627. if (ha->irq == 0) {
  628. TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
  629. for (i = 0, irq_found = FALSE;
  630. i < MAXHA && irq[i] != 0xff; ++i) {
  631. if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
  632. irq_found = TRUE;
  633. break;
  634. }
  635. }
  636. if (irq_found) {
  637. ha->irq = irq[i];
  638. irq[i] = 0;
  639. printk("GDT-EISA: Can not detect controller IRQ,\n");
  640. printk("Use IRQ setting from command line (IRQ = %d)\n",
  641. ha->irq);
  642. } else {
  643. printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
  644. printk("the controller BIOS or use command line parameters\n");
  645. return 0;
  646. }
  647. }
  648. } else {
  649. eisacf = inb(eisa_adr+EISAREG) & 7;
  650. if (eisacf > 4) /* level triggered */
  651. eisacf -= 4;
  652. ha->irq = gdth_irq_tab[eisacf];
  653. ha->oem_id = OEM_ID_ICP;
  654. ha->type = GDT_EISA;
  655. ha->stype = id;
  656. }
  657. ha->dma64_support = 0;
  658. return 1;
  659. }
  660. #endif /* CONFIG_EISA */
  661. #ifdef CONFIG_ISA
  662. static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
  663. {
  664. register gdt2_dpram_str __iomem *dp2_ptr;
  665. int i;
  666. unchar irq_drq,prot_ver;
  667. ulong32 retries;
  668. TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
  669. ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
  670. if (ha->brd == NULL) {
  671. printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
  672. return 0;
  673. }
  674. dp2_ptr = ha->brd;
  675. writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
  676. /* reset interface area */
  677. memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
  678. if (readl(&dp2_ptr->u) != 0) {
  679. printk("GDT-ISA: Initialization error (DPMEM write error)\n");
  680. iounmap(ha->brd);
  681. return 0;
  682. }
  683. /* disable board interrupts, read DRQ and IRQ */
  684. writeb(0xff, &dp2_ptr->io.irqdel);
  685. writeb(0x00, &dp2_ptr->io.irqen);
  686. writeb(0x00, &dp2_ptr->u.ic.S_Status);
  687. writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
  688. irq_drq = readb(&dp2_ptr->io.rq);
  689. for (i=0; i<3; ++i) {
  690. if ((irq_drq & 1)==0)
  691. break;
  692. irq_drq >>= 1;
  693. }
  694. ha->drq = gdth_drq_tab[i];
  695. irq_drq = readb(&dp2_ptr->io.rq) >> 3;
  696. for (i=1; i<5; ++i) {
  697. if ((irq_drq & 1)==0)
  698. break;
  699. irq_drq >>= 1;
  700. }
  701. ha->irq = gdth_irq_tab[i];
  702. /* deinitialize services */
  703. writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
  704. writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
  705. writeb(0, &dp2_ptr->io.event);
  706. retries = INIT_RETRIES;
  707. gdth_delay(20);
  708. while (readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
  709. if (--retries == 0) {
  710. printk("GDT-ISA: Initialization error (DEINIT failed)\n");
  711. iounmap(ha->brd);
  712. return 0;
  713. }
  714. gdth_delay(1);
  715. }
  716. prot_ver = (unchar)readl(&dp2_ptr->u.ic.S_Info[0]);
  717. writeb(0, &dp2_ptr->u.ic.Status);
  718. writeb(0xff, &dp2_ptr->io.irqdel);
  719. if (prot_ver != PROTOCOL_VERSION) {
  720. printk("GDT-ISA: Illegal protocol version\n");
  721. iounmap(ha->brd);
  722. return 0;
  723. }
  724. ha->oem_id = OEM_ID_ICP;
  725. ha->type = GDT_ISA;
  726. ha->ic_all_size = sizeof(dp2_ptr->u);
  727. ha->stype= GDT2_ID;
  728. ha->brd_phys = bios_adr >> 4;
  729. /* special request to controller BIOS */
  730. writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
  731. writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
  732. writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
  733. writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
  734. writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
  735. writeb(0, &dp2_ptr->io.event);
  736. retries = INIT_RETRIES;
  737. gdth_delay(20);
  738. while (readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
  739. if (--retries == 0) {
  740. printk("GDT-ISA: Initialization error\n");
  741. iounmap(ha->brd);
  742. return 0;
  743. }
  744. gdth_delay(1);
  745. }
  746. writeb(0, &dp2_ptr->u.ic.Status);
  747. writeb(0xff, &dp2_ptr->io.irqdel);
  748. ha->dma64_support = 0;
  749. return 1;
  750. }
  751. #endif /* CONFIG_ISA */
  752. #ifdef CONFIG_PCI
  753. static int gdth_init_pci(struct pci_dev *pdev, gdth_pci_str *pcistr,
  754. gdth_ha_str *ha)
  755. {
  756. register gdt6_dpram_str __iomem *dp6_ptr;
  757. register gdt6c_dpram_str __iomem *dp6c_ptr;
  758. register gdt6m_dpram_str __iomem *dp6m_ptr;
  759. ulong32 retries;
  760. unchar prot_ver;
  761. ushort command;
  762. int i, found = FALSE;
  763. TRACE(("gdth_init_pci()\n"));
  764. if (pdev->vendor == PCI_VENDOR_ID_INTEL)
  765. ha->oem_id = OEM_ID_INTEL;
  766. else
  767. ha->oem_id = OEM_ID_ICP;
  768. ha->brd_phys = (pdev->bus->number << 8) | (pdev->devfn & 0xf8);
  769. ha->stype = (ulong32)pdev->device;
  770. ha->irq = pdev->irq;
  771. ha->pdev = pdev;
  772. if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
  773. TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  774. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
  775. if (ha->brd == NULL) {
  776. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  777. return 0;
  778. }
  779. /* check and reset interface area */
  780. dp6_ptr = ha->brd;
  781. writel(DPMEM_MAGIC, &dp6_ptr->u);
  782. if (readl(&dp6_ptr->u) != DPMEM_MAGIC) {
  783. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  784. pcistr->dpmem);
  785. found = FALSE;
  786. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  787. iounmap(ha->brd);
  788. ha->brd = ioremap(i, sizeof(ushort));
  789. if (ha->brd == NULL) {
  790. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  791. return 0;
  792. }
  793. if (readw(ha->brd) != 0xffff) {
  794. TRACE2(("init_pci_old() address 0x%x busy\n", i));
  795. continue;
  796. }
  797. iounmap(ha->brd);
  798. pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i);
  799. ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
  800. if (ha->brd == NULL) {
  801. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  802. return 0;
  803. }
  804. dp6_ptr = ha->brd;
  805. writel(DPMEM_MAGIC, &dp6_ptr->u);
  806. if (readl(&dp6_ptr->u) == DPMEM_MAGIC) {
  807. printk("GDT-PCI: Use free address at 0x%x\n", i);
  808. found = TRUE;
  809. break;
  810. }
  811. }
  812. if (!found) {
  813. printk("GDT-PCI: No free address found!\n");
  814. iounmap(ha->brd);
  815. return 0;
  816. }
  817. }
  818. memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
  819. if (readl(&dp6_ptr->u) != 0) {
  820. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  821. iounmap(ha->brd);
  822. return 0;
  823. }
  824. /* disable board interrupts, deinit services */
  825. writeb(0xff, &dp6_ptr->io.irqdel);
  826. writeb(0x00, &dp6_ptr->io.irqen);
  827. writeb(0x00, &dp6_ptr->u.ic.S_Status);
  828. writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
  829. writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
  830. writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
  831. writeb(0, &dp6_ptr->io.event);
  832. retries = INIT_RETRIES;
  833. gdth_delay(20);
  834. while (readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  835. if (--retries == 0) {
  836. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  837. iounmap(ha->brd);
  838. return 0;
  839. }
  840. gdth_delay(1);
  841. }
  842. prot_ver = (unchar)readl(&dp6_ptr->u.ic.S_Info[0]);
  843. writeb(0, &dp6_ptr->u.ic.S_Status);
  844. writeb(0xff, &dp6_ptr->io.irqdel);
  845. if (prot_ver != PROTOCOL_VERSION) {
  846. printk("GDT-PCI: Illegal protocol version\n");
  847. iounmap(ha->brd);
  848. return 0;
  849. }
  850. ha->type = GDT_PCI;
  851. ha->ic_all_size = sizeof(dp6_ptr->u);
  852. /* special command to controller BIOS */
  853. writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
  854. writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
  855. writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
  856. writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
  857. writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
  858. writeb(0, &dp6_ptr->io.event);
  859. retries = INIT_RETRIES;
  860. gdth_delay(20);
  861. while (readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  862. if (--retries == 0) {
  863. printk("GDT-PCI: Initialization error\n");
  864. iounmap(ha->brd);
  865. return 0;
  866. }
  867. gdth_delay(1);
  868. }
  869. writeb(0, &dp6_ptr->u.ic.S_Status);
  870. writeb(0xff, &dp6_ptr->io.irqdel);
  871. ha->dma64_support = 0;
  872. } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
  873. ha->plx = (gdt6c_plx_regs *)pcistr->io;
  874. TRACE2(("init_pci_new() dpmem %lx irq %d\n",
  875. pcistr->dpmem,ha->irq));
  876. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
  877. if (ha->brd == NULL) {
  878. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  879. iounmap(ha->brd);
  880. return 0;
  881. }
  882. /* check and reset interface area */
  883. dp6c_ptr = ha->brd;
  884. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  885. if (readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
  886. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  887. pcistr->dpmem);
  888. found = FALSE;
  889. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  890. iounmap(ha->brd);
  891. ha->brd = ioremap(i, sizeof(ushort));
  892. if (ha->brd == NULL) {
  893. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  894. return 0;
  895. }
  896. if (readw(ha->brd) != 0xffff) {
  897. TRACE2(("init_pci_plx() address 0x%x busy\n", i));
  898. continue;
  899. }
  900. iounmap(ha->brd);
  901. pci_write_config_dword(pdev, PCI_BASE_ADDRESS_2, i);
  902. ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
  903. if (ha->brd == NULL) {
  904. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  905. return 0;
  906. }
  907. dp6c_ptr = ha->brd;
  908. writel(DPMEM_MAGIC, &dp6c_ptr->u);
  909. if (readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
  910. printk("GDT-PCI: Use free address at 0x%x\n", i);
  911. found = TRUE;
  912. break;
  913. }
  914. }
  915. if (!found) {
  916. printk("GDT-PCI: No free address found!\n");
  917. iounmap(ha->brd);
  918. return 0;
  919. }
  920. }
  921. memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
  922. if (readl(&dp6c_ptr->u) != 0) {
  923. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  924. iounmap(ha->brd);
  925. return 0;
  926. }
  927. /* disable board interrupts, deinit services */
  928. outb(0x00,PTR2USHORT(&ha->plx->control1));
  929. outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
  930. writeb(0x00, &dp6c_ptr->u.ic.S_Status);
  931. writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
  932. writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
  933. writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
  934. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  935. retries = INIT_RETRIES;
  936. gdth_delay(20);
  937. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  938. if (--retries == 0) {
  939. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  940. iounmap(ha->brd);
  941. return 0;
  942. }
  943. gdth_delay(1);
  944. }
  945. prot_ver = (unchar)readl(&dp6c_ptr->u.ic.S_Info[0]);
  946. writeb(0, &dp6c_ptr->u.ic.Status);
  947. if (prot_ver != PROTOCOL_VERSION) {
  948. printk("GDT-PCI: Illegal protocol version\n");
  949. iounmap(ha->brd);
  950. return 0;
  951. }
  952. ha->type = GDT_PCINEW;
  953. ha->ic_all_size = sizeof(dp6c_ptr->u);
  954. /* special command to controller BIOS */
  955. writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
  956. writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
  957. writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
  958. writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
  959. writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
  960. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  961. retries = INIT_RETRIES;
  962. gdth_delay(20);
  963. while (readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  964. if (--retries == 0) {
  965. printk("GDT-PCI: Initialization error\n");
  966. iounmap(ha->brd);
  967. return 0;
  968. }
  969. gdth_delay(1);
  970. }
  971. writeb(0, &dp6c_ptr->u.ic.S_Status);
  972. ha->dma64_support = 0;
  973. } else { /* MPR */
  974. TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  975. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
  976. if (ha->brd == NULL) {
  977. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  978. return 0;
  979. }
  980. /* manipulate config. space to enable DPMEM, start RP controller */
  981. pci_read_config_word(pdev, PCI_COMMAND, &command);
  982. command |= 6;
  983. pci_write_config_word(pdev, PCI_COMMAND, command);
  984. if (pci_resource_start(pdev, 8) == 1UL)
  985. pci_resource_start(pdev, 8) = 0UL;
  986. i = 0xFEFF0001UL;
  987. pci_write_config_dword(pdev, PCI_ROM_ADDRESS, i);
  988. gdth_delay(1);
  989. pci_write_config_dword(pdev, PCI_ROM_ADDRESS,
  990. pci_resource_start(pdev, 8));
  991. dp6m_ptr = ha->brd;
  992. /* Ensure that it is safe to access the non HW portions of DPMEM.
  993. * Aditional check needed for Xscale based RAID controllers */
  994. while( ((int)readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
  995. gdth_delay(1);
  996. /* check and reset interface area */
  997. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  998. if (readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
  999. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1000. pcistr->dpmem);
  1001. found = FALSE;
  1002. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1003. iounmap(ha->brd);
  1004. ha->brd = ioremap(i, sizeof(ushort));
  1005. if (ha->brd == NULL) {
  1006. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1007. return 0;
  1008. }
  1009. if (readw(ha->brd) != 0xffff) {
  1010. TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
  1011. continue;
  1012. }
  1013. iounmap(ha->brd);
  1014. pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, i);
  1015. ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
  1016. if (ha->brd == NULL) {
  1017. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1018. return 0;
  1019. }
  1020. dp6m_ptr = ha->brd;
  1021. writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1022. if (readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
  1023. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1024. found = TRUE;
  1025. break;
  1026. }
  1027. }
  1028. if (!found) {
  1029. printk("GDT-PCI: No free address found!\n");
  1030. iounmap(ha->brd);
  1031. return 0;
  1032. }
  1033. }
  1034. memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
  1035. /* disable board interrupts, deinit services */
  1036. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
  1037. &dp6m_ptr->i960r.edoor_en_reg);
  1038. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1039. writeb(0x00, &dp6m_ptr->u.ic.S_Status);
  1040. writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
  1041. writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
  1042. writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1043. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1044. retries = INIT_RETRIES;
  1045. gdth_delay(20);
  1046. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
  1047. if (--retries == 0) {
  1048. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1049. iounmap(ha->brd);
  1050. return 0;
  1051. }
  1052. gdth_delay(1);
  1053. }
  1054. prot_ver = (unchar)readl(&dp6m_ptr->u.ic.S_Info[0]);
  1055. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1056. if (prot_ver != PROTOCOL_VERSION) {
  1057. printk("GDT-PCI: Illegal protocol version\n");
  1058. iounmap(ha->brd);
  1059. return 0;
  1060. }
  1061. ha->type = GDT_PCIMPR;
  1062. ha->ic_all_size = sizeof(dp6m_ptr->u);
  1063. /* special command to controller BIOS */
  1064. writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
  1065. writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
  1066. writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
  1067. writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
  1068. writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1069. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1070. retries = INIT_RETRIES;
  1071. gdth_delay(20);
  1072. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
  1073. if (--retries == 0) {
  1074. printk("GDT-PCI: Initialization error\n");
  1075. iounmap(ha->brd);
  1076. return 0;
  1077. }
  1078. gdth_delay(1);
  1079. }
  1080. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1081. /* read FW version to detect 64-bit DMA support */
  1082. writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1083. writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1084. retries = INIT_RETRIES;
  1085. gdth_delay(20);
  1086. while (readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
  1087. if (--retries == 0) {
  1088. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1089. iounmap(ha->brd);
  1090. return 0;
  1091. }
  1092. gdth_delay(1);
  1093. }
  1094. prot_ver = (unchar)(readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
  1095. writeb(0, &dp6m_ptr->u.ic.S_Status);
  1096. if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
  1097. ha->dma64_support = 0;
  1098. else
  1099. ha->dma64_support = 1;
  1100. }
  1101. return 1;
  1102. }
  1103. #endif /* CONFIG_PCI */
  1104. /* controller protocol functions */
  1105. static void __init gdth_enable_int(gdth_ha_str *ha)
  1106. {
  1107. ulong flags;
  1108. gdt2_dpram_str __iomem *dp2_ptr;
  1109. gdt6_dpram_str __iomem *dp6_ptr;
  1110. gdt6m_dpram_str __iomem *dp6m_ptr;
  1111. TRACE(("gdth_enable_int() hanum %d\n",ha->hanum));
  1112. spin_lock_irqsave(&ha->smp_lock, flags);
  1113. if (ha->type == GDT_EISA) {
  1114. outb(0xff, ha->bmic + EDOORREG);
  1115. outb(0xff, ha->bmic + EDENABREG);
  1116. outb(0x01, ha->bmic + EINTENABREG);
  1117. } else if (ha->type == GDT_ISA) {
  1118. dp2_ptr = ha->brd;
  1119. writeb(1, &dp2_ptr->io.irqdel);
  1120. writeb(0, &dp2_ptr->u.ic.Cmd_Index);
  1121. writeb(1, &dp2_ptr->io.irqen);
  1122. } else if (ha->type == GDT_PCI) {
  1123. dp6_ptr = ha->brd;
  1124. writeb(1, &dp6_ptr->io.irqdel);
  1125. writeb(0, &dp6_ptr->u.ic.Cmd_Index);
  1126. writeb(1, &dp6_ptr->io.irqen);
  1127. } else if (ha->type == GDT_PCINEW) {
  1128. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  1129. outb(0x03, PTR2USHORT(&ha->plx->control1));
  1130. } else if (ha->type == GDT_PCIMPR) {
  1131. dp6m_ptr = ha->brd;
  1132. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1133. writeb(readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
  1134. &dp6m_ptr->i960r.edoor_en_reg);
  1135. }
  1136. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1137. }
  1138. /* return IStatus if interrupt was from this card else 0 */
  1139. static unchar gdth_get_status(gdth_ha_str *ha)
  1140. {
  1141. unchar IStatus = 0;
  1142. TRACE(("gdth_get_status() irq %d ctr_count %d\n", ha->irq, gdth_ctr_count));
  1143. if (ha->type == GDT_EISA)
  1144. IStatus = inb((ushort)ha->bmic + EDOORREG);
  1145. else if (ha->type == GDT_ISA)
  1146. IStatus =
  1147. readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1148. else if (ha->type == GDT_PCI)
  1149. IStatus =
  1150. readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1151. else if (ha->type == GDT_PCINEW)
  1152. IStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
  1153. else if (ha->type == GDT_PCIMPR)
  1154. IStatus =
  1155. readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
  1156. return IStatus;
  1157. }
  1158. static int gdth_test_busy(gdth_ha_str *ha)
  1159. {
  1160. register int gdtsema0 = 0;
  1161. TRACE(("gdth_test_busy() hanum %d\n", ha->hanum));
  1162. if (ha->type == GDT_EISA)
  1163. gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
  1164. else if (ha->type == GDT_ISA)
  1165. gdtsema0 = (int)readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1166. else if (ha->type == GDT_PCI)
  1167. gdtsema0 = (int)readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1168. else if (ha->type == GDT_PCINEW)
  1169. gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
  1170. else if (ha->type == GDT_PCIMPR)
  1171. gdtsema0 =
  1172. (int)readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1173. return (gdtsema0 & 1);
  1174. }
  1175. static int gdth_get_cmd_index(gdth_ha_str *ha)
  1176. {
  1177. int i;
  1178. TRACE(("gdth_get_cmd_index() hanum %d\n", ha->hanum));
  1179. for (i=0; i<GDTH_MAXCMDS; ++i) {
  1180. if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
  1181. ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
  1182. ha->cmd_tab[i].service = ha->pccb->Service;
  1183. ha->pccb->CommandIndex = (ulong32)i+2;
  1184. return (i+2);
  1185. }
  1186. }
  1187. return 0;
  1188. }
  1189. static void gdth_set_sema0(gdth_ha_str *ha)
  1190. {
  1191. TRACE(("gdth_set_sema0() hanum %d\n", ha->hanum));
  1192. if (ha->type == GDT_EISA) {
  1193. outb(1, ha->bmic + SEMA0REG);
  1194. } else if (ha->type == GDT_ISA) {
  1195. writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1196. } else if (ha->type == GDT_PCI) {
  1197. writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1198. } else if (ha->type == GDT_PCINEW) {
  1199. outb(1, PTR2USHORT(&ha->plx->sema0_reg));
  1200. } else if (ha->type == GDT_PCIMPR) {
  1201. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1202. }
  1203. }
  1204. static void gdth_copy_command(gdth_ha_str *ha)
  1205. {
  1206. register gdth_cmd_str *cmd_ptr;
  1207. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1208. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1209. gdt6_dpram_str __iomem *dp6_ptr;
  1210. gdt2_dpram_str __iomem *dp2_ptr;
  1211. ushort cp_count,dp_offset,cmd_no;
  1212. TRACE(("gdth_copy_command() hanum %d\n", ha->hanum));
  1213. cp_count = ha->cmd_len;
  1214. dp_offset= ha->cmd_offs_dpmem;
  1215. cmd_no = ha->cmd_cnt;
  1216. cmd_ptr = ha->pccb;
  1217. ++ha->cmd_cnt;
  1218. if (ha->type == GDT_EISA)
  1219. return; /* no DPMEM, no copy */
  1220. /* set cpcount dword aligned */
  1221. if (cp_count & 3)
  1222. cp_count += (4 - (cp_count & 3));
  1223. ha->cmd_offs_dpmem += cp_count;
  1224. /* set offset and service, copy command to DPMEM */
  1225. if (ha->type == GDT_ISA) {
  1226. dp2_ptr = ha->brd;
  1227. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1228. &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
  1229. writew((ushort)cmd_ptr->Service,
  1230. &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1231. memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1232. } else if (ha->type == GDT_PCI) {
  1233. dp6_ptr = ha->brd;
  1234. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1235. &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
  1236. writew((ushort)cmd_ptr->Service,
  1237. &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1238. memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1239. } else if (ha->type == GDT_PCINEW) {
  1240. dp6c_ptr = ha->brd;
  1241. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1242. &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
  1243. writew((ushort)cmd_ptr->Service,
  1244. &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1245. memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1246. } else if (ha->type == GDT_PCIMPR) {
  1247. dp6m_ptr = ha->brd;
  1248. writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1249. &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
  1250. writew((ushort)cmd_ptr->Service,
  1251. &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1252. memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1253. }
  1254. }
  1255. static void gdth_release_event(gdth_ha_str *ha)
  1256. {
  1257. TRACE(("gdth_release_event() hanum %d\n", ha->hanum));
  1258. #ifdef GDTH_STATISTICS
  1259. {
  1260. ulong32 i,j;
  1261. for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
  1262. if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
  1263. ++i;
  1264. }
  1265. if (max_index < i) {
  1266. max_index = i;
  1267. TRACE3(("GDT: max_index = %d\n",(ushort)i));
  1268. }
  1269. }
  1270. #endif
  1271. if (ha->pccb->OpCode == GDT_INIT)
  1272. ha->pccb->Service |= 0x80;
  1273. if (ha->type == GDT_EISA) {
  1274. if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
  1275. outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
  1276. outb(ha->pccb->Service, ha->bmic + LDOORREG);
  1277. } else if (ha->type == GDT_ISA) {
  1278. writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
  1279. } else if (ha->type == GDT_PCI) {
  1280. writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
  1281. } else if (ha->type == GDT_PCINEW) {
  1282. outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
  1283. } else if (ha->type == GDT_PCIMPR) {
  1284. writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
  1285. }
  1286. }
  1287. static int gdth_wait(gdth_ha_str *ha, int index, ulong32 time)
  1288. {
  1289. int answer_found = FALSE;
  1290. int wait_index = 0;
  1291. TRACE(("gdth_wait() hanum %d index %d time %d\n", ha->hanum, index, time));
  1292. if (index == 0)
  1293. return 1; /* no wait required */
  1294. do {
  1295. __gdth_interrupt(ha, true, &wait_index);
  1296. if (wait_index == index) {
  1297. answer_found = TRUE;
  1298. break;
  1299. }
  1300. gdth_delay(1);
  1301. } while (--time);
  1302. while (gdth_test_busy(ha))
  1303. gdth_delay(0);
  1304. return (answer_found);
  1305. }
  1306. static int gdth_internal_cmd(gdth_ha_str *ha, unchar service, ushort opcode,
  1307. ulong32 p1, ulong64 p2, ulong64 p3)
  1308. {
  1309. register gdth_cmd_str *cmd_ptr;
  1310. int retries,index;
  1311. TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
  1312. cmd_ptr = ha->pccb;
  1313. memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
  1314. /* make command */
  1315. for (retries = INIT_RETRIES;;) {
  1316. cmd_ptr->Service = service;
  1317. cmd_ptr->RequestBuffer = INTERNAL_CMND;
  1318. if (!(index=gdth_get_cmd_index(ha))) {
  1319. TRACE(("GDT: No free command index found\n"));
  1320. return 0;
  1321. }
  1322. gdth_set_sema0(ha);
  1323. cmd_ptr->OpCode = opcode;
  1324. cmd_ptr->BoardNode = LOCALBOARD;
  1325. if (service == CACHESERVICE) {
  1326. if (opcode == GDT_IOCTL) {
  1327. cmd_ptr->u.ioctl.subfunc = p1;
  1328. cmd_ptr->u.ioctl.channel = (ulong32)p2;
  1329. cmd_ptr->u.ioctl.param_size = (ushort)p3;
  1330. cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
  1331. } else {
  1332. if (ha->cache_feat & GDT_64BIT) {
  1333. cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
  1334. cmd_ptr->u.cache64.BlockNo = p2;
  1335. } else {
  1336. cmd_ptr->u.cache.DeviceNo = (ushort)p1;
  1337. cmd_ptr->u.cache.BlockNo = (ulong32)p2;
  1338. }
  1339. }
  1340. } else if (service == SCSIRAWSERVICE) {
  1341. if (ha->raw_feat & GDT_64BIT) {
  1342. cmd_ptr->u.raw64.direction = p1;
  1343. cmd_ptr->u.raw64.bus = (unchar)p2;
  1344. cmd_ptr->u.raw64.target = (unchar)p3;
  1345. cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
  1346. } else {
  1347. cmd_ptr->u.raw.direction = p1;
  1348. cmd_ptr->u.raw.bus = (unchar)p2;
  1349. cmd_ptr->u.raw.target = (unchar)p3;
  1350. cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
  1351. }
  1352. } else if (service == SCREENSERVICE) {
  1353. if (opcode == GDT_REALTIME) {
  1354. *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
  1355. *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
  1356. *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
  1357. }
  1358. }
  1359. ha->cmd_len = sizeof(gdth_cmd_str);
  1360. ha->cmd_offs_dpmem = 0;
  1361. ha->cmd_cnt = 0;
  1362. gdth_copy_command(ha);
  1363. gdth_release_event(ha);
  1364. gdth_delay(20);
  1365. if (!gdth_wait(ha, index, INIT_TIMEOUT)) {
  1366. printk("GDT: Initialization error (timeout service %d)\n",service);
  1367. return 0;
  1368. }
  1369. if (ha->status != S_BSY || --retries == 0)
  1370. break;
  1371. gdth_delay(1);
  1372. }
  1373. return (ha->status != S_OK ? 0:1);
  1374. }
  1375. /* search for devices */
  1376. static int __init gdth_search_drives(gdth_ha_str *ha)
  1377. {
  1378. ushort cdev_cnt, i;
  1379. int ok;
  1380. ulong32 bus_no, drv_cnt, drv_no, j;
  1381. gdth_getch_str *chn;
  1382. gdth_drlist_str *drl;
  1383. gdth_iochan_str *ioc;
  1384. gdth_raw_iochan_str *iocr;
  1385. gdth_arcdl_str *alst;
  1386. gdth_alist_str *alst2;
  1387. gdth_oem_str_ioctl *oemstr;
  1388. #ifdef INT_COAL
  1389. gdth_perf_modes *pmod;
  1390. #endif
  1391. #ifdef GDTH_RTC
  1392. unchar rtc[12];
  1393. ulong flags;
  1394. #endif
  1395. TRACE(("gdth_search_drives() hanum %d\n", ha->hanum));
  1396. ok = 0;
  1397. /* initialize controller services, at first: screen service */
  1398. ha->screen_feat = 0;
  1399. if (!force_dma32) {
  1400. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_X_INIT_SCR, 0, 0, 0);
  1401. if (ok)
  1402. ha->screen_feat = GDT_64BIT;
  1403. }
  1404. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1405. ok = gdth_internal_cmd(ha, SCREENSERVICE, GDT_INIT, 0, 0, 0);
  1406. if (!ok) {
  1407. printk("GDT-HA %d: Initialization error screen service (code %d)\n",
  1408. ha->hanum, ha->status);
  1409. return 0;
  1410. }
  1411. TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
  1412. #ifdef GDTH_RTC
  1413. /* read realtime clock info, send to controller */
  1414. /* 1. wait for the falling edge of update flag */
  1415. spin_lock_irqsave(&rtc_lock, flags);
  1416. for (j = 0; j < 1000000; ++j)
  1417. if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
  1418. break;
  1419. for (j = 0; j < 1000000; ++j)
  1420. if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
  1421. break;
  1422. /* 2. read info */
  1423. do {
  1424. for (j = 0; j < 12; ++j)
  1425. rtc[j] = CMOS_READ(j);
  1426. } while (rtc[0] != CMOS_READ(0));
  1427. spin_unlock_irqrestore(&rtc_lock, flags);
  1428. TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
  1429. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
  1430. /* 3. send to controller firmware */
  1431. gdth_internal_cmd(ha, SCREENSERVICE, GDT_REALTIME, *(ulong32 *)&rtc[0],
  1432. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
  1433. #endif
  1434. /* unfreeze all IOs */
  1435. gdth_internal_cmd(ha, CACHESERVICE, GDT_UNFREEZE_IO, 0, 0, 0);
  1436. /* initialize cache service */
  1437. ha->cache_feat = 0;
  1438. if (!force_dma32) {
  1439. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INIT_HOST, LINUX_OS,
  1440. 0, 0);
  1441. if (ok)
  1442. ha->cache_feat = GDT_64BIT;
  1443. }
  1444. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1445. ok = gdth_internal_cmd(ha, CACHESERVICE, GDT_INIT, LINUX_OS, 0, 0);
  1446. if (!ok) {
  1447. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1448. ha->hanum, ha->status);
  1449. return 0;
  1450. }
  1451. TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
  1452. cdev_cnt = (ushort)ha->info;
  1453. ha->fw_vers = ha->service;
  1454. #ifdef INT_COAL
  1455. if (ha->type == GDT_PCIMPR) {
  1456. /* set perf. modes */
  1457. pmod = (gdth_perf_modes *)ha->pscratch;
  1458. pmod->version = 1;
  1459. pmod->st_mode = 1; /* enable one status buffer */
  1460. *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
  1461. pmod->st_buff_indx1 = COALINDEX;
  1462. pmod->st_buff_addr2 = 0;
  1463. pmod->st_buff_u_addr2 = 0;
  1464. pmod->st_buff_indx2 = 0;
  1465. pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
  1466. pmod->cmd_mode = 0; // disable all cmd buffers
  1467. pmod->cmd_buff_addr1 = 0;
  1468. pmod->cmd_buff_u_addr1 = 0;
  1469. pmod->cmd_buff_indx1 = 0;
  1470. pmod->cmd_buff_addr2 = 0;
  1471. pmod->cmd_buff_u_addr2 = 0;
  1472. pmod->cmd_buff_indx2 = 0;
  1473. pmod->cmd_buff_size = 0;
  1474. pmod->reserved1 = 0;
  1475. pmod->reserved2 = 0;
  1476. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, SET_PERF_MODES,
  1477. INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
  1478. printk("GDT-HA %d: Interrupt coalescing activated\n", ha->hanum);
  1479. }
  1480. }
  1481. #endif
  1482. /* detect number of buses - try new IOCTL */
  1483. iocr = (gdth_raw_iochan_str *)ha->pscratch;
  1484. iocr->hdr.version = 0xffffffff;
  1485. iocr->hdr.list_entries = MAXBUS;
  1486. iocr->hdr.first_chan = 0;
  1487. iocr->hdr.last_chan = MAXBUS-1;
  1488. iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
  1489. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_RAW_DESC,
  1490. INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
  1491. TRACE2(("IOCHAN_RAW_DESC supported!\n"));
  1492. ha->bus_cnt = iocr->hdr.chan_count;
  1493. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1494. if (iocr->list[bus_no].proc_id < MAXID)
  1495. ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
  1496. else
  1497. ha->bus_id[bus_no] = 0xff;
  1498. }
  1499. } else {
  1500. /* old method */
  1501. chn = (gdth_getch_str *)ha->pscratch;
  1502. for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
  1503. chn->channel_no = bus_no;
  1504. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1505. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1506. IO_CHANNEL | INVALID_CHANNEL,
  1507. sizeof(gdth_getch_str))) {
  1508. if (bus_no == 0) {
  1509. printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
  1510. ha->hanum, ha->status);
  1511. return 0;
  1512. }
  1513. break;
  1514. }
  1515. if (chn->siop_id < MAXID)
  1516. ha->bus_id[bus_no] = chn->siop_id;
  1517. else
  1518. ha->bus_id[bus_no] = 0xff;
  1519. }
  1520. ha->bus_cnt = (unchar)bus_no;
  1521. }
  1522. TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
  1523. /* read cache configuration */
  1524. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_INFO,
  1525. INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
  1526. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1527. ha->hanum, ha->status);
  1528. return 0;
  1529. }
  1530. ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
  1531. TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
  1532. ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
  1533. ha->cpar.write_back,ha->cpar.block_size));
  1534. /* read board info and features */
  1535. ha->more_proc = FALSE;
  1536. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_INFO,
  1537. INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
  1538. memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
  1539. sizeof(gdth_binfo_str));
  1540. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, BOARD_FEATURES,
  1541. INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
  1542. TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
  1543. ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
  1544. ha->more_proc = TRUE;
  1545. }
  1546. } else {
  1547. TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
  1548. strcpy(ha->binfo.type_string, gdth_ctr_name(ha));
  1549. }
  1550. TRACE2(("Controller name: %s\n",ha->binfo.type_string));
  1551. /* read more informations */
  1552. if (ha->more_proc) {
  1553. /* physical drives, channel addresses */
  1554. ioc = (gdth_iochan_str *)ha->pscratch;
  1555. ioc->hdr.version = 0xffffffff;
  1556. ioc->hdr.list_entries = MAXBUS;
  1557. ioc->hdr.first_chan = 0;
  1558. ioc->hdr.last_chan = MAXBUS-1;
  1559. ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
  1560. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, IOCHAN_DESC,
  1561. INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
  1562. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1563. ha->raw[bus_no].address = ioc->list[bus_no].address;
  1564. ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
  1565. }
  1566. } else {
  1567. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1568. ha->raw[bus_no].address = IO_CHANNEL;
  1569. ha->raw[bus_no].local_no = bus_no;
  1570. }
  1571. }
  1572. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1573. chn = (gdth_getch_str *)ha->pscratch;
  1574. chn->channel_no = ha->raw[bus_no].local_no;
  1575. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1576. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1577. ha->raw[bus_no].address | INVALID_CHANNEL,
  1578. sizeof(gdth_getch_str))) {
  1579. ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
  1580. TRACE2(("Channel %d: %d phys. drives\n",
  1581. bus_no,chn->drive_cnt));
  1582. }
  1583. if (ha->raw[bus_no].pdev_cnt > 0) {
  1584. drl = (gdth_drlist_str *)ha->pscratch;
  1585. drl->sc_no = ha->raw[bus_no].local_no;
  1586. drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
  1587. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1588. SCSI_DR_LIST | L_CTRL_PATTERN,
  1589. ha->raw[bus_no].address | INVALID_CHANNEL,
  1590. sizeof(gdth_drlist_str))) {
  1591. for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
  1592. ha->raw[bus_no].id_list[j] = drl->sc_list[j];
  1593. } else {
  1594. ha->raw[bus_no].pdev_cnt = 0;
  1595. }
  1596. }
  1597. }
  1598. /* logical drives */
  1599. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_CNT,
  1600. INVALID_CHANNEL,sizeof(ulong32))) {
  1601. drv_cnt = *(ulong32 *)ha->pscratch;
  1602. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL, CACHE_DRV_LIST,
  1603. INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
  1604. for (j = 0; j < drv_cnt; ++j) {
  1605. drv_no = ((ulong32 *)ha->pscratch)[j];
  1606. if (drv_no < MAX_LDRIVES) {
  1607. ha->hdr[drv_no].is_logdrv = TRUE;
  1608. TRACE2(("Drive %d is log. drive\n",drv_no));
  1609. }
  1610. }
  1611. }
  1612. alst = (gdth_arcdl_str *)ha->pscratch;
  1613. alst->entries_avail = MAX_LDRIVES;
  1614. alst->first_entry = 0;
  1615. alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
  1616. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1617. ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
  1618. INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
  1619. (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
  1620. for (j = 0; j < alst->entries_init; ++j) {
  1621. ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
  1622. ha->hdr[j].is_master = alst->list[j].is_master;
  1623. ha->hdr[j].is_parity = alst->list[j].is_parity;
  1624. ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
  1625. ha->hdr[j].master_no = alst->list[j].cd_handle;
  1626. }
  1627. } else if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1628. ARRAY_DRV_LIST | LA_CTRL_PATTERN,
  1629. 0, 35 * sizeof(gdth_alist_str))) {
  1630. for (j = 0; j < 35; ++j) {
  1631. alst2 = &((gdth_alist_str *)ha->pscratch)[j];
  1632. ha->hdr[j].is_arraydrv = alst2->is_arrayd;
  1633. ha->hdr[j].is_master = alst2->is_master;
  1634. ha->hdr[j].is_parity = alst2->is_parity;
  1635. ha->hdr[j].is_hotfix = alst2->is_hotfix;
  1636. ha->hdr[j].master_no = alst2->cd_handle;
  1637. }
  1638. }
  1639. }
  1640. }
  1641. /* initialize raw service */
  1642. ha->raw_feat = 0;
  1643. if (!force_dma32) {
  1644. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_X_INIT_RAW, 0, 0, 0);
  1645. if (ok)
  1646. ha->raw_feat = GDT_64BIT;
  1647. }
  1648. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1649. ok = gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_INIT, 0, 0, 0);
  1650. if (!ok) {
  1651. printk("GDT-HA %d: Initialization error raw service (code %d)\n",
  1652. ha->hanum, ha->status);
  1653. return 0;
  1654. }
  1655. TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
  1656. /* set/get features raw service (scatter/gather) */
  1657. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_SET_FEAT, SCATTER_GATHER,
  1658. 0, 0)) {
  1659. TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
  1660. if (gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1661. TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
  1662. ha->info));
  1663. ha->raw_feat |= (ushort)ha->info;
  1664. }
  1665. }
  1666. /* set/get features cache service (equal to raw service) */
  1667. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_SET_FEAT, 0,
  1668. SCATTER_GATHER,0)) {
  1669. TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
  1670. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_GET_FEAT, 0, 0, 0)) {
  1671. TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
  1672. ha->info));
  1673. ha->cache_feat |= (ushort)ha->info;
  1674. }
  1675. }
  1676. /* reserve drives for raw service */
  1677. if (reserve_mode != 0) {
  1678. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE_ALL,
  1679. reserve_mode == 1 ? 1 : 3, 0, 0);
  1680. TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
  1681. ha->status));
  1682. }
  1683. for (i = 0; i < MAX_RES_ARGS; i += 4) {
  1684. if (reserve_list[i] == ha->hanum && reserve_list[i+1] < ha->bus_cnt &&
  1685. reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
  1686. TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
  1687. reserve_list[i], reserve_list[i+1],
  1688. reserve_list[i+2], reserve_list[i+3]));
  1689. if (!gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESERVE, 0,
  1690. reserve_list[i+1], reserve_list[i+2] |
  1691. (reserve_list[i+3] << 8))) {
  1692. printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
  1693. ha->hanum, ha->status);
  1694. }
  1695. }
  1696. }
  1697. /* Determine OEM string using IOCTL */
  1698. oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
  1699. oemstr->params.ctl_version = 0x01;
  1700. oemstr->params.buffer_size = sizeof(oemstr->text);
  1701. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_IOCTL,
  1702. CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
  1703. sizeof(gdth_oem_str_ioctl))) {
  1704. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
  1705. printk("GDT-HA %d: Vendor: %s Name: %s\n",
  1706. ha->hanum, oemstr->text.oem_company_name, ha->binfo.type_string);
  1707. /* Save the Host Drive inquiry data */
  1708. strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
  1709. sizeof(ha->oem_name));
  1710. } else {
  1711. /* Old method, based on PCI ID */
  1712. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
  1713. printk("GDT-HA %d: Name: %s\n",
  1714. ha->hanum, ha->binfo.type_string);
  1715. if (ha->oem_id == OEM_ID_INTEL)
  1716. strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
  1717. else
  1718. strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
  1719. }
  1720. /* scanning for host drives */
  1721. for (i = 0; i < cdev_cnt; ++i)
  1722. gdth_analyse_hdrive(ha, i);
  1723. TRACE(("gdth_search_drives() OK\n"));
  1724. return 1;
  1725. }
  1726. static int gdth_analyse_hdrive(gdth_ha_str *ha, ushort hdrive)
  1727. {
  1728. ulong32 drv_cyls;
  1729. int drv_hds, drv_secs;
  1730. TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n", ha->hanum, hdrive));
  1731. if (hdrive >= MAX_HDRIVES)
  1732. return 0;
  1733. if (!gdth_internal_cmd(ha, CACHESERVICE, GDT_INFO, hdrive, 0, 0))
  1734. return 0;
  1735. ha->hdr[hdrive].present = TRUE;
  1736. ha->hdr[hdrive].size = ha->info;
  1737. /* evaluate mapping (sectors per head, heads per cylinder) */
  1738. ha->hdr[hdrive].size &= ~SECS32;
  1739. if (ha->info2 == 0) {
  1740. gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
  1741. } else {
  1742. drv_hds = ha->info2 & 0xff;
  1743. drv_secs = (ha->info2 >> 8) & 0xff;
  1744. drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
  1745. }
  1746. ha->hdr[hdrive].heads = (unchar)drv_hds;
  1747. ha->hdr[hdrive].secs = (unchar)drv_secs;
  1748. /* round size */
  1749. ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
  1750. if (ha->cache_feat & GDT_64BIT) {
  1751. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_X_INFO, hdrive, 0, 0)
  1752. && ha->info2 != 0) {
  1753. ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
  1754. }
  1755. }
  1756. TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
  1757. hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
  1758. /* get informations about device */
  1759. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_DEVTYPE, hdrive, 0, 0)) {
  1760. TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
  1761. hdrive,ha->info));
  1762. ha->hdr[hdrive].devtype = (ushort)ha->info;
  1763. }
  1764. /* cluster info */
  1765. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_CLUST_INFO, hdrive, 0, 0)) {
  1766. TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
  1767. hdrive,ha->info));
  1768. if (!shared_access)
  1769. ha->hdr[hdrive].cluster_type = (unchar)ha->info;
  1770. }
  1771. /* R/W attributes */
  1772. if (gdth_internal_cmd(ha, CACHESERVICE, GDT_RW_ATTRIBS, hdrive, 0, 0)) {
  1773. TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
  1774. hdrive,ha->info));
  1775. ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
  1776. }
  1777. return 1;
  1778. }
  1779. /* command queueing/sending functions */
  1780. static void gdth_putq(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar priority)
  1781. {
  1782. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  1783. register Scsi_Cmnd *pscp;
  1784. register Scsi_Cmnd *nscp;
  1785. ulong flags;
  1786. unchar b, t;
  1787. TRACE(("gdth_putq() priority %d\n",priority));
  1788. spin_lock_irqsave(&ha->smp_lock, flags);
  1789. if (!cmndinfo->internal_command) {
  1790. cmndinfo->priority = priority;
  1791. b = scp->device->channel;
  1792. t = scp->device->id;
  1793. if (priority >= DEFAULT_PRI) {
  1794. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1795. (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
  1796. TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
  1797. cmndinfo->timeout = gdth_update_timeout(scp, 0);
  1798. }
  1799. }
  1800. }
  1801. if (ha->req_first==NULL) {
  1802. ha->req_first = scp; /* queue was empty */
  1803. scp->SCp.ptr = NULL;
  1804. } else { /* queue not empty */
  1805. pscp = ha->req_first;
  1806. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1807. /* priority: 0-highest,..,0xff-lowest */
  1808. while (nscp && gdth_cmnd_priv(nscp)->priority <= priority) {
  1809. pscp = nscp;
  1810. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1811. }
  1812. pscp->SCp.ptr = (char *)scp;
  1813. scp->SCp.ptr = (char *)nscp;
  1814. }
  1815. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1816. #ifdef GDTH_STATISTICS
  1817. flags = 0;
  1818. for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  1819. ++flags;
  1820. if (max_rq < flags) {
  1821. max_rq = flags;
  1822. TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
  1823. }
  1824. #endif
  1825. }
  1826. static void gdth_next(gdth_ha_str *ha)
  1827. {
  1828. register Scsi_Cmnd *pscp;
  1829. register Scsi_Cmnd *nscp;
  1830. unchar b, t, l, firsttime;
  1831. unchar this_cmd, next_cmd;
  1832. ulong flags = 0;
  1833. int cmd_index;
  1834. TRACE(("gdth_next() hanum %d\n", ha->hanum));
  1835. if (!gdth_polling)
  1836. spin_lock_irqsave(&ha->smp_lock, flags);
  1837. ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
  1838. this_cmd = firsttime = TRUE;
  1839. next_cmd = gdth_polling ? FALSE:TRUE;
  1840. cmd_index = 0;
  1841. for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
  1842. struct gdth_cmndinfo *nscp_cmndinfo = gdth_cmnd_priv(nscp);
  1843. if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
  1844. pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  1845. if (!nscp_cmndinfo->internal_command) {
  1846. b = nscp->device->channel;
  1847. t = nscp->device->id;
  1848. l = nscp->device->lun;
  1849. if (nscp_cmndinfo->priority >= DEFAULT_PRI) {
  1850. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  1851. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
  1852. continue;
  1853. }
  1854. } else
  1855. b = t = l = 0;
  1856. if (firsttime) {
  1857. if (gdth_test_busy(ha)) { /* controller busy ? */
  1858. TRACE(("gdth_next() controller %d busy !\n", ha->hanum));
  1859. if (!gdth_polling) {
  1860. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1861. return;
  1862. }
  1863. while (gdth_test_busy(ha))
  1864. gdth_delay(1);
  1865. }
  1866. firsttime = FALSE;
  1867. }
  1868. if (!nscp_cmndinfo->internal_command) {
  1869. if (nscp_cmndinfo->phase == -1) {
  1870. nscp_cmndinfo->phase = CACHESERVICE; /* default: cache svc. */
  1871. if (nscp->cmnd[0] == TEST_UNIT_READY) {
  1872. TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
  1873. b, t, l));
  1874. /* TEST_UNIT_READY -> set scan mode */
  1875. if ((ha->scan_mode & 0x0f) == 0) {
  1876. if (b == 0 && t == 0 && l == 0) {
  1877. ha->scan_mode |= 1;
  1878. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1879. }
  1880. } else if ((ha->scan_mode & 0x0f) == 1) {
  1881. if (b == 0 && ((t == 0 && l == 1) ||
  1882. (t == 1 && l == 0))) {
  1883. nscp_cmndinfo->OpCode = GDT_SCAN_START;
  1884. nscp_cmndinfo->phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
  1885. | SCSIRAWSERVICE;
  1886. ha->scan_mode = 0x12;
  1887. TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
  1888. ha->scan_mode));
  1889. } else {
  1890. ha->scan_mode &= 0x10;
  1891. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  1892. }
  1893. } else if (ha->scan_mode == 0x12) {
  1894. if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
  1895. nscp_cmndinfo->phase = SCSIRAWSERVICE;
  1896. nscp_cmndinfo->OpCode = GDT_SCAN_END;
  1897. ha->scan_mode &= 0x10;
  1898. TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
  1899. ha->scan_mode));
  1900. }
  1901. }
  1902. }
  1903. if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
  1904. nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
  1905. (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
  1906. /* always GDT_CLUST_INFO! */
  1907. nscp_cmndinfo->OpCode = GDT_CLUST_INFO;
  1908. }
  1909. }
  1910. }
  1911. if (nscp_cmndinfo->OpCode != -1) {
  1912. if ((nscp_cmndinfo->phase & 0xff) == CACHESERVICE) {
  1913. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1914. this_cmd = FALSE;
  1915. next_cmd = FALSE;
  1916. } else if ((nscp_cmndinfo->phase & 0xff) == SCSIRAWSERVICE) {
  1917. if (!(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1918. this_cmd = FALSE;
  1919. next_cmd = FALSE;
  1920. } else {
  1921. memset((char*)nscp->sense_buffer,0,16);
  1922. nscp->sense_buffer[0] = 0x70;
  1923. nscp->sense_buffer[2] = NOT_READY;
  1924. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1925. if (!nscp_cmndinfo->wait_for_completion)
  1926. nscp_cmndinfo->wait_for_completion++;
  1927. else
  1928. gdth_scsi_done(nscp);
  1929. }
  1930. } else if (gdth_cmnd_priv(nscp)->internal_command) {
  1931. if (!(cmd_index=gdth_special_cmd(ha, nscp)))
  1932. this_cmd = FALSE;
  1933. next_cmd = FALSE;
  1934. } else if (b != ha->virt_bus) {
  1935. if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
  1936. !(cmd_index=gdth_fill_raw_cmd(ha, nscp, BUS_L2P(ha, b))))
  1937. this_cmd = FALSE;
  1938. else
  1939. ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
  1940. } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
  1941. TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
  1942. nscp->cmnd[0], b, t, l));
  1943. nscp->result = DID_BAD_TARGET << 16;
  1944. if (!nscp_cmndinfo->wait_for_completion)
  1945. nscp_cmndinfo->wait_for_completion++;
  1946. else
  1947. gdth_scsi_done(nscp);
  1948. } else {
  1949. switch (nscp->cmnd[0]) {
  1950. case TEST_UNIT_READY:
  1951. case INQUIRY:
  1952. case REQUEST_SENSE:
  1953. case READ_CAPACITY:
  1954. case VERIFY:
  1955. case START_STOP:
  1956. case MODE_SENSE:
  1957. case SERVICE_ACTION_IN:
  1958. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  1959. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  1960. nscp->cmnd[4],nscp->cmnd[5]));
  1961. if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
  1962. /* return UNIT_ATTENTION */
  1963. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  1964. nscp->cmnd[0], t));
  1965. ha->hdr[t].media_changed = FALSE;
  1966. memset((char*)nscp->sense_buffer,0,16);
  1967. nscp->sense_buffer[0] = 0x70;
  1968. nscp->sense_buffer[2] = UNIT_ATTENTION;
  1969. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  1970. if (!nscp_cmndinfo->wait_for_completion)
  1971. nscp_cmndinfo->wait_for_completion++;
  1972. else
  1973. gdth_scsi_done(nscp);
  1974. } else if (gdth_internal_cache_cmd(ha, nscp))
  1975. gdth_scsi_done(nscp);
  1976. break;
  1977. case ALLOW_MEDIUM_REMOVAL:
  1978. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  1979. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  1980. nscp->cmnd[4],nscp->cmnd[5]));
  1981. if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
  1982. TRACE(("Prevent r. nonremov. drive->do nothing\n"));
  1983. nscp->result = DID_OK << 16;
  1984. nscp->sense_buffer[0] = 0;
  1985. if (!nscp_cmndinfo->wait_for_completion)
  1986. nscp_cmndinfo->wait_for_completion++;
  1987. else
  1988. gdth_scsi_done(nscp);
  1989. } else {
  1990. nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
  1991. TRACE(("Prevent/allow r. %d rem. drive %d\n",
  1992. nscp->cmnd[4],nscp->cmnd[3]));
  1993. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  1994. this_cmd = FALSE;
  1995. }
  1996. break;
  1997. case RESERVE:
  1998. case RELEASE:
  1999. TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
  2000. "RESERVE" : "RELEASE"));
  2001. if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2002. this_cmd = FALSE;
  2003. break;
  2004. case READ_6:
  2005. case WRITE_6:
  2006. case READ_10:
  2007. case WRITE_10:
  2008. case READ_16:
  2009. case WRITE_16:
  2010. if (ha->hdr[t].media_changed) {
  2011. /* return UNIT_ATTENTION */
  2012. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2013. nscp->cmnd[0], t));
  2014. ha->hdr[t].media_changed = FALSE;
  2015. memset((char*)nscp->sense_buffer,0,16);
  2016. nscp->sense_buffer[0] = 0x70;
  2017. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2018. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2019. if (!nscp_cmndinfo->wait_for_completion)
  2020. nscp_cmndinfo->wait_for_completion++;
  2021. else
  2022. gdth_scsi_done(nscp);
  2023. } else if (!(cmd_index=gdth_fill_cache_cmd(ha, nscp, t)))
  2024. this_cmd = FALSE;
  2025. break;
  2026. default:
  2027. TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
  2028. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2029. nscp->cmnd[4],nscp->cmnd[5]));
  2030. printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
  2031. ha->hanum, nscp->cmnd[0]);
  2032. nscp->result = DID_ABORT << 16;
  2033. if (!nscp_cmndinfo->wait_for_completion)
  2034. nscp_cmndinfo->wait_for_completion++;
  2035. else
  2036. gdth_scsi_done(nscp);
  2037. break;
  2038. }
  2039. }
  2040. if (!this_cmd)
  2041. break;
  2042. if (nscp == ha->req_first)
  2043. ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
  2044. else
  2045. pscp->SCp.ptr = nscp->SCp.ptr;
  2046. if (!next_cmd)
  2047. break;
  2048. }
  2049. if (ha->cmd_cnt > 0) {
  2050. gdth_release_event(ha);
  2051. }
  2052. if (!gdth_polling)
  2053. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2054. if (gdth_polling && ha->cmd_cnt > 0) {
  2055. if (!gdth_wait(ha, cmd_index, POLL_TIMEOUT))
  2056. printk("GDT-HA %d: Command %d timed out !\n",
  2057. ha->hanum, cmd_index);
  2058. }
  2059. }
  2060. /*
  2061. * gdth_copy_internal_data() - copy to/from a buffer onto a scsi_cmnd's
  2062. * buffers, kmap_atomic() as needed.
  2063. */
  2064. static void gdth_copy_internal_data(gdth_ha_str *ha, Scsi_Cmnd *scp,
  2065. char *buffer, ushort count)
  2066. {
  2067. ushort cpcount,i, max_sg = scsi_sg_count(scp);
  2068. ushort cpsum,cpnow;
  2069. struct scatterlist *sl;
  2070. char *address;
  2071. cpcount = min_t(ushort, count, scsi_bufflen(scp));
  2072. if (cpcount) {
  2073. cpsum=0;
  2074. scsi_for_each_sg(scp, sl, max_sg, i) {
  2075. unsigned long flags;
  2076. cpnow = (ushort)sl->length;
  2077. TRACE(("copy_internal() now %d sum %d count %d %d\n",
  2078. cpnow, cpsum, cpcount, scsi_bufflen(scp)));
  2079. if (cpsum+cpnow > cpcount)
  2080. cpnow = cpcount - cpsum;
  2081. cpsum += cpnow;
  2082. if (!sg_page(sl)) {
  2083. printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
  2084. ha->hanum);
  2085. return;
  2086. }
  2087. local_irq_save(flags);
  2088. address = kmap_atomic(sg_page(sl), KM_BIO_SRC_IRQ) + sl->offset;
  2089. memcpy(address, buffer, cpnow);
  2090. flush_dcache_page(sg_page(sl));
  2091. kunmap_atomic(address, KM_BIO_SRC_IRQ);
  2092. local_irq_restore(flags);
  2093. if (cpsum == cpcount)
  2094. break;
  2095. buffer += cpnow;
  2096. }
  2097. } else if (count) {
  2098. printk("GDT-HA %d: SCSI command with no buffers but data transfer expected!\n",
  2099. ha->hanum);
  2100. WARN_ON(1);
  2101. }
  2102. }
  2103. static int gdth_internal_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2104. {
  2105. unchar t;
  2106. gdth_inq_data inq;
  2107. gdth_rdcap_data rdc;
  2108. gdth_sense_data sd;
  2109. gdth_modep_data mpd;
  2110. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2111. t = scp->device->id;
  2112. TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
  2113. scp->cmnd[0],t));
  2114. scp->result = DID_OK << 16;
  2115. scp->sense_buffer[0] = 0;
  2116. switch (scp->cmnd[0]) {
  2117. case TEST_UNIT_READY:
  2118. case VERIFY:
  2119. case START_STOP:
  2120. TRACE2(("Test/Verify/Start hdrive %d\n",t));
  2121. break;
  2122. case INQUIRY:
  2123. TRACE2(("Inquiry hdrive %d devtype %d\n",
  2124. t,ha->hdr[t].devtype));
  2125. inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
  2126. /* you can here set all disks to removable, if you want to do
  2127. a flush using the ALLOW_MEDIUM_REMOVAL command */
  2128. inq.modif_rmb = 0x00;
  2129. if ((ha->hdr[t].devtype & 1) ||
  2130. (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
  2131. inq.modif_rmb = 0x80;
  2132. inq.version = 2;
  2133. inq.resp_aenc = 2;
  2134. inq.add_length= 32;
  2135. strcpy(inq.vendor,ha->oem_name);
  2136. sprintf(inq.product,"Host Drive #%02d",t);
  2137. strcpy(inq.revision," ");
  2138. gdth_copy_internal_data(ha, scp, (char*)&inq, sizeof(gdth_inq_data));
  2139. break;
  2140. case REQUEST_SENSE:
  2141. TRACE2(("Request sense hdrive %d\n",t));
  2142. sd.errorcode = 0x70;
  2143. sd.segno = 0x00;
  2144. sd.key = NO_SENSE;
  2145. sd.info = 0;
  2146. sd.add_length= 0;
  2147. gdth_copy_internal_data(ha, scp, (char*)&sd, sizeof(gdth_sense_data));
  2148. break;
  2149. case MODE_SENSE:
  2150. TRACE2(("Mode sense hdrive %d\n",t));
  2151. memset((char*)&mpd,0,sizeof(gdth_modep_data));
  2152. mpd.hd.data_length = sizeof(gdth_modep_data);
  2153. mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
  2154. mpd.hd.bd_length = sizeof(mpd.bd);
  2155. mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
  2156. mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
  2157. mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
  2158. gdth_copy_internal_data(ha, scp, (char*)&mpd, sizeof(gdth_modep_data));
  2159. break;
  2160. case READ_CAPACITY:
  2161. TRACE2(("Read capacity hdrive %d\n",t));
  2162. if (ha->hdr[t].size > (ulong64)0xffffffff)
  2163. rdc.last_block_no = 0xffffffff;
  2164. else
  2165. rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
  2166. rdc.block_length = cpu_to_be32(SECTOR_SIZE);
  2167. gdth_copy_internal_data(ha, scp, (char*)&rdc, sizeof(gdth_rdcap_data));
  2168. break;
  2169. case SERVICE_ACTION_IN:
  2170. if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
  2171. (ha->cache_feat & GDT_64BIT)) {
  2172. gdth_rdcap16_data rdc16;
  2173. TRACE2(("Read capacity (16) hdrive %d\n",t));
  2174. rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
  2175. rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
  2176. gdth_copy_internal_data(ha, scp, (char*)&rdc16,
  2177. sizeof(gdth_rdcap16_data));
  2178. } else {
  2179. scp->result = DID_ABORT << 16;
  2180. }
  2181. break;
  2182. default:
  2183. TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
  2184. break;
  2185. }
  2186. if (!cmndinfo->wait_for_completion)
  2187. cmndinfo->wait_for_completion++;
  2188. else
  2189. return 1;
  2190. return 0;
  2191. }
  2192. static int gdth_fill_cache_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, ushort hdrive)
  2193. {
  2194. register gdth_cmd_str *cmdp;
  2195. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2196. ulong32 cnt, blockcnt;
  2197. ulong64 no, blockno;
  2198. int i, cmd_index, read_write, sgcnt, mode64;
  2199. cmdp = ha->pccb;
  2200. TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
  2201. scp->cmnd[0],scp->cmd_len,hdrive));
  2202. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2203. return 0;
  2204. mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
  2205. /* test for READ_16, WRITE_16 if !mode64 ? ---
  2206. not required, should not occur due to error return on
  2207. READ_CAPACITY_16 */
  2208. cmdp->Service = CACHESERVICE;
  2209. cmdp->RequestBuffer = scp;
  2210. /* search free command index */
  2211. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2212. TRACE(("GDT: No free command index found\n"));
  2213. return 0;
  2214. }
  2215. /* if it's the first command, set command semaphore */
  2216. if (ha->cmd_cnt == 0)
  2217. gdth_set_sema0(ha);
  2218. /* fill command */
  2219. read_write = 0;
  2220. if (cmndinfo->OpCode != -1)
  2221. cmdp->OpCode = cmndinfo->OpCode; /* special cache cmd. */
  2222. else if (scp->cmnd[0] == RESERVE)
  2223. cmdp->OpCode = GDT_RESERVE_DRV;
  2224. else if (scp->cmnd[0] == RELEASE)
  2225. cmdp->OpCode = GDT_RELEASE_DRV;
  2226. else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
  2227. if (scp->cmnd[4] & 1) /* prevent ? */
  2228. cmdp->OpCode = GDT_MOUNT;
  2229. else if (scp->cmnd[3] & 1) /* removable drive ? */
  2230. cmdp->OpCode = GDT_UNMOUNT;
  2231. else
  2232. cmdp->OpCode = GDT_FLUSH;
  2233. } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
  2234. scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
  2235. ) {
  2236. read_write = 1;
  2237. if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
  2238. (ha->cache_feat & GDT_WR_THROUGH)))
  2239. cmdp->OpCode = GDT_WRITE_THR;
  2240. else
  2241. cmdp->OpCode = GDT_WRITE;
  2242. } else {
  2243. read_write = 2;
  2244. cmdp->OpCode = GDT_READ;
  2245. }
  2246. cmdp->BoardNode = LOCALBOARD;
  2247. if (mode64) {
  2248. cmdp->u.cache64.DeviceNo = hdrive;
  2249. cmdp->u.cache64.BlockNo = 1;
  2250. cmdp->u.cache64.sg_canz = 0;
  2251. } else {
  2252. cmdp->u.cache.DeviceNo = hdrive;
  2253. cmdp->u.cache.BlockNo = 1;
  2254. cmdp->u.cache.sg_canz = 0;
  2255. }
  2256. if (read_write) {
  2257. if (scp->cmd_len == 16) {
  2258. memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
  2259. blockno = be64_to_cpu(no);
  2260. memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
  2261. blockcnt = be32_to_cpu(cnt);
  2262. } else if (scp->cmd_len == 10) {
  2263. memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
  2264. blockno = be32_to_cpu(no);
  2265. memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
  2266. blockcnt = be16_to_cpu(cnt);
  2267. } else {
  2268. memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
  2269. blockno = be32_to_cpu(no) & 0x001fffffUL;
  2270. blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
  2271. }
  2272. if (mode64) {
  2273. cmdp->u.cache64.BlockNo = blockno;
  2274. cmdp->u.cache64.BlockCnt = blockcnt;
  2275. } else {
  2276. cmdp->u.cache.BlockNo = (ulong32)blockno;
  2277. cmdp->u.cache.BlockCnt = blockcnt;
  2278. }
  2279. if (scsi_bufflen(scp)) {
  2280. cmndinfo->dma_dir = (read_write == 1 ?
  2281. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2282. sgcnt = pci_map_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
  2283. cmndinfo->dma_dir);
  2284. if (mode64) {
  2285. struct scatterlist *sl;
  2286. cmdp->u.cache64.DestAddr= (ulong64)-1;
  2287. cmdp->u.cache64.sg_canz = sgcnt;
  2288. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2289. cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2290. #ifdef GDTH_DMA_STATISTICS
  2291. if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2292. ha->dma64_cnt++;
  2293. else
  2294. ha->dma32_cnt++;
  2295. #endif
  2296. cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
  2297. }
  2298. } else {
  2299. struct scatterlist *sl;
  2300. cmdp->u.cache.DestAddr= 0xffffffff;
  2301. cmdp->u.cache.sg_canz = sgcnt;
  2302. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2303. cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2304. #ifdef GDTH_DMA_STATISTICS
  2305. ha->dma32_cnt++;
  2306. #endif
  2307. cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
  2308. }
  2309. }
  2310. #ifdef GDTH_STATISTICS
  2311. if (max_sg < (ulong32)sgcnt) {
  2312. max_sg = (ulong32)sgcnt;
  2313. TRACE3(("GDT: max_sg = %d\n",max_sg));
  2314. }
  2315. #endif
  2316. }
  2317. }
  2318. /* evaluate command size, check space */
  2319. if (mode64) {
  2320. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2321. cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
  2322. cmdp->u.cache64.sg_lst[0].sg_ptr,
  2323. cmdp->u.cache64.sg_lst[0].sg_len));
  2324. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2325. cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
  2326. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
  2327. (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
  2328. } else {
  2329. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2330. cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
  2331. cmdp->u.cache.sg_lst[0].sg_ptr,
  2332. cmdp->u.cache.sg_lst[0].sg_len));
  2333. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2334. cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
  2335. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
  2336. (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
  2337. }
  2338. if (ha->cmd_len & 3)
  2339. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2340. if (ha->cmd_cnt > 0) {
  2341. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2342. ha->ic_all_size) {
  2343. TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
  2344. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2345. return 0;
  2346. }
  2347. }
  2348. /* copy command */
  2349. gdth_copy_command(ha);
  2350. return cmd_index;
  2351. }
  2352. static int gdth_fill_raw_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp, unchar b)
  2353. {
  2354. register gdth_cmd_str *cmdp;
  2355. ushort i;
  2356. dma_addr_t sense_paddr;
  2357. int cmd_index, sgcnt, mode64;
  2358. unchar t,l;
  2359. struct page *page;
  2360. ulong offset;
  2361. struct gdth_cmndinfo *cmndinfo;
  2362. t = scp->device->id;
  2363. l = scp->device->lun;
  2364. cmdp = ha->pccb;
  2365. TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
  2366. scp->cmnd[0],b,t,l));
  2367. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2368. return 0;
  2369. mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
  2370. cmdp->Service = SCSIRAWSERVICE;
  2371. cmdp->RequestBuffer = scp;
  2372. /* search free command index */
  2373. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2374. TRACE(("GDT: No free command index found\n"));
  2375. return 0;
  2376. }
  2377. /* if it's the first command, set command semaphore */
  2378. if (ha->cmd_cnt == 0)
  2379. gdth_set_sema0(ha);
  2380. cmndinfo = gdth_cmnd_priv(scp);
  2381. /* fill command */
  2382. if (cmndinfo->OpCode != -1) {
  2383. cmdp->OpCode = cmndinfo->OpCode; /* special raw cmd. */
  2384. cmdp->BoardNode = LOCALBOARD;
  2385. if (mode64) {
  2386. cmdp->u.raw64.direction = (cmndinfo->phase >> 8);
  2387. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2388. cmdp->OpCode, cmdp->u.raw64.direction));
  2389. /* evaluate command size */
  2390. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
  2391. } else {
  2392. cmdp->u.raw.direction = (cmndinfo->phase >> 8);
  2393. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2394. cmdp->OpCode, cmdp->u.raw.direction));
  2395. /* evaluate command size */
  2396. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
  2397. }
  2398. } else {
  2399. page = virt_to_page(scp->sense_buffer);
  2400. offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
  2401. sense_paddr = pci_map_page(ha->pdev,page,offset,
  2402. 16,PCI_DMA_FROMDEVICE);
  2403. cmndinfo->sense_paddr = sense_paddr;
  2404. cmdp->OpCode = GDT_WRITE; /* always */
  2405. cmdp->BoardNode = LOCALBOARD;
  2406. if (mode64) {
  2407. cmdp->u.raw64.reserved = 0;
  2408. cmdp->u.raw64.mdisc_time = 0;
  2409. cmdp->u.raw64.mcon_time = 0;
  2410. cmdp->u.raw64.clen = scp->cmd_len;
  2411. cmdp->u.raw64.target = t;
  2412. cmdp->u.raw64.lun = l;
  2413. cmdp->u.raw64.bus = b;
  2414. cmdp->u.raw64.priority = 0;
  2415. cmdp->u.raw64.sdlen = scsi_bufflen(scp);
  2416. cmdp->u.raw64.sense_len = 16;
  2417. cmdp->u.raw64.sense_data = sense_paddr;
  2418. cmdp->u.raw64.direction =
  2419. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2420. memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
  2421. cmdp->u.raw64.sg_ranz = 0;
  2422. } else {
  2423. cmdp->u.raw.reserved = 0;
  2424. cmdp->u.raw.mdisc_time = 0;
  2425. cmdp->u.raw.mcon_time = 0;
  2426. cmdp->u.raw.clen = scp->cmd_len;
  2427. cmdp->u.raw.target = t;
  2428. cmdp->u.raw.lun = l;
  2429. cmdp->u.raw.bus = b;
  2430. cmdp->u.raw.priority = 0;
  2431. cmdp->u.raw.link_p = 0;
  2432. cmdp->u.raw.sdlen = scsi_bufflen(scp);
  2433. cmdp->u.raw.sense_len = 16;
  2434. cmdp->u.raw.sense_data = sense_paddr;
  2435. cmdp->u.raw.direction =
  2436. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2437. memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
  2438. cmdp->u.raw.sg_ranz = 0;
  2439. }
  2440. if (scsi_bufflen(scp)) {
  2441. cmndinfo->dma_dir = PCI_DMA_BIDIRECTIONAL;
  2442. sgcnt = pci_map_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
  2443. cmndinfo->dma_dir);
  2444. if (mode64) {
  2445. struct scatterlist *sl;
  2446. cmdp->u.raw64.sdata = (ulong64)-1;
  2447. cmdp->u.raw64.sg_ranz = sgcnt;
  2448. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2449. cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2450. #ifdef GDTH_DMA_STATISTICS
  2451. if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2452. ha->dma64_cnt++;
  2453. else
  2454. ha->dma32_cnt++;
  2455. #endif
  2456. cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
  2457. }
  2458. } else {
  2459. struct scatterlist *sl;
  2460. cmdp->u.raw.sdata = 0xffffffff;
  2461. cmdp->u.raw.sg_ranz = sgcnt;
  2462. scsi_for_each_sg(scp, sl, sgcnt, i) {
  2463. cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2464. #ifdef GDTH_DMA_STATISTICS
  2465. ha->dma32_cnt++;
  2466. #endif
  2467. cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
  2468. }
  2469. }
  2470. #ifdef GDTH_STATISTICS
  2471. if (max_sg < sgcnt) {
  2472. max_sg = sgcnt;
  2473. TRACE3(("GDT: max_sg = %d\n",sgcnt));
  2474. }
  2475. #endif
  2476. }
  2477. if (mode64) {
  2478. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2479. cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
  2480. cmdp->u.raw64.sg_lst[0].sg_ptr,
  2481. cmdp->u.raw64.sg_lst[0].sg_len));
  2482. /* evaluate command size */
  2483. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
  2484. (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
  2485. } else {
  2486. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2487. cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
  2488. cmdp->u.raw.sg_lst[0].sg_ptr,
  2489. cmdp->u.raw.sg_lst[0].sg_len));
  2490. /* evaluate command size */
  2491. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
  2492. (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
  2493. }
  2494. }
  2495. /* check space */
  2496. if (ha->cmd_len & 3)
  2497. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2498. if (ha->cmd_cnt > 0) {
  2499. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2500. ha->ic_all_size) {
  2501. TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
  2502. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2503. return 0;
  2504. }
  2505. }
  2506. /* copy command */
  2507. gdth_copy_command(ha);
  2508. return cmd_index;
  2509. }
  2510. static int gdth_special_cmd(gdth_ha_str *ha, Scsi_Cmnd *scp)
  2511. {
  2512. register gdth_cmd_str *cmdp;
  2513. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2514. int cmd_index;
  2515. cmdp= ha->pccb;
  2516. TRACE2(("gdth_special_cmd(): "));
  2517. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2518. return 0;
  2519. *cmdp = *cmndinfo->internal_cmd_str;
  2520. cmdp->RequestBuffer = scp;
  2521. /* search free command index */
  2522. if (!(cmd_index=gdth_get_cmd_index(ha))) {
  2523. TRACE(("GDT: No free command index found\n"));
  2524. return 0;
  2525. }
  2526. /* if it's the first command, set command semaphore */
  2527. if (ha->cmd_cnt == 0)
  2528. gdth_set_sema0(ha);
  2529. /* evaluate command size, check space */
  2530. if (cmdp->OpCode == GDT_IOCTL) {
  2531. TRACE2(("IOCTL\n"));
  2532. ha->cmd_len =
  2533. GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
  2534. } else if (cmdp->Service == CACHESERVICE) {
  2535. TRACE2(("cache command %d\n",cmdp->OpCode));
  2536. if (ha->cache_feat & GDT_64BIT)
  2537. ha->cmd_len =
  2538. GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
  2539. else
  2540. ha->cmd_len =
  2541. GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
  2542. } else if (cmdp->Service == SCSIRAWSERVICE) {
  2543. TRACE2(("raw command %d\n",cmdp->OpCode));
  2544. if (ha->raw_feat & GDT_64BIT)
  2545. ha->cmd_len =
  2546. GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
  2547. else
  2548. ha->cmd_len =
  2549. GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
  2550. }
  2551. if (ha->cmd_len & 3)
  2552. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2553. if (ha->cmd_cnt > 0) {
  2554. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2555. ha->ic_all_size) {
  2556. TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
  2557. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2558. return 0;
  2559. }
  2560. }
  2561. /* copy command */
  2562. gdth_copy_command(ha);
  2563. return cmd_index;
  2564. }
  2565. /* Controller event handling functions */
  2566. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  2567. ushort idx, gdth_evt_data *evt)
  2568. {
  2569. gdth_evt_str *e;
  2570. struct timeval tv;
  2571. /* no GDTH_LOCK_HA() ! */
  2572. TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
  2573. if (source == 0) /* no source -> no event */
  2574. return NULL;
  2575. if (ebuffer[elastidx].event_source == source &&
  2576. ebuffer[elastidx].event_idx == idx &&
  2577. ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
  2578. !memcmp((char *)&ebuffer[elastidx].event_data.eu,
  2579. (char *)&evt->eu, evt->size)) ||
  2580. (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
  2581. !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
  2582. (char *)&evt->event_string)))) {
  2583. e = &ebuffer[elastidx];
  2584. do_gettimeofday(&tv);
  2585. e->last_stamp = tv.tv_sec;
  2586. ++e->same_count;
  2587. } else {
  2588. if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
  2589. ++elastidx;
  2590. if (elastidx == MAX_EVENTS)
  2591. elastidx = 0;
  2592. if (elastidx == eoldidx) { /* reached mark ? */
  2593. ++eoldidx;
  2594. if (eoldidx == MAX_EVENTS)
  2595. eoldidx = 0;
  2596. }
  2597. }
  2598. e = &ebuffer[elastidx];
  2599. e->event_source = source;
  2600. e->event_idx = idx;
  2601. do_gettimeofday(&tv);
  2602. e->first_stamp = e->last_stamp = tv.tv_sec;
  2603. e->same_count = 1;
  2604. e->event_data = *evt;
  2605. e->application = 0;
  2606. }
  2607. return e;
  2608. }
  2609. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
  2610. {
  2611. gdth_evt_str *e;
  2612. int eindex;
  2613. ulong flags;
  2614. TRACE2(("gdth_read_event() handle %d\n", handle));
  2615. spin_lock_irqsave(&ha->smp_lock, flags);
  2616. if (handle == -1)
  2617. eindex = eoldidx;
  2618. else
  2619. eindex = handle;
  2620. estr->event_source = 0;
  2621. if (eindex >= MAX_EVENTS) {
  2622. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2623. return eindex;
  2624. }
  2625. e = &ebuffer[eindex];
  2626. if (e->event_source != 0) {
  2627. if (eindex != elastidx) {
  2628. if (++eindex == MAX_EVENTS)
  2629. eindex = 0;
  2630. } else {
  2631. eindex = -1;
  2632. }
  2633. memcpy(estr, e, sizeof(gdth_evt_str));
  2634. }
  2635. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2636. return eindex;
  2637. }
  2638. static void gdth_readapp_event(gdth_ha_str *ha,
  2639. unchar application, gdth_evt_str *estr)
  2640. {
  2641. gdth_evt_str *e;
  2642. int eindex;
  2643. ulong flags;
  2644. unchar found = FALSE;
  2645. TRACE2(("gdth_readapp_event() app. %d\n", application));
  2646. spin_lock_irqsave(&ha->smp_lock, flags);
  2647. eindex = eoldidx;
  2648. for (;;) {
  2649. e = &ebuffer[eindex];
  2650. if (e->event_source == 0)
  2651. break;
  2652. if ((e->application & application) == 0) {
  2653. e->application |= application;
  2654. found = TRUE;
  2655. break;
  2656. }
  2657. if (eindex == elastidx)
  2658. break;
  2659. if (++eindex == MAX_EVENTS)
  2660. eindex = 0;
  2661. }
  2662. if (found)
  2663. memcpy(estr, e, sizeof(gdth_evt_str));
  2664. else
  2665. estr->event_source = 0;
  2666. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2667. }
  2668. static void gdth_clear_events(void)
  2669. {
  2670. TRACE(("gdth_clear_events()"));
  2671. eoldidx = elastidx = 0;
  2672. ebuffer[0].event_source = 0;
  2673. }
  2674. /* SCSI interface functions */
  2675. static irqreturn_t __gdth_interrupt(gdth_ha_str *ha,
  2676. int gdth_from_wait, int* pIndex)
  2677. {
  2678. gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
  2679. gdt6_dpram_str __iomem *dp6_ptr;
  2680. gdt2_dpram_str __iomem *dp2_ptr;
  2681. Scsi_Cmnd *scp;
  2682. int rval, i;
  2683. unchar IStatus;
  2684. ushort Service;
  2685. ulong flags = 0;
  2686. #ifdef INT_COAL
  2687. int coalesced = FALSE;
  2688. int next = FALSE;
  2689. gdth_coal_status *pcs = NULL;
  2690. int act_int_coal = 0;
  2691. #endif
  2692. TRACE(("gdth_interrupt() IRQ %d\n", ha->irq));
  2693. /* if polling and not from gdth_wait() -> return */
  2694. if (gdth_polling) {
  2695. if (!gdth_from_wait) {
  2696. return IRQ_HANDLED;
  2697. }
  2698. }
  2699. if (!gdth_polling)
  2700. spin_lock_irqsave(&ha->smp_lock, flags);
  2701. /* search controller */
  2702. IStatus = gdth_get_status(ha);
  2703. if (IStatus == 0) {
  2704. /* spurious interrupt */
  2705. if (!gdth_polling)
  2706. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2707. return IRQ_HANDLED;
  2708. }
  2709. #ifdef GDTH_STATISTICS
  2710. ++act_ints;
  2711. #endif
  2712. #ifdef INT_COAL
  2713. /* See if the fw is returning coalesced status */
  2714. if (IStatus == COALINDEX) {
  2715. /* Coalesced status. Setup the initial status
  2716. buffer pointer and flags */
  2717. pcs = ha->coal_stat;
  2718. coalesced = TRUE;
  2719. next = TRUE;
  2720. }
  2721. do {
  2722. if (coalesced) {
  2723. /* For coalesced requests all status
  2724. information is found in the status buffer */
  2725. IStatus = (unchar)(pcs->status & 0xff);
  2726. }
  2727. #endif
  2728. if (ha->type == GDT_EISA) {
  2729. if (IStatus & 0x80) { /* error flag */
  2730. IStatus &= ~0x80;
  2731. ha->status = inw(ha->bmic + MAILBOXREG+8);
  2732. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2733. } else /* no error */
  2734. ha->status = S_OK;
  2735. ha->info = inl(ha->bmic + MAILBOXREG+12);
  2736. ha->service = inw(ha->bmic + MAILBOXREG+10);
  2737. ha->info2 = inl(ha->bmic + MAILBOXREG+4);
  2738. outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
  2739. outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
  2740. } else if (ha->type == GDT_ISA) {
  2741. dp2_ptr = ha->brd;
  2742. if (IStatus & 0x80) { /* error flag */
  2743. IStatus &= ~0x80;
  2744. ha->status = readw(&dp2_ptr->u.ic.Status);
  2745. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2746. } else /* no error */
  2747. ha->status = S_OK;
  2748. ha->info = readl(&dp2_ptr->u.ic.Info[0]);
  2749. ha->service = readw(&dp2_ptr->u.ic.Service);
  2750. ha->info2 = readl(&dp2_ptr->u.ic.Info[1]);
  2751. writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
  2752. writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
  2753. writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
  2754. } else if (ha->type == GDT_PCI) {
  2755. dp6_ptr = ha->brd;
  2756. if (IStatus & 0x80) { /* error flag */
  2757. IStatus &= ~0x80;
  2758. ha->status = readw(&dp6_ptr->u.ic.Status);
  2759. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2760. } else /* no error */
  2761. ha->status = S_OK;
  2762. ha->info = readl(&dp6_ptr->u.ic.Info[0]);
  2763. ha->service = readw(&dp6_ptr->u.ic.Service);
  2764. ha->info2 = readl(&dp6_ptr->u.ic.Info[1]);
  2765. writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
  2766. writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
  2767. writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
  2768. } else if (ha->type == GDT_PCINEW) {
  2769. if (IStatus & 0x80) { /* error flag */
  2770. IStatus &= ~0x80;
  2771. ha->status = inw(PTR2USHORT(&ha->plx->status));
  2772. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2773. } else
  2774. ha->status = S_OK;
  2775. ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
  2776. ha->service = inw(PTR2USHORT(&ha->plx->service));
  2777. ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
  2778. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  2779. outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
  2780. } else if (ha->type == GDT_PCIMPR) {
  2781. dp6m_ptr = ha->brd;
  2782. if (IStatus & 0x80) { /* error flag */
  2783. IStatus &= ~0x80;
  2784. #ifdef INT_COAL
  2785. if (coalesced)
  2786. ha->status = pcs->ext_status & 0xffff;
  2787. else
  2788. #endif
  2789. ha->status = readw(&dp6m_ptr->i960r.status);
  2790. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  2791. } else /* no error */
  2792. ha->status = S_OK;
  2793. #ifdef INT_COAL
  2794. /* get information */
  2795. if (coalesced) {
  2796. ha->info = pcs->info0;
  2797. ha->info2 = pcs->info1;
  2798. ha->service = (pcs->ext_status >> 16) & 0xffff;
  2799. } else
  2800. #endif
  2801. {
  2802. ha->info = readl(&dp6m_ptr->i960r.info[0]);
  2803. ha->service = readw(&dp6m_ptr->i960r.service);
  2804. ha->info2 = readl(&dp6m_ptr->i960r.info[1]);
  2805. }
  2806. /* event string */
  2807. if (IStatus == ASYNCINDEX) {
  2808. if (ha->service != SCREENSERVICE &&
  2809. (ha->fw_vers & 0xff) >= 0x1a) {
  2810. ha->dvr.severity = readb
  2811. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
  2812. for (i = 0; i < 256; ++i) {
  2813. ha->dvr.event_string[i] = readb
  2814. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
  2815. if (ha->dvr.event_string[i] == 0)
  2816. break;
  2817. }
  2818. }
  2819. }
  2820. #ifdef INT_COAL
  2821. /* Make sure that non coalesced interrupts get cleared
  2822. before being handled by gdth_async_event/gdth_sync_event */
  2823. if (!coalesced)
  2824. #endif
  2825. {
  2826. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2827. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2828. }
  2829. } else {
  2830. TRACE2(("gdth_interrupt() unknown controller type\n"));
  2831. if (!gdth_polling)
  2832. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2833. return IRQ_HANDLED;
  2834. }
  2835. TRACE(("gdth_interrupt() index %d stat %d info %d\n",
  2836. IStatus,ha->status,ha->info));
  2837. if (gdth_from_wait) {
  2838. *pIndex = (int)IStatus;
  2839. }
  2840. if (IStatus == ASYNCINDEX) {
  2841. TRACE2(("gdth_interrupt() async. event\n"));
  2842. gdth_async_event(ha);
  2843. if (!gdth_polling)
  2844. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2845. gdth_next(ha);
  2846. return IRQ_HANDLED;
  2847. }
  2848. if (IStatus == SPEZINDEX) {
  2849. TRACE2(("Service unknown or not initialized !\n"));
  2850. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2851. ha->dvr.eu.driver.ionode = ha->hanum;
  2852. gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
  2853. if (!gdth_polling)
  2854. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2855. return IRQ_HANDLED;
  2856. }
  2857. scp = ha->cmd_tab[IStatus-2].cmnd;
  2858. Service = ha->cmd_tab[IStatus-2].service;
  2859. ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
  2860. if (scp == UNUSED_CMND) {
  2861. TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
  2862. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  2863. ha->dvr.eu.driver.ionode = ha->hanum;
  2864. ha->dvr.eu.driver.index = IStatus;
  2865. gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
  2866. if (!gdth_polling)
  2867. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2868. return IRQ_HANDLED;
  2869. }
  2870. if (scp == INTERNAL_CMND) {
  2871. TRACE(("gdth_interrupt() answer to internal command\n"));
  2872. if (!gdth_polling)
  2873. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2874. return IRQ_HANDLED;
  2875. }
  2876. TRACE(("gdth_interrupt() sync. status\n"));
  2877. rval = gdth_sync_event(ha,Service,IStatus,scp);
  2878. if (!gdth_polling)
  2879. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2880. if (rval == 2) {
  2881. gdth_putq(ha, scp, gdth_cmnd_priv(scp)->priority);
  2882. } else if (rval == 1) {
  2883. gdth_scsi_done(scp);
  2884. }
  2885. #ifdef INT_COAL
  2886. if (coalesced) {
  2887. /* go to the next status in the status buffer */
  2888. ++pcs;
  2889. #ifdef GDTH_STATISTICS
  2890. ++act_int_coal;
  2891. if (act_int_coal > max_int_coal) {
  2892. max_int_coal = act_int_coal;
  2893. printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
  2894. }
  2895. #endif
  2896. /* see if there is another status */
  2897. if (pcs->status == 0)
  2898. /* Stop the coalesce loop */
  2899. next = FALSE;
  2900. }
  2901. } while (next);
  2902. /* coalescing only for new GDT_PCIMPR controllers available */
  2903. if (ha->type == GDT_PCIMPR && coalesced) {
  2904. writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  2905. writeb(0, &dp6m_ptr->i960r.sema1_reg);
  2906. }
  2907. #endif
  2908. gdth_next(ha);
  2909. return IRQ_HANDLED;
  2910. }
  2911. static irqreturn_t gdth_interrupt(int irq, void *dev_id)
  2912. {
  2913. gdth_ha_str *ha = dev_id;
  2914. return __gdth_interrupt(ha, false, NULL);
  2915. }
  2916. static int gdth_sync_event(gdth_ha_str *ha, int service, unchar index,
  2917. Scsi_Cmnd *scp)
  2918. {
  2919. gdth_msg_str *msg;
  2920. gdth_cmd_str *cmdp;
  2921. unchar b, t;
  2922. struct gdth_cmndinfo *cmndinfo = gdth_cmnd_priv(scp);
  2923. cmdp = ha->pccb;
  2924. TRACE(("gdth_sync_event() serv %d status %d\n",
  2925. service,ha->status));
  2926. if (service == SCREENSERVICE) {
  2927. msg = ha->pmsg;
  2928. TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
  2929. msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
  2930. if (msg->msg_len > MSGLEN+1)
  2931. msg->msg_len = MSGLEN+1;
  2932. if (msg->msg_len)
  2933. if (!(msg->msg_answer && msg->msg_ext)) {
  2934. msg->msg_text[msg->msg_len] = '\0';
  2935. printk("%s",msg->msg_text);
  2936. }
  2937. if (msg->msg_ext && !msg->msg_answer) {
  2938. while (gdth_test_busy(ha))
  2939. gdth_delay(0);
  2940. cmdp->Service = SCREENSERVICE;
  2941. cmdp->RequestBuffer = SCREEN_CMND;
  2942. gdth_get_cmd_index(ha);
  2943. gdth_set_sema0(ha);
  2944. cmdp->OpCode = GDT_READ;
  2945. cmdp->BoardNode = LOCALBOARD;
  2946. cmdp->u.screen.reserved = 0;
  2947. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  2948. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  2949. ha->cmd_offs_dpmem = 0;
  2950. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  2951. + sizeof(ulong64);
  2952. ha->cmd_cnt = 0;
  2953. gdth_copy_command(ha);
  2954. gdth_release_event(ha);
  2955. return 0;
  2956. }
  2957. if (msg->msg_answer && msg->msg_alen) {
  2958. /* default answers (getchar() not possible) */
  2959. if (msg->msg_alen == 1) {
  2960. msg->msg_alen = 0;
  2961. msg->msg_len = 1;
  2962. msg->msg_text[0] = 0;
  2963. } else {
  2964. msg->msg_alen -= 2;
  2965. msg->msg_len = 2;
  2966. msg->msg_text[0] = 1;
  2967. msg->msg_text[1] = 0;
  2968. }
  2969. msg->msg_ext = 0;
  2970. msg->msg_answer = 0;
  2971. while (gdth_test_busy(ha))
  2972. gdth_delay(0);
  2973. cmdp->Service = SCREENSERVICE;
  2974. cmdp->RequestBuffer = SCREEN_CMND;
  2975. gdth_get_cmd_index(ha);
  2976. gdth_set_sema0(ha);
  2977. cmdp->OpCode = GDT_WRITE;
  2978. cmdp->BoardNode = LOCALBOARD;
  2979. cmdp->u.screen.reserved = 0;
  2980. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  2981. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  2982. ha->cmd_offs_dpmem = 0;
  2983. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  2984. + sizeof(ulong64);
  2985. ha->cmd_cnt = 0;
  2986. gdth_copy_command(ha);
  2987. gdth_release_event(ha);
  2988. return 0;
  2989. }
  2990. printk("\n");
  2991. } else {
  2992. b = scp->device->channel;
  2993. t = scp->device->id;
  2994. if (cmndinfo->OpCode == -1 && b != ha->virt_bus) {
  2995. ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
  2996. }
  2997. /* cache or raw service */
  2998. if (ha->status == S_BSY) {
  2999. TRACE2(("Controller busy -> retry !\n"));
  3000. if (cmndinfo->OpCode == GDT_MOUNT)
  3001. cmndinfo->OpCode = GDT_CLUST_INFO;
  3002. /* retry */
  3003. return 2;
  3004. }
  3005. if (scsi_bufflen(scp))
  3006. pci_unmap_sg(ha->pdev, scsi_sglist(scp), scsi_sg_count(scp),
  3007. cmndinfo->dma_dir);
  3008. if (cmndinfo->sense_paddr)
  3009. pci_unmap_page(ha->pdev, cmndinfo->sense_paddr, 16,
  3010. PCI_DMA_FROMDEVICE);
  3011. if (ha->status == S_OK) {
  3012. cmndinfo->status = S_OK;
  3013. cmndinfo->info = ha->info;
  3014. if (cmndinfo->OpCode != -1) {
  3015. TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
  3016. cmndinfo->OpCode));
  3017. /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
  3018. if (cmndinfo->OpCode == GDT_CLUST_INFO) {
  3019. ha->hdr[t].cluster_type = (unchar)ha->info;
  3020. if (!(ha->hdr[t].cluster_type &
  3021. CLUSTER_MOUNTED)) {
  3022. /* NOT MOUNTED -> MOUNT */
  3023. cmndinfo->OpCode = GDT_MOUNT;
  3024. if (ha->hdr[t].cluster_type &
  3025. CLUSTER_RESERVED) {
  3026. /* cluster drive RESERVED (on the other node) */
  3027. cmndinfo->phase = -2; /* reservation conflict */
  3028. }
  3029. } else {
  3030. cmndinfo->OpCode = -1;
  3031. }
  3032. } else {
  3033. if (cmndinfo->OpCode == GDT_MOUNT) {
  3034. ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
  3035. ha->hdr[t].media_changed = TRUE;
  3036. } else if (cmndinfo->OpCode == GDT_UNMOUNT) {
  3037. ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
  3038. ha->hdr[t].media_changed = TRUE;
  3039. }
  3040. cmndinfo->OpCode = -1;
  3041. }
  3042. /* retry */
  3043. cmndinfo->priority = HIGH_PRI;
  3044. return 2;
  3045. } else {
  3046. /* RESERVE/RELEASE ? */
  3047. if (scp->cmnd[0] == RESERVE) {
  3048. ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
  3049. } else if (scp->cmnd[0] == RELEASE) {
  3050. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3051. }
  3052. scp->result = DID_OK << 16;
  3053. scp->sense_buffer[0] = 0;
  3054. }
  3055. } else {
  3056. cmndinfo->status = ha->status;
  3057. cmndinfo->info = ha->info;
  3058. if (cmndinfo->OpCode != -1) {
  3059. TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
  3060. cmndinfo->OpCode, ha->status));
  3061. if (cmndinfo->OpCode == GDT_SCAN_START ||
  3062. cmndinfo->OpCode == GDT_SCAN_END) {
  3063. cmndinfo->OpCode = -1;
  3064. /* retry */
  3065. cmndinfo->priority = HIGH_PRI;
  3066. return 2;
  3067. }
  3068. memset((char*)scp->sense_buffer,0,16);
  3069. scp->sense_buffer[0] = 0x70;
  3070. scp->sense_buffer[2] = NOT_READY;
  3071. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3072. } else if (service == CACHESERVICE) {
  3073. if (ha->status == S_CACHE_UNKNOWN &&
  3074. (ha->hdr[t].cluster_type &
  3075. CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
  3076. /* bus reset -> force GDT_CLUST_INFO */
  3077. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3078. }
  3079. memset((char*)scp->sense_buffer,0,16);
  3080. if (ha->status == (ushort)S_CACHE_RESERV) {
  3081. scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
  3082. } else {
  3083. scp->sense_buffer[0] = 0x70;
  3084. scp->sense_buffer[2] = NOT_READY;
  3085. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3086. }
  3087. if (!cmndinfo->internal_command) {
  3088. ha->dvr.size = sizeof(ha->dvr.eu.sync);
  3089. ha->dvr.eu.sync.ionode = ha->hanum;
  3090. ha->dvr.eu.sync.service = service;
  3091. ha->dvr.eu.sync.status = ha->status;
  3092. ha->dvr.eu.sync.info = ha->info;
  3093. ha->dvr.eu.sync.hostdrive = t;
  3094. if (ha->status >= 0x8000)
  3095. gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
  3096. else
  3097. gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
  3098. }
  3099. } else {
  3100. /* sense buffer filled from controller firmware (DMA) */
  3101. if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
  3102. scp->result = DID_BAD_TARGET << 16;
  3103. } else {
  3104. scp->result = (DID_OK << 16) | ha->info;
  3105. }
  3106. }
  3107. }
  3108. if (!cmndinfo->wait_for_completion)
  3109. cmndinfo->wait_for_completion++;
  3110. else
  3111. return 1;
  3112. }
  3113. return 0;
  3114. }
  3115. static char *async_cache_tab[] = {
  3116. /* 0*/ "\011\000\002\002\002\004\002\006\004"
  3117. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3118. /* 1*/ "\011\000\002\002\002\004\002\006\004"
  3119. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3120. /* 2*/ "\005\000\002\006\004"
  3121. "GDT HA %u, Host Drive %lu not ready",
  3122. /* 3*/ "\005\000\002\006\004"
  3123. "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3124. /* 4*/ "\005\000\002\006\004"
  3125. "GDT HA %u, mirror update on Host Drive %lu failed",
  3126. /* 5*/ "\005\000\002\006\004"
  3127. "GDT HA %u, Mirror Drive %lu failed",
  3128. /* 6*/ "\005\000\002\006\004"
  3129. "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3130. /* 7*/ "\005\000\002\006\004"
  3131. "GDT HA %u, Host Drive %lu write protected",
  3132. /* 8*/ "\005\000\002\006\004"
  3133. "GDT HA %u, media changed in Host Drive %lu",
  3134. /* 9*/ "\005\000\002\006\004"
  3135. "GDT HA %u, Host Drive %lu is offline",
  3136. /*10*/ "\005\000\002\006\004"
  3137. "GDT HA %u, media change of Mirror Drive %lu",
  3138. /*11*/ "\005\000\002\006\004"
  3139. "GDT HA %u, Mirror Drive %lu is write protected",
  3140. /*12*/ "\005\000\002\006\004"
  3141. "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
  3142. /*13*/ "\007\000\002\006\002\010\002"
  3143. "GDT HA %u, Array Drive %u: Cache Drive %u failed",
  3144. /*14*/ "\005\000\002\006\002"
  3145. "GDT HA %u, Array Drive %u: FAIL state entered",
  3146. /*15*/ "\005\000\002\006\002"
  3147. "GDT HA %u, Array Drive %u: error",
  3148. /*16*/ "\007\000\002\006\002\010\002"
  3149. "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
  3150. /*17*/ "\005\000\002\006\002"
  3151. "GDT HA %u, Array Drive %u: parity build failed",
  3152. /*18*/ "\005\000\002\006\002"
  3153. "GDT HA %u, Array Drive %u: drive rebuild failed",
  3154. /*19*/ "\005\000\002\010\002"
  3155. "GDT HA %u, Test of Hot Fix %u failed",
  3156. /*20*/ "\005\000\002\006\002"
  3157. "GDT HA %u, Array Drive %u: drive build finished successfully",
  3158. /*21*/ "\005\000\002\006\002"
  3159. "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
  3160. /*22*/ "\007\000\002\006\002\010\002"
  3161. "GDT HA %u, Array Drive %u: Hot Fix %u activated",
  3162. /*23*/ "\005\000\002\006\002"
  3163. "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
  3164. /*24*/ "\005\000\002\010\002"
  3165. "GDT HA %u, mirror update on Cache Drive %u completed",
  3166. /*25*/ "\005\000\002\010\002"
  3167. "GDT HA %u, mirror update on Cache Drive %lu failed",
  3168. /*26*/ "\005\000\002\006\002"
  3169. "GDT HA %u, Array Drive %u: drive rebuild started",
  3170. /*27*/ "\005\000\002\012\001"
  3171. "GDT HA %u, Fault bus %u: SHELF OK detected",
  3172. /*28*/ "\005\000\002\012\001"
  3173. "GDT HA %u, Fault bus %u: SHELF not OK detected",
  3174. /*29*/ "\007\000\002\012\001\013\001"
  3175. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
  3176. /*30*/ "\007\000\002\012\001\013\001"
  3177. "GDT HA %u, Fault bus %u, ID %u: new disk detected",
  3178. /*31*/ "\007\000\002\012\001\013\001"
  3179. "GDT HA %u, Fault bus %u, ID %u: old disk detected",
  3180. /*32*/ "\007\000\002\012\001\013\001"
  3181. "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
  3182. /*33*/ "\007\000\002\012\001\013\001"
  3183. "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
  3184. /*34*/ "\011\000\002\012\001\013\001\006\004"
  3185. "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
  3186. /*35*/ "\007\000\002\012\001\013\001"
  3187. "GDT HA %u, Fault bus %u, ID %u: disk write protected",
  3188. /*36*/ "\007\000\002\012\001\013\001"
  3189. "GDT HA %u, Fault bus %u, ID %u: disk not available",
  3190. /*37*/ "\007\000\002\012\001\006\004"
  3191. "GDT HA %u, Fault bus %u: swap detected (%lu)",
  3192. /*38*/ "\007\000\002\012\001\013\001"
  3193. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
  3194. /*39*/ "\007\000\002\012\001\013\001"
  3195. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
  3196. /*40*/ "\007\000\002\012\001\013\001"
  3197. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
  3198. /*41*/ "\007\000\002\012\001\013\001"
  3199. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
  3200. /*42*/ "\005\000\002\006\002"
  3201. "GDT HA %u, Array Drive %u: drive build started",
  3202. /*43*/ "\003\000\002"
  3203. "GDT HA %u, DRAM parity error detected",
  3204. /*44*/ "\005\000\002\006\002"
  3205. "GDT HA %u, Mirror Drive %u: update started",
  3206. /*45*/ "\007\000\002\006\002\010\002"
  3207. "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
  3208. /*46*/ "\005\000\002\006\002"
  3209. "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
  3210. /*47*/ "\005\000\002\006\002"
  3211. "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
  3212. /*48*/ "\005\000\002\006\002"
  3213. "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
  3214. /*49*/ "\005\000\002\006\002"
  3215. "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
  3216. /*50*/ "\007\000\002\012\001\013\001"
  3217. "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
  3218. /*51*/ "\005\000\002\006\002"
  3219. "GDT HA %u, Array Drive %u: expand started",
  3220. /*52*/ "\005\000\002\006\002"
  3221. "GDT HA %u, Array Drive %u: expand finished successfully",
  3222. /*53*/ "\005\000\002\006\002"
  3223. "GDT HA %u, Array Drive %u: expand failed",
  3224. /*54*/ "\003\000\002"
  3225. "GDT HA %u, CPU temperature critical",
  3226. /*55*/ "\003\000\002"
  3227. "GDT HA %u, CPU temperature OK",
  3228. /*56*/ "\005\000\002\006\004"
  3229. "GDT HA %u, Host drive %lu created",
  3230. /*57*/ "\005\000\002\006\002"
  3231. "GDT HA %u, Array Drive %u: expand restarted",
  3232. /*58*/ "\005\000\002\006\002"
  3233. "GDT HA %u, Array Drive %u: expand stopped",
  3234. /*59*/ "\005\000\002\010\002"
  3235. "GDT HA %u, Mirror Drive %u: drive build quited",
  3236. /*60*/ "\005\000\002\006\002"
  3237. "GDT HA %u, Array Drive %u: parity build quited",
  3238. /*61*/ "\005\000\002\006\002"
  3239. "GDT HA %u, Array Drive %u: drive rebuild quited",
  3240. /*62*/ "\005\000\002\006\002"
  3241. "GDT HA %u, Array Drive %u: parity verify started",
  3242. /*63*/ "\005\000\002\006\002"
  3243. "GDT HA %u, Array Drive %u: parity verify done",
  3244. /*64*/ "\005\000\002\006\002"
  3245. "GDT HA %u, Array Drive %u: parity verify failed",
  3246. /*65*/ "\005\000\002\006\002"
  3247. "GDT HA %u, Array Drive %u: parity error detected",
  3248. /*66*/ "\005\000\002\006\002"
  3249. "GDT HA %u, Array Drive %u: parity verify quited",
  3250. /*67*/ "\005\000\002\006\002"
  3251. "GDT HA %u, Host Drive %u reserved",
  3252. /*68*/ "\005\000\002\006\002"
  3253. "GDT HA %u, Host Drive %u mounted and released",
  3254. /*69*/ "\005\000\002\006\002"
  3255. "GDT HA %u, Host Drive %u released",
  3256. /*70*/ "\003\000\002"
  3257. "GDT HA %u, DRAM error detected and corrected with ECC",
  3258. /*71*/ "\003\000\002"
  3259. "GDT HA %u, Uncorrectable DRAM error detected with ECC",
  3260. /*72*/ "\011\000\002\012\001\013\001\014\001"
  3261. "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
  3262. /*73*/ "\005\000\002\006\002"
  3263. "GDT HA %u, Host drive %u resetted locally",
  3264. /*74*/ "\005\000\002\006\002"
  3265. "GDT HA %u, Host drive %u resetted remotely",
  3266. /*75*/ "\003\000\002"
  3267. "GDT HA %u, async. status 75 unknown",
  3268. };
  3269. static int gdth_async_event(gdth_ha_str *ha)
  3270. {
  3271. gdth_cmd_str *cmdp;
  3272. int cmd_index;
  3273. cmdp= ha->pccb;
  3274. TRACE2(("gdth_async_event() ha %d serv %d\n",
  3275. ha->hanum, ha->service));
  3276. if (ha->service == SCREENSERVICE) {
  3277. if (ha->status == MSG_REQUEST) {
  3278. while (gdth_test_busy(ha))
  3279. gdth_delay(0);
  3280. cmdp->Service = SCREENSERVICE;
  3281. cmdp->RequestBuffer = SCREEN_CMND;
  3282. cmd_index = gdth_get_cmd_index(ha);
  3283. gdth_set_sema0(ha);
  3284. cmdp->OpCode = GDT_READ;
  3285. cmdp->BoardNode = LOCALBOARD;
  3286. cmdp->u.screen.reserved = 0;
  3287. cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
  3288. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3289. ha->cmd_offs_dpmem = 0;
  3290. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3291. + sizeof(ulong64);
  3292. ha->cmd_cnt = 0;
  3293. gdth_copy_command(ha);
  3294. if (ha->type == GDT_EISA)
  3295. printk("[EISA slot %d] ",(ushort)ha->brd_phys);
  3296. else if (ha->type == GDT_ISA)
  3297. printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
  3298. else
  3299. printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
  3300. (ushort)((ha->brd_phys>>3)&0x1f));
  3301. gdth_release_event(ha);
  3302. }
  3303. } else {
  3304. if (ha->type == GDT_PCIMPR &&
  3305. (ha->fw_vers & 0xff) >= 0x1a) {
  3306. ha->dvr.size = 0;
  3307. ha->dvr.eu.async.ionode = ha->hanum;
  3308. ha->dvr.eu.async.status = ha->status;
  3309. /* severity and event_string already set! */
  3310. } else {
  3311. ha->dvr.size = sizeof(ha->dvr.eu.async);
  3312. ha->dvr.eu.async.ionode = ha->hanum;
  3313. ha->dvr.eu.async.service = ha->service;
  3314. ha->dvr.eu.async.status = ha->status;
  3315. ha->dvr.eu.async.info = ha->info;
  3316. *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
  3317. }
  3318. gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
  3319. gdth_log_event( &ha->dvr, NULL );
  3320. /* new host drive from expand? */
  3321. if (ha->service == CACHESERVICE && ha->status == 56) {
  3322. TRACE2(("gdth_async_event(): new host drive %d created\n",
  3323. (ushort)ha->info));
  3324. /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
  3325. }
  3326. }
  3327. return 1;
  3328. }
  3329. static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
  3330. {
  3331. gdth_stackframe stack;
  3332. char *f = NULL;
  3333. int i,j;
  3334. TRACE2(("gdth_log_event()\n"));
  3335. if (dvr->size == 0) {
  3336. if (buffer == NULL) {
  3337. printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
  3338. } else {
  3339. sprintf(buffer,"Adapter %d: %s\n",
  3340. dvr->eu.async.ionode,dvr->event_string);
  3341. }
  3342. } else if (dvr->eu.async.service == CACHESERVICE &&
  3343. INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
  3344. TRACE2(("GDT: Async. event cache service, event no.: %d\n",
  3345. dvr->eu.async.status));
  3346. f = async_cache_tab[dvr->eu.async.status];
  3347. /* i: parameter to push, j: stack element to fill */
  3348. for (j=0,i=1; i < f[0]; i+=2) {
  3349. switch (f[i+1]) {
  3350. case 4:
  3351. stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
  3352. break;
  3353. case 2:
  3354. stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
  3355. break;
  3356. case 1:
  3357. stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
  3358. break;
  3359. default:
  3360. break;
  3361. }
  3362. }
  3363. if (buffer == NULL) {
  3364. printk(&f[(int)f[0]],stack);
  3365. printk("\n");
  3366. } else {
  3367. sprintf(buffer,&f[(int)f[0]],stack);
  3368. }
  3369. } else {
  3370. if (buffer == NULL) {
  3371. printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
  3372. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3373. } else {
  3374. sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
  3375. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3376. }
  3377. }
  3378. }
  3379. #ifdef GDTH_STATISTICS
  3380. static unchar gdth_timer_running;
  3381. static void gdth_timeout(ulong data)
  3382. {
  3383. ulong32 i;
  3384. Scsi_Cmnd *nscp;
  3385. gdth_ha_str *ha;
  3386. ulong flags;
  3387. if(unlikely(list_empty(&gdth_instances))) {
  3388. gdth_timer_running = 0;
  3389. return;
  3390. }
  3391. ha = list_first_entry(&gdth_instances, gdth_ha_str, list);
  3392. spin_lock_irqsave(&ha->smp_lock, flags);
  3393. for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
  3394. if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
  3395. ++act_stats;
  3396. for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  3397. ++act_rq;
  3398. TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
  3399. act_ints, act_ios, act_stats, act_rq));
  3400. act_ints = act_ios = 0;
  3401. gdth_timer.expires = jiffies + 30 * HZ;
  3402. add_timer(&gdth_timer);
  3403. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3404. }
  3405. static void gdth_timer_init(void)
  3406. {
  3407. if (gdth_timer_running)
  3408. return;
  3409. gdth_timer_running = 1;
  3410. TRACE2(("gdth_detect(): Initializing timer !\n"));
  3411. gdth_timer.expires = jiffies + HZ;
  3412. gdth_timer.data = 0L;
  3413. gdth_timer.function = gdth_timeout;
  3414. add_timer(&gdth_timer);
  3415. }
  3416. #else
  3417. static inline void gdth_timer_init(void)
  3418. {
  3419. }
  3420. #endif
  3421. static void __init internal_setup(char *str,int *ints)
  3422. {
  3423. int i, argc;
  3424. char *cur_str, *argv;
  3425. TRACE2(("internal_setup() str %s ints[0] %d\n",
  3426. str ? str:"NULL", ints ? ints[0]:0));
  3427. /* read irq[] from ints[] */
  3428. if (ints) {
  3429. argc = ints[0];
  3430. if (argc > 0) {
  3431. if (argc > MAXHA)
  3432. argc = MAXHA;
  3433. for (i = 0; i < argc; ++i)
  3434. irq[i] = ints[i+1];
  3435. }
  3436. }
  3437. /* analyse string */
  3438. argv = str;
  3439. while (argv && (cur_str = strchr(argv, ':'))) {
  3440. int val = 0, c = *++cur_str;
  3441. if (c == 'n' || c == 'N')
  3442. val = 0;
  3443. else if (c == 'y' || c == 'Y')
  3444. val = 1;
  3445. else
  3446. val = (int)simple_strtoul(cur_str, NULL, 0);
  3447. if (!strncmp(argv, "disable:", 8))
  3448. disable = val;
  3449. else if (!strncmp(argv, "reserve_mode:", 13))
  3450. reserve_mode = val;
  3451. else if (!strncmp(argv, "reverse_scan:", 13))
  3452. reverse_scan = val;
  3453. else if (!strncmp(argv, "hdr_channel:", 12))
  3454. hdr_channel = val;
  3455. else if (!strncmp(argv, "max_ids:", 8))
  3456. max_ids = val;
  3457. else if (!strncmp(argv, "rescan:", 7))
  3458. rescan = val;
  3459. else if (!strncmp(argv, "shared_access:", 14))
  3460. shared_access = val;
  3461. else if (!strncmp(argv, "probe_eisa_isa:", 15))
  3462. probe_eisa_isa = val;
  3463. else if (!strncmp(argv, "reserve_list:", 13)) {
  3464. reserve_list[0] = val;
  3465. for (i = 1; i < MAX_RES_ARGS; i++) {
  3466. cur_str = strchr(cur_str, ',');
  3467. if (!cur_str)
  3468. break;
  3469. if (!isdigit((int)*++cur_str)) {
  3470. --cur_str;
  3471. break;
  3472. }
  3473. reserve_list[i] =
  3474. (int)simple_strtoul(cur_str, NULL, 0);
  3475. }
  3476. if (!cur_str)
  3477. break;
  3478. argv = ++cur_str;
  3479. continue;
  3480. }
  3481. if ((argv = strchr(argv, ',')))
  3482. ++argv;
  3483. }
  3484. }
  3485. int __init option_setup(char *str)
  3486. {
  3487. int ints[MAXHA];
  3488. char *cur = str;
  3489. int i = 1;
  3490. TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
  3491. while (cur && isdigit(*cur) && i <= MAXHA) {
  3492. ints[i++] = simple_strtoul(cur, NULL, 0);
  3493. if ((cur = strchr(cur, ',')) != NULL) cur++;
  3494. }
  3495. ints[0] = i - 1;
  3496. internal_setup(cur, ints);
  3497. return 1;
  3498. }
  3499. static const char *gdth_ctr_name(gdth_ha_str *ha)
  3500. {
  3501. TRACE2(("gdth_ctr_name()\n"));
  3502. if (ha->type == GDT_EISA) {
  3503. switch (ha->stype) {
  3504. case GDT3_ID:
  3505. return("GDT3000/3020");
  3506. case GDT3A_ID:
  3507. return("GDT3000A/3020A/3050A");
  3508. case GDT3B_ID:
  3509. return("GDT3000B/3010A");
  3510. }
  3511. } else if (ha->type == GDT_ISA) {
  3512. return("GDT2000/2020");
  3513. } else if (ha->type == GDT_PCI) {
  3514. switch (ha->pdev->device) {
  3515. case PCI_DEVICE_ID_VORTEX_GDT60x0:
  3516. return("GDT6000/6020/6050");
  3517. case PCI_DEVICE_ID_VORTEX_GDT6000B:
  3518. return("GDT6000B/6010");
  3519. }
  3520. }
  3521. /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
  3522. return("");
  3523. }
  3524. static const char *gdth_info(struct Scsi_Host *shp)
  3525. {
  3526. gdth_ha_str *ha = shost_priv(shp);
  3527. TRACE2(("gdth_info()\n"));
  3528. return ((const char *)ha->binfo.type_string);
  3529. }
  3530. static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
  3531. {
  3532. gdth_ha_str *ha = shost_priv(scp->device->host);
  3533. int i;
  3534. ulong flags;
  3535. Scsi_Cmnd *cmnd;
  3536. unchar b;
  3537. TRACE2(("gdth_eh_bus_reset()\n"));
  3538. b = scp->device->channel;
  3539. /* clear command tab */
  3540. spin_lock_irqsave(&ha->smp_lock, flags);
  3541. for (i = 0; i < GDTH_MAXCMDS; ++i) {
  3542. cmnd = ha->cmd_tab[i].cmnd;
  3543. if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
  3544. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  3545. }
  3546. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3547. if (b == ha->virt_bus) {
  3548. /* host drives */
  3549. for (i = 0; i < MAX_HDRIVES; ++i) {
  3550. if (ha->hdr[i].present) {
  3551. spin_lock_irqsave(&ha->smp_lock, flags);
  3552. gdth_polling = TRUE;
  3553. while (gdth_test_busy(ha))
  3554. gdth_delay(0);
  3555. if (gdth_internal_cmd(ha, CACHESERVICE,
  3556. GDT_CLUST_RESET, i, 0, 0))
  3557. ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
  3558. gdth_polling = FALSE;
  3559. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3560. }
  3561. }
  3562. } else {
  3563. /* raw devices */
  3564. spin_lock_irqsave(&ha->smp_lock, flags);
  3565. for (i = 0; i < MAXID; ++i)
  3566. ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
  3567. gdth_polling = TRUE;
  3568. while (gdth_test_busy(ha))
  3569. gdth_delay(0);
  3570. gdth_internal_cmd(ha, SCSIRAWSERVICE, GDT_RESET_BUS,
  3571. BUS_L2P(ha,b), 0, 0);
  3572. gdth_polling = FALSE;
  3573. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3574. }
  3575. return SUCCESS;
  3576. }
  3577. static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
  3578. {
  3579. unchar b, t;
  3580. gdth_ha_str *ha = shost_priv(sdev->host);
  3581. struct scsi_device *sd;
  3582. unsigned capacity;
  3583. sd = sdev;
  3584. capacity = cap;
  3585. b = sd->channel;
  3586. t = sd->id;
  3587. TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", ha->hanum, b, t));
  3588. if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
  3589. /* raw device or host drive without mapping information */
  3590. TRACE2(("Evaluate mapping\n"));
  3591. gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
  3592. } else {
  3593. ip[0] = ha->hdr[t].heads;
  3594. ip[1] = ha->hdr[t].secs;
  3595. ip[2] = capacity / ip[0] / ip[1];
  3596. }
  3597. TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
  3598. ip[0],ip[1],ip[2]));
  3599. return 0;
  3600. }
  3601. static int gdth_queuecommand(struct scsi_cmnd *scp,
  3602. void (*done)(struct scsi_cmnd *))
  3603. {
  3604. gdth_ha_str *ha = shost_priv(scp->device->host);
  3605. struct gdth_cmndinfo *cmndinfo;
  3606. TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
  3607. cmndinfo = gdth_get_cmndinfo(ha);
  3608. BUG_ON(!cmndinfo);
  3609. scp->scsi_done = done;
  3610. gdth_update_timeout(scp, scp->timeout_per_command * 6);
  3611. cmndinfo->priority = DEFAULT_PRI;
  3612. return __gdth_queuecommand(ha, scp, cmndinfo);
  3613. }
  3614. static int __gdth_queuecommand(gdth_ha_str *ha, struct scsi_cmnd *scp,
  3615. struct gdth_cmndinfo *cmndinfo)
  3616. {
  3617. scp->host_scribble = (unsigned char *)cmndinfo;
  3618. cmndinfo->wait_for_completion = 1;
  3619. cmndinfo->phase = -1;
  3620. cmndinfo->OpCode = -1;
  3621. #ifdef GDTH_STATISTICS
  3622. ++act_ios;
  3623. #endif
  3624. gdth_putq(ha, scp, cmndinfo->priority);
  3625. gdth_next(ha);
  3626. return 0;
  3627. }
  3628. static int gdth_open(struct inode *inode, struct file *filep)
  3629. {
  3630. gdth_ha_str *ha;
  3631. lock_kernel();
  3632. list_for_each_entry(ha, &gdth_instances, list) {
  3633. if (!ha->sdev)
  3634. ha->sdev = scsi_get_host_dev(ha->shost);
  3635. }
  3636. unlock_kernel();
  3637. TRACE(("gdth_open()\n"));
  3638. return 0;
  3639. }
  3640. static int gdth_close(struct inode *inode, struct file *filep)
  3641. {
  3642. TRACE(("gdth_close()\n"));
  3643. return 0;
  3644. }
  3645. static int ioc_event(void __user *arg)
  3646. {
  3647. gdth_ioctl_event evt;
  3648. gdth_ha_str *ha;
  3649. ulong flags;
  3650. if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)))
  3651. return -EFAULT;
  3652. ha = gdth_find_ha(evt.ionode);
  3653. if (!ha)
  3654. return -EFAULT;
  3655. if (evt.erase == 0xff) {
  3656. if (evt.event.event_source == ES_TEST)
  3657. evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
  3658. else if (evt.event.event_source == ES_DRIVER)
  3659. evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
  3660. else if (evt.event.event_source == ES_SYNC)
  3661. evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
  3662. else
  3663. evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
  3664. spin_lock_irqsave(&ha->smp_lock, flags);
  3665. gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
  3666. &evt.event.event_data);
  3667. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3668. } else if (evt.erase == 0xfe) {
  3669. gdth_clear_events();
  3670. } else if (evt.erase == 0) {
  3671. evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
  3672. } else {
  3673. gdth_readapp_event(ha, evt.erase, &evt.event);
  3674. }
  3675. if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
  3676. return -EFAULT;
  3677. return 0;
  3678. }
  3679. static int ioc_lockdrv(void __user *arg)
  3680. {
  3681. gdth_ioctl_lockdrv ldrv;
  3682. unchar i, j;
  3683. ulong flags;
  3684. gdth_ha_str *ha;
  3685. if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)))
  3686. return -EFAULT;
  3687. ha = gdth_find_ha(ldrv.ionode);
  3688. if (!ha)
  3689. return -EFAULT;
  3690. for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
  3691. j = ldrv.drives[i];
  3692. if (j >= MAX_HDRIVES || !ha->hdr[j].present)
  3693. continue;
  3694. if (ldrv.lock) {
  3695. spin_lock_irqsave(&ha->smp_lock, flags);
  3696. ha->hdr[j].lock = 1;
  3697. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3698. gdth_wait_completion(ha, ha->bus_cnt, j);
  3699. gdth_stop_timeout(ha, ha->bus_cnt, j);
  3700. } else {
  3701. spin_lock_irqsave(&ha->smp_lock, flags);
  3702. ha->hdr[j].lock = 0;
  3703. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3704. gdth_start_timeout(ha, ha->bus_cnt, j);
  3705. gdth_next(ha);
  3706. }
  3707. }
  3708. return 0;
  3709. }
  3710. static int ioc_resetdrv(void __user *arg, char *cmnd)
  3711. {
  3712. gdth_ioctl_reset res;
  3713. gdth_cmd_str cmd;
  3714. gdth_ha_str *ha;
  3715. int rval;
  3716. if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
  3717. res.number >= MAX_HDRIVES)
  3718. return -EFAULT;
  3719. ha = gdth_find_ha(res.ionode);
  3720. if (!ha)
  3721. return -EFAULT;
  3722. if (!ha->hdr[res.number].present)
  3723. return 0;
  3724. memset(&cmd, 0, sizeof(gdth_cmd_str));
  3725. cmd.Service = CACHESERVICE;
  3726. cmd.OpCode = GDT_CLUST_RESET;
  3727. if (ha->cache_feat & GDT_64BIT)
  3728. cmd.u.cache64.DeviceNo = res.number;
  3729. else
  3730. cmd.u.cache.DeviceNo = res.number;
  3731. rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
  3732. if (rval < 0)
  3733. return rval;
  3734. res.status = rval;
  3735. if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
  3736. return -EFAULT;
  3737. return 0;
  3738. }
  3739. static int ioc_general(void __user *arg, char *cmnd)
  3740. {
  3741. gdth_ioctl_general gen;
  3742. char *buf = NULL;
  3743. ulong64 paddr;
  3744. gdth_ha_str *ha;
  3745. int rval;
  3746. if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)))
  3747. return -EFAULT;
  3748. ha = gdth_find_ha(gen.ionode);
  3749. if (!ha)
  3750. return -EFAULT;
  3751. if (gen.data_len + gen.sense_len != 0) {
  3752. if (!(buf = gdth_ioctl_alloc(ha, gen.data_len + gen.sense_len,
  3753. FALSE, &paddr)))
  3754. return -EFAULT;
  3755. if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
  3756. gen.data_len + gen.sense_len)) {
  3757. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3758. return -EFAULT;
  3759. }
  3760. if (gen.command.OpCode == GDT_IOCTL) {
  3761. gen.command.u.ioctl.p_param = paddr;
  3762. } else if (gen.command.Service == CACHESERVICE) {
  3763. if (ha->cache_feat & GDT_64BIT) {
  3764. /* copy elements from 32-bit IOCTL structure */
  3765. gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
  3766. gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
  3767. gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
  3768. /* addresses */
  3769. if (ha->cache_feat & SCATTER_GATHER) {
  3770. gen.command.u.cache64.DestAddr = (ulong64)-1;
  3771. gen.command.u.cache64.sg_canz = 1;
  3772. gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
  3773. gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
  3774. gen.command.u.cache64.sg_lst[1].sg_len = 0;
  3775. } else {
  3776. gen.command.u.cache64.DestAddr = paddr;
  3777. gen.command.u.cache64.sg_canz = 0;
  3778. }
  3779. } else {
  3780. if (ha->cache_feat & SCATTER_GATHER) {
  3781. gen.command.u.cache.DestAddr = 0xffffffff;
  3782. gen.command.u.cache.sg_canz = 1;
  3783. gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
  3784. gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
  3785. gen.command.u.cache.sg_lst[1].sg_len = 0;
  3786. } else {
  3787. gen.command.u.cache.DestAddr = paddr;
  3788. gen.command.u.cache.sg_canz = 0;
  3789. }
  3790. }
  3791. } else if (gen.command.Service == SCSIRAWSERVICE) {
  3792. if (ha->raw_feat & GDT_64BIT) {
  3793. /* copy elements from 32-bit IOCTL structure */
  3794. char cmd[16];
  3795. gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
  3796. gen.command.u.raw64.bus = gen.command.u.raw.bus;
  3797. gen.command.u.raw64.lun = gen.command.u.raw.lun;
  3798. gen.command.u.raw64.target = gen.command.u.raw.target;
  3799. memcpy(cmd, gen.command.u.raw.cmd, 16);
  3800. memcpy(gen.command.u.raw64.cmd, cmd, 16);
  3801. gen.command.u.raw64.clen = gen.command.u.raw.clen;
  3802. gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
  3803. gen.command.u.raw64.direction = gen.command.u.raw.direction;
  3804. /* addresses */
  3805. if (ha->raw_feat & SCATTER_GATHER) {
  3806. gen.command.u.raw64.sdata = (ulong64)-1;
  3807. gen.command.u.raw64.sg_ranz = 1;
  3808. gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
  3809. gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
  3810. gen.command.u.raw64.sg_lst[1].sg_len = 0;
  3811. } else {
  3812. gen.command.u.raw64.sdata = paddr;
  3813. gen.command.u.raw64.sg_ranz = 0;
  3814. }
  3815. gen.command.u.raw64.sense_data = paddr + gen.data_len;
  3816. } else {
  3817. if (ha->raw_feat & SCATTER_GATHER) {
  3818. gen.command.u.raw.sdata = 0xffffffff;
  3819. gen.command.u.raw.sg_ranz = 1;
  3820. gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
  3821. gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
  3822. gen.command.u.raw.sg_lst[1].sg_len = 0;
  3823. } else {
  3824. gen.command.u.raw.sdata = paddr;
  3825. gen.command.u.raw.sg_ranz = 0;
  3826. }
  3827. gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
  3828. }
  3829. } else {
  3830. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3831. return -EFAULT;
  3832. }
  3833. }
  3834. rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
  3835. if (rval < 0)
  3836. return rval;
  3837. gen.status = rval;
  3838. if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
  3839. gen.data_len + gen.sense_len)) {
  3840. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3841. return -EFAULT;
  3842. }
  3843. if (copy_to_user(arg, &gen,
  3844. sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
  3845. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3846. return -EFAULT;
  3847. }
  3848. gdth_ioctl_free(ha, gen.data_len+gen.sense_len, buf, paddr);
  3849. return 0;
  3850. }
  3851. static int ioc_hdrlist(void __user *arg, char *cmnd)
  3852. {
  3853. gdth_ioctl_rescan *rsc;
  3854. gdth_cmd_str *cmd;
  3855. gdth_ha_str *ha;
  3856. unchar i;
  3857. int rc = -ENOMEM;
  3858. u32 cluster_type = 0;
  3859. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3860. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3861. if (!rsc || !cmd)
  3862. goto free_fail;
  3863. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3864. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3865. rc = -EFAULT;
  3866. goto free_fail;
  3867. }
  3868. memset(cmd, 0, sizeof(gdth_cmd_str));
  3869. for (i = 0; i < MAX_HDRIVES; ++i) {
  3870. if (!ha->hdr[i].present) {
  3871. rsc->hdr_list[i].bus = 0xff;
  3872. continue;
  3873. }
  3874. rsc->hdr_list[i].bus = ha->virt_bus;
  3875. rsc->hdr_list[i].target = i;
  3876. rsc->hdr_list[i].lun = 0;
  3877. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  3878. if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
  3879. cmd->Service = CACHESERVICE;
  3880. cmd->OpCode = GDT_CLUST_INFO;
  3881. if (ha->cache_feat & GDT_64BIT)
  3882. cmd->u.cache64.DeviceNo = i;
  3883. else
  3884. cmd->u.cache.DeviceNo = i;
  3885. if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
  3886. rsc->hdr_list[i].cluster_type = cluster_type;
  3887. }
  3888. }
  3889. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  3890. rc = -EFAULT;
  3891. else
  3892. rc = 0;
  3893. free_fail:
  3894. kfree(rsc);
  3895. kfree(cmd);
  3896. return rc;
  3897. }
  3898. static int ioc_rescan(void __user *arg, char *cmnd)
  3899. {
  3900. gdth_ioctl_rescan *rsc;
  3901. gdth_cmd_str *cmd;
  3902. ushort i, status, hdr_cnt;
  3903. ulong32 info;
  3904. int cyls, hds, secs;
  3905. int rc = -ENOMEM;
  3906. ulong flags;
  3907. gdth_ha_str *ha;
  3908. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  3909. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  3910. if (!cmd || !rsc)
  3911. goto free_fail;
  3912. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  3913. (NULL == (ha = gdth_find_ha(rsc->ionode)))) {
  3914. rc = -EFAULT;
  3915. goto free_fail;
  3916. }
  3917. memset(cmd, 0, sizeof(gdth_cmd_str));
  3918. if (rsc->flag == 0) {
  3919. /* old method: re-init. cache service */
  3920. cmd->Service = CACHESERVICE;
  3921. if (ha->cache_feat & GDT_64BIT) {
  3922. cmd->OpCode = GDT_X_INIT_HOST;
  3923. cmd->u.cache64.DeviceNo = LINUX_OS;
  3924. } else {
  3925. cmd->OpCode = GDT_INIT;
  3926. cmd->u.cache.DeviceNo = LINUX_OS;
  3927. }
  3928. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3929. i = 0;
  3930. hdr_cnt = (status == S_OK ? (ushort)info : 0);
  3931. } else {
  3932. i = rsc->hdr_no;
  3933. hdr_cnt = i + 1;
  3934. }
  3935. for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
  3936. cmd->Service = CACHESERVICE;
  3937. cmd->OpCode = GDT_INFO;
  3938. if (ha->cache_feat & GDT_64BIT)
  3939. cmd->u.cache64.DeviceNo = i;
  3940. else
  3941. cmd->u.cache.DeviceNo = i;
  3942. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3943. spin_lock_irqsave(&ha->smp_lock, flags);
  3944. rsc->hdr_list[i].bus = ha->virt_bus;
  3945. rsc->hdr_list[i].target = i;
  3946. rsc->hdr_list[i].lun = 0;
  3947. if (status != S_OK) {
  3948. ha->hdr[i].present = FALSE;
  3949. } else {
  3950. ha->hdr[i].present = TRUE;
  3951. ha->hdr[i].size = info;
  3952. /* evaluate mapping */
  3953. ha->hdr[i].size &= ~SECS32;
  3954. gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
  3955. ha->hdr[i].heads = hds;
  3956. ha->hdr[i].secs = secs;
  3957. /* round size */
  3958. ha->hdr[i].size = cyls * hds * secs;
  3959. }
  3960. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3961. if (status != S_OK)
  3962. continue;
  3963. /* extended info, if GDT_64BIT, for drives > 2 TB */
  3964. /* but we need ha->info2, not yet stored in scp->SCp */
  3965. /* devtype, cluster info, R/W attribs */
  3966. cmd->Service = CACHESERVICE;
  3967. cmd->OpCode = GDT_DEVTYPE;
  3968. if (ha->cache_feat & GDT_64BIT)
  3969. cmd->u.cache64.DeviceNo = i;
  3970. else
  3971. cmd->u.cache.DeviceNo = i;
  3972. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3973. spin_lock_irqsave(&ha->smp_lock, flags);
  3974. ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
  3975. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3976. cmd->Service = CACHESERVICE;
  3977. cmd->OpCode = GDT_CLUST_INFO;
  3978. if (ha->cache_feat & GDT_64BIT)
  3979. cmd->u.cache64.DeviceNo = i;
  3980. else
  3981. cmd->u.cache.DeviceNo = i;
  3982. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3983. spin_lock_irqsave(&ha->smp_lock, flags);
  3984. ha->hdr[i].cluster_type =
  3985. ((status == S_OK && !shared_access) ? (ushort)info : 0);
  3986. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3987. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  3988. cmd->Service = CACHESERVICE;
  3989. cmd->OpCode = GDT_RW_ATTRIBS;
  3990. if (ha->cache_feat & GDT_64BIT)
  3991. cmd->u.cache64.DeviceNo = i;
  3992. else
  3993. cmd->u.cache.DeviceNo = i;
  3994. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  3995. spin_lock_irqsave(&ha->smp_lock, flags);
  3996. ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
  3997. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3998. }
  3999. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4000. rc = -EFAULT;
  4001. else
  4002. rc = 0;
  4003. free_fail:
  4004. kfree(rsc);
  4005. kfree(cmd);
  4006. return rc;
  4007. }
  4008. static int gdth_ioctl(struct inode *inode, struct file *filep,
  4009. unsigned int cmd, unsigned long arg)
  4010. {
  4011. gdth_ha_str *ha;
  4012. Scsi_Cmnd *scp;
  4013. ulong flags;
  4014. char cmnd[MAX_COMMAND_SIZE];
  4015. void __user *argp = (void __user *)arg;
  4016. memset(cmnd, 0xff, 12);
  4017. TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
  4018. switch (cmd) {
  4019. case GDTIOCTL_CTRCNT:
  4020. {
  4021. int cnt = gdth_ctr_count;
  4022. if (put_user(cnt, (int __user *)argp))
  4023. return -EFAULT;
  4024. break;
  4025. }
  4026. case GDTIOCTL_DRVERS:
  4027. {
  4028. int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
  4029. if (put_user(ver, (int __user *)argp))
  4030. return -EFAULT;
  4031. break;
  4032. }
  4033. case GDTIOCTL_OSVERS:
  4034. {
  4035. gdth_ioctl_osvers osv;
  4036. osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
  4037. osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
  4038. osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
  4039. if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
  4040. return -EFAULT;
  4041. break;
  4042. }
  4043. case GDTIOCTL_CTRTYPE:
  4044. {
  4045. gdth_ioctl_ctrtype ctrt;
  4046. if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
  4047. (NULL == (ha = gdth_find_ha(ctrt.ionode))))
  4048. return -EFAULT;
  4049. if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
  4050. ctrt.type = (unchar)((ha->stype>>20) - 0x10);
  4051. } else {
  4052. if (ha->type != GDT_PCIMPR) {
  4053. ctrt.type = (unchar)((ha->stype<<4) + 6);
  4054. } else {
  4055. ctrt.type =
  4056. (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
  4057. if (ha->stype >= 0x300)
  4058. ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
  4059. else
  4060. ctrt.ext_type = 0x6000 | ha->stype;
  4061. }
  4062. ctrt.device_id = ha->pdev->device;
  4063. ctrt.sub_device_id = ha->pdev->subsystem_device;
  4064. }
  4065. ctrt.info = ha->brd_phys;
  4066. ctrt.oem_id = ha->oem_id;
  4067. if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
  4068. return -EFAULT;
  4069. break;
  4070. }
  4071. case GDTIOCTL_GENERAL:
  4072. return ioc_general(argp, cmnd);
  4073. case GDTIOCTL_EVENT:
  4074. return ioc_event(argp);
  4075. case GDTIOCTL_LOCKDRV:
  4076. return ioc_lockdrv(argp);
  4077. case GDTIOCTL_LOCKCHN:
  4078. {
  4079. gdth_ioctl_lockchn lchn;
  4080. unchar i, j;
  4081. if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
  4082. (NULL == (ha = gdth_find_ha(lchn.ionode))))
  4083. return -EFAULT;
  4084. i = lchn.channel;
  4085. if (i < ha->bus_cnt) {
  4086. if (lchn.lock) {
  4087. spin_lock_irqsave(&ha->smp_lock, flags);
  4088. ha->raw[i].lock = 1;
  4089. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4090. for (j = 0; j < ha->tid_cnt; ++j) {
  4091. gdth_wait_completion(ha, i, j);
  4092. gdth_stop_timeout(ha, i, j);
  4093. }
  4094. } else {
  4095. spin_lock_irqsave(&ha->smp_lock, flags);
  4096. ha->raw[i].lock = 0;
  4097. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4098. for (j = 0; j < ha->tid_cnt; ++j) {
  4099. gdth_start_timeout(ha, i, j);
  4100. gdth_next(ha);
  4101. }
  4102. }
  4103. }
  4104. break;
  4105. }
  4106. case GDTIOCTL_RESCAN:
  4107. return ioc_rescan(argp, cmnd);
  4108. case GDTIOCTL_HDRLIST:
  4109. return ioc_hdrlist(argp, cmnd);
  4110. case GDTIOCTL_RESET_BUS:
  4111. {
  4112. gdth_ioctl_reset res;
  4113. int rval;
  4114. if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
  4115. (NULL == (ha = gdth_find_ha(res.ionode))))
  4116. return -EFAULT;
  4117. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  4118. if (!scp)
  4119. return -ENOMEM;
  4120. scp->device = ha->sdev;
  4121. scp->cmd_len = 12;
  4122. scp->device->channel = res.number;
  4123. rval = gdth_eh_bus_reset(scp);
  4124. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  4125. kfree(scp);
  4126. if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
  4127. return -EFAULT;
  4128. break;
  4129. }
  4130. case GDTIOCTL_RESET_DRV:
  4131. return ioc_resetdrv(argp, cmnd);
  4132. default:
  4133. break;
  4134. }
  4135. return 0;
  4136. }
  4137. /* flush routine */
  4138. static void gdth_flush(gdth_ha_str *ha)
  4139. {
  4140. int i;
  4141. gdth_cmd_str gdtcmd;
  4142. char cmnd[MAX_COMMAND_SIZE];
  4143. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4144. TRACE2(("gdth_flush() hanum %d\n", ha->hanum));
  4145. for (i = 0; i < MAX_HDRIVES; ++i) {
  4146. if (ha->hdr[i].present) {
  4147. gdtcmd.BoardNode = LOCALBOARD;
  4148. gdtcmd.Service = CACHESERVICE;
  4149. gdtcmd.OpCode = GDT_FLUSH;
  4150. if (ha->cache_feat & GDT_64BIT) {
  4151. gdtcmd.u.cache64.DeviceNo = i;
  4152. gdtcmd.u.cache64.BlockNo = 1;
  4153. gdtcmd.u.cache64.sg_canz = 0;
  4154. } else {
  4155. gdtcmd.u.cache.DeviceNo = i;
  4156. gdtcmd.u.cache.BlockNo = 1;
  4157. gdtcmd.u.cache.sg_canz = 0;
  4158. }
  4159. TRACE2(("gdth_flush(): flush ha %d drive %d\n", ha->hanum, i));
  4160. gdth_execute(ha->shost, &gdtcmd, cmnd, 30, NULL);
  4161. }
  4162. }
  4163. }
  4164. /* configure lun */
  4165. static int gdth_slave_configure(struct scsi_device *sdev)
  4166. {
  4167. scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
  4168. sdev->skip_ms_page_3f = 1;
  4169. sdev->skip_ms_page_8 = 1;
  4170. return 0;
  4171. }
  4172. static struct scsi_host_template gdth_template = {
  4173. .name = "GDT SCSI Disk Array Controller",
  4174. .info = gdth_info,
  4175. .queuecommand = gdth_queuecommand,
  4176. .eh_bus_reset_handler = gdth_eh_bus_reset,
  4177. .slave_configure = gdth_slave_configure,
  4178. .bios_param = gdth_bios_param,
  4179. .proc_info = gdth_proc_info,
  4180. .proc_name = "gdth",
  4181. .can_queue = GDTH_MAXCMDS,
  4182. .this_id = -1,
  4183. .sg_tablesize = GDTH_MAXSG,
  4184. .cmd_per_lun = GDTH_MAXC_P_L,
  4185. .unchecked_isa_dma = 1,
  4186. .use_clustering = ENABLE_CLUSTERING,
  4187. };
  4188. #ifdef CONFIG_ISA
  4189. static int __init gdth_isa_probe_one(ulong32 isa_bios)
  4190. {
  4191. struct Scsi_Host *shp;
  4192. gdth_ha_str *ha;
  4193. dma_addr_t scratch_dma_handle = 0;
  4194. int error, i;
  4195. if (!gdth_search_isa(isa_bios))
  4196. return -ENXIO;
  4197. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4198. if (!shp)
  4199. return -ENOMEM;
  4200. ha = shost_priv(shp);
  4201. error = -ENODEV;
  4202. if (!gdth_init_isa(isa_bios,ha))
  4203. goto out_host_put;
  4204. /* controller found and initialized */
  4205. printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
  4206. isa_bios, ha->irq, ha->drq);
  4207. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4208. if (error) {
  4209. printk("GDT-ISA: Unable to allocate IRQ\n");
  4210. goto out_host_put;
  4211. }
  4212. error = request_dma(ha->drq, "gdth");
  4213. if (error) {
  4214. printk("GDT-ISA: Unable to allocate DMA channel\n");
  4215. goto out_free_irq;
  4216. }
  4217. set_dma_mode(ha->drq,DMA_MODE_CASCADE);
  4218. enable_dma(ha->drq);
  4219. shp->unchecked_isa_dma = 1;
  4220. shp->irq = ha->irq;
  4221. shp->dma_channel = ha->drq;
  4222. ha->hanum = gdth_ctr_count++;
  4223. ha->shost = shp;
  4224. ha->pccb = &ha->cmdext;
  4225. ha->ccb_phys = 0L;
  4226. ha->pdev = NULL;
  4227. error = -ENOMEM;
  4228. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4229. &scratch_dma_handle);
  4230. if (!ha->pscratch)
  4231. goto out_dec_counters;
  4232. ha->scratch_phys = scratch_dma_handle;
  4233. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4234. &scratch_dma_handle);
  4235. if (!ha->pmsg)
  4236. goto out_free_pscratch;
  4237. ha->msg_phys = scratch_dma_handle;
  4238. #ifdef INT_COAL
  4239. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4240. sizeof(gdth_coal_status) * MAXOFFSETS,
  4241. &scratch_dma_handle);
  4242. if (!ha->coal_stat)
  4243. goto out_free_pmsg;
  4244. ha->coal_stat_phys = scratch_dma_handle;
  4245. #endif
  4246. ha->scratch_busy = FALSE;
  4247. ha->req_first = NULL;
  4248. ha->tid_cnt = MAX_HDRIVES;
  4249. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4250. ha->tid_cnt = max_ids;
  4251. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4252. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4253. ha->scan_mode = rescan ? 0x10 : 0;
  4254. error = -ENODEV;
  4255. if (!gdth_search_drives(ha)) {
  4256. printk("GDT-ISA: Error during device scan\n");
  4257. goto out_free_coal_stat;
  4258. }
  4259. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4260. hdr_channel = ha->bus_cnt;
  4261. ha->virt_bus = hdr_channel;
  4262. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4263. shp->max_cmd_len = 16;
  4264. shp->max_id = ha->tid_cnt;
  4265. shp->max_lun = MAXLUN;
  4266. shp->max_channel = ha->bus_cnt;
  4267. spin_lock_init(&ha->smp_lock);
  4268. gdth_enable_int(ha);
  4269. error = scsi_add_host(shp, NULL);
  4270. if (error)
  4271. goto out_free_coal_stat;
  4272. list_add_tail(&ha->list, &gdth_instances);
  4273. gdth_timer_init();
  4274. scsi_scan_host(shp);
  4275. return 0;
  4276. out_free_coal_stat:
  4277. #ifdef INT_COAL
  4278. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4279. ha->coal_stat, ha->coal_stat_phys);
  4280. out_free_pmsg:
  4281. #endif
  4282. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4283. ha->pmsg, ha->msg_phys);
  4284. out_free_pscratch:
  4285. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4286. ha->pscratch, ha->scratch_phys);
  4287. out_dec_counters:
  4288. gdth_ctr_count--;
  4289. out_free_irq:
  4290. free_irq(ha->irq, ha);
  4291. out_host_put:
  4292. scsi_host_put(shp);
  4293. return error;
  4294. }
  4295. #endif /* CONFIG_ISA */
  4296. #ifdef CONFIG_EISA
  4297. static int __init gdth_eisa_probe_one(ushort eisa_slot)
  4298. {
  4299. struct Scsi_Host *shp;
  4300. gdth_ha_str *ha;
  4301. dma_addr_t scratch_dma_handle = 0;
  4302. int error, i;
  4303. if (!gdth_search_eisa(eisa_slot))
  4304. return -ENXIO;
  4305. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4306. if (!shp)
  4307. return -ENOMEM;
  4308. ha = shost_priv(shp);
  4309. error = -ENODEV;
  4310. if (!gdth_init_eisa(eisa_slot,ha))
  4311. goto out_host_put;
  4312. /* controller found and initialized */
  4313. printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
  4314. eisa_slot >> 12, ha->irq);
  4315. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4316. if (error) {
  4317. printk("GDT-EISA: Unable to allocate IRQ\n");
  4318. goto out_host_put;
  4319. }
  4320. shp->unchecked_isa_dma = 0;
  4321. shp->irq = ha->irq;
  4322. shp->dma_channel = 0xff;
  4323. ha->hanum = gdth_ctr_count++;
  4324. ha->shost = shp;
  4325. TRACE2(("EISA detect Bus 0: hanum %d\n", ha->hanum));
  4326. ha->pccb = &ha->cmdext;
  4327. ha->ccb_phys = 0L;
  4328. error = -ENOMEM;
  4329. ha->pdev = NULL;
  4330. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4331. &scratch_dma_handle);
  4332. if (!ha->pscratch)
  4333. goto out_free_irq;
  4334. ha->scratch_phys = scratch_dma_handle;
  4335. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4336. &scratch_dma_handle);
  4337. if (!ha->pmsg)
  4338. goto out_free_pscratch;
  4339. ha->msg_phys = scratch_dma_handle;
  4340. #ifdef INT_COAL
  4341. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4342. sizeof(gdth_coal_status) * MAXOFFSETS,
  4343. &scratch_dma_handle);
  4344. if (!ha->coal_stat)
  4345. goto out_free_pmsg;
  4346. ha->coal_stat_phys = scratch_dma_handle;
  4347. #endif
  4348. ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
  4349. sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
  4350. if (!ha->ccb_phys)
  4351. goto out_free_coal_stat;
  4352. ha->scratch_busy = FALSE;
  4353. ha->req_first = NULL;
  4354. ha->tid_cnt = MAX_HDRIVES;
  4355. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4356. ha->tid_cnt = max_ids;
  4357. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4358. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4359. ha->scan_mode = rescan ? 0x10 : 0;
  4360. if (!gdth_search_drives(ha)) {
  4361. printk("GDT-EISA: Error during device scan\n");
  4362. error = -ENODEV;
  4363. goto out_free_ccb_phys;
  4364. }
  4365. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4366. hdr_channel = ha->bus_cnt;
  4367. ha->virt_bus = hdr_channel;
  4368. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4369. shp->max_cmd_len = 16;
  4370. shp->max_id = ha->tid_cnt;
  4371. shp->max_lun = MAXLUN;
  4372. shp->max_channel = ha->bus_cnt;
  4373. spin_lock_init(&ha->smp_lock);
  4374. gdth_enable_int(ha);
  4375. error = scsi_add_host(shp, NULL);
  4376. if (error)
  4377. goto out_free_coal_stat;
  4378. list_add_tail(&ha->list, &gdth_instances);
  4379. gdth_timer_init();
  4380. scsi_scan_host(shp);
  4381. return 0;
  4382. out_free_ccb_phys:
  4383. pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
  4384. PCI_DMA_BIDIRECTIONAL);
  4385. out_free_coal_stat:
  4386. #ifdef INT_COAL
  4387. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4388. ha->coal_stat, ha->coal_stat_phys);
  4389. out_free_pmsg:
  4390. #endif
  4391. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4392. ha->pmsg, ha->msg_phys);
  4393. out_free_pscratch:
  4394. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4395. ha->pscratch, ha->scratch_phys);
  4396. out_free_irq:
  4397. free_irq(ha->irq, ha);
  4398. gdth_ctr_count--;
  4399. out_host_put:
  4400. scsi_host_put(shp);
  4401. return error;
  4402. }
  4403. #endif /* CONFIG_EISA */
  4404. #ifdef CONFIG_PCI
  4405. static int gdth_pci_probe_one(gdth_pci_str *pcistr,
  4406. gdth_ha_str **ha_out)
  4407. {
  4408. struct Scsi_Host *shp;
  4409. gdth_ha_str *ha;
  4410. dma_addr_t scratch_dma_handle = 0;
  4411. int error, i;
  4412. struct pci_dev *pdev = pcistr->pdev;
  4413. *ha_out = NULL;
  4414. shp = scsi_host_alloc(&gdth_template, sizeof(gdth_ha_str));
  4415. if (!shp)
  4416. return -ENOMEM;
  4417. ha = shost_priv(shp);
  4418. error = -ENODEV;
  4419. if (!gdth_init_pci(pdev, pcistr, ha))
  4420. goto out_host_put;
  4421. /* controller found and initialized */
  4422. printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
  4423. pdev->bus->number,
  4424. PCI_SLOT(pdev->devfn),
  4425. ha->irq);
  4426. error = request_irq(ha->irq, gdth_interrupt,
  4427. IRQF_DISABLED|IRQF_SHARED, "gdth", ha);
  4428. if (error) {
  4429. printk("GDT-PCI: Unable to allocate IRQ\n");
  4430. goto out_host_put;
  4431. }
  4432. shp->unchecked_isa_dma = 0;
  4433. shp->irq = ha->irq;
  4434. shp->dma_channel = 0xff;
  4435. ha->hanum = gdth_ctr_count++;
  4436. ha->shost = shp;
  4437. ha->pccb = &ha->cmdext;
  4438. ha->ccb_phys = 0L;
  4439. error = -ENOMEM;
  4440. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4441. &scratch_dma_handle);
  4442. if (!ha->pscratch)
  4443. goto out_free_irq;
  4444. ha->scratch_phys = scratch_dma_handle;
  4445. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4446. &scratch_dma_handle);
  4447. if (!ha->pmsg)
  4448. goto out_free_pscratch;
  4449. ha->msg_phys = scratch_dma_handle;
  4450. #ifdef INT_COAL
  4451. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  4452. sizeof(gdth_coal_status) * MAXOFFSETS,
  4453. &scratch_dma_handle);
  4454. if (!ha->coal_stat)
  4455. goto out_free_pmsg;
  4456. ha->coal_stat_phys = scratch_dma_handle;
  4457. #endif
  4458. ha->scratch_busy = FALSE;
  4459. ha->req_first = NULL;
  4460. ha->tid_cnt = pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
  4461. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4462. ha->tid_cnt = max_ids;
  4463. for (i = 0; i < GDTH_MAXCMDS; ++i)
  4464. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4465. ha->scan_mode = rescan ? 0x10 : 0;
  4466. error = -ENODEV;
  4467. if (!gdth_search_drives(ha)) {
  4468. printk("GDT-PCI %d: Error during device scan\n", ha->hanum);
  4469. goto out_free_coal_stat;
  4470. }
  4471. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4472. hdr_channel = ha->bus_cnt;
  4473. ha->virt_bus = hdr_channel;
  4474. /* 64-bit DMA only supported from FW >= x.43 */
  4475. if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT) ||
  4476. !ha->dma64_support) {
  4477. if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  4478. printk(KERN_WARNING "GDT-PCI %d: "
  4479. "Unable to set 32-bit DMA\n", ha->hanum);
  4480. goto out_free_coal_stat;
  4481. }
  4482. } else {
  4483. shp->max_cmd_len = 16;
  4484. if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
  4485. printk("GDT-PCI %d: 64-bit DMA enabled\n", ha->hanum);
  4486. } else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  4487. printk(KERN_WARNING "GDT-PCI %d: "
  4488. "Unable to set 64/32-bit DMA\n", ha->hanum);
  4489. goto out_free_coal_stat;
  4490. }
  4491. }
  4492. shp->max_id = ha->tid_cnt;
  4493. shp->max_lun = MAXLUN;
  4494. shp->max_channel = ha->bus_cnt;
  4495. spin_lock_init(&ha->smp_lock);
  4496. gdth_enable_int(ha);
  4497. error = scsi_add_host(shp, &pdev->dev);
  4498. if (error)
  4499. goto out_free_coal_stat;
  4500. list_add_tail(&ha->list, &gdth_instances);
  4501. pci_set_drvdata(ha->pdev, ha);
  4502. gdth_timer_init();
  4503. scsi_scan_host(shp);
  4504. *ha_out = ha;
  4505. return 0;
  4506. out_free_coal_stat:
  4507. #ifdef INT_COAL
  4508. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  4509. ha->coal_stat, ha->coal_stat_phys);
  4510. out_free_pmsg:
  4511. #endif
  4512. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4513. ha->pmsg, ha->msg_phys);
  4514. out_free_pscratch:
  4515. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4516. ha->pscratch, ha->scratch_phys);
  4517. out_free_irq:
  4518. free_irq(ha->irq, ha);
  4519. gdth_ctr_count--;
  4520. out_host_put:
  4521. scsi_host_put(shp);
  4522. return error;
  4523. }
  4524. #endif /* CONFIG_PCI */
  4525. static void gdth_remove_one(gdth_ha_str *ha)
  4526. {
  4527. struct Scsi_Host *shp = ha->shost;
  4528. TRACE2(("gdth_remove_one()\n"));
  4529. scsi_remove_host(shp);
  4530. gdth_flush(ha);
  4531. if (ha->sdev) {
  4532. scsi_free_host_dev(ha->sdev);
  4533. ha->sdev = NULL;
  4534. }
  4535. if (shp->irq)
  4536. free_irq(shp->irq,ha);
  4537. #ifdef CONFIG_ISA
  4538. if (shp->dma_channel != 0xff)
  4539. free_dma(shp->dma_channel);
  4540. #endif
  4541. #ifdef INT_COAL
  4542. if (ha->coal_stat)
  4543. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4544. MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
  4545. #endif
  4546. if (ha->pscratch)
  4547. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4548. ha->pscratch, ha->scratch_phys);
  4549. if (ha->pmsg)
  4550. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4551. ha->pmsg, ha->msg_phys);
  4552. if (ha->ccb_phys)
  4553. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4554. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4555. scsi_host_put(shp);
  4556. }
  4557. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
  4558. {
  4559. gdth_ha_str *ha;
  4560. TRACE2(("gdth_halt() event %d\n", (int)event));
  4561. if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
  4562. return NOTIFY_DONE;
  4563. list_for_each_entry(ha, &gdth_instances, list)
  4564. gdth_flush(ha);
  4565. return NOTIFY_OK;
  4566. }
  4567. static struct notifier_block gdth_notifier = {
  4568. gdth_halt, NULL, 0
  4569. };
  4570. static int __init gdth_init(void)
  4571. {
  4572. if (disable) {
  4573. printk("GDT-HA: Controller driver disabled from"
  4574. " command line !\n");
  4575. return 0;
  4576. }
  4577. printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",
  4578. GDTH_VERSION_STR);
  4579. /* initializations */
  4580. gdth_polling = TRUE;
  4581. gdth_clear_events();
  4582. init_timer(&gdth_timer);
  4583. /* As default we do not probe for EISA or ISA controllers */
  4584. if (probe_eisa_isa) {
  4585. /* scanning for controllers, at first: ISA controller */
  4586. #ifdef CONFIG_ISA
  4587. ulong32 isa_bios;
  4588. for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
  4589. isa_bios += 0x8000UL)
  4590. gdth_isa_probe_one(isa_bios);
  4591. #endif
  4592. #ifdef CONFIG_EISA
  4593. {
  4594. ushort eisa_slot;
  4595. for (eisa_slot = 0x1000; eisa_slot <= 0x8000;
  4596. eisa_slot += 0x1000)
  4597. gdth_eisa_probe_one(eisa_slot);
  4598. }
  4599. #endif
  4600. }
  4601. #ifdef CONFIG_PCI
  4602. /* scanning for PCI controllers */
  4603. if (pci_register_driver(&gdth_pci_driver)) {
  4604. gdth_ha_str *ha;
  4605. list_for_each_entry(ha, &gdth_instances, list)
  4606. gdth_remove_one(ha);
  4607. return -ENODEV;
  4608. }
  4609. #endif /* CONFIG_PCI */
  4610. TRACE2(("gdth_detect() %d controller detected\n", gdth_ctr_count));
  4611. major = register_chrdev(0,"gdth", &gdth_fops);
  4612. register_reboot_notifier(&gdth_notifier);
  4613. gdth_polling = FALSE;
  4614. return 0;
  4615. }
  4616. static void __exit gdth_exit(void)
  4617. {
  4618. gdth_ha_str *ha;
  4619. unregister_chrdev(major, "gdth");
  4620. unregister_reboot_notifier(&gdth_notifier);
  4621. #ifdef GDTH_STATISTICS
  4622. del_timer_sync(&gdth_timer);
  4623. #endif
  4624. #ifdef CONFIG_PCI
  4625. pci_unregister_driver(&gdth_pci_driver);
  4626. #endif
  4627. list_for_each_entry(ha, &gdth_instances, list)
  4628. gdth_remove_one(ha);
  4629. }
  4630. module_init(gdth_init);
  4631. module_exit(gdth_exit);
  4632. #ifndef MODULE
  4633. __setup("gdth=", option_setup);
  4634. #endif