ioasm.h 2.7 KB

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  1. #ifndef S390_CIO_IOASM_H
  2. #define S390_CIO_IOASM_H
  3. #include <asm/chpid.h>
  4. #include <asm/schid.h>
  5. /*
  6. * TPI info structure
  7. */
  8. struct tpi_info {
  9. struct subchannel_id schid;
  10. __u32 intparm; /* interruption parameter */
  11. __u32 adapter_IO : 1;
  12. __u32 reserved2 : 1;
  13. __u32 isc : 3;
  14. __u32 reserved3 : 12;
  15. __u32 int_type : 3;
  16. __u32 reserved4 : 12;
  17. } __attribute__ ((packed));
  18. /*
  19. * Some S390 specific IO instructions as inline
  20. */
  21. static inline int stsch(struct subchannel_id schid,
  22. volatile struct schib *addr)
  23. {
  24. register struct subchannel_id reg1 asm ("1") = schid;
  25. int ccode;
  26. asm volatile(
  27. " stsch 0(%2)\n"
  28. " ipm %0\n"
  29. " srl %0,28"
  30. : "=d" (ccode) : "d" (reg1), "a" (addr), "m" (*addr) : "cc");
  31. return ccode;
  32. }
  33. static inline int stsch_err(struct subchannel_id schid,
  34. volatile struct schib *addr)
  35. {
  36. register struct subchannel_id reg1 asm ("1") = schid;
  37. int ccode = -EIO;
  38. asm volatile(
  39. " stsch 0(%2)\n"
  40. "0: ipm %0\n"
  41. " srl %0,28\n"
  42. "1:\n"
  43. EX_TABLE(0b,1b)
  44. : "+d" (ccode) : "d" (reg1), "a" (addr), "m" (*addr) : "cc");
  45. return ccode;
  46. }
  47. static inline int msch(struct subchannel_id schid,
  48. volatile struct schib *addr)
  49. {
  50. register struct subchannel_id reg1 asm ("1") = schid;
  51. int ccode;
  52. asm volatile(
  53. " msch 0(%2)\n"
  54. " ipm %0\n"
  55. " srl %0,28"
  56. : "=d" (ccode) : "d" (reg1), "a" (addr), "m" (*addr) : "cc");
  57. return ccode;
  58. }
  59. static inline int msch_err(struct subchannel_id schid,
  60. volatile struct schib *addr)
  61. {
  62. register struct subchannel_id reg1 asm ("1") = schid;
  63. int ccode = -EIO;
  64. asm volatile(
  65. " msch 0(%2)\n"
  66. "0: ipm %0\n"
  67. " srl %0,28\n"
  68. "1:\n"
  69. EX_TABLE(0b,1b)
  70. : "+d" (ccode) : "d" (reg1), "a" (addr), "m" (*addr) : "cc");
  71. return ccode;
  72. }
  73. static inline int tsch(struct subchannel_id schid,
  74. volatile struct irb *addr)
  75. {
  76. register struct subchannel_id reg1 asm ("1") = schid;
  77. int ccode;
  78. asm volatile(
  79. " tsch 0(%2)\n"
  80. " ipm %0\n"
  81. " srl %0,28"
  82. : "=d" (ccode) : "d" (reg1), "a" (addr), "m" (*addr) : "cc");
  83. return ccode;
  84. }
  85. static inline int tpi( volatile struct tpi_info *addr)
  86. {
  87. int ccode;
  88. asm volatile(
  89. " tpi 0(%1)\n"
  90. " ipm %0\n"
  91. " srl %0,28"
  92. : "=d" (ccode) : "a" (addr), "m" (*addr) : "cc");
  93. return ccode;
  94. }
  95. static inline int chsc(void *chsc_area)
  96. {
  97. typedef struct { char _[4096]; } addr_type;
  98. int cc;
  99. asm volatile(
  100. " .insn rre,0xb25f0000,%2,0\n"
  101. " ipm %0\n"
  102. " srl %0,28\n"
  103. : "=d" (cc), "=m" (*(addr_type *) chsc_area)
  104. : "d" (chsc_area), "m" (*(addr_type *) chsc_area)
  105. : "cc");
  106. return cc;
  107. }
  108. static inline int rchp(struct chp_id chpid)
  109. {
  110. register struct chp_id reg1 asm ("1") = chpid;
  111. int ccode;
  112. asm volatile(
  113. " lr 1,%1\n"
  114. " rchp\n"
  115. " ipm %0\n"
  116. " srl %0,28"
  117. : "=d" (ccode) : "d" (reg1) : "cc");
  118. return ccode;
  119. }
  120. #endif